JP5440295B2 - Pressure sensor and manufacturing method thereof - Google Patents

Description

  The present invention relates to a pressure sensor and a manufacturing method thereof.

  Pressure sensors are widely used for the purpose of measuring various pressures such as water pressure and atmospheric pressure. There are various types of pressure sensors. In a sensor using a piezoelectric thin film as a sensor unit for detecting pressure, the pressure is measured by using the amount of charge induced in the piezoelectric thin film by the pressure.

  However, in this type of pressure sensor, since the pressure is measured based on the amount of charge induced in the entire piezoelectric thin film, only the pressure in the entire region where the piezoelectric thin film is formed can be measured. The local pressure cannot be measured. In addition, when a plurality of pressure sensors are used in a single plane to measure local pressure, if the film quality of the piezoelectric thin film in one pressure sensor is poor, the pressure measurement value in the pressure sensor becomes inaccurate. .

JP 2006-308559 A JP 2008-162885 A JP 2007-182370 A

  An object of the pressure sensor and the manufacturing method thereof is to make it possible to measure a pressure in a smaller region than in the past.

According to one aspect discussed herein, a transistor having a graphene layer as a channel, one end portion on the gate of the transistor is connected, have a wire including a piezoelectric material, wherein the transistor is on the substrate A catalyst layer formed on the side surface and an upper surface of the catalyst layer; a gate insulating film formed on a part of the side surface and the upper surface of the graphene layer; and the gate insulation It is formed and on the sides and on the upper surface of the membrane, the pressure sensor that has a said gate having an overhang portion which faces a side surface of the graphene layer.

According to another aspect of the disclosure, on a substrate, forming a transistor having a graphene layer as a channel, on the gate of the transistor, have a growing a wire comprising a piezoelectric material Forming the transistor on the substrate; forming the graphene layer on a side surface and an upper surface of the catalyst layer; and forming a gate on the side surface and the upper surface of the graphene layer. forming an insulating film, on the on side and on the upper surface of the gate insulating film, a manufacturing method of the pressure sensor for chromatic and forming the gate with an overhang portion which faces a side surface of the graphene layer Provided.

  Since the nanowire used in the following disclosure occupies a small area in the pressure sensor as compared with the piezoelectric thin film, it is advantageous for detecting pressure in a minute region.

  In addition, by using a transistor in which a graphene layer is formed as a channel, minute fluctuations in induced voltage generated in the nanowire can be detected with high sensitivity.

FIG. 1 is a perspective view of a pressure sensor according to the first embodiment. FIG. 2 is a cross-sectional view taken along the line II of FIG. FIG. 3 is a perspective view of a model used for the simulation in the first embodiment. FIG. 4 is a perspective view when the nanowire is bent in the pressure sensor according to the first embodiment. FIG. 5 is a diagram schematically showing the significance of the formula (3). FIG. 6 is a graph obtained by simulating the relationship between the length of the nanowire and the induced voltage in the first embodiment. FIG. 7 is a graph obtained by simulating the relationship between the gate voltage and the drain current in the first embodiment. FIG. 8 is a graph obtained by simulating the relationship between wind speed and induced voltage in the first embodiment. FIG. 9 is a graph obtained by simulating the relationship between blood pressure and induced voltage in the first embodiment. FIG. 10 is a circuit diagram of the second embodiment. FIG. 11 is a functional block diagram of the second embodiment. FIG. 12 is a perspective view (No. 1) in the middle of manufacturing of the pressure sensor according to the third embodiment. FIG. 13: is a perspective view (the 2) in the middle of manufacture of the pressure sensor which concerns on 3rd Embodiment. FIG. 14 is a perspective view (No. 3) in the middle of manufacturing the pressure sensor according to the third embodiment. FIG. 15: is a perspective view (the 4) in the middle of manufacture of the pressure sensor which concerns on 3rd Embodiment. 16A to 16C are a cross-sectional view and a side view (No. 1) in the middle of manufacturing the pressure sensor according to the third embodiment. 17A to 17C are a cross-sectional view and a side view (part 2) in the middle of manufacturing the pressure sensor according to the third embodiment. 18A and 18B are a sectional view and a side view (No. 3) in the middle of manufacturing the pressure sensor according to the third embodiment. FIGS. 19A and 19B are a cross-sectional view and a side view (part 4) in the middle of manufacturing the pressure sensor according to the third embodiment. 20A and 20B are a cross-sectional view and a side view (part 5) in the middle of manufacturing the pressure sensor according to the third embodiment. 20A and 20B are a cross-sectional view and a side view (No. 6) in the middle of manufacturing the pressure sensor according to the third embodiment.

(First embodiment)
Hereinafter, the present embodiment will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a perspective view of a pressure sensor according to the present embodiment.

  The pressure sensor 10 includes a transistor TR on a silicon substrate 1 on which a base insulating film 2 such as a thermal oxide film is formed.

  The transistor TR includes a graphene layer 3 that functions as a channel, and a gate insulating film 4 and a gate 5 that are sequentially formed thereon. Among these, the graphene layer 3 has about 5 carbon atom layers, and can be formed by, for example, a CVD method.

As the gate insulating film 4, a hafnium oxide (HfO ₂ ) layer having a thickness of about 50 nm is formed. The gate 5 is formed by patterning a conductive layer such as a gold layer.

  A source electrode 6 and a drain electrode 7 including a titanium layer for drawing a drain current flowing through the graphene layer 3 are formed at both ends of the graphene layer 3.

  Then, one end of the nanowire 8 is connected to the upper surface 5 a of the gate 5. The material of the nanowire 8 is not particularly limited as long as it is a piezoelectric material. In this embodiment, a zinc oxide (ZnO) nanowire is erected on the gate 5 as the nanowire 8. Instead of zinc oxide nanowires, aluminum nitride (AlN) nanowires may be formed.

  The length of the nanowire 8 is not particularly limited, but in this embodiment, the nanowire 8 is formed to a length of about 100 μm to 500 μm. The reason why the lower limit of the length is set to 100 μm is that if the length is shorter than this, the nanowire 8 is not easily deformed even when an external pressure is applied. In order to induce a charge in the nanowire 8 by strain, a certain amount of deformation is required, and if it is at least about 100 μm, a sufficient charge for detection is induced.

  On the other hand, the reason why the upper limit of the length is set to 500 μm is that if the length is longer than this, the strength of the nanowire 8 is weakened and the nanowire 8 may be defective.

  The diameter of the nanowire 8 is not particularly limited, but is preferably 50 nm or more from the viewpoint of ensuring the strength of the nanowire 8. From the standpoint that more nanowires 8 are erected on the gate 5, the diameter of the nanowires 8 is preferably 100 nm or less.

According to such a pressure sensor 10, each wire 8 is deformed by an externally applied pressure ω, and an induced voltage is generated at the end of the wire 8 connected to the gate 5. Since the gate voltage of the gate 5 is changed by the induced voltage also varies the drain current I _d flowing between the electrodes 6,7.

Therefore, in the pressure sensor 10, it may be based on a variation of the drain current I _d, measuring the magnitude of the pressure ω applied to the respective wires 8.

The transistor TR included in the pressure sensor 10 includes the graphene layer 3 as a channel. Since the graphene layer 3 has very high electron mobility compared to silicon, even if the fluctuation range of the induced voltage generated in the wire 8 is as small as several hundred nV to several tens mV, the drain flowing in the graphene layer 3 The current I _d can be amplified to an amplitude that can be practically used.

  Thereby, the minute fluctuation of the induced voltage generated in the nanowire 8 can be captured with high sensitivity, and the pressure detection sensitivity can be increased.

  Further, since the nanowire 8 occupies a small area in the pressure sensor 10 compared to the piezoelectric thin film, the pressure in the minute region can be detected by the pressure sensor 10.

  In addition, by forming a plurality of wires 8 on the gate 5, even if several of them are defective, the gate voltage can be changed by the induced voltage normally generated in the remaining wires 8, so that the pressure ω The reliability of the measured value increases.

  Further, by making the extending direction of the nanowire 8 perpendicular to the upper surface 5a of the gate 5 as shown in FIG. 1, when the pressure ω is applied from the lateral direction of the substrate, the nanowire 8 is easily bent in the lateral direction of the substrate. . Thereby, compared with the case where the extending direction of the nanowire 8 is inclined from the upper surface 5a of the gate 5, the induced voltage generated in the wire 8 can be increased and the detection sensitivity of the pressure ω can be increased.

  FIG. 2 is a cross-sectional view taken along the line II of FIG.

  As shown in FIG. 2, a first catalyst layer 13 that functions as a catalyst during the growth of the graphene layer 3 is formed on the base insulating film 2. In the present embodiment, an iron layer having a thickness of about 200 nm is formed as the first catalyst layer 13.

  The graphene layer 3 is formed on the upper surface 13 a and the side surface 13 b of the first catalyst layer 13, and the gate insulating film 4 is formed so as to cover the graphene layer 3.

  The gate 5 has a main body 5 d formed on the upper surface 4 a of the gate insulating film 4 and an overhang portion 5 c that protrudes from the main body 5 d and is formed on the side surface 4 b of the gate insulating film 4.

  Thus, by forming the overhang portion 5 c so as to face the side surface 3 b of the graphene layer 3, not only the drain current flowing through the upper surface 3 a but also the drain current at the side surface 3 b can be controlled by the gate 5. Therefore, the drain current responds sensitively to the induced voltage generated in the wire 8, and the pressure detection sensitivity can be increased.

  Next, the simulation result about the operation of the pressure sensor 10 will be described.

  FIG. 3 is a perspective view of the model used for the simulation.

  In FIG. 3, the same elements as those described in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted below.

In this model, it is assumed that the graphene layer 3 is formed on the entire surface of the base insulating film 2. Further, the gate 5 was formed only on the upper surface of the gate insulating film 4. The gate width W is 100 μm, the gate length L ₀ is 1 μm, and the lengths L ₁ of the electrodes 6 and 7 are 10 μm. The distance L ₂ between the electrodes 6 and 7 and the gate 5 is 5 μm, and the thickness of the gate insulating film 4 is 50 nm.

  Furthermore, it was assumed that only one nanowire 8 was formed on the gate 5. For the coordinate system, an X axis, a Y axis, and a Z axis were set in the directions shown in FIG. The origin of the coordinate system coincides with the end connected to the gate 5 among the two ends of the nanowire 8.

When a piezoelectric material having a wurtzite structure such as zinc oxide is used as the material of the nanowire 8, the charge densities P _XX , P _YY , and P _ZZ induced in the nanowire 8 are expressed by the following formula (1). The

In the formula (1), P _XX is a charge density induced on a plane perpendicular to the X-axis direction. Similarly, P _YY and P _ZZ are charge densities induced on the planes perpendicular to the Y-axis direction and the Z-axis direction, respectively.

Σ _ij is the pressure in the j direction applied to the i plane.

Further, _dij is an electromechanical coupling constant of the piezoelectric material in the nanowire 8. When zinc oxide is used as the piezoelectric material as in the present embodiment, the value of each component is as follows.

d ₁₅ = -41.7 × 10 ^-8 (CGSesu / dyn)
d ₃₃ = 31.8 × 10 ^-8 (CGSesu / dyn)
d ₃₁ = -15.6 × 10 ^-8 (CGSesu / dyn)
FIG. 4 is a perspective view when the wire 8 is bent in the Y-axis direction by a pressure ω applied in a direction parallel to the Y-axis direction.

When the pressure ω is uniform in the X-axis direction, it is known that the stress f _x applied to the wire 8 at the height _x is expressed by the following equation (2).

  In Expression (2), L is the length of the wire 8.

It is known that using the stress f _x , the electromechanical coupling constant σ _XY is expressed by the following equation (3).

FIG. 5 is a diagram schematically showing the significance of the formula (3). As shown in FIG. 5, the electromechanical coupling constant sigma _XY is equal to the area of the portion between the graph and the X-axis of stress f _x.

On the other hand, when the wire 8 bends in the Y-axis direction as described above, P _YY of the charge density induced in the wire 8 is represented by the following equation (4) from the equation (1).

When the expression (3) is substituted into the expression (4) and the integral of the expression (3) is calculated, P _YY is expressed as the following expression (5).

  One use of the pressure sensor according to this embodiment is an anemometer.

Therefore, in the following, how much drain current I _d flows through the pressure sensor 10 when wind is applied to the nanowire 8 from the side will be described using Equation (5).

When the wind speed is 5 m / s, the pressure ω is empirically about 1.3 N / m ² . When the value of ω and the value of d _{15 described} above are used in the equation (5) and the induced voltage V _I induced in the nanowire 8 is calculated from the charge amount P _YY obtained thereby, the result shown in FIG. 6 is obtained. It became.

From the results of FIG. 6, it was found that when the wire length L is 320 μm, the induced voltage V _I is about 1 μV.

On the other hand, in the model of FIG. 3, when the carrier mobility in the graphene layer 3 is assumed to be 10 ⁵ cm ² / V · s, the relationship between the gate voltage V _g and the drain current I _d is simulated. It became so.

As described above, the induced voltage generated in the gate 5 by the wind having a wind speed of 5 m / s is about 1 μV. Therefore, when the wind 5 m / s blew from no wind, so that the gate voltage V _g around the operating point voltage applied to the gate 5 increases by about 1 uV. According to FIG. 7, by increasing the gate voltage V _g to about 1 uV, so that the drain current rises to approximately 10 .mu.A.

FIG. 8 is a diagram obtained by simulating the relationship between the wind speed of the wind hitting the nanowire 8 from the side and the induced voltage V _I induced in the nanowire 8.

As shown in FIG. 8, an induced voltage V _I of about several hundred nV to several μV is generated in the range of wind speed 5 m / s to typhoon class wind speed 40 m / s. According to the induced voltage V _I in this range, it is clear that a drain current I _d of 1 μA to 100 μA flows when the operating point voltage of the transistor TR is 2.0V. This value is large enough to withstand practical use.

  From this result, it became clear that the pressure sensor according to the present embodiment can be used for an anemometer.

  On the other hand, there is a blood pressure monitor as another application of the pressure sensor.

In the case of a sphygmomanometer, the pressure range to be measured is about 10 mmHg to 200 mmHg. FIG. 9 is a diagram obtained by simulating the relationship between the blood pressure in this range and the induced voltage V _I induced in the nanowire 8.

As shown in FIG. 9, when the blood pressure is in the range of 10 mmHg to 200 mmHg, an induced voltage V _{I of} several mV to several tens of mV is generated. According to the induced voltage V _I in this range, it has been found by simulation that a sufficiently large drain current of about 10 mA to 100 mA flows when the operating point voltage of the transistor TR is 2.0 V.

  From this, it became clear that the pressure sensor according to the present embodiment can be used as a sphygmomanometer.

(Second Embodiment)
In the present embodiment, a plurality of the pressure sensors 10 of the first embodiment are arranged in a matrix in one plane so that a local pressure in the plane can be detected.

  FIG. 10 is a circuit diagram of this embodiment.

As shown in FIG. 10, in this embodiment, the gates 5 of the plurality of pressure sensors 10 are electrically connected to the plurality of word lines WL _{1 to} WL ₃ .

Among these pressure sensors 10, those in the same row have their drains electrically connected to the same bit lines BL _{1 to} BL ₃ .

Further, the drain of each pressure sensor 10 is electrically connected to the resistor R via the capacitor C. According to such a circuit, the DC component of the drain current I _d is cut by the capacitor C, only an AC component of the drain current I _d flows through the resistor R. The sense voltage V _ij is generated by the alternating current component of the drain current I _d flowing at both ends of the resistor R in the i-th row and j-th column.

In order to generate a sufficiently large sense voltage V _ij , the resistance value of the resistor R is preferably several tens of Ω to several MΩ.

The sense voltage V _ij is output to the bit lines BL _{1 to} BL ₃ via the capacitor C. Note that which of the sense voltages V _ij in the same row is output to the bit lines BL _{1 to} BL ₃ can be selected by applying column selection voltages V _{g1 to} V _g3 to the word lines WL _{1 to} WL ₃ . For example, if only the column selection voltage V _g1 is set to the high level and other column selection voltages V _g2 and V _g3 are set to the low level, only the sensor 10 connected to the word line WL ₁ is turned on, and these sensors 10, sense voltages V ₁₁ , V ₂₁ and V ₃₁ are output to bit lines BL _{1 to} BL ₃ .

FIG. 11 is a functional block diagram of the subsequent stage of each of the bit lines BL _{1 to} BL ₃ .

As shown in FIG. 11, the sense voltage V _ij output from each of the bit lines BL _{1 to} BL ₃ is amplified by the amplifier circuit 101, and then the waveform shaping circuit 102 adjusts the waveform.

Thereafter, an excess noise component included in the sense voltage V _ij is removed by the noise removal filter 103, and the sense voltage V _ij is digitized in the A / D conversion circuit.

Based on the digitized sense voltage V _ij , the i-th and j-th column pressure values are displayed on the display 105 such as a monitor.

  According to the present embodiment described above, since a plurality of pressure sensors 10 are provided in one plane as shown in FIG. 10, a local pressure in the plane can be measured by each pressure sensor 10. .

Furthermore, since the nanowires 8 (see FIG. 1) included in each pressure sensor 10 are provided upright on the gate 5, the substrate in the lateral direction of the pressure sensor 10 is compared with the conventional example in which pressure is detected using a piezoelectric thin film. The size of becomes smaller. Therefore, in the conventional example, only one pressure sensor can be provided in a 1 cm ² region, whereas in the present embodiment, 1000 pressure sensors 10 can be provided in a 1 cm ² region. As described above, by arranging the pressure sensors 10 at a high density in one plane, it is possible to detect a pressure change in a region smaller than the conventional one.

  In addition, by making the number of nanowires 8 provided in one pressure sensor 10 plural, even if any of the nanowires 8 has a defect, the pressure can be detected by the remaining nanowires. Therefore, it is rare that one pressure sensor 10 completely fails, and it is possible to suppress an inaccurate local pressure measurement value in one plane.

(Third embodiment)
In the present embodiment, a manufacturing method of the pressure sensor described in the second embodiment will be described.

  12 to 15 are perspective views in the course of manufacturing the pressure sensor according to the present embodiment, and FIGS. 16 to 21 are sectional views and side views thereof.

  In manufacturing the pressure sensor, first, as shown in FIG. 12, the surface of the silicon substrate 1 is thermally oxidized to form a thermal oxide film as the base insulating film 2.

Then, a metal film such as aluminum is formed on the base insulating film 2 by sputtering, and the metal film is patterned to form word lines WL _{1 to} WL ₃ and capacitors C extending in the row direction. To do.

  In this step, simultaneously with the formation of the capacitor C, the first and second wirings 21 and 22 connected to the bipolar plates of the capacitor C and the third resistor R connected to the resistor R (see FIG. 10) described above. A wiring 23 is also formed.

Each word line WL _{1 to} WL ₃ is formed with a first extending portion 24 extending in the column direction.

Then, as shown in FIG. 13, on the word line WL ₁ to WL ₃ of a portion intersecting the bit lines BL ₁ to BL _3, to selectively form a silicon oxide film as the interlayer insulating film 30. In order to selectively form the interlayer insulating film 30 in this manner, for example, a resist pattern is formed on the entire upper surface of the silicon substrate 1, the interlayer insulating film 30 is formed in the window of the resist pattern, and then the resist pattern is formed. Just lift off.

Thereafter, BL _{1 to} BL ₃ extending in the column direction are formed on the base insulating film 2 and the interlayer insulating film 30. The bit lines BL _{1 to} BL ₃ are formed by lifting off a metal film such as an aluminum film using a resist pattern, like the interlayer insulating film 30.

Further, in this step, simultaneously with the formation of the bit lines BL ₁ to BL _3, the second extending portion 25 extending in the column direction are connected to the bit lines BL ₁ to BL ₃ is also formed.

  Next, as shown in FIG. 14, a resistor R is selectively formed by lift-off using a resist pattern. As the material of the resistance R, for example, nichrome, cyclome, tantalum nitride or the like is used. The second wiring 22 and the third wiring 23 described above are electrically connected to both ends of the resistor R.

  The basic structure of the circuit board 35 is completed through the steps so far.

  Thereafter, the process proceeds to a step of forming a stress sensor in the sensor formation region 35a of the circuit board 35. The process will be described with reference to FIGS.

  16 to 21 corresponds to a cross section taken along line I-I in FIG. The side views in FIGS. 16 to 21 correspond to the side surfaces of the transistor TR in FIG. 1 viewed from the channel width direction A.

  First, as shown in FIG. 16A, an iron layer having a thickness of about 200 nm is formed on the base insulating film 2 as a first catalyst layer 13 by lift-off using a resist pattern (not shown).

  Next, as shown in FIG. 16B, the graphene layer 3 is formed on the upper surface 13a and the side surface 13b of the first catalyst layer 13 by the CVD method while using iron in the first catalyst layer 13 as a catalyst. Grow. In the CVD method, a mixed gas of acetylene gas and argon gas is used as a reaction gas, and the substrate temperature is set to about 650 ° C.

  In the CVD method, the growth of the graphene layer 3 is stopped when about five carbon atom layers are stacked by controlling the film formation time.

  Next, as shown in FIG. 16C, a hafnium oxide film is selectively formed as the gate insulating film 4 on the upper surface 3a and the side surface 3b of the graphene layer 3 by an ALD (Atomic Layer Deposition) method. . The thickness of the gate insulating film 4 is not particularly limited, but in this embodiment, the thickness of the gate insulating film 4 on the upper surface 3a of the graphene layer 3 is about 50 nm.

  As a method for selectively forming the gate insulating film 4 only on the upper surface 3a and the side surface 3b as described above, lift-off using a resist pattern (not shown) is used.

  Next, as shown in FIG. 17A, a photoresist is applied to the entire upper surface of the silicon substrate 1, and the photoresist is baked to form a first resist layer 32.

  Then, by selectively exposing the portion of the first resist layer 32 in contact with the side surface 4a of the gate insulating film 4, a groove-like latent image 32a is formed in that portion.

  Subsequently, as shown in FIG. 17B, the first resist layer 32 is developed to remove the latent image 32a, and a groove 32b in which the side surface 4a of the gate insulating film 4 appears is formed in the resist layer 32. To do.

  The depth of the groove 32b is not particularly limited, but in this embodiment, the distance between the bottom surface of the groove 32b and the upper surface of the base insulating film 2 is about 10 μm.

  Next, as shown in FIG. 17C, a gold layer is formed as a first conductive layer 5x on the entire upper surface of the first resist layer 32 by vapor deposition, and the resist layer 32 is formed by the first conductive layer 5x. The groove 32b is completely embedded.

  Thereafter, as shown in FIG. 18A, the first resist layer 32 is lifted off to leave the first conductive layer 5x on the side surface 4b of the gate insulating film 4 as the gate overhang portion 5c. .

  Next, as shown in FIG. 18B, a second resist layer 36 having a window 36a is formed by applying a photoresist to the entire upper surface of the silicon substrate 1 and exposing and developing it. From the window 36a, the gate overhang 5c and the upper surface 4a of the gate insulating film 4 are exposed.

  Subsequently, as shown in FIG. 19A, a gold layer is formed by vapor deposition as the second conductive layer 5y in the upper surface of the second resist layer 36 and in the window 36a, and the second conductive layer 5y The window 36a is completely embedded.

  Thereafter, as shown in FIG. 19B, the body 5d of the gate 5 is formed on the overhang portion 5c and the upper surface 4a of the gate insulating film 4 by lifting off the second resist layer 36.

  Next, as shown in FIG. 20A, a titanium layer is formed as a source electrode 6 and a drain electrode 7 on the base insulating film 2 by lift-off using a resist layer (not shown). In addition, the material of each electrode 6 and 7 is not limited to titanium, Any of iron, palladium, platinum, and vanadium may be sufficient.

  Through the steps so far, the transistor TR including the graphene layer 3 as a channel is formed above the silicon substrate 1.

  Thereafter, the process proceeds to a process of growing nanowires on the gate 5 of the transistor TR.

  First, as shown in FIG. 20B, a photoresist is applied on each of the base insulating film 2 and the gate 5 and developed to form a plurality of fine windows 38 a on the gate electrode 5. The provided third resist layer 38 is formed.

  Then, a nickel layer is formed as the second catalyst layer 39 in the window 38a and on the third resist layer 38 by sputtering or vapor deposition.

  A zinc oxide layer may be formed as the second catalyst layer 39 instead of the nickel layer.

  Thereafter, as shown in FIG. 21A, the third resist layer 38 is lifted off, and the second catalyst layer 39 is left in the form of dots only on the upper surface 5a of the gate 5.

  Next, steps required until a sectional structure shown in FIG.

First, the silicon substrate 1 is placed in a growth furnace (not shown), and the silicon substrate 1 is heated to a temperature of about 800 to 1000 ° C. Thereafter, diethyl zinc ((C ₂ H ₅ ) ₂ Zn) vaporized by heating is supplied as a zinc raw material into the growth furnace, and gaseous water is supplied as an oxygen raw material.

  Instead of diethyl zinc, powdered zinc vaporized by heating may be supplied into the growth furnace as a zinc material.

  As a result, nickel in the second catalyst layer 39 becomes a catalyst, and zinc oxide nanowires grow as nanowires 8 on the second catalyst layer 39.

  The length of the nanowire 8 can be controlled by changing the growth time. In this embodiment, the nanowire 8 is formed to a length of about 100 μm to 500 μm. The diameter of the nanowire 8 can be controlled by the diameter of the dot-like second catalyst layer 39, and the nanowire 8 is formed to a diameter of about 50 nm to 100 nm.

  The material of the nanowire 8 is not limited to zinc oxide as long as it is a piezoelectric material, and may be aluminum nitride.

  As described above, the basic structure of the pressure sensor 10 is completed.

  FIG. 15 is a perspective view after this process is completed.

  As shown in FIG. 15, the drain electrode 7 of the pressure sensor 10 is connected to each of the first wiring 21 and the second extending portion 25. The gate 5 of the pressure sensor 10 is connected to the first extending portion 24.

  According to this embodiment described above, a plurality of pressure sensors 10 can be arranged in a matrix as in the second embodiment, and a local pressure in one plane can be detected by each pressure sensor 10. it can.

  Further, as shown in FIGS. 17B to 18A, the overhang portion 5c of the gate 5 can be formed by lifting off the first conductive layer 5x. Due to the overhang portion 5c, as described in the first embodiment, the drain current flowing through the side surface 3b of the graphene layer 3 is sensitive to the gate voltage, so that the pressure detection sensitivity can be increased. Become.

  The following additional notes are disclosed for each embodiment described above.

(Supplementary note 1) a transistor having a graphene layer as a channel;
A wire having one end connected on the gate of the transistor and comprising a piezoelectric material;
A pressure sensor comprising:

  (Supplementary note 2) The pressure sensor according to supplementary note 1, wherein a plurality of the wires are provided.

  (Supplementary note 3) The pressure sensor according to supplementary note 1, wherein the wire extends in a direction perpendicular to an upper surface of the gate.

  (Supplementary note 4) The pressure sensor according to supplementary note 1, wherein the wire has a diameter of 50 nm to 100 nm and a length of 100 μm to 500 μm.

  (Additional remark 5) The said gate has an overhang part which opposes the side surface of the said graphene layer, The pressure sensor of Additional remark 1 characterized by the above-mentioned.

  (Supplementary note 6) The pressure sensor according to supplementary note 1, wherein a plurality of the transistors are arranged in a matrix in one plane.

  (Supplementary note 7) The pressure sensor according to supplementary note 1, wherein the piezoelectric material is zinc oxide or aluminum nitride.

(Appendix 8) Forming a transistor having a graphene layer as a channel on a substrate;
Growing a wire comprising a piezoelectric material on the gate of the transistor;
A method for manufacturing a pressure sensor, comprising:

(Supplementary Note 9) The step of growing the wire includes
Forming a dot-shaped first catalyst layer on the upper surface of the gate;
The method further includes the step of growing the wire on the catalyst layer by supplying a raw material of piezoelectric material onto the first catalyst layer while heating the substrate. Manufacturing method of pressure sensor.

(Supplementary Note 10) The step of forming the transistor includes
Forming a second catalyst layer on the substrate;
Growing the graphene layer on side and top surfaces of the second catalyst layer;
Forming a gate insulating film on a side surface and an upper surface of the graphene layer;
Forming the gate on a side surface and an upper surface of the gate insulating film;
The method for manufacturing a pressure sensor according to appendix 7, wherein:

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Base insulating film, 3 ... Graphene layer, 3a ... Upper surface, 3b ... Side surface, 4 ... Gate insulating film, 4a ... Upper surface, 4b ... Side surface, 5 ... Gate, 5a ... Upper surface, 5c ... Overhang Part, 5d ... main body, 5x ... first conductive layer, 5y ... second conductive layer, 6 ... source electrode, 7 ... drain electrode, 8 ... nanowire, 10 ... pressure sensor, 13 ... first catalyst layer, 21 ˜23... First to third wirings 24, 25, first and second extending portions, 30, interlayer insulating film, 32, first resist layer, 32 a, latent image, 32 b, groove, 35,. Circuit board 35a ... sensor formation region 36 ... second resist layer 36a ... window 38 ... third resist layer 38a ... window 39 ... second catalyst layer 101 ... amplifier circuit 102 ... waveform shaping Circuit 103 ... Noise removal filter 104 ... A / D conversion circuit 105 ...示器.

Claims (7)

A transistor with a graphene layer as a channel;
A wire having one end connected on the gate of the transistor and comprising a piezoelectric material;
I have a,
The transistor is
A catalyst layer formed on the substrate;
The graphene layer formed on the side and top surfaces of the catalyst layer;
A gate insulating film formed on a side surface and an upper surface of a part of the graphene layer;
Wherein formed on the gate insulating the side of the membrane and the upper surface, the pressure sensor, characterized that you have a said gate having an overhang portion which faces a side surface of the graphene layer. 2. The pressure sensor according to claim 1, wherein the overhang portion of the gate is formed on a side surface of the gate insulating film in the channel width direction. The pressure sensor according to claim 1 , wherein the wire extends in a direction perpendicular to an upper surface of the gate. The pressure sensor according to claim 1 , wherein the wire has a diameter of 50 nm to 100 nm and a length of 100 μm to 500 μm. The pressure sensor according to any one of claims 1 to 4, wherein the piezoelectric material is zinc oxide or aluminum nitride. Forming a transistor with a graphene layer as a channel on a substrate;
Growing a wire comprising a piezoelectric material on the gate of the transistor;
I have a,
The step of forming the transistor comprises:
Forming a catalyst layer on the substrate;
Forming the graphene layer on a side surface and an upper surface of the catalyst layer;
Forming a gate insulating film on a side surface and an upper surface of the graphene layer;
On the on side and on the upper surface of the gate insulating film, a manufacturing method of the pressure sensor, characterized by chromatic and forming the gate with an overhang portion which faces a side surface of the graphene layer. The method for manufacturing a pressure sensor according to claim 6, wherein in the step of forming the gate, an overhang portion of the gate is formed on a side surface in a channel width direction of the gate insulating film.

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