CN105036059B - Processing method of capacitor type MEMS sensor and sensor structure - Google Patents
Processing method of capacitor type MEMS sensor and sensor structure Download PDFInfo
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Abstract
The invention provides a processing method of a capacitor type MEMS sensor and the capacitor type MEMS sensor. The method adopts a SON (silicon-on-nothing) technology to perform single-faced processing to obtain two layers of silicon films to be used as two electrodes of a capacitor, and measures pressure by utilizing capacitance change brought by shape change after the lower silicon film is pressed. The processing method can be implemented with an IC production line and does not need extra equipment or non-CMOS production line technology, such as anodic bonding. The processing method of the invention facilitates the control of the consistence of the performance of sensors on a whole wafer.
Description
Technical field
The present invention relates to semiconductor equipment processing technique field, more particularly, to a kind of processing side of condenser type mems sensor
Method and sensor construction.
Background technology
Produce condenser type mems sensor in prior art and generally adopt anode linkage technique, such as american documentation literature
Us5200363 proposes a kind of electronic component with least one silicon, and this patent is based on silica glass bonding techniques, i.e. sun
Pole is bonded.Silicon chip and glass are bonded together by silica glass bonding techniques.One cavity is etched on glass, by silicon
After film upper surface applies pressure deformation, the detection pressure drag changing value that causes of stress is detecting pressure size.
Although technique relative maturity is simple, can affect due to the problems such as thermal coefficient of expansion gap is big between si-glass
Device performance, leads to sensor temperature drift larger.And anode linkage technique is not cmos standard technology, and glass is due to containing
Conductive ion typically cannot flow on cmos production line, so technique needs outsourcing to lead to difficult quality to monitor, and invest
Relevant device can increase fixed assets investment again.
And in other modes of production, be all to define piezoresistive detection structure, such as Chinese patent literature cn
102285633 a disclose for a kind of manufacture method of composite integrated sensor structure, the silicon of this patent utilization<111>crystal orientation
Piece, using the method for wet etching, etches cavity, regrowth silicon epitaxy is to fill up etched hole, and forms silicon thin film structure.So
Do piezo-resistive arrangement afterwards on a cantilever beam, detect pressure size by detecting the pressure drag changing value that stress causes.
With respect to piezoresistive detection, the signal noise of capacitance detecting is low, and signal to noise ratio is high, and pressure resistance type device, due to intrinsic heat
Noise is very greatly it is difficult to accomplish the sensor component of high s/n ratio.Secondly, capacitive detection scheme temperature influence is less, and due to
Temperature is larger on pressure drag impact, and output result varies with temperature very greatly, increased difficulty and the cost that follow-up chip temperature compensates.
Content of the invention
It is an object of the present invention to: a kind of processing method of the condenser type mems sensor of low cost is provided.
Further object is that: provide a kind of processing method of condenser type mems sensor, its product is same
In wafer, the consistency of performance of sensor is high.
Another object of the present invention is: provides a kind of condenser type mems sensor, capacitance type structure signal to noise ratio is high, subtracts
Few temperature improves device precision to component influences.
For reaching above-mentioned purpose, the present invention employs the following technical solutions:
On the one hand, provide a kind of processing method of condenser type mems sensor it is characterised in that comprising the following steps:
Step s1, offer silicon wafer substrate, carry out pattern processing in described silicon wafer substrate；
Step s2, adopt dry etching shape from the flat, etching deep trouth or deep hole in described silicon wafer substrate；
Step s3, described silicon wafer substrate is made annealing treatment under high temperature anaerobic environment, make silicon wafer substrate surface
Silicon atom migrates, and forms the first hanging silicon fiml, the second hanging silicon fiml and is located at the first hanging silicon fiml and the second hanging silicon
The first cavity between film, the second cavity being located between the second hanging silicon fiml and described silicon wafer substrate；
Step s4, in described silicon wafer substrate photomask surface figure, and pass through dry etching according to the shape of litho pattern
First hanging silicon fiml is cut through, makes the former first hanging silicon fiml form free standing structure film structure, and ensure that this free standing structure film structure is passed through
Attachment structure is connected with described silicon wafer substrate；
Step s5, make electric isolution structure using semiconductor machining mode so that free standing structure film and described silicon wafer substrate
Junction electrically insulates completely:
Specifically, thermal oxidation is carried out to described silicon wafer substrate, so that the free standing structure film being exposed under external environment condition is tied
Structure surface forms the electric isolution structure of electric insulation, and free standing structure film is completely oxidized with described silicon wafer substrate junction；
Step s6, deposit sealing semiconductor material, and cover whole silicon wafer substrate surface formation sealant, make described close
Etched open structure before the sealing of sealing material；
Specifically, carry out first time growing epitaxial silicon technique, in described silicon wafer substrate superficial growth sealant, make sealing
The etched open structure before covering whole wafer upper surface and sealing of layer material；
Step s7, on described sealant litho pattern, remove figure in described sealing semiconductor material and electric isolution
Structure is so that the superiors' silicon fiml and section silicon wafer substrate appear；
Specifically, litho pattern on described sealant, by dry etch process remove portion of epi grow silicon and
Electric isolution structure is it is ensured that the superiors' silicon fiml and section silicon wafer substrate appear；
Step s8, deposit conducting semiconductor material, form conductive material layer on described silicon wafer substrate surface, by before
The opening of etching, realizes the electrical contact between the superiors' silicon fiml, substrate and conductive material layer；
Specifically, carry out second growing epitaxial silicon technique, in first time growing epitaxial silicon technique growth sealant,
First hanging silicon fiml and section silicon wafer Grown conductive material layer, realize the superiors' silicon fiml, substrate and conductive material
Electrical contact between layer；
Step s9, litho pattern, carve remove sealant and conductive material layer, make the described first hanging silicon fiml, Silicon Wafer with
Remaining sealant and conductive material layer realize insulation；
Step s10, outside described conductive material layer deposit semi-conductive insulating layer；
Step s11, graphically etch afterwards and appear conductive material layer；
Step s12, deposit metal electrode are simultaneously graphical；
Step s13, graphical again, the first hanging silicon fiml is cut through, forms inlet structure.
As a kind of optimal technical scheme of the processing method of described condenser type mems sensor, silicon described in step s1
Wafer substrate is using the Silicon Wafer of the Silicon Wafer, the Silicon Wafer of<110>crystal orientation or<111>crystal orientation of<100>crystal orientation.
It is pointed out that the crystal orientation for Silicon Wafer does not excessively require in the technical program, any crystal orientation knot
The Silicon Wafer of structure all can be used as the substrate silicon materials adopting in this programme.
As a kind of optimal technical scheme of the processing method of described condenser type mems sensor, scheme described in step s2
Sample shape can be one of rectangle, square, hexagon or circle or arbitrarily several combinations.
As a kind of optimal technical scheme of the processing method of described condenser type mems sensor, high described in step s3
Warm oxygen-free environment is: at 1000 DEG C～1300 DEG C, in vacuum environment or ar gas environment or hydrogen environment, anneal duration is temperature
5min～60min.
As a kind of optimal technical scheme of the processing method of described condenser type mems sensor, connect described in step s4
Access node structure is less than or equal to 4 microns of elongated strip shaped connector for cross-sectional width.
As a kind of optimal technical scheme of the processing method of described condenser type mems sensor, form sediment described in step s6
Long-pending sealing semiconductor material technology is chemical vapor deposition.
As a kind of optimal technical scheme of the processing method of described condenser type mems sensor, described in step s14
Dry etching is deep reaction ion etching technology (drie), and described inlet structure is deep trouth or deep hole.
On the other hand, provide a kind of condenser type mems sensor it is characterised in that adopting condenser type mems as above
The processing method of sensor processes.
The invention has the benefit that whole set process is based on cmos processing line and silicon chip, it is to avoid the non-cmos such as anode linkage
Technique and extra fixed assets investment it is ensured that the concordance of processing and manufacturing, the number of plies of silicon fiml, silicon film thickness and every layer of cavity
Depth can control within the specific limits and adjust, and can adjust transducer range by adjusting silicon film thickness.
Brief description
Below according to drawings and Examples, the present invention is described in further detail.
Fig. 1 is condenser type mems sensor processing method flow chart described in embodiment.
Fig. 2 is the Silicon Wafer top view after processing pattern described in embodiment.
Fig. 3 is the Silicon Wafer schematic cross-section after processing pattern described in embodiment.
Fig. 4 is structural representation after Silicon Wafer annealing.
Fig. 5 forms free standing structure film structural representation for after etching in silicon wafer surface.
Fig. 6 is Fig. 5 top view.
Fig. 7 is to make Silicon Wafer sectional view after electric isolution structure using semiconductor machining mode.
Fig. 8 is Silicon Wafer sectional view after deposit sealant.
Fig. 9 is that etching removes sectional view after part sealant and electric isolution structure.
Figure 10 is Silicon Wafer sectional view after layer of conductive material.
Figure 11 is Silicon Wafer sectional view after etching sealant and conductive material layer.
Figure 12 is to carry out the deposited and patterned rear sectional view of semi-conductive insulating layer.
Figure 13 is deposit metal electrode graphical rear structural representation.
Figure 14 is Silicon Wafer sectional view after processing gas inlet mouth.
In figure:
100th, silicon wafer substrate；101st, deep hole；102nd, the first hanging silicon fiml；103rd, the second hanging silicon fiml；104th, first is empty
Chamber；105th, the second cavity；106th, electrically insulate structure；107th, sealant；108th, conductive material layer；109th, semi-conductive insulating layer；
110th, electrode；111st, air inlet.
Specific embodiment
Further illustrate technical scheme below in conjunction with the accompanying drawings and by specific embodiment.
As shown in Fig. 1～14, in the present embodiment, a kind of processing side of condenser type mems sensor of the present invention
Method, comprises the following steps:
Step s1, offer silicon wafer substrate 100, carry out pattern processing in described silicon wafer substrate 100；
Step s2, from the flat shape etch deep hole 101 in described silicon wafer substrate 100；
Step s3, described silicon wafer substrate 100 is made annealing treatment under high temperature anaerobic environment, make Silicon Wafer 1 substrate
Surface silicon atoms migrate, and form the first hanging silicon fiml 102, the second hanging silicon fiml 103 and are located at the first hanging silicon fiml 102
The first cavity 104 and the second hanging silicon fiml 103 between, it is located between the second hanging silicon fiml 103 and described silicon wafer substrate 100
The second cavity 105；
Step s4, in described silicon wafer substrate 100 photomask surface figure, and according to litho pattern shape etching by first
Hanging silicon fiml 102 cuts through, and makes the former first hanging silicon fiml 102 form free standing structure film structure, and ensures that this free standing structure film structure is passed through
Attachment structure is connected with described silicon wafer substrate 100；
Step s5, make electric isolution structure using semiconductor machining mode so that free standing structure film and described silicon wafer substrate
100 junctions electrically insulate completely:
Specifically, thermal oxidation is carried out to described silicon wafer substrate 100, make the free standing structure film being exposed under external environment condition
Body structure surface forms the electric isolution structure 106 of electric insulation, and free standing structure film and described silicon wafer substrate 100 junction quilt completely
Oxidation, forms electric insulation；
Step s6, deposit sealing conducting semiconductor material, and cover whole silicon wafer substrate 100 surface formation sealant
107, etched open structure before making described sealant 107 sealing；
Specifically, carry out first time growing epitaxial silicon technique, in described silicon wafer substrate 100 superficial growth sealant 107,
Make the etched open structure before covering whole wafer upper surface and sealing of sealant 107；
Step s7, on described sealant 107 litho pattern, remove the described sealant 107 in figure and electric isolution knot
Structure 106 is so that the superiors' silicon fiml and section silicon wafer substrate 100 appear；
Specifically, litho pattern on described sealant 107, by dry etch process remove part sealant 107 with
And electric isolution structure is it is ensured that the superiors' silicon fiml and section silicon wafer substrate 100 appear；
Step s8, deposit conducting semiconductor material, form conductive material layer 108 on described silicon wafer substrate 100 surface, lead to
Before crossing, the opening of etching, realizes the electrical contact between the superiors' silicon fiml, substrate and conductive material layer 108；
Specifically, carry out second growing epitaxial silicon technique, the sealant of growth in first time growing epitaxial silicon technique
107th, grow conductive material layer 108 on the first hanging silicon fiml 102 and section silicon wafer substrate 100, realize the superiors' silicon fiml, lining
Electrical contact between bottom and conductive material layer 108；
Step s9, litho pattern, carve remove sealant 107 and conductive material layer 108, make the described first hanging silicon fiml 102,
Silicon wafer substrate 100 realizes insulation with remaining sealant 107 and conductive material layer 108；
Step s10, outside described conductive material layer 108 deposit semi-conductive insulating layer 109；
Step s11, graphically etch afterwards and appear conductive material layer by layer 108；
Step s12, deposit metal electrode are simultaneously graphical；
Step s13, graphical again, the first hanging silicon fiml 102 is cut through, forms air inlet 112 structure.
Further, silicon wafer substrate 100 described in step s1 adopts the Silicon Wafer of<100>crystal orientation, the silicon of<110>crystal orientation
Wafer or the Silicon Wafer of<111>crystal orientation.
Shape from the flat described in step s2 etch in described silicon wafer substrate 100 can also for etching deep trouth or
Other structures.
It is pointed out that the crystal orientation for Silicon Wafer does not excessively require in the technical program, any crystal orientation knot
The Silicon Wafer of structure all can be used as the silicon wafer substrate material adopting in this programme.
Further, pattern shape described in step s2 is circular.
This pattern shape can also be one of rectangle, square, hexagon or arbitrarily several in other embodiments
Combination.
Further, high temperature anaerobic environment described in step s3 is: temperature is 1050 DEG C, anneals under ar gas environment
10min.
Further, the elongated strip shaped connector that attachment structure described in step s4 is 2 microns for cross-sectional width.
Further, growing epitaxial silicon technique described in step s6 is chemical vapor deposition.
Further, dry etching described in step s14 is deep reaction ion etching technology (drie), described air inlet
111 structures are deep trouth or deep hole.
Specifically, use<100>crystal orientation Silicon Wafer 100 substrate, make a series of little circular patterns first by lithography.A diameter of
D, spacing is s.
Carve deep hole 101 using deep reaction ion etching technology, depth h,.
Anneal under 1050 DEG C of ar gas environments 10min, due to the physical phenomenon of high temperature lower surface silicon atom migration, defines
First hanging silicon fiml 102, the second hanging silicon fiml 103 two-layer silicon fiml and the first cavity 104, the second cavity 105 two-layer cavity.Now
The number of plies of silicon fiml that the thickness h of dry etching substrate silicon, pattern pitch s and diameter d are formed after just determining, silicon fiml are thick
Degree and the depth of every layer of cavity.
In the present embodiment the thickness h of etched substrate silicon be 8 μm, pattern pitch s be 0.5 μm, diameter d be 0.9 μm, silicon film
Number is two-layer, and silicon film thickness is 1 μm, the depth of every layer of cavity is 1 μm.
First hanging silicon fiml 102 is cut through into required figure using dry etching by crystal column surface litho pattern.First is hanging
Form a free standing structure film structure after silicon fiml 102 is etched.The main body attachment structure of free standing structure film structure and silicon wafer substrate is adopted
The elongated stripe shape being 2 microns with cross-sectional width, to guarantee the complete oxidation of this part in next step process, forms electric isolution material
Material.
After the completion of etching, remove mask lithography glue, whole wafer is carried out thermal oxidation, due to the whole first hanging silicon
Film 102 and the second hanging silicon fiml 103 upper surface all expose in the environment it is possible on the first hanging silicon fiml 102 surface and
The upper surface of two hanging silicon fimls 103 forms a layer insulating as electric isolution structure 106, because attachment structure is elongated strip shaped
Shape, so being easy to be fully oxidized, to realize the electric insulation of the first hanging silicon fiml 102 and the other position of silicon wafer substrate 100.
Carry out first time growing epitaxial silicon technique in whole silicon wafer substrate 100 upper surface on this basis, in electric isolution
Sealant 107 is grown on structure 106.After this step epitaxy technique can block back thermal oxide, crystal column surface may remaining
Pinhole arrangement, preventing from subsequently cleaning has liquid to flow into cavity, impact structure and subsequent technique in lithography step.
After epitaxial growth terminates, litho pattern, remove sealant 107 and electric isolution structure 106 using dry etch process.
Second growing epitaxial silicon technique, in sealant 107, the first hanging silicon fiml 102 and section silicon wafer substrate 100
Upper growth conductive material layer 108, realizes the electrical contact of levels silicon
Litho pattern, using dry etching, conductive material layer 108 is etched.Specifically, carry out semi-conductive insulating layer 109
Growth is so that electrodeposition afterwards.Grow semi-conductive insulating layer 109 using chemical vapor deposition, graphical after, carry out dry method
Etching is it is ensured that silicon wafer substrate 100 upper surface of corresponding part exposes.
Deposit metal electrode, and patterned electrodes, then anneal, realize electrode 110 and connect for 102 ohm with the first hanging silicon fiml
Touch, electrode 110 and section silicon wafer 100 substrate realize Ohmic contact.
Finally, the first hanging silicon fiml 102 is cut through by photolithography patterning again using dry etching, forms a deep hole and makees
Structure for air inlet 111.
A kind of condenser type mems sensor, using condenser type mems sensor as above processing method process and
Become.
In the description herein it is to be understood that term " on ", D score, etc. orientation or position relationship be based on accompanying drawing
Shown orientation or position relationship, be for only for ease of description and simplify operation, rather than instruction or hint indication device or
Element must have specific orientation, with specific azimuth configuration and operation, be therefore not considered as limiting the invention.This
Outward, term " first ", " second ", is used only for being distinguish between in description, not special implication.
It is to be understood that, above-mentioned specific embodiment is only presently preferred embodiments of the present invention and institute's application technology is former
Reason, in technical scope disclosed in this invention, change that any those familiar with the art is readily apparent that or
Replace, all should cover within the scope of the present invention.
Claims (8)
1. a kind of processing method of condenser type mems sensor is it is characterised in that comprise the following steps:
Step s1, offer silicon wafer substrate, carry out pattern processing in described silicon wafer substrate；
Step s2, adopt dry etching shape from the flat, etching deep trouth or deep hole in described silicon wafer substrate；
Step s3, described silicon wafer substrate is made annealing treatment under high temperature anaerobic environment, make silicon wafer substrate surface silicon former
Son migrates, formed the first hanging silicon fiml, the second hanging silicon fiml and positioned at the first hanging silicon fiml and the second hanging silicon fiml it
Between the first cavity, be located at the second cavity between the second hanging silicon fiml and described silicon wafer substrate；
Step s4, in described silicon wafer substrate photomask surface figure, and pass through dry etching by the according to the shape of litho pattern
One hanging silicon fiml cuts through, and makes the former first hanging silicon fiml form free standing structure film structure, and ensures that this free standing structure film structure is passed through to connect
Structure is connected with described silicon wafer substrate；
Step s5, using semiconductor machining mode make electric isolution structure so that free standing structure film is connected with described silicon wafer substrate
Place electrically insulates completely:
Step s6, deposit sealing semiconductor material, and cover whole silicon wafer substrate surface formation sealant, make described sealant
Etched open structure before sealing；
Step s7, on described sealant litho pattern, remove figure in described sealing semiconductor material and electric isolution structure,
The superiors' silicon fiml and section silicon wafer substrate are appeared；
Step s8, deposit conducting semiconductor material, form conductive material layer on described silicon wafer substrate surface, by etching before
Opening, realize the electrical contact between the superiors' silicon fiml, substrate and conductive material layer；
Step s9, litho pattern, carve remove sealant and conductive material layer, make the described first hanging silicon fiml, Silicon Wafer and remaining
Sealant and conductive material layer realize insulation；
Step s10, outside described conductive material layer deposit semi-conductive insulating layer；
Step s11, graphically etch afterwards and appear conductive material layer；
Step s12, deposit metal electrode are simultaneously graphical；
Step s13, graphical again, the first hanging silicon fiml is cut through, forms inlet structure.
2. the processing method of condenser type mems sensor according to claim 1 is it is characterised in that silicon described in step s1
Wafer substrate is using the Silicon Wafer of the Silicon Wafer, the Silicon Wafer of<110>crystal orientation or<111>crystal orientation of<100>crystal orientation.
3. the processing method of condenser type mems sensor according to claim 2 is it is characterised in that scheme described in step s2
Sample shape can be one of rectangle, square, hexagon or circle or arbitrarily several combinations.
4. the processing method of condenser type mems sensor according to claim 3 is it is characterised in that high described in step s3
Warm oxygen-free environment is: at 1000 DEG C～1300 DEG C, in vacuum environment or ar gas environment or hydrogen environment, anneal duration is temperature
5min～60min.
5. the processing method of condenser type mems sensor according to claim 4 is it is characterised in that connect described in step s4
Access node structure is less than or equal to 4 microns of elongated strip shaped connector for cross-sectional width.
6. the processing method of condenser type mems sensor according to claim 5 is it is characterised in that form sediment described in step s6
Long-pending sealing semiconductor material technology is chemical vapor deposition.
7. the processing method of condenser type mems sensor according to claim 6 is it is characterised in that described in step s14
Dry etching is deep reaction ion etching technology (drie), and described inlet structure is deep trouth or deep hole.
8. a kind of condenser type mems sensor is it is characterised in that adopt the condenser type any one of claim 1 to 7
The processing method of mems sensor processes.
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| CN105890827B (en) * | 2016-01-18 | 2019-05-21 | 广东合微集成电路技术有限公司 | A kind of capacitance pressure transducer, and its manufacturing method |
| CN105883713B (en) * | 2016-01-18 | 2017-08-29 | 上海芯赫科技有限公司 | A kind of condenser type compound sensor and its manufacture method |
| CN105905866B (en) * | 2016-05-12 | 2017-10-31 | 广东合微集成电路技术有限公司 | A kind of compound sensor and manufacture method |
| CN106006542B (en) * | 2016-06-06 | 2018-10-12 | 杭州电子科技大学 | A kind of research method of control silicon substrate microstructure portion cavity forming position |
| CN109205549A (en) * | 2017-07-03 | 2019-01-15 | 无锡华润上华科技有限公司 | The preparation method of double cavity structures |
| US10266389B2 (en) * | 2017-07-31 | 2019-04-23 | Infineon Technologies Dresden Gmbh | Forming an offset in an interdigitated capacitor of a microelectromechanical systems (MEMS) device |
| CN109384195B (en) * | 2017-08-14 | 2020-08-14 | 无锡华润上华科技有限公司 | Cavity forming method based on deep groove corrosion |
| CN109399553A (en) * | 2017-08-15 | 2019-03-01 | 无锡华润上华科技有限公司 | A kind of preparation method of semiconductor devices |
| CN109399555A (en) * | 2017-08-18 | 2019-03-01 | 无锡华润上华科技有限公司 | A kind of preparation method of semiconductor devices |
| CN110862063A (en) * | 2018-08-28 | 2020-03-06 | 无锡华润上华科技有限公司 | Temperature sensor preparation method and temperature sensor |
| CN110963458B (en) * | 2018-09-30 | 2023-09-15 | 上海新微技术研发中心有限公司 | Method for forming microstructure in substrate and microstructure |
| CN109809355A (en) * | 2019-03-06 | 2019-05-28 | 苏州敏芯微电子技术股份有限公司 | Pressure sensor and its manufacturing method |
| CN112701079B (en) * | 2020-12-29 | 2023-02-21 | 上海烨映微电子科技股份有限公司 | SON structure and preparation method thereof |
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