JP5423381B2 - Semiconductor integrated circuit device and power amplifier - Google Patents

Description

  The present invention relates to a stable operation technique in an amplifier circuit, and more particularly to a technique effective in preventing thermal runaway in an amplifier circuit that performs high-frequency power amplification.

  In recent years, high-frequency power amplification modules used for mobile phones and the like have a demand for higher efficiency, smaller size, and lower cost, and have a feature of operating with high efficiency to meet the demand for higher efficiency. A GaAs HBT (Heterojunction Bipolar Transistor) is widely used.

  The power stage HBT element used in this type of high-frequency power amplification module is composed of, for example, two or more cells, each of which has a configuration in which an HBT, a base ballast resistor, and a capacitance element are provided. What is known.

  The HBT of each cell is connected in parallel, and one base ballast resistor connection and one capacitance element connection are connected to the base of the HBT, respectively. The other connection portion is connected to a bias transistor of an emitter follower (see Patent Document 1 and Patent Document 2).

  The power stage HBT becomes unstable (thermal instability) when the output power is reduced above a certain collector voltage (operating voltage). In extreme cases, the HBT itself may be destroyed. There is.

  This destruction is likely to occur under extreme conditions where the antenna output load is large and deviates from a design value (for example, about 50Ω). For this reason, the above-described base ballast resistor is added to the base of the HBT.

  In general, when 1 W class power is output in a high-power HBT module, a large current flows through the HBT in the cell, and the junction temperature rises. Due to the thermal environment around each cell, for example, this increased temperature is high in a cell located in the central part and in the vicinity thereof, while it is low in cells arranged in the peripheral part, and the temperature between the cells is high. A difference is born. Further, the junction temperature increases as the current flowing through the cell increases, and the temperature difference between the cells also increases.

  However, by adding a base ballast resistor, the base ballast resistor is placed at the base of each cell so that the temperature of the cell is as uniform as possible without causing a non-uniform distribution of this temperature, preventing thermal runaway, HBT destruction is avoided.

  In the base ballast resistor, as the base current of the HBT increases, the voltage drop of the base ballast resistor increases. As a result, the base-emitter voltage Vbe of the HBT of each cell is suppressed, the collector current is reduced, and the junction temperature is reduced. It works as a negative feedback to suppress the rise. Thereby, temperature uniformity is realized.

US Pat. No. 5,608,353 US Pat. No. 5,629,648

  However, the present inventors have found that the configuration of the high-power HBT module as described above has the following problems.

  As described above, in order to reduce the cost, a further reduction in size of the power stage HBT occupying a large occupied area in the chip is required. In order to reduce the size, it is an effective technique to reduce the layout pitch of each HBT cell in the power stage.

  However, when the layout pitch is reduced, the junction temperature near the center of the cell row becomes higher than when the cell pitch is large, and as a result, sufficient temperature uniformity between the cells cannot be obtained, There is a problem that thermal instability increases.

  As a technique for avoiding this thermal instability, increasing the resistance value of the base ballast resistor is one of the most effective means, but in this case, the output power decreases as the base current increases due to the self-bias effect. As a result, there is a certain limit such as the deterioration of linearity.

  Further, when the base ballast resistance is increased, the layout area occupied by the resistance is increased, which causes problems such as an increase in chip size.

  An object of the present invention is to provide a technique capable of preventing a thermal runaway of a transistor and stabilizing the operation while reducing a layout area of an amplifier circuit that performs power amplification.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention is a semiconductor integrated circuit device including an amplifier circuit composed of a plurality of unit cells, the unit cell including a first transistor that amplifies power of an input signal, an input terminal to which the input signal is input, A capacitance element that is connected between the first transistor and attenuates a signal in an unnecessary frequency band; a second transistor that supplies bias power to a base of the first transistor; and the second transistor And a base ballast resistor connected between the first transistor and the base of the first transistor to prevent an increase in the base current of the first transistor, and each first transistor provided in the unit cell includes: The output terminal for outputting the output signal and the reference potential are connected in parallel. Thus, the amplifier circuit has a configuration in which the bias circuit is provided in each unit cell.

  In the present invention, the first transistor and the second transistor are laid out with at least either a base ballast resistor and / or a capacitance element interposed therebetween, and serve as a heat source. By laying out the second transistor away from the first transistor, the thermal runaway start current can be increased.

  Further, in the present invention, the transistor size of the second transistor is formed smaller than the transistor size of the first transistor, and the semiconductor chip area can be reduced.

  In the present invention, the second transistor is an FET such as a HEMT (High Electron Mobility Transistor) or a MESFET (Metal-Semiconductor Field Effect Transistor), or an HBT.

  Furthermore, according to the present invention, by configuring the second transistor from a multi-emitter transistor, the number of second transistors can be made smaller than the number of unit cells, and the area of the semiconductor chip can be further reduced. it can.

  Furthermore, the outline | summary of the other invention of this application is shown briefly.

  The present invention is a power amplifier including an amplifier circuit composed of a plurality of unit cells, the unit cell including a first transistor that performs power amplification of an input signal, an input terminal to which an input signal is input, and a first transistor A capacitive element connected between the first transistor, a second transistor for supplying a bias power to the base of the first transistor, and a base between the second transistor and the first transistor Each of the first transistors provided in the unit cell is connected to an output terminal that outputs an output signal, a reference potential, and a reference potential. Are connected in parallel.

  In the present invention, the first transistor and the second transistor are laid out with at least one of a base ballast resistor and / or a capacitance element interposed therebetween.

  In the present invention, the transistor size of the second transistor is smaller than the transistor size of the first transistor.

  In the present invention, the second transistor is composed of an FET or an HBT.

  Furthermore, the present invention is a power amplifier including an amplifier circuit composed of a plurality of unit cells and a plurality of multi-emitter transistors, wherein the unit cell includes a first transistor that performs power amplification of an input signal; A capacitive element connected between an input terminal to which an input signal is input and the first transistor, and a base of the first transistor connected between the second transistor and the base of the first transistor. Each having a base ballast resistor for preventing an increase in current, and the multi-emitter transistor has at least two emitters, and a first cell provided in at least two unit cells via the at least two emitters. Bias power is supplied to the base of each transistor.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  (1) Since the thermal runaway start current can be increased while reducing the layout area of the amplifier circuit, stable operation can be realized.

  (2) According to the above (1), the semiconductor chip area can be reduced while improving the reliability of the amplifier circuit, and the semiconductor integrated circuit device and power amplifier provided with the amplifier circuit can be miniaturized. .

It is a block diagram which shows an example of the high frequency power amplification module by Embodiment 1 of this invention. It is a circuit diagram which shows an example of a structure of the power stage amplifier circuit provided in the high frequency power amplifier module of FIG. It is a circuit diagram which shows the structural example of the power stage amplifier circuit which this inventor examined. It is explanatory drawing which shows an example of the electric current-voltage range which starts the thermal runaway in a power stage amplifier circuit. FIG. 3 is an explanatory diagram showing an example of a unit cell layout in the power stage amplifier circuit of FIG. 2. It is explanatory drawing which shows an example of the whole layout of the power stage amplifier circuit which combined the unit cell with 12 fingers. It is a circuit diagram which shows an example of the power stage amplifier circuit by Embodiment 2 of this invention. It is a circuit diagram which shows an example of the power stage amplifier circuit by Embodiment 3 of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a block diagram showing an example of a high-frequency power amplification module according to Embodiment 1 of the present invention, and FIG. 2 is a circuit diagram showing an example of the configuration of a power stage amplification circuit provided in the high-frequency power amplification module of FIG. 3 is a circuit diagram showing a configuration example of a power stage amplifier circuit examined by the present inventor, FIG. 4 is an explanatory diagram showing an example of a current-voltage range in which thermal runaway in the power stage amplifier circuit is started, and FIG. FIG. 6 is an explanatory diagram showing an example of a layout of unit cells in the power stage amplifier circuit of FIG. 2, and FIG. 6 is an explanatory diagram showing an example of an overall layout of a power stage amplifier circuit in which unit fingers are combined with 12 fingers.

  In the first embodiment, the high-frequency power amplification module 1 is a power amplifier used for, for example, a mobile phone. As shown in FIG. 1, the high frequency power amplifier module 1 has a control circuit 2, a first stage amplifier circuit 3, a power stage amplifier circuit 4, an input stage matching circuit 5, an interstage matching circuit 6, an output stage matching circuit 7, and the like. doing.

  The control circuit 2 controls the first stage amplifier circuit 3 and the power stage amplifier circuit 4 based on the control signal Vcontrol input from the outside. The control circuit 2 is composed of, for example, a MOSFET (Metal Oxide Semiconductor Field Effect Transistor).

  The first stage amplifier circuit 3 and the power stage amplifier circuit 4 efficiently reduce power loss as much as possible by using the input stage matching circuit 5, the interstage matching circuit 6, and the output stage matching circuit 7 over two stages of the input power Pin. It is comprised so that it may amplify.

  Thereafter, the output power Pout is output from the high-frequency power amplification module 1. Here, the transistors constituting the first stage amplifier circuit 3 and the power stage amplifier circuit 4 are configured to use, for example, an HBT.

  FIG. 2 is a circuit diagram showing an example of the configuration of the power stage amplifier circuit 4.

The power stage amplifier circuit 4 is composed of a plurality of unit cells 8 ₁ to 8 _N as shown in the figure. The unit cell 8 ₁ includes an emitter-follower transistor Q 2 ₁ that functions as a bias circuit, a first transistor Q 3 ₁ , a capacitive element C ₁ , and a ballast resistor (base ballast resistor) Rb _1. Has been.

Similarly, the unit cell 8 ₂ includes a transistor Q2 ₂ , a transistor Q3 ₂ , a capacitance element C ₂ , and a resistor Rb ₂ .

Similarly, the other unit cells 8 ₃ to 8 _N are configured by transistors Q2 _{3 to} Q2 _N , transistors Q3 _{3 to} Q3 _N , capacitance elements C _{3 to} C _N , and resistors Rb _{3 to} Rb _N , respectively. ing.

In the unit cell 8 ₁ , the bias voltage Vbias is connected to the collector of the transistor Q2 ₁ as the second transistor, and one connection portion of the resistor Rb ₁ is connected to the emitter of the transistor Q2 ₁ . .

_One connection portion of the capacitive element C ₁ and the base of the transistor Q3 ₁ are connected to the other connection portion of the resistor Rb ₁ . In addition, the other connection portion of the capacitive element C _1, is connected to an input terminal RFIN the RF signal for amplification is input.

The collector of the transistor Q3 _1, along with the amplified RF signal is connected to the output terminal RFOUT output is connected to the output terminal RFOUT from the power supply voltage VCC is supplied, of the transistor Q3 ₁ A reference potential VSS is connected to the emitter.

Further, the base of the transistor Q2 ₁ is connected so that the control power supply voltage Vreg is input. In the other unit cells 8 ₂ to 8 _N , the connection configuration is the same as that of the unit cell 8 _1, and thus the description is omitted.

As described above, the unit cells 8 ₁ to 8 _N have not only the base ballast resistors Rb _{1 to} Rb _N but also transistors Q2 _{1 to} Q2 _{N serving} as bias circuits.

  Here, a configuration example of a general power stage amplifier circuit 50 examined by the present inventor will be described with reference to FIG.

In this case, the power stage amplifier circuit 50 includes an emitter follower transistor Q50 functioning as a bias circuit and a plurality of unit cells 50 ₁ to 50 _N as shown in the figure.

The unit cells 50 ₁ to 50 _N are each composed of a transistor Q51, a capacitance element C51, and a resistor R51 serving as a ballast resistor. In the unit cell 50 ₁ , the emitter of the transistor Q50 is connected to one connection portion of the resistor R51.

  In addition, one connection portion of the capacitive element C51 is connected to an input terminal RFIN to which an amplification RF signal is input. The base of the transistor Q51 is connected to the other connection portion of the capacitive element C51 and the other connection portion of the resistor R51.

  The collector of the transistor Q51 is connected to the output terminal RFOUT from which the amplified RF signal is output, and the reference potential VSS is connected to the emitter of the transistor Q51.

A bias voltage Vbias is connected to the collector of the transistor Q50, and the other connection portion of the resistor R51 of each of the unit cells 50 ₁ to 50 _N is commonly connected to the emitter of the transistor Q50. The control power supply voltage Vreg is connected to the base of the transistor Q50. The other unit cells 50 ₂ to 50 _N have the same connection configuration.

In the configuration in which the unit cells 50 ₁ to 50 _N are connected to the bias circuit (transistor Q50) of one emitter follower shown in FIG. 3, the current Icc = Icrit at which thermal runaway starts for the given power supply voltage Vcc is Is given by

On the other hand, by configuring the power stage amplifier circuit 4 shown in FIG. 2 of the present invention and further laying out the transistors Q2 _{1 to} Q2 _N and the transistors Q3 _{1 to} Q3 _N as far as possible as will be described later, By making the junction temperature of the transistor Q2k (k = 1 to N) as close as possible to the environmental temperature T _A , the thermal runaway start current Icrit can be increased approximately twice.

  Here, if the transistor Q2k (k = 1 to N) is laid out close to the transistor Q3k (k = 1 to N) and linked to the junction temperature of the transistor Q3k, this double effect is reduced to 1. It will approach. However, even in this case, if the configuration of FIG. 2 is used, the thermal runaway start current Icrit is always larger than that of FIG.

  Qualitatively, it is explained as follows.

  In the case of the circuit configuration of FIG. 3, the potential VA of the node A shown in FIG. 3 is substantially constant unless the control power supply voltage Vreg is changed. Therefore, the potential difference between the potential VA and the emitter voltage Ve51 of FIG. 3 needs to be supported by the voltage drop in the base-emitter voltage Vbe51 of the transistor Q51 and the resistor R51.

  The thermal runaway causes the transistor Q51 to generate heat and increase the junction temperature. Therefore, the base-emitter voltage Vbe51 decreases, and as a result, the collector current Ic1 of the transistor Q51 increases.

  As a result, positive feedback that accelerates the increase in the junction temperature is applied, and the base-emitter voltage Vbe51 becomes smaller and the collector current Ic1 further increases. The base ballast resistor (resistor R51) of the power stage amplifier circuit 50 has a function of suppressing the start of positive feedback accompanying a decrease in the base-emitter voltage Vbe51 due to an increase in the voltage drop amount of the resistor 51 due to an increase in the base current Ib1. However, when a certain thermal runaway starting current Icrit flows, the potential difference between the potential VA and the emitter voltage Ve51 cannot be supported, and thermal runaway starts.

However, in the circuit configuration of the power stage amplifier circuit 4 of the present invention shown in FIG. 2, the potential difference between the control power supply voltage Vreg and the emitter voltage Ve31 of the transistor shown in FIG. 2 is the base-emitter voltage Vbe31 and the resistance Rb _1. in addition to the voltage drop, the transistor Q2 ₁ base - was supported by three emitter voltage Veb21.

  Accordingly, as the base current Ib1 increases, the base-emitter voltage Vbe21 also increases, and the start of thermal runaway can be delayed. That is, the thermal runaway start current Icrit can be increased.

  Accordingly, in the circuit configuration of the power stage amplifier circuit 4 of FIG. 2, as shown in FIG. 4, the voltage that can ensure the stability of the operation of the power stage amplifier circuit 4 as compared with the power stage amplifier circuit 50 of FIG. , And the range of current can be expanded.

  FIG. 5 is an explanatory diagram showing an example of the layout of an arbitrary unit cell in the power stage amplifier circuit 4.

  A transistor Q2k is laid out on the left side of FIG. 5, and a capacitance element Ck is laid out on the right side of the transistor Q2k. A resistor Rbk is laid out on the right side of the capacitance element Ck. A transistor Q3k is laid out on the right side of the resistor Rbk.

Here, transistor Q2k is sufficiently away from the transistor Q3k as a heat source, the temperature is close to the ambient temperature T _A, more binding to the junction temperature of the transistor Q3k is smaller is more preferable.

  Therefore, as shown in the layout of FIG. 5, by disposing the electrostatic capacitance element Ck and the resistor Rbk between the transistor Q2k and the transistor Q3k, respectively, a layout that can increase the distance between the transistor Q2k and the transistor Q3k. It has become.

  FIG. 5 shows a layout example of the k-th unit cell, and the power stage amplifier circuit 4 has a configuration in which N unit cells of FIG. 5 are arranged.

FIG. 6 is an explanatory diagram showing an example of the overall layout of the power stage amplifier circuit 4 in which unit cells 8 ₁ to 8 ₁₂ having 12 fingers are combined.

In the center of FIG. 6, via holes V1 and V2 serving as a reference potential VSS are laid out, and on the left side of the via holes V1 and V2, six unit cells 8 ₁ to 8 ₆ are laid out from above to below. ing.

In addition, on the right side of the via holes V1 and V2, six unit cells 8 ₇ to 8 ₁₂ are laid out from above to below. Thus, the unit cells 8 ₁ to 8 ₆ and the unit cells 8 ₇ to 8 ₁₂ are laid out so as to be line-symmetric with respect to the via holes V1 and V2.

Transistor Q3 ₇ to Q3 ₁₂ provided in the unit cell 8 _{1-8 6} transistors Q3 ₁ to Q3 ₆ provided and the unit cell 8 _{7-8 12,} is such that the near reference potential VSS via hole V1, It is laid out in the vicinity of V2.

Further, the transistors Q3 ₁ to Q3 ₆ and the transistor Q2 ₁ ~Q2 ₆ of the unit cell 8 _{1-8 6,} as described with reference to FIG. 5, the capacitance element C ₁ -C _6, and the resistor Rb ₁ ~Rb ₆ and a are laid over each transistor Q2 ₁ ~Q2 ₆ is a is laid to place the distance from the transistors Q3 ₁ to Q3 ₆ as a heat source.

Layout Similarly, transistor Q3 ₇ to Q3 ₁₂ and transistor Q2 ₇ ~Q2 ₁₂ of the unit cell 8 _{7-8 12} also across the capacitance element C ₇ -C _12, and the resistor Rb ₇ ~Rb ₁₂ between each Has been.

The collectors of the transistors Q3 _{1 to} Q3 ₁₂ are connected to, for example, the second wiring layer, and are commonly connected to the wiring H1 laid out below these transistors Q3 _{1 to} Q3 ₁₂ and connected to the output terminal RFOUT via the wiring H1. It is connected.

The emitters of the transistors Q3 _{1 to} Q3 ₁₂ are formed, for example, in the first wiring layer and connected to the via holes V1 and V2 via the wiring H2. The capacitive elements C _{1 to} C ₁₂ of the unit cells 8 ₁ to 8 ₁₂ are connected to, for example, the second wiring layer and commonly connected to the wiring H 3 laid out above the capacitive elements C _{1 to} C _12. And connected to the input terminal RFIN via the wiring H3.

Further, the bases of the transistors Q2 _{1 to} Q2 ₁₂ are connected to, for example, the first wiring layer and commonly connected to the wiring H4 laid out on the outer periphery of the transistors Q2 _{1 to} Q2 ₁₂ , and the control power supply is connected via the wiring H4. A voltage Vreg is supplied.

  The transistor Q2k is preferably laid out with a smaller emitter size than the transistor Q3k serving as the power stage HBT in order to reduce the area of the semiconductor chip (for example, the transistor Q3k has a transistor size of about 3 μm × 40 μm). The emitter size of Q2k is about 2μm × 2μm).

  As a result, according to the first embodiment, the current value for starting thermal runaway in the power stage amplifier circuit can be increased, so that the reliability in the high frequency power amplifier module can be improved.

Further, when the current amplification factor β is increased, the current amplification factor β is increased without increasing the resistances Rb ₁ to Rb _N when ensuring the same region of the thermal runaway start current Icrit that is not thermal runaway. Is possible.

(Embodiment 2)
FIG. 7 is a circuit diagram showing an example of a power stage amplifier circuit according to Embodiment 2 of the present invention.

  In the second embodiment, a configuration when a multi-emitter HBT is used for the power stage amplifier circuit 4 will be described.

In this case, as shown in FIG. 7, the power stage amplifying circuit 4 includes transistors QM2 _{1 to} QM2 _{M made} of a multi-emitter type HBT and a plurality of unit cells 8 ₁ to 8 _N.

The difference from FIG. 2 of the first embodiment is that the unit cells 8 ₁ to 8 _N are composed of transistors Q 3 _{1 to} Q 3 _N , capacitance elements C _{1 to} C _N , and resistors Rb _{1 to} Rb _N. in that the transistor QM2 ₁ ~QM2 _M emitter follower which functions as a circuit has two emitters.

Therefore, the number of transistors QM2 _{1 to} QM2 _M is half that of unit cells 8 ₁ to 8 _N. For example, one emitter of transistor QM2 ₁ is connected to the other connection portion of resistor Rb ₁ of unit cell 8 _1. The other emitter of the transistor QM2 ₁ is connected to the other connection portion of the resistor Rb ₂ of the unit cell 8 ₂ .

7, the connection configuration is the same as that in FIG. 2 except that the transistors QM2 _{1 to} QM2 _M have a multi-emitter configuration. As a result, the layout area of the power stage amplifier circuit 4 can be reduced.

In FIG. 7, the number of emitters of the multi-emitter transistors QM2 _{1 to} QM2 _M is assumed to have two emitters. For example, the transistors QM2 _{1 to} QM2 _M have three emitters or more. Also good. As the number of emitters increases, the layout area occupied by the transistors can be reduced.

  As a result, in the second embodiment, the layout area of the semiconductor chip can be reduced while increasing the current value for starting thermal runaway in the power stage amplifier circuit.

(Embodiment 3)
FIG. 8 is a circuit diagram showing an example of a power stage amplifier circuit according to Embodiment 3 of the present invention.

  In the third embodiment, a configuration using an FET instead of an HBT as an emitter-follower transistor that functions as a bias circuit of the power stage amplifier circuit 4 will be described.

In this case, as shown in FIG. 8, the power stage amplifier circuit 4 uses transistors T1 to TN made of FETs such as pHEMT and MESFET instead of the transistors Q2 _{1 to} Q2 _N of the HBT. 1 is different from FIG. 2 and other connection configurations are the same as those in FIG.

  The power stage amplifier circuit 4 shown in FIG. 8 may be formed using, for example, a BiFET process in which the HBT and the FET are formed on the same GaAs substrate.

With this configuration, the potential difference between the control power supply voltage Vreg and the emitter voltage Ve31 in Figure 8, base - in addition to the voltage drop of the emitter voltage Vbe31 and resistance Rb _1, the gate of the transistor T1 consisting FET - source voltage Vgs21 It is supported by three.

  Therefore, as the base current Ib1 increases, the gate-source voltage Vgs21 also increases, and the start of thermal runaway can be delayed. That is, the thermal runaway start current Icrit can be increased.

  In this case, as compared with the first embodiment in which the base current Ib1 is proportional to the exponential function of the base-emitter voltage, the transistor composed of the FET has a base current Ib1 proportional to the square of the gate-source voltage. As the base current Ib1 increases, the gate-source voltage increases more.

  As a result, in the third embodiment, the start of thermal runaway can be delayed more than that in the first embodiment, and thus the thermal runaway start current Icrit can be increased.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is suitable for a stable operation technique in a high-frequency power amplifier used in various wireless communication fields such as a mobile phone, a wireless local area network (LAN), or WiMAX (Worldwide Interoperability for Microwave Access).

DESCRIPTION OF SYMBOLS 1 High frequency power amplifier module 2 Control circuit 3 First stage amplifier circuit 4 Power stage amplifier circuit 5 Input stage matching circuit 6 Interstage matching circuit 7 Output stage matching circuit 8 ₁ to 8 _N Unit cell Q2 _{1 to} Q2 _N Transistors Q3 _{1 to} Q3 _N Transistors C _{1 to} C _N Capacitance elements Rb _{1 to} Rb _N resistors V1, V2 Via holes H1 to H4 Wiring QM2 _{1 to} QM2 _M transistors T1 to TN Transistor 50 Power stage amplifier circuit R51 Resistors 50 ₁ to 50 _N Unit cell C51 Static Capacitance element R51 Resistance

Claims (12)

A semiconductor integrated circuit device comprising an amplifier circuit composed of a plurality of unit cells,
The unit cell is
A first transistor for amplifying the power of the input signal;
A capacitive element connected between an input terminal to which an input signal is input and the first transistor;
A second transistor for supplying a bias power to the base of the first transistor;
A base ballast resistor connected between the second transistor and the base of the first transistor to prevent an increase in base current of the first transistor;
Each first transistor provided in the unit cell is connected in parallel between an output terminal that outputs an output signal and a reference potential,
The first transistor and the second transistor are laid out with at least either the base ballast resistor or the capacitance element interposed therebetween,
It said amplifier circuit is a semiconductor integrated circuit device, wherein a plurality of the unit cells to the right and left around the vias holes connected to a reference potential are laid in line symmetry. The semiconductor integrated circuit device according to claim 1.
2. The semiconductor integrated circuit device according to claim 1, wherein a transistor size of the second transistor is smaller than a transistor size of the first transistor. The semiconductor integrated circuit device according to claim 1 or 2,
The semiconductor integrated circuit device, wherein the second transistor is an FET. The semiconductor integrated circuit device according to claim 1 or 2,
The semiconductor integrated circuit device, wherein the second transistor is made of HBT. A semiconductor integrated circuit device comprising an amplifier circuit composed of a plurality of unit cells and a plurality of multi-emitter transistors,
The unit cell is
A first transistor for amplifying the power of the input signal;
A second transistor for supplying a bias power to the base of the first transistor;
A capacitive element connected between an input terminal to which an input signal is input and the first transistor;
A base ballast resistor connected between the second transistor and the base of the first transistor to prevent an increase in base current of the first transistor;
The multi-emitter transistor is
A bias power source is provided to each of the bases of the first transistors provided in the at least two unit cells, each having at least two emitters;
The first transistor and the multi-emitter transistor are laid out with at least either the base ballast resistor or the capacitance element interposed therebetween,
It said amplifier circuit is a semiconductor integrated circuit device, wherein a plurality of the unit cells to the right and left around the vias holes connected to a reference potential are laid in line symmetry. The semiconductor integrated circuit device according to claim 5.
The semiconductor integrated circuit device, wherein the multi-emitter transistor is made of HBT. A power amplifier including an amplifier circuit composed of a plurality of unit cells,
The unit cell is
A first transistor for amplifying the power of the input signal;
A capacitive element connected between an input terminal to which an input signal is input and the first transistor;
A second transistor for supplying a bias power to the base of the first transistor;
A base ballast resistor connected between the second transistor and the base of the first transistor to prevent an increase in base current of the first transistor;
Each first transistor provided in the unit cell is connected in parallel between an output terminal that outputs an output signal and a reference potential,
The first transistor and the second transistor are laid out with at least either the base ballast resistor or the capacitance element interposed therebetween,
The amplifier circuit includes power plurality of the unit cells to the right and left around the vias holes are connected to a reference potential, characterized in that it is laid out in a line symmetrical amplifier. The power amplifier according to claim 7, wherein
The power amplifier according to claim 1, wherein a transistor size of the second transistor is smaller than a transistor size of the first transistor. The power amplifier according to claim 7 or 8,
The power amplifier, wherein the second transistor is an FET. The power amplifier according to claim 7 or 8,
The power amplifier, wherein the second transistor is made of HBT. A power amplifier including an amplifier circuit composed of a plurality of unit cells and a plurality of multi-emitter transistors,
The unit cell is
A first transistor for amplifying the power of the input signal;
A second transistor for supplying a bias power to the base of the first transistor;
A capacitive element connected between an input terminal to which an input signal is input and the first transistor;
A base ballast resistor connected between the second transistor and the base of the first transistor to prevent an increase in base current of the first transistor;
The multi-emitter transistor is
A bias power source is provided to each of the bases of the first transistors provided in the at least two unit cells, each having at least two emitters;
The first transistor and the multi-emitter transistor are laid out with at least either the base ballast resistor or the capacitance element interposed therebetween,
The amplifier circuit includes power plurality of the unit cells to the right and left around the vias holes are connected to a reference potential, characterized in that it is laid out in a line symmetrical amplifier. The power amplifier according to claim 11, wherein
The multi-emitter transistor is made of HBT.

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