JP5409525B2 - Packet multiplexer - Google Patents

Description

  The present invention relates to a packet multiplexing apparatus that multiplexes a plurality of packets (high-speed data packets) received via a plurality of different communication lines.

  In a general packet multiplexing apparatus for packet communication, when a plurality of packets respectively received via a plurality of different communication lines are multiplexed in the order of reception, the packet multiplexing apparatus is arranged between the previous packet and the next packet. It is desired to insert an appropriate control signal bit string for representing a packet delimiter at an appropriate location. This control signal bit string includes information on the start and end of a packet and information on a packet length (frame length). In a device that handles packets, various types of packet control are performed based on these pieces of information.

  Here, originally, packet communication is premised on a communication method using a serial signal, and a control signal bit string is also defined in the standard on the premise of a communication method using a serial signal (see, for example, Non-Patent Document 1). In addition to Non-Patent Document 1, there are, for example, Patent Documents 1 to 3 as prior art documents related to the invention of the present application.

JP-A-6-152651 Japanese Patent Laid-Open No. 2002-247073 JP 2004-289567 A

Osamu Ishida et al., “Revised 10 Gigabit Ethernet Textbook”, impress, April 1, 2005, p181-186

  Since the conventional packet multiplexing apparatus is configured on the assumption that the line speed is low, the data width is small even if the received serial signal packet is expanded into multiple bits and converted into a parallel signal. There was also a margin in the interval from one to the next packet. Therefore, it is possible to perform IPG adjustment in which an interpacket gap (hereinafter referred to as “IPG”), which is a kind of control signal bit string, is inserted between packets in units of clocks, and the IPG adjustment method is particularly considered. There was no need.

  Here, FIG. 5 shows an example of IPG adjustment of a conventional packet multiplexing apparatus. As shown in FIG. 5, in the conventional packet multiplexing apparatus, when the data bus width after parallelization does not exceed IPG, the packet interval is adjusted in units of clocks, and the average value of IPG is set as the IPG specified value. It was possible to control to be.

  However, if the device operating speed cannot be improved despite the increase in the line speed, it is necessary to develop a multi-bit packet with a larger data width and perform signal processing as a parallel signal. In consideration of the case where the data bus width of the bus in the device exceeds the IPG at the time of this signal processing, if the interval between packets is adjusted to an appropriate IPG, the above clock unit adjustment is impossible. It becomes.

  Further, in the IPG adjustment of the conventional packet multiplexing apparatus as shown in FIG. 5, since the packets are sequentially processed with 1 clock as the minimum unit, as shown in FIG. 6, the minimum time is required in the parallel data bus width. Even if the internal processing is performed, the average value of the IPG may become a specified value or more. If the purpose of the conventional apparatus configuration is to be achieved, in order to avoid this problem, the parallel signal width due to multi-bit expansion is suppressed by operating at a higher speed using a higher-speed device, It is necessary to keep the data bus width smaller than the IPG. However, the operation clock of current hardware is in a peak state, and it is not possible to expect a significant clock increase beyond the present level.

  The present invention has been made in order to solve the above-described problems. Even when the line speed is increased and a packet having a larger data width is multiplexed by multi-bit expansion, it is possible to reduce the gap between packets. It is an object of the present invention to obtain a packet multiplexing apparatus capable of inserting an appropriate interpacket gap.

  The packet multiplexing device of the present invention has a received packet storage means for storing a received packet, and receives a plurality of buffer units respectively corresponding to a plurality of different communication lines, and when the buffer unit receives a packet. A packet information acquisition unit that acquires, as packet information, information on the communication line of the received packet and packet length information of the received packet; and the plurality of buffer units based on the packet information acquired by the packet information acquisition unit A buffer unit that determines the received packet storage means belonging to any of the above as a read target, and calculates a read time for the received packet storage means and an interpacket gap that is an interval between packets before and after multiplexing Calculated by the operation calculation unit and the buffer unit operation calculation unit Packets read out from the received packet storage means to be read, determined by the buffer unit operation calculation unit, at a read-out time so as to correspond to the interpacket gap calculated by the buffer unit operation calculation unit A packet interval adjusting unit that adjusts the first byte position of the packet, and a buffer-external multiplexing processing unit that acquires a plurality of packets after the position adjustment by the packet interval adjusting unit and multiplexes the acquired packets into a transmission packet sequence Are provided.

  According to the packet multiplexing apparatus of the present invention, the buffer unit operation calculation unit determines a reception packet storage unit to be read, calculates a read time and an interpacket gap of the reception packet storage unit, and a packet interval adjustment unit The packet is read from the received packet storage means to be read determined by the buffer unit operation calculation unit with the read time calculated by the buffer unit operation calculation unit, and corresponds to the interpacket gap calculated by the buffer unit operation calculation unit. In this way, the leading byte position of the read packet is adjusted, so that the line speed is increased, and even when a packet with a larger data width is multiplexed by multi-bit expansion, an appropriate inter-packet between packets A gap can be inserted.

It is a block diagram which shows the packet multiplexing apparatus by Embodiment 1 of this invention. It is explanatory drawing for demonstrating the outline | summary of the FIFO front stage process part of FIG. It is explanatory drawing for demonstrating the IPG adjustment system by the packet space | interval adjustment part of FIG. 3 is a flowchart illustrating an operation of a read enable signal generation unit in FIG. 1. It is explanatory drawing for demonstrating an example of the IPG adjustment of the conventional packet multiplexing apparatus. It is explanatory drawing for demonstrating an example of the IPG adjustment of the conventional packet multiplexing apparatus.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.
Embodiment 1 FIG.
1 is a block diagram showing a packet multiplexing apparatus (packet multiplexing circuit) according to Embodiment 1 of the present invention. FIG. 2 is an explanatory diagram for explaining an overview of the FIFO pre-processing unit 2 in FIG.
1 and 2, the packet multiplexing apparatus of the first embodiment is used in a layer 2 switch that multiplexes Ethernet frames (packets), receives signals from each of all n communication lines, and receives these signals. It is a device that can multiplex and output at a bit rate of 40 Gbps / 100 Gbps (or higher).

  In addition, the packet multiplexing apparatus according to the first embodiment uses an IPG of 96 bits (12 bytes) or longer (+8 bytes if the preamble is included) provided to absorb the clock deviation for each packet according to the Ethernet (registered trademark) standard. This is a device that can insert received packets before and after multiplexing received packets and output a transmission packet sequence at the wire rate in the inserted state.

  Here, the IPG satisfies the standard if it is 96 bits (12 bytes) or longer (+8 bytes if the preamble is included). The packet multiplexing apparatus according to the first embodiment is assumed to receive packets from n systems of communication lines and use all the bandwidth based on the output data bus width when multiplexing these packets. In this case, in order to realize a wire rate corresponding to the output data bus width, for example, when packets arrive in succession with the shortest 96-bit IPG inserted between packets (n communication lines) The IPG to be inserted at the packet transmission side must also be the shortest 96-bit IPG. For this reason, the configuration of the packet multiplexing device of the first embodiment is a configuration in which 96-bit IPG can be inserted when packets arrive continuously.

  In addition, the packet multiplexing apparatus according to the first embodiment includes the first to n-th buffer units 1 that correspond one-to-one to the first to n-th communication lines (hereinafter also referred to as “input 1 to input n”). -1 to 1-n, a queuing control unit 10 as a buffer unit operation calculation unit, and an out-buffer MUX unit (MUX circuit, MUX: Multiplexer) 20 as an out-buffer multiplexing processing unit Yes. Here, the first buffer unit 1-1 among the first to nth buffer units 1-1 to 1-n will be mainly described. Note that one queuing control unit 10 is used for the plurality of buffer units 1 of the first to n-th buffer units 1-1 to 1-n.

  The first to n-th buffer units 1-1 to 1-n include a FIFO pre-processing unit 2 and a plurality of received packet FIFOs (FIFO memory, FIFO: First In First Out) 3-1 to 3 as received packet storage means. -N, a packet arrival information generation unit (packet arrival completion signal generation unit) 4, a packet length measurement unit (packet length calculation unit) 5, a received packet FIFO read control unit 6, a packet interval adjustment control unit 7, Packet interval adjustment units 8-1 to 8-n and an intra-buffer MUX unit 9 serving as an intra-buffer multiplexing processing unit are provided.

  The queuing control unit 10 performs queuing control on all the received packet FIFOs 3 of all the buffer units 1. In addition, the queuing control unit 10 includes a queue waiting FIFO (FIFO memory) 11, a read enable signal generation unit 12, and an IPG calculation unit 13.

  As shown in FIG. 2, the FIFO pre-processing unit 2 includes a parallel expansion unit 2A, a FIFO distribution unit 2B, and a distribution control unit 2C. The parallel expansion unit 2A expands a packet received from the input 1 reception system to a data bus width corresponding to an operation speed capable of being internally processed. The FIFO distribution unit 2B distributes the packets expanded by the parallel expansion unit 2A to n systems and sends them to the reception packet FIFOs 3-1 to 3-n.

  Here, the packet distributed by the FIFO distribution unit 2B arrives at all the systems of the received packet FIFOs 3-1 to 3-n. However, one packet of the received packets FIFO 3-1 to 3-n is received on a packet basis. It is written in the received packet FIFO3. In order to realize such an operation, the distribution control unit 2C generates a write enable signal (write command), and sends the generated write enable signal to the reception packet FIFO3 to be written, thereby receiving the write target. The packet is written (stored) in the packet FIFO 3. For example, the distribution control unit 2C writes the packets in the order of the first received packet FIFO 3-1, the second received packet FIFO 3-2,..., The nth received packet FIFO 3-n.

  The packet arrival information generation unit 4 monitors the reception status of the packet from the input 1, and according to the arrival of the packet at each buffer unit 1-1 to 1-n, the reception completion time and the identification information of the buffer unit 1 Packet arrival information indicating the above is generated. The packet length measurement unit 5 measures the packet length of the input 1 packet, and generates packet length information. Here, the packet arrival information generation unit 4 and the packet length measurement unit 5 constitute a packet information acquisition unit that acquires the packet length information and the packet arrival information as packet information.

  The packet length information and the packet arrival information are sent to the queue waiting FIFO 11, correlated with each other, and stored in the queue waiting FIFO 11. Here, the queue waiting FIFO 11 receives packet length information and packet arrival information from the packet arrival information generation unit 4 and the packet length measurement unit 5 of all the buffer units 1-1 to 1-n, respectively.

  The read enable signal generation unit 12 reads a set of packet length information and packet arrival information stored in the queue waiting FIFO 11. Further, the read enable signal generation unit 12 determines which input system the target packet belongs to from the packet arrival information, calculates a time for reading the target packet from the received packet FIFO 3 from the packet length information, A read enable signal (read command) corresponding to the read time is generated.

  Based on the packet length information and the packet arrival information, the IPG calculation unit 13 inserts an IPG to be inserted between the target packet and the packet before or after the packet so that the average value of the IPG becomes a specified IPG. The packet interval information including the calculated IPG information is generated.

  The read enable signal generated by the read enable signal generation unit 12 is sent to the received packet FIFO read control unit 6 and the packet interval adjustment control unit 7. Similarly, the packet interval information generated by the IPG calculation unit 13 is sent to the received packet FIFO read control unit 6 and the packet interval adjustment control unit 7.

  The received packet FIFO read control unit 6 controls reading of packets from the received packet FIFOs 3-1 to 3-n based on the read enable signal. The packets read from the reception packet FIFOs 3-1 to 3-n are sent to the packet interval adjustment units 8-1 to 8-n, respectively.

  The packet interval adjustment control unit 7 sends packet interval information to the packet interval adjustment units 8-1 to 8-n corresponding to the received packet FIFOs 3-1 to 3-n to be read. The packet interval adjustment units 8-1 to 8-n receive the packets from the received packet FIFOs 3-1 to 3-n of each system, and adjust the leading byte positions of the packets corresponding to the IPG of the packet interval information. (Perform IPG adjustment).

  The MUX unit 9 in the buffer unit multiplexes a plurality of packets after the IPG adjustment by the packet interval adjustment units 8-1 to 8-n into a packet string. At the same time, the MUX unit 9 in the buffer unit performs parallel / serial conversion on the multiplexed packet sequence. The MUX unit 20 outside the buffer unit multiplexes the serial signal packet sequences output from the in-buffer MUX units 9 of all the buffer units 1-1 to 1-n to form a transmission packet sequence.

  Next, an IPG adjustment method by the packet interval adjustment units 8-1 to 8-n will be described. FIG. 3 is an explanatory diagram for explaining an IPG adjustment method by the packet interval adjustment units 8-1 to 8-n of FIG. Here, consider a case where packets P1 and P2 arrive in succession. First, these packets P1 and P2 are distributed to n systems (in FIG. 3, simplified to two systems for explanation) by the FIFO distribution unit 2B and the distribution control unit 2C of the FIFO pre-processing unit 2. . Then, the distributed packets P1 and P2 are written in reception packet FIFOs 3-1 and 3-2 provided in the respective systems.

  The packets are read from the reception packet FIFOs 3-1 and 3-2 by queuing control by the queuing control unit 10, and the read packets are respectively sent to the packet interval adjustment units 8-1 and 8-2. The packet is subjected to a deformation operation accompanied by movement of the first byte position by the packet interval adjustment units 8-1 and 8-2.

  Here, the packet interval adjustment control unit 7 stores a value obtained by adding the remainder (the circle in FIG. 3) obtained by dividing the packet length of the packet P1 by the data bus width and the specified IPG, From this value, the first byte position of the transformation operation to be performed on the packet P2 is determined. It is to be noted that the same surplus is transferred from the packet P2 to the next packet of the packet P2 (the remainder is shifted). A value calculated from the packet after the transformation operation is used.

  The packets P1 and P2 that have undergone such a modification operation are output from the packet interval adjustment units 8-1 and 8-2 to the MUX unit 9 in the buffer unit, multiplexed by the MUX unit 9 in the buffer unit, and then sent to one system. Assembled into a packet sequence. Since the packets P1 and P2 are already in the state where the leading byte position has been moved to an appropriate location by the packet interval adjustment units 8-1 and 8-2, a simple OR circuit is used as the MUX unit 9 in the buffer unit. Also good. In the multiplexed state, as shown in FIG. 3, the interval between the parallel signal packets P1 and P2 is a prescribed IPG. Further, the interval between the serialized packets P1 and P2 is also a specified IPG.

  Next, FIG. 4 is a flowchart showing the operation of the read enable signal generation unit 12 of FIG. Here, description will be made assuming that the packet arrival information and the packet length information are started from a state where the queue waiting FIFO 11 stores them. In FIG. 4, when packet arrival information and packet length information are first written in the queue waiting FIFO 11, the read enable signal generator 12 cancels the EMPTY state (empty state) of the queue waiting FIFO 11. After waiting, the first set of packet arrival information and packet length information is read from the queue waiting FIFO 11 (steps S1 and S3).

  Then, the read enable signal generation unit 12 makes the read enable signal to the received packet FIFO 3 of the corresponding buffer unit 1 positive based on the packet arrival information (step S2).

  In parallel with this, the read enable signal generation unit 12 adds the count value calculated from the packet length and the data bus width to the read time counter for determining the time for positiveizing the read enable signal based on the packet length information. Set (step S4). Here, the read enable signal generation unit 12 sets a count value in the read time counter. At this time, the read enable signal generation unit 12 sets a count value assuming an output signal in a state where the packet interval is adjusted to an appropriate specified IPG.

  Then, the read enable signal generation unit 12 subtracts 1 from the count value of the read time counter per clock (steps S5 and S6). When the read time counter has been rotated, at that time (counter value = 0), the read enable signal generation unit 12 checks whether the next packet after the currently read packet is waiting to be read (step S7).

  Here, when the packet next to the currently read packet is waiting to be read (when the arrival of the next packet is completed), the packet arrival information and the packet length information are stored in the queue waiting FIFO 11. The read enable signal generation unit 12 reads new packet arrival information and packet length information from the queue waiting FIFO 11 (steps S8, S1, and S2), and repeats the same operation.

  On the other hand, when the packet next to the currently read packet is not waiting to be read (when the arrival of the next packet is not completed), the read enable signal generation unit 12 negatively sets the read enable signal to the received packet FIFO 3. Until the arrival of the next packet is completed (step S7), and the same operation is repeated.

  According to the packet multiplexing apparatus of the first embodiment as described above, the packet interval adjustment units 8-1 to 8-n have the read enable signal generation unit 12 with the read time calculated by the read enable signal generation unit 12. The packet is read from the reception target packet FIFOs 3-1 to 3-n determined by the above, and the head byte position of the read packet is adjusted so as to correspond to the IPG calculated by the IPG calculation unit 13. With this configuration, the line speed is increased, and an appropriate interpacket gap can be inserted between packets even when a packet having a larger data width is multiplexed by multi-bit expansion.

  Here, in the conventional packet multiplexing apparatus, when a received packet is expanded in parallel to a data bus width exceeding the IPG in order to suppress the operation clock, the data bus width for one clock already exceeds the IPG. The wire rate could not be realized. On the other hand, by using the packet multiplexing apparatus of the first embodiment, it is possible to output a packet in which an IPG of an appropriate size is inserted at an appropriate position at a wire rate. As a result, it is possible to configure a packet multiplexing device using a low-speed device. Therefore, it is possible to configure a packet multiplexing apparatus that can multiplex high-speed packets with high efficiency while suppressing the operation clock, and it is possible to reduce costs and flexibly design by using the current device as it is. .

  1, 1-1 to 1-n First to n-th buffer unit, 2 FIFO pre-processing unit, 2A parallel expansion unit, 2B FIFO distribution unit, 2C distribution control unit, 3,3-1 to 3-n received packet FIFO (Received packet storage means) 4 Packet arrival information generation unit 5 Packet length measurement unit 6 Received packet FIFO read control unit 7 Packet interval adjustment control unit 8-1 to 8-n Packet interval adjustment unit 9 In buffer unit MUX section (intra-buffer multiplexing processing section), 10 queuing control section (buffer section operation calculation section), 11 queue waiting FIFO, 12 enable signal generation section, 13 IPG calculation section, 20 outside buffer section MUX section (outside buffer section) Multiplexing processing unit).

Claims (3)

Receiving packet storage means for storing received packets, a plurality of buffer units respectively corresponding to different communication lines;
A packet information acquisition unit that acquires, as packet information, information on the communication line of the received packet and packet length information of the received packet when the buffer unit receives the packet;
Based on the packet information acquired by the packet information acquisition unit, the received packet storage unit belonging to any of the plurality of buffer units is determined as a read target, and the read time for the received packet storage unit is multiplexed with A buffer unit operation calculation unit that calculates an inter-packet gap that is an interval between packets before and after
An interpacket gap calculated by the buffer unit operation calculation unit by reading a packet from the received packet storage unit to be read determined by the buffer unit operation calculation unit with the read time calculated by the buffer unit operation calculation unit A packet interval adjustment unit that adjusts the first byte position of the read packet so as to correspond to
A packet multiplexing apparatus comprising: a plurality of packets whose positions are adjusted by the packet interval adjusting unit; and an extra-buffer multiplexing processing unit that multiplexes the plurality of acquired packets into a transmission packet sequence. The plurality of buffer units are:
A plurality of packet storage means;
A distribution unit that distributes the plurality of packets received by the buffer unit to the plurality of packet storage units in units of packets;
The buffer unit operation calculation unit determines one of the plurality of received packet storage units belonging to any of the plurality of buffer units as a reading target based on the packet information acquired by the packet information acquisition unit. The packet multiplexing apparatus according to claim 1, wherein: The packet interval adjustment unit is provided in each of the plurality of buffer units so as to correspond to the plurality of packet storage units on a one-to-one basis, and the first byte position of the packet read from the packet storage unit corresponding to itself Adjust
The packet multiplexing apparatus according to claim 2, further comprising: an in-buffer multiplexing processing unit that multiplexes a plurality of packets after the interval adjustment by the plurality of packet interval adjusting units.

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