JP4607003B2 - Packet processing device - Google Patents

Description

  The present invention relates to a packet processing apparatus that analyzes information such as a packet destination and a transmission source.

  A router device or the like that processes packets such as IP is equipped with a packet processing module that is a main component of the packet processing device, and performs packet transfer processing according to information such as the destination and source of the packet analyzed by the packet processing module. Is going.

  In recent years, with the increase in data speed, the transfer speed tends to increase in router devices, etc., but there is a limit to the processing speed in the packet processing module. A method is adopted in which a packet stream is distributed into a plurality of low-speed packet streams by a distributor and processed in parallel by a plurality of packet processing modules arranged in parallel. At this time, the processing time of the packet processing modules arranged in parallel varies due to the variable length of packets such as IP, etc., so conventionally, the order of packets is corrected after parallel processing. (For example, Patent Document 1).

  That is, in Patent Document 1, as a method for realizing packet order correction, a serial number is assigned when distributing a packet stream at a distributor, and after parallel processing, the packets are arranged according to the serial number assigned by the distributor by an order correction unit. There has been proposed a method of outputting in place.

JP 2004-158903 A (Packet Processing Device)

  As described above, in the conventional packet processing apparatus, when packet processing is performed in parallel, the processing time in each packet processing module arranged in parallel is fixed due to the variable length of packets such as IP. Since it is not time, it is necessary to correct the packet order after parallel processing, and special circuits such as serial number assigning means and order correcting means are required.

  The present invention has been made in view of the above, and by providing means for fixing the processing time in each packet processing module arranged in parallel, special means such as serial number assigning means and order correcting means. It is an object of the present invention to obtain a packet processing device that realizes parallel packet processing without providing a packet.

  In addition, the present invention provides a packet processing apparatus that realizes parallel packet processing without providing special means such as serial number assigning means and order correction means, and that can reduce the number of packet processing modules arranged in parallel. For the purpose.

In order to achieve the above-described object, the present invention relates to a transfer of an input packet stream in a packet processing device in which a plurality of packet processing modules that perform packet processing including determination of a transfer destination of a variable length packet are arranged in parallel. Packet information extraction means for extracting packet information required for performing the packet processing from each variable length packet in the process, and adding overhead to the packet information extracted by the packet information extraction means The fixed-length cell generating means for generating fixed-length cells and the fixed-length cells generated by the fixed-length cell converting means are adjusted in order to the respective input speeds in order for a plurality of the packet processing modules arranged in parallel. The fixed length cell converting means to the packet stream inputted from the packet information extracting means. A fixed delay means for performing delay processing in consideration of the processing time to the packet processing module, and a packet for inserting information on the transfer destination determined by a plurality of the packet processing modules into a corresponding packet input from the fixed delay means Each packet processing module sets the forwarding destination information, which is a result of packet processing, as overhead included in the fixed-length cell, and the forwarding destination information is set as overhead. The long cell is output to the packet information insertion means.

  According to the present invention, only information such as a header necessary for packet processing such as forwarding destination determination is converted into fixed-length cells from an input variable-length packet and distributed to a plurality of packet processing modules arranged in parallel. The processing time in each packet processing module can be fixed. That is, it is not necessary to correct the packet order after parallel processing.

  According to the present invention, it is possible to obtain a packet processing apparatus that realizes parallel packet processing without providing special means such as serial number assigning means and order correcting means.

  Exemplary embodiments of a packet processing apparatus according to the present invention will be explained below in detail with reference to the drawings.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a configuration of a packet processing apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, the packet processing device 1 according to the first embodiment is a packet information extraction unit 2, a packet delay circuit 3a, a packet information insertion unit 4a, a fixed length cell conversion unit 5, and a distribution means. Distributor 6 and packet processing modules 7-1 to 7-x arranged in parallel are provided. The distributor 6 includes a distribution circuit 6a and a speed conversion circuit 6b (1-x) arranged in a one-to-one relationship with the packet processing module 7 (1-x).

  The packet information extraction unit 2 sends information such as headers necessary for performing packet processing such as forwarding destination determination from each input packet in the process of sending each variable-length packet input from the outside to the packet delay circuit 3a. (Hereinafter referred to as “packet information”) is extracted and output to the fixed-length cell converting unit 5.

  The packet delay circuit 3a includes, for example, a memory, and each packet sent from the packet information extraction unit 2 is sent to the fixed length cell conversion unit 5, the distributor 6 and the packet processing module 7 (7-1 to 7-x). Delay processing for the total processing time (fixed delay time) is performed, and the packets are sequentially output to the packet information insertion unit 4a.

  The packet information insertion unit 4a inserts information such as the transfer destination of the packet processed by the packet processing module 7 (1-x) into each packet subjected to the delay processing by the packet delay circuit 3a, and outputs each packet. Generate a packet and send it out.

  Now, the fixed-length cell converting unit 5 adds overhead to each packet information input from the packet information extracting unit 2 to transform it into a fixed-length cell, and gives it to the distributor 6.

  In the distributor 6, first, the distribution circuit 6a distributes the fixed-length cells generated by the fixed-length cell converting unit 5 to the speed conversion circuits 6b (1 to x) in order. In the speed conversion circuit 6b (1-x), the fixed-length cell to be input is converted to the input speed of the corresponding packet processing module 7 (1-x) and output.

  Each of the packet processing modules 7-1 to 7-x includes a so-called associative memory (CAM), performs packet transfer destination determination from packet information included in the fixed-length cell, and fixes the determination result of the transfer destination and the like. The overhead included in the long cell is set and given to the packet information insertion unit 4.

  Next, the operation of the packet processing apparatus 1 configured as described above will be described along FIG. 2 with reference to FIG. FIG. 2 is a time chart for explaining the operation of the packet processing apparatus shown in FIG. Here, in order to facilitate understanding, two packet processing modules 7-1 and 7-2 among the packet processing modules 7-1 to 7-x will be described.

  As shown in FIG. 2A, there are two packets input to the packet information extraction unit 2, for example, a packet (A) and a packet (B), each having a different length. The packet information of packet (a) is Ph1, and the packet information of packet (b) is Ph2.

  The packet information extraction unit 2 extracts the packet information Ph1 of the packet (b) and the packet information Ph2 of the packet (b), and gives them to the fixed-length cell unit 5 (FIG. 2 (2)).

  The fixed-length cell converting unit 5 adds the overhead a1 to the packet information Ph1 to form a fixed-length cell, and adds the overhead a2 to the packet information Ph2 to form a fixed-length cell (FIG. 2 (3)). These are subjected to speed conversion processing in the speed conversion circuits 6b1 and 6b2.

Therefore, the packet processing module 7-1 receives the fixed-length cell including the packet information Ph1 whose length has been changed and the overhead b1 (FIG. 2 (4)), and the packet processing module 7-2 receives the length. Is input as a fixed-length cell composed of packet information Ph2 and overhead b2 (FIG. 2 ( 5)).

  In the packet processing modules 7-1 and 7-2, packet processing such as forwarding destination determination is performed within a fixed time based on the packet information Ph 1 and Ph 2 in the fixed-length cell, and the processing result is obtained in overhead c 1 and c 2 with different signs Is set and output to the packet information insertion unit 4a (FIGS. 2 (6) and (7)).

  In the packet delay circuit 3a, delay processing is performed so that the input packets (a) and (b) reach the packet information insertion unit 4a in accordance with the timing at which the packet processing modules 7-1 and 7-2 output the processing results. Therefore, the packet information insertion unit 4a generates the output packet (c) for the input packet (b) by adding the overhead d1 in which the transfer destination information is inserted to the packet information Ph1 in the input packet (b), and subsequently An output packet (d) for the input packet (b) can be generated by adding the overhead d2 in which the transfer destination information is inserted to the packet information Ph2 in the input packet (b), and each can be continuously output ( FIG. 2 (8)). The packet information insertion unit 4a also performs speed adjustment and the like when adding overhead d1 and d2.

  As described above, according to the first embodiment, for variable-length packets, only header information required for packet processing is converted into fixed-length cells and distributed to packet processing modules arranged in parallel. Since the packet processing time is fixed and the packet processing result is output after the packet input order fixed delay, the packets can be processed in parallel without preparing a special packet order correction circuit.

  Here, when the input packet rate is Z, the processing rate of the packet processing module is Y, the number of parallel arrangements of the packet processing modules is X, and the cell size for making the fixed-length cell is 64 bytes, Z = Y × X. Then, even when only the shortest packet (64 bytes) is input continuously, the distributor distributes fixed-length cells in order and converts the speed to the input speed of the packet processing module without preparing a special buffer. Only by performing it, packet processing (wire rate processing) X times the processing speed Y of the packet processing module becomes possible, so that the packet processing capability of the entire apparatus can be easily improved.

Embodiment 2. FIG.
FIG. 3 is a block diagram showing the configuration of the packet processing apparatus according to the second embodiment of the present invention. In FIG. 3, the same reference numerals are given to components that are the same as or equivalent to those shown in FIG. 1 (Embodiment 1). Here, the description will be focused on the portion related to the second embodiment.

  In the first embodiment, a case has been described in which a predetermined number of packet processing modules are arranged in parallel so as to satisfy Z = Y × X in order to realize wire rate processing, but in this second embodiment, Z> Y A configuration example when a predetermined number of packet processing modules are arranged in parallel so as to be × X is shown. In this case, the number of parallel arrangements of packet processing modules can be reduced as compared with the first embodiment.

  As shown in FIG. 3, in the packet processing apparatus 10 according to the second embodiment, in the configuration shown in FIG. 1 (first embodiment), the packet information extraction unit 11, the packet delay circuit 3b, and the packet information insertion with the signs changed. A part 4b and a distributor 12 are provided.

  In the distributor 12, a buffer 12a (1 to x) is provided between the distribution circuit 6a and the speed conversion circuit 6b (1 to x), and a packet is discarded when cell discard occurs in the buffer 12a (1 to x). A packet discard instruction signal 13 is output to the information extraction unit 11. In addition to the function of the packet information extraction unit 2, the packet information extraction unit 11 receives a packet discard instruction signal 13 and performs a discard process for a specified packet among the input packets.

  The packet delay circuit 3b is not a fixed delay type but a FIFO type delay circuit capable of variably operating the delay time. When the processing result is input from the packet processing module 7 (1 to x), the packet information insertion unit 4b reads the packet from the FIFO of the packet delay circuit 3b in response to it and generates an output packet.

  When reducing the number of packet processing modules arranged in parallel, the number to be reduced is calculated in consideration of the average packet length and the like. For example, if the average packet length is 128 bytes, the packet processing modules arranged in parallel can process one fixed-length cell (64 bytes in this example) in the time within 128 bytes of the input packet on average. Since it is good, it is possible to reduce the number of parallel arrangements to about half of the maximum in the first embodiment.

  However, if packets with an average packet length or shorter are temporarily continuous, it is conceivable that the packet processing module is congested. Therefore, as shown in FIG. 3, the distributor 12 is provided with a buffer 12a (1-x) in a one-to-one relationship with the packet processing module 7 (1-x), and the packet processing module 7 (1-x) When the fixed-length cell processing is congested, this buffer is used to wait, and when a buffer overflow occurs, a packet discard process is performed to cope with it.

  Next, the operation of the packet processing apparatus 10 according to the second embodiment configured as described above will be described.

  The packet information extraction unit 11 extracts packet information necessary for performing packet processing such as forwarding destination determination from each input packet in the process of writing each packet input from the outside to the FIFO of the packet delay circuit 3b. It is output to the fixed-length cell unit 5. Note that the packet information extraction unit 11 determines that the fixed-length cell buffer 12a (1 to x) corresponding to the input packet can be written, that is, from the distributor 12, the discard instruction signal 13 When there is no input, the input packet is written into the FIFO type of the packet delay circuit 3b.

  The fixed-length cell converting unit 5 adds overhead to each packet information input from the packet information extracting unit 11 to convert it into a fixed-length cell (64 bytes in the present example), and gives it to the distributor 12.

  In the distributor 12, the distribution circuit 6a sequentially places the fixed-length cells generated by the fixed-length cell unit 5 in the buffer 12a (1-x) arranged in a one-to-one relationship with the packet processing module 7 (1-x). Distribute. The fixed-length cells distributed to the buffer 12a (1-x) are transferred to the packet processing module 7 (1-x) via the corresponding speed conversion circuit 6b (1-x).

  Here, when the fixed-length cell rate input to the distributor 12 is larger than the total fixed-length cell processing rate of the packet processing modules 7 (1-x) arranged in parallel, the buffer 12a (1-x) is stored in the buffer 12a (1-x). Waiting is performed to deal with congestion in the packet processing module 7 (1 to x).

  However, since the buffer 12a (1 to x) has a finite size, a buffer overflow may occur in the buffer 12a (1 to x). In that case, the overflowed fixed-length cell is discarded, and a packet discard instruction signal 13 is issued to the packet information extraction unit 11 in order to discard the corresponding packet. The packet information extraction unit 11 discards the packet designated by the packet discard instruction signal 13 without sending it to the packet delay circuit 3b.

  The packet information insertion unit 4 reads out the packet from the FIFO of the packet delay circuit 3b using the processing result output from the packet processing module 7 (1-x) as a trigger, and the processing result from the packet processing module 7 (1-x). Insert. At that time, when overhead is added to the packet, speed adjustment and the like are also performed.

  As described above, according to the second embodiment, the buffer is prepared for the packet processing module in the distributor, and the temporary congestion of the fixed-length cell processing in the packet processing module is waited. When the buffer overflows, Since the corresponding packet is discarded, the number of packet processing modules arranged in parallel can be reduced as compared with the first embodiment.

Embodiment 3 FIG.
FIG. 4 is a block diagram showing a configuration of a packet processing apparatus according to Embodiment 3 of the present invention. In FIG. 4, the same or similar components as those shown in FIG. 3 (Embodiment 2) are denoted by the same reference numerals. Here, the description will be focused on the portion related to the third embodiment.

  In the second embodiment, when the fixed-length cell processing is congested, the buffer in the distributor waits, and when the buffer overflows, the overflowing fixed-length cell is discarded and the corresponding packet is discarded. Explained the method. In this method, a discarded packet is discarded regardless of the priority of the packet. Therefore, in the third embodiment, a configuration example is shown in which when the packet discard occurs, it can be selected and discarded, and the number of discarded high priority packets is reduced.

  That is, the packet processing device 20 according to the third embodiment shown in FIG. 4 is provided with a distributor 21 instead of the distributor 12 in the configuration shown in FIG. 3 (second embodiment). In the distributor 21, a priority determination circuit 21a is added, and a threshold value 22 is provided in the buffer 21b (1 to x) whose code is changed.

The priority determination circuit 21 a determines the priority of the packet from the packet information of a fixed length in the cell (service-type field, etc.). In discard processing of the packet determines the discarded packet with reference to the priorities determined by the priority determination circuit 21 a.

  Next, a packet discarding process performed by the packet processing apparatus 20 according to the third embodiment configured as described above will be described.

  As described in the second embodiment, when the fixed-length cell rate input to the distributor 21 is larger than the total fixed-length cell processing rate of the packet processing modules 7 (1 to x) arranged in parallel, Waiting is performed in the buffer 21b (1-x), which corresponds to the congestion of the packet processing module 7 (1-x).

  In the third embodiment, when the distributor 21 waits in the buffer 21b (1-x), if the accumulated amount of the buffer 21b (1-x) exceeds the threshold 22, the priority determination The fixed-length cell determined to be low priority by the circuit 21a is discarded without being distributed to the buffer 21b (1-x).

  Then, the distributor 21 issues a packet discard instruction signal 13 to the packet information extraction unit 11 in order to discard the corresponding input packet. The packet information extraction unit 11 discards the input packet specified by the packet discard instruction signal 13 without writing it into the FIFO of the hacket delay circuit 3b.

  At this time, if a buffer overflow occurs in the buffer 21b (1-x) even if the low-priority discarding is performed, the overflowing fixed-length cell is discarded and the corresponding packet is discarded. A packet discard instruction signal 13 is issued to the information extraction unit 11, and the corresponding packet is discarded without being written in the FIFO of the hacket delay circuit 3b.

  Although only one threshold is provided in the buffer 21b (1 to x) in FIG. 4, a plurality of thresholds are prepared, the plurality of priorities are determined by the priority determination circuit 21a, and discarded for each priority. Control may be implemented.

  As described above, according to the third embodiment, a threshold value is prepared in the buffer in the distributor, the priority of the packet is determined by the priority determination circuit, and the low priority packet is discarded preferentially. As a result, the number of high-priority packets discarded can be reduced.

Embodiment 4 FIG.
FIG. 5 is a block diagram showing a configuration of a packet processing apparatus according to Embodiment 4 of the present invention. In FIG. 5, the same or similar components as those shown in FIG. 4 (Embodiment 3) are denoted by the same reference numerals. Here, the description will be focused on the portion related to the fourth embodiment.

  In the third embodiment, a case has been described in which priority determination is performed in the distributor on the assumption that the priority is explicitly displayed in the service type field or the like of the packet header. Then, when there is no such display, the example of a structure which implements the same packet discard process using priority determination by the packet processing result in a packet processing module is shown.

  That is, the packet processing device 30 according to the fourth embodiment shown in FIG. 5 is provided with a distributor 31 instead of the distributor 12 in the configuration shown in FIG. 4 (third embodiment), and the packet processing module 7 (1 ˜x), packet processing modules 32 (1˜x) are provided.

  In the distributor 31, a compressed code insertion circuit 31 a and a priority determination table 31 b are added to the distributor 12.

  The compression code insertion circuit 31a compresses the packet information stored in the fixed-length cell into a compression code using a hash or the like, and inserts it into the overhead area of the fixed-length cell.

  Therefore, the packet processing module 32 (1 to x) performs transfer destination determination and the like based on the compression-coded packet information and outputs the packet information to the packet information insertion unit 4b. In addition, the priority of the packet is also determined, the determined priority is stored in the overhead area of the fixed-length cell in a form corresponding to the compression code, and the priority is stored in the priority determination table 31b provided in the distributor 31. Output.

  The priority determination table 31b stores the compressed code sent from the packet processing module 32 (1-x) and the priority in association with each other, and performs a search using the compressed code received from the compressed code insertion circuit 31a as a key. The priority determination is performed.

That is, in the distributor 31, when the accumulated amount of the buffer 21b (1 to x) exceeds the threshold 22, the fixed-length cell determined as low priority as a result of the determination in the priority determination table 31b is Similarly to embodiment 3, and discarded without distribution to the buffer 21b (1 to x), is discarded input packet corresponding to the packet information extraction unit 11 without writing into the FIFO of the packet delay circuit 3b.

  In the distributor 31, even if the low priority discarding is performed and the buffer overflow occurs in the buffer 21b (1-x), the overflowing fixed-length cell is discarded as in the third embodiment. At the same time, the packet information extraction unit 11 discards the corresponding packet.

  Although only one threshold is provided in the buffer 21b (1 to x) in FIG. 5, a plurality of thresholds are prepared, a plurality of priorities are determined by the priority determination table 31b, and discarded for each priority. Control may be implemented.

  As described above, according to the fourth embodiment, the priority determination result of the packet executed by the packet processing module is stored in the priority determination table in the distributor. Even when the priority is not explicitly displayed, the priority determination can be performed, the low-priority packets can be preferentially discarded, and the number of high-priority packets discarded can be reduced.

  As described above, the packet processing apparatus according to the present invention does not include special means such as a serial number assigning means and an order correcting means when performing packet processing such as determination of a transfer destination of a variable length packet in parallel. Useful for implementing parallel packet processing.

  The packet processing apparatus according to the present invention realizes parallel packet processing without special provision of a serial number assigning means or an order correcting means when performing packet processing such as determination of a transfer destination of a variable length packet in parallel. In addition, it is useful for reducing the number of packet processing modules arranged in parallel.

It is a block diagram which shows the structure of the packet processing apparatus by Embodiment 1 of this invention. It is a time chart explaining operation | movement of the packet processing apparatus shown in FIG. It is a block diagram which shows the structure of the packet processing apparatus by Embodiment 2 of this invention. It is a block diagram which shows the structure of the packet processing apparatus by Embodiment 3 of this invention. It is a block diagram which shows the structure of the packet processing apparatus by Embodiment 4 of this invention.

Explanation of symbols

1, 10, 20, 30 Packet processing device 2,11 Packet information extraction unit 3a Packet delay circuit (fixed delay type)
3b Packet delay circuit (variable delay type)
4a, 4b Packet information insertion unit 5 Fixed-length cell unit 6, 12, 21, 31 Distributor (distribution means)
6a Distribution circuit 6b1 to 6bx Speed conversion circuit 7-1 to 7-x, 32-1 to 32-x Packet processing module 12a1 to 12ax buffer 13 Packet discard instruction signal 21a Priority determination circuit 21b1 to 21bx buffer 22 Threshold value 31a Compression code Insertion unit 31b Priority determination table

Claims (4)

In a packet processing device in which a plurality of packet processing modules that perform packet processing including determination of a transfer destination of a variable-length packet are arranged in parallel,
Packet information extracting means for extracting packet information required for performing the packet processing from the variable-length packets in the transfer process of the input packet stream;
Fixed-length cell forming means for generating a fixed-length cell by adding overhead to the packet information extracted by the packet information extracting means;
Distributing means for adjusting and distributing the fixed length cells generated by the fixed length cell converting means in order to the respective input speeds to a plurality of the packet processing modules arranged in parallel;
Fixed delay means for performing a delay process in consideration of a processing time from the fixed length cell converting means to the packet processing module to the packet stream input from the packet information extracting means;
Packet information insertion means for inserting information on transfer destinations determined by a plurality of the packet processing modules into corresponding packets input from the fixed delay means;
With
Each packet processing module sets the transfer destination information as a result of packet processing in the overhead included in the fixed-length cell, and sets the fixed-length cell in which the transfer destination information is set as the overhead to the packet information insertion unit Output to
A packet processing apparatus. In a packet processing device in which a plurality of packet processing modules that perform packet processing including determination of a transfer destination of a variable-length packet are arranged in parallel,
Extracts packet information required for performing the packet processing from each variable-length packet during the transfer process of the input packet stream, and discards the corresponding packet without transferring it in response to a packet discard instruction Packet information extraction means;
Fixed-length cell forming means for generating a fixed-length cell by adding overhead to the packet information extracted by the packet information extracting means;
The fixed-length cells generated by the fixed-length cell forming means are sequentially distributed to a plurality of buffers arranged in parallel with the plurality of packet processing modules arranged in a one-to-one relationship, and the corresponding buffers The packet processing module adjusts and outputs to each input speed, and controls waiting for temporary congestion caused by the processing of the fixed-length cell in the packet processing module. When a buffer overflow occurs, the packet discard instruction is issued. Distribution means to issue;
Variable delay means for holding each packet input from the packet information extraction means in the order of input until read out;
Packet information insertion means for receiving input of transfer destination information determined from a plurality of the packet processing modules and reading the corresponding packet from the variable delay means and inserting the transfer destination information;
With
Each packet processing module sets the transfer destination information as a result of packet processing in the overhead included in the fixed-length cell, and sets the fixed-length cell in which the transfer destination information is set as the overhead to the packet information insertion unit Output to
A packet processing apparatus.   The distribution means includes means for determining a priority from a predetermined display in the packet information included in the fixed-length cell, and means for monitoring a relationship between a threshold value determined in each buffer and an accumulation amount. 3. The packet processing apparatus according to claim 2, wherein when the amount exceeds a threshold, the packet discard instruction is issued by selecting a low priority packet. Each of the plurality of packet processing modules arranged in parallel comprises means for determining the priority of the packet from the fixed-length cell to be processed and outputting it in association with the fixed-length cell,
The distribution means includes storage means for associating and storing priorities output by a plurality of the packet processing modules and fixed-length cells, and means for monitoring a relationship between a threshold value and an accumulation amount set for each buffer. When the accumulated amount exceeds a threshold value, the storage unit is searched based on the fixed-length cell generated by the fixed-length cell unit, the low-priority packet is selected, and the packet discard instruction is issued The packet processing device according to claim 2.

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