JP2003037615A - Packet switch - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reconfigurable packet switch, with which an optimum circuit configuration can be automatically reconstructed in real time without requiring setting from the outside. SOLUTION: In this packet switch, the state of an inputted variable length packet is monitored by a packet length monitoring part 40, an optimum fixed packet length is automatically decided from the result by a fixed packet length instructing part 50, and the circuit of selector parts 10-1 to 10-N, fixed length packet switch parts 20-1 and 20-2 and output buffer parts 30-1 to 30-N is reconfigured.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a packet switch, and more particularly to a packet switch for switching variable length packets represented by IP (Internet Protocol) packets.

[0002]

2. Description of the Related Art Due to the recent popularity of the Internet, the traffic of packets flowing on the Internet is increasing rapidly. Along with this, high-speed, large-capacity packet switching technology is required.

The common bus system is widely adopted in conventional packet switches. However, since it is difficult to increase the capacity with this method, small-scale switch elements (4 × 4 ~
It is considered to increase the capacity by connecting multiple stages (Banyan connection) of 32 × 32). However, since internal blocking occurs in this method, as disclosed in 2000/11 Vol.J83-B No.11 "Large-capacity IP datagram switching method using multistage connection network" , A "pseudo variable length exchange" system has been proposed in which switching is performed after converting a variable length packet into a fixed length packet.

FIG. 7 is a block diagram showing the structure of the above-mentioned pseudo variable length exchange. The pseudo variable length exchange includes a selector unit 60, a fixed length packet switch unit 70 (n-plane configuration),
It is composed of an output buffer unit 80.

As shown in FIG. 8, the selector unit 60 includes a switch selection unit 61 and a fixed length packet conversion waiting buffer 6
2. The fixed-length packet conversion unit 63. The switch selection unit 61 reads the packet length from the header in the input variable length packet, selects the fixed packet length that is the smallest within the range where the variable length packet is not divided, and stores the variable length packet in the fixed length packet conversion waiting buffer 62. input. After that, the fixed-length packet conversion unit 63 reads out the variable-length packets in the fixed-length packet conversion waiting buffer 62 at fixed-length packet conversion times, converts them into fixed-length packets, and outputs them. During this conversion, dummy data is inserted in the empty area.

The fixed-length packet output from the selector unit 60 is input to the fixed-length packet switch unit 70 which processes the fixed packet length selected by the switch selection unit 61 in the selector unit 60, and is switched. The fixed-length packet switch unit 70 has a configuration in which small-scale switch elements 71 are connected in multiple stages as shown in FIG. 9, and each switch element operates in parallel, which is suitable for high-speed and large-capacity. It has become.

As shown in FIG. 10, the output buffer unit 80 is composed of a variable length packet conversion unit 81, a contention control waiting buffer 82, and a contention control unit 83. The fixed-length packet input from each fixed-length packet switch unit 70 is converted into the original variable-length packet by the variable-length packet conversion unit 81 and input to the contention control waiting buffer unit 82. After that, the contention control unit 83 performs contention control of the output port, and then sequentially reads from the contention control waiting buffer unit 82,
Is output.

[0008]

In the above-mentioned conventional technique, the fixed packet length switch 70 used for switching is selected according to the packet length of the input variable length packet. However, the packet length of the input variable length packet is selected. When the input frequency is uneven for each, there was a problem as described below.

First, the number of switch planes is two (n bytes,
In a pseudo variable length exchange consisting of 2n bytes),
When a large number of variable-length packets having a packet length of n + several bytes are input, the selector unit 60 selects the fixed packet length that is the smallest within the range in which the variable-length packet is not divided. However, the fixed packet switch 70 having a fixed packet length of 2n bytes is selected. As a result, there is a problem in that the load on the switch surface is biased and the throughput of the entire switch is reduced.

Further, when the packet is converted into the fixed length packet, many parts are filled with the dummy information, so that there is a problem that the throughput is lowered.

As a method of avoiding these problems, it is conceivable to increase the number of planes of the fixed-length packet switch unit 70, but since the circuit scale increases and problems such as power consumption, mounting area, and cost occur, the fixed-length packet switch unit 70 has a problem. The number of planes of section 70 should be minimized. For that purpose, it is necessary to select the optimum fixed packet length at the design stage in consideration of the input frequency for each packet length of the input packet. However, even if it is optimal in one specific usage pattern, it cannot be said that it is optimal in another usage pattern, so there is a problem that it is difficult to select the optimal fixed packet length in the design stage.

The present invention has been made in view of the problems of the above-mentioned conventional technique, and it is an object of the present invention to provide a packet switch that can always obtain an optimum throughput regardless of the usage pattern. To aim.

[0013]

The invention according to claim 1 is
A packet switch that is connected to a plurality of input ports and output ports and switches variable-length packets input from each input port and outputs the packets to a specific output port. A plurality of fixed length packet switch units each having a switch input port and a switch output port, each having a different fixed packet length, and each of the input ports,
The fixed packet length that is the smallest in the range in which the variable length packet received from the input port is not divided is selected, the variable length packet is converted to a fixed length packet, and the fixed length packet switch unit having the fixed packet length is output. A selector unit, an output buffer unit provided for each of the output ports, which receives a fixed-length packet output from the switch output port, converts the fixed-length packet into an original variable-length packet, and outputs the variable-length packet to the output port; A packet length monitoring unit that monitors the frequency of input of variable length packets input to the input port for each packet length and outputs a monitoring result, and an appropriate fixed packet length is automatically determined according to the monitoring result of the packet length monitoring unit. A fixed packet length instruction for changing the fixed packet lengths of the packet switch unit, the selector unit, and the output buffer unit. Characterized by including the.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment relating to the packet switch of the present invention. FIG. 2 is a block diagram showing a configuration of a packet switch before reconfiguration having four input ports and four output ports and two switch planes of 750 bytes and 1500 bytes. FIG. 3 is an explanatory diagram showing an example of variable-length packets and fixed-length packets input / output by the packet switch before reconfiguration. FIG. 4 is a graph showing the monitoring result of the packet length monitoring unit of FIG. FIG. 5 is a block diagram showing the configuration of the packet switch after reconfiguration.
FIG. 6 is an explanatory diagram showing an example of variable-length packets and fixed-length packets that are input / output by the reconfigured packet switch of FIG.

As shown in FIG. 1, the packet switch of the present embodiment selects a fixed packet length that is the smallest within the range in which the variable length packet is not divided based on the packet length of the input variable length packet. Fixed-length packet switch units 20-1 and 20-2 for switching fixed-length packets with a configuration in which selector units 10-1 to N for packetizing and small-scale switch elements are connected in multiple stages, and fixed-length packet switch unit 20. -1, 20-2 is provided with output buffer units 30-1 to 30-N that convert fixed-length packets input to variable-length packets to original variable-length packets and perform output port contention control, and further monitor the input packet length. Packet length monitor 40 for counting the input frequency for each packet length, selectors 10-1 to 10-N, fixed length packet switch 20-
1, 20-2, fixed packet length instruction unit 5 which issues an instruction of fixed packet length to be processed to the output buffer units 30-1 to 30-N
It is characterized by having 0.

The fixed packet length instructing unit 50 is inserted when the load on each switch plane is distributed based on the input frequency information for each packet length input from the packet length monitoring unit 40 and fixed length packetization is performed. The fixed packet length that minimizes the dummy information to be automatically determined, and the selector unit 10
-1 to N, fixed-length packet switch units 20-1, 20-
2. Send an instruction to the output buffer units 30-1 to 30-N.

The selector units 10-1 to 10-N, the fixed-length packet switch units 20-1 and 20-2, and the output buffer units 30-1 to 30-N are composed of dynamically reconfigurable devices. According to the instruction from the length instruction unit 50, the fixed packet length to be processed is changed by reconfiguring the circuit. A specific example of the dynamically reconfigurable device is, for example, an FPGA (Field Programmable Gate Arra).
y), PLD (Programmable Logic Devices) and the like.

Next, the operation of this embodiment will be described with reference to FIGS.
Will be described with reference to.

FIG. 2 is a block diagram showing the configuration of a packet switch before reconfiguration having four input ports and four output ports and two switch planes of 750 bytes and 1500 bytes.

Fixed length packet switch # 1 20-1
Is a packet switch for switching a fixed length packet of 750 bytes, and the fixed length packet is input 4
It has one switch input port and four switch output ports for outputting the switched fixed length packets.

Fixed length packet switch # 2 20-2
Is a packet switch for switching fixed-length packets of 1500 bytes, and has four switch input ports for inputting fixed-length packets and four switch output ports for outputting switched fixed-length packets.

The selector units 10-1 to 10-4 are connected to the input port 1
Input port 1 is provided corresponding to 00 to 400.
The fixed-length packet switch # 1 20-1 and the fixed-length packet size # 2 20-2 having a length that can accommodate the variable-length packet without dividing the variable-length packet are referred to by referring to the packet length of the variable-length packet input from 00 to 400. Choose one,
The dummy information is added to the variable-length packet to convert it into a fixed-length packet, the contention control is performed, and then the variable-length packet is output.

The output buffer units 30-1 to 30-4 are provided corresponding to the output ports 500 to 800, and switch output ports of the fixed length packet switch # 1 20-1 and the fixed length packet switch # 2 20-2. After receiving the fixed length packets of 750 bytes and 1500 bytes output from the device, converting them to the original variable length packets and performing the contention control, the variable length packets are output to the output ports 500 to 80.
Output to 0.

The packet length monitor 40 is provided for the input port 10
The packet length of the variable length packet input from 0 to 400 is monitored, and the monitoring result is output.

The fixed packet length instruction unit 50 determines the optimum fixed packet length based on the monitoring result from the packet length monitoring unit 40, and the fixed length packet switch unit # 1 20-
1, the fixed-length packet switch unit # 2 20-2, the selector units 10-1 to 10-4, and the output buffer units 30-1 to 30-4 are instructed to reconfigure the circuit.

The selector units 10-1 to 10-4, the fixed length packet switch unit # 1 20-1, the fixed length packet switch unit # 2 20-2, and the output buffer units 30-1 to 30-4 can be reconfigured. The device is used.

Next, the operation of the packet switch shown in FIG. 2 will be described. When the variable-length packet shown in FIG. 3A is input to the input port 100 shown in FIG. 2 at a certain time t, the selector unit 10-1 has a fixed minimum value in the range in which the variable-length packet is not divided. In order to select the long packet switch, all the packets No1 to No4 select the fixed packet switch # 2 20-2 having the fixed packet length of 1500 bytes. No1 to No
The variable-length packet of No. 4 is converted into a fixed-length packet of 1500 bytes by adding a dummy byte as shown in FIG. It is output to the output port 600 after being competitively controlled by.

The packet length monitor 40 monitors the input frequency for each packet length of the packets input within the packet length monitoring cycle. In FIG. 4, No1 to No1 input at time t
The monitoring result after packet processing of No. 4 is shown. In this example, the number of inputs for each packet length is counted in units of 10 bytes, but the minimum unit to monitor may be arbitrary.

The fixed packet length instructing unit 50 determines 750 bytes and 15 bytes based on the packet length monitoring result shown in FIG.
Two switch plane configuration of 00 bytes, 760 bytes
By changing the switch plane configuration to two switch planes of e and 1500 bytes, it is automatically determined that the load of each switch plane is distributed and the dummy information inserted when packetized into a fixed length is minimized, and the selector unit 10-1 To 4, fixed length packet switch unit # 120-1, output buffer unit 30-
Instructs 1 to 4 to perform circuit reconfiguration.

Selector units 10-1 to 10-4, fixed length packet switch unit # 1 20-1, output buffer units 30-1 to 30-1
4 reconfigures the circuit according to the fixed packet length change instruction from the fixed packet length instruction unit 50.

FIG. 5 shows selector sections 10-1 to 10-4 of FIG.
The fixed length packet switch unit # 1 20-1 and the output buffer units 30-1 to 30-4 follow the instructions from the fixed packet length instruction unit 50, and 10-1 'to 4', 20-1 ', and 3 respectively.
The reconstructed state is shown in 0-1 'to 4'. In this state, the input port 100 shown in FIG.
When the variable-length packet shown in (a) is input, the selector unit 10-1 ′ selects the fixed packet length that is the smallest in the range in which the variable-length packet is not divided.
The fixed packet length of No. 5, No. 6 and No. 8 packets is 76
0-byte fixed length packet switch # 1 20-1 '
Is selected, the fixed packet length of the No. 7 packet is 150
The 0-byte fixed length packet switch # 2 20-2 is selected. The variable length packets of No5 to No8 are shown in FIG.
After being converted into the fixed length packet shown in (b) and (c), switching is performed by the fixed length packet switches # 1 and # 2,
After the contention control is performed by the output buffer unit 30-2 ′, the data is output to the output port 600.

As described above, in this embodiment, the load on the switch surface is distributed, and the dummy information inserted when the packet is converted into a fixed length packet is also reduced.

[0033]

As described above, according to the present invention,
The input frequency for each packet length of the input packet is monitored, and the fixed packet length optimal for switch processing is automatically determined from the monitoring result and the fixed packet length is switched, so it responds in real time to the usage pattern of the device and is always optimal. It is possible to obtain high throughput.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment relating to a packet switch of the present invention.

FIG. 2 shows that both input ports and output ports are 4
FIG. 3 is a block diagram showing a configuration of a packet switch before reconfiguration having two switch planes of 750 bytes and 1500 bytes.

FIG. 3 is an explanatory diagram showing an example of variable-length packets and fixed-length packets that are input and output by the packet switch before reconfiguration.

FIG. 4 is a graph showing a monitoring result in the packet length monitoring unit of FIG.

FIG. 5 is a block diagram showing a configuration of a packet switch after reconfiguration.

6 is an explanatory diagram showing an example of variable-length packets and fixed-length packets that are input / output by the packet switch after the reconfiguration of FIG.

FIG. 7 is a block diagram showing a configuration of a conventional pseudo variable length exchange.

FIG. 8 is a block diagram showing a configuration of a selector unit 60.

FIG. 9 is a block diagram showing a configuration of a fixed length packet switch unit 70.

FIG. 10 is a block diagram showing a configuration of an output buffer section 80.

[Explanation of symbols]

10-1 to 4, 10-N, 60 selector section 20-1, 20-2, 70 fixed length packet switch section 30-1 to 4, 30-N, 80 output buffer section 40 packet length monitoring section 50 fixed packet length Instructing unit 61 Switch selecting unit 62 Fixed length packet conversion waiting buffer 63 Fixed length packet converting unit 71 2 × 2 switch element 81 Variable length packet converting unit 82 Contention control waiting buffer 83 Contention control unit

Claims (3)

[Claims] 1. A packet switch connected to a plurality of input ports and an output port, for switching a variable length packet input from each input port and outputting it to a specific output port, wherein the plurality of input ports and the plurality of outputs are provided. A plurality of fixed-length packet switch units having a plurality of switch input ports and switch output ports corresponding to the ports, each having a different fixed packet length, and a variable-length packet received from the input port provided for each input port. A selector unit that selects a fixed packet length that is the smallest in the range that is not divided, converts the variable-length packet to a fixed-length packet, and outputs the fixed-length packet switch unit that has the fixed packet length, and a selector unit for each output port The fixed-length packet output from the switch output port is received and the original An output buffer unit that converts the variable-length packets to output to the output port, and a packet-length monitoring unit that monitors the input frequency for each packet length of variable-length packets input to the plurality of input ports and outputs the monitoring result And a fixed packet length instruction unit that automatically determines an appropriate fixed packet length according to the monitoring result of the packet length monitoring unit and changes the fixed packet length of the packet switch unit, the selector unit, and the output buffer unit. A packet switch characterized by being provided. 2. The packet switch unit, the selector unit, and the output buffer unit are an FPGA (Field Prog).
The packet switch according to claim 1, wherein the packet switch is formed of a rammable gate array. 3. The packet switch unit, the selector unit, and the output buffer unit are PLD (Programmable).
The packet switch according to claim 1, wherein the packet switch is configured with Logic Devices).