JP5406634B2 - Operational amplifier - Google Patents

Description

  The present invention relates to an operational amplifier with an increased slew rate.

  In an operational amplifier, it is ideal to have a high-speed and highly stable pulse response characteristic. In general operational amplifiers, a phase compensation capacitor is provided to ensure stability in the feedback circuit. To increase the speed, the capacitance of the capacitor is reduced or the current flowing through the capacitor is reduced. Need to increase. However, if it is attempted to increase the speed by these methods, the stability of the operational amplifier decreases.

  FIG. 9 shows a configuration example of the operational amplifier 10 shown in FIG. This operational amplifier amplifies the difference between the voltage signals input between the non-inverting input terminal IN + and the inverting input terminal IN− within the voltage range of the high-voltage power supply line V + and the low-voltage power supply line V−. A differential amplifier circuit that outputs a voltage signal as a voltage, a high-impedance voltage amplifier Gm that amplifies and outputs a single-phase voltage signal, and a buffer for outputting the amplified voltage signal to the output terminal OUT with a low output impedance The circuit BF is composed of a phase compensation capacitor Cc that increases the phase margin by creating a pole in the frequency characteristic of the amplified voltage signal and maintains the stability of the operational amplifier when the feedback circuit is configured.

  Here, Q1 and Q2 are PNP type transistors, Q3 and Q4 are NPN type transistors, CS1 is a constant current source of current I1, and the transistors Q1 and Q2 and the constant current source CS1 constitute a differential circuit. Q3 and Q4 constitute a current mirror circuit as an active load. These transistors Q1 to Q4 and the constant current source CS1 constitute a differential amplifier circuit.

  As shown in FIG. 2, the operational amplifier configured as described above is directly connected between the inverting input terminal IN− and the output terminal OUT to form a voltage follower, and the normal rotation in which the low voltage VL is input. The operation when a pulse signal of the high voltage VH (> VL) is input to the input terminal IN + will be described.

このスルーレートＳＲの値が大きいほど、パルス応答速度が速い。 Initially, the terminals IN + and IN− are at the same potential at the voltage VL. Next, when the voltage VH is applied to the terminal IN + at an arbitrary pulse rising speed, the transistor Q1 is turned off and the transistor Q2 is turned on, so that all the current I1 flowing from the constant current source CS1 flows to the transistor Q2. The current I1 is mirrored by a current mirror circuit constituted by the transistors Q3 and Q4, and the value of the collector current IC3 of the transistor Q3 becomes I1. Here, since the transistor Q1 is in the OFF state, the collector current of the transistor Q1 is zero. Since the voltage amplifier Gm has a high input impedance, the collector current IC3 becomes a current drawn from the capacitor Cc, charges the capacitor Cc, and raises the potential at the point P. Since the buffer circuit BF is configured from the point P to the output terminal OUT, the output voltage VOUT, which is the potential of the output terminal OUT, also rises following the potential at the point P. At this time, the potential at the point P and the output voltage VOUT reach the voltage VH at a certain speed. This speed is also called a slew rate SR as a pulse response speed, and is defined by the following equation in which the current I1 charges the capacitor Cc.

The larger the value of the slew rate SR, the faster the pulse response speed.

  In the prior art, a method of increasing the value of the current I1 or decreasing the value of the capacitor Cc has been used to increase the slew rate SR with reference to the equation (1). However, when the slew rate SR is increased by the above-described method, there is a problem that the phase margin, which is an index of stability of the operational amplifier, is decreased, the output voltage VOUT is oscillated, and the operation stability is impaired.

  A circuit that solves this problem and increases the slew rate without impairing the stability of the operational amplifier is described in FIGS. The slew rate increasing circuit of FIG. 1 is composed of two differential pairs including a current source and a current mirror circuit. A feature of this slew rate increasing circuit is that a diode is connected to the emitter of one transistor of each differential pair connected to each input terminal. The potential difference Vdif between the input terminals is detected by this unbalanced differential pair. The output of the current mirror circuit is connected to the emitter common connection point of the differential amplifier circuit of the operational amplifier.

  As a result, when the potential difference Vdif between the input terminals exceeds about 0.5 V, additional current starts to be supplied to the differential amplifier circuit, and the slew rate is increased by increasing the current for charging the capacitor Cc. Further, when the potential difference Vdif between the input terminals is less than about 0.5 V, no current is supplied from the slew rate increasing circuit to the differential amplifier circuit, so that the stability of the operational amplifier is not impaired.

Japanese Patent No. 2812103

  In the conventional operational amplifier described with reference to FIG. 9, if the current I1 is increased or the capacitor Cc is decreased in order to increase the slew rate with reference to the equation (1), the stability of the operation is impaired. there were. Further, in FIG. 1 and FIG. 2 of Patent Document 1 for improving this problem, in addition to the conventional operational amplifier, a differential pair and a current mirror circuit including six transistors, two diodes, and two constant current sources are used. There is a disadvantage that the circuit scale becomes large.

  An object of the present invention is to provide an operational amplifier having a small circuit scale and an increased slew rate while maintaining the stability of the circuit.

To achieve the above object, an operational amplifier according to a first aspect of the present invention includes an emitter of a first transistor having a base connected to a first input terminal and a base connected to a second input terminal. A differential amplifier circuit in which an emitter of a second transistor of the same conductivity type as that of the first transistor is commonly connected to a first constant current source, and collectors of the first and second transistors are connected to a load; when the potential of the input terminal of the absence et a high first predetermined value or more than the potential of the emitter of the first transistor supplying a first current to be subtracted with respect to the current by the first constant current source characterized by and a first subtraction current supply circuit to stop the supply of the first predetermined value or more becomes higher when the first current.

The invention according to claim 2, in the operational amplifier according to claim 1, when the potential of the second input terminal is a second no al a higher than a predetermined value with respect to the emitter potential of said second transistor second current supply, the second predetermined value or more becomes higher when the second subtraction current supply circuit to stop the supply of the second current subtracted from the current by the first constant current source It is characterized by providing.

According to a third aspect of the present invention, in the operational amplifier according to the first aspect, the first subtracting current supply circuit has a second constant emitter connected to the emitter of the two transistors of the opposite conductivity type to the first transistor. Commonly connected to a current source, the base of one of the two transistors is connected to the base of the first transistor, the collector is connected to a power supply terminal, and the base and collector of the other transistor are connected to the first transistor and wherein the Rukoto such connected to the emitter of the transistor.

Such invention in claim 4, in the operational amplifier according to claim 2, wherein the second subtraction current supply circuit comprises a second transistor the emitter of the two transistors of opposite conductivity type third constant Commonly connected to a current source, the base of one of the two transistors is connected to the base of the second transistor, the collector is connected to a power supply terminal, and the base and collector of the other transistor are connected to the second transistor and wherein the Rukoto such connected to the emitter of the transistor.

According to a fifth aspect of the present invention, in the operational amplifier according to any one of the first to fourth aspects, the transistor is replaced with a MOS transistor, the base is used as a gate, the emitter is used as a source, and the collector is used as a drain. It is characterized by the replacement .

  According to a sixth aspect of the present invention, in the operational amplifier according to the second aspect, the second addition current supply circuit is configured such that the emitters of two transistors having the same conductivity type as the second transistor are connected to a third constant current. And the base of one of the two transistors is connected to the base of the second transistor, the collector is connected to a power supply terminal, and the base and collector of the other transistor are connected to the second transistor. It is characterized by being connected to the emitter.

  According to a seventh aspect of the present invention, in the operational amplifier according to the first aspect, the first addition current supply circuit uses two constant current emitters of two transistors having the same conductivity type as the first transistor. The base of one of the two transistors is connected to the base of the first transistor, the collector is connected to the power supply terminal, and the base of the other transistor is connected to the emitter of the first transistor. And a collector connected to the collector of the second transistor.

  According to an eighth aspect of the present invention, in the operational amplifier according to the second aspect, the second addition current supply circuit is configured such that the emitters of two transistors having the same conductivity type as the second transistor are connected to a third constant current. The base of one of the two transistors is connected to the base of the second transistor, the collector is connected to the power supply terminal, and the base of the other transistor is connected to the emitter of the second transistor. And a collector connected to the collector of the first transistor.

  According to a ninth aspect of the present invention, in the operational amplifier according to the third aspect, the first subtracting current supply circuit has a second constant emitter connected to the emitters of two transistors of the conductivity type opposite to the first transistor. Commonly connected to a current source, the base of one of the two transistors is connected to the base of the first transistor, the collector is connected to a power supply terminal, and the base and collector of the other transistor are connected to the first transistor It is characterized by being connected to the emitter of a transistor.

  According to a tenth aspect of the present invention, in the operational amplifier according to the fourth aspect, the second subtracting current supply circuit has a third constant emitter connected to the emitters of two transistors having opposite conductivity types to the second transistor. Commonly connected to a current source, the base of one of the two transistors is connected to the base of the second transistor, the collector is connected to a power supply terminal, and the base and collector of the other transistor are connected to the second transistor It is characterized by being connected to the emitter of a transistor.

  An operational amplifier according to an eleventh aspect of the present invention is the operational amplifier having the same conductivity type as that of the first transistor, the emitter of the first transistor having the base connected to the first input terminal and the base connected to the second input terminal. A first differential amplifier circuit in which the emitters of the two transistors are connected to a first constant current source, and the collectors of the first and second transistors are connected to a first load; and the second input terminal The base is connected to the emitter of the third transistor having the opposite conductivity type to the first transistor, and the emitter of the fourth transistor having the same conductivity type as the third transistor having the base connected to the first input terminal. Are connected to a fourth constant current source, and the collectors of the third and fourth transistors are connected to a second load, and the potential of the second input terminal is the second 2 A first addition current supply circuit for supplying a first current to be added to the current from the first constant current source when the potential becomes higher than the first predetermined value by the potential of the emitter of the transistor. And

  According to a twelfth aspect of the present invention, in the operational amplifier according to the eleventh aspect, when the potential of the second input terminal becomes lower than the potential of the emitter of the third transistor by a second predetermined value or more, And a second addition current supply circuit for supplying a second current to be added to the current from the constant current source.

  According to a thirteenth aspect of the present invention, in the operational amplifier according to any one of the first to twelfth aspects, the transistor is replaced with a MOS transistor, the base is used as a gate, the emitter is used as a source, and the collector is used as a drain. It is characterized by the replacement.

  According to the present invention, since the operating current of the differential amplifier circuit temporarily increases only when the input voltage transitions, the slew rate can be increased without impairing the stability of the operation. The number of elements required to obtain this characteristic is only two transistors and one constant current source when applied to either rising or falling, and double that when applying to both rising and falling. There are only four transistors and two constant current sources. Therefore, the number of elements can be greatly reduced (decrease by 4 elements when applied to rising and falling) than the countermeasure described in Patent Document 1, and the circuit scale can be reduced.

1 is a circuit diagram illustrating an operational amplifier according to a first embodiment of the present invention. It is the circuit diagram which comprised the operational amplifier of each Example and the prior art example as a voltage follower. FIG. 3 is a time-varying characteristic diagram of each input and output voltage when the operational amplifiers of the embodiments and the conventional example are operated with the voltage follower configuration of FIG. 2. FIG. 3 is a characteristic diagram of time variation of slew rate when the operational amplifiers of the embodiments and the conventional example are operated with the voltage follower configuration of FIG. 2. It is a circuit diagram which shows the operational amplifier of the 2nd Example of this invention. It is a circuit diagram which shows the operational amplifier of the 3rd Example of this invention. It is a circuit diagram which shows the operational amplifier of the 4th Example of this invention. It is a circuit diagram which shows the 5th Example of this invention. It is a circuit diagram of a conventional operational amplifier.

<First embodiment>
FIG. 1 shows an operational amplifier 10A of the first embodiment. A circuit configuration of the operational amplifier 10A of the present embodiment will be described. However, the same components as those described in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted. In this embodiment, PNP transistors QA1, QA2, QA3, QA4 and constant current sources CS2, CS3 are further added to the operational amplifier 10 described in FIG.

  The transistor QA1 has a base connected to the normal input terminal IN +, a collector connected to the low voltage power supply line V-, and an emitter connected to the constant current source CS2. The transistor QA2 has a base and a collector connected to the emitters of the transistors Q1 and Q2, and an emitter connected to the constant current source CS2. The transistor QA3 has a base connected to the inverting input terminal IN−, a collector connected to the low voltage power supply line V−, and an emitter connected to the constant current source CS3. The transistor QA4 has a base and a collector connected to the emitters of the transistors Q1 and Q2, and an emitter connected to the constant current source CS3. The current of the constant current source CS2 is I2, and the current of the constant current source CS3 is I3. The current values of the currents I2 and I3 may be I2 = I3 or I2 ≠ I3. The input stage of the operational amplifier 10A of this embodiment is composed of the transistors Q1, Q2, QA1 to QA4 and the constant current sources CS1 to CS3. Transistors Q3 and Q4 function as an active load in a current mirror circuit configuration, and the configuration from the active load to the output terminal OUT is the same as that in FIG.

  The relationship between the first, second, fifth and sixth embodiments and the present embodiment is that the differential amplifier circuit corresponds to a circuit comprising transistors Q1 to Q4 and a constant current source CS1, and the first addition current supply circuit is the transistors QA1, QA2. The second addition current supply circuit corresponds to a circuit composed of transistors QA3 and QA4 and a constant current source CS3.

  The number of additional elements in the present embodiment is a total of six elements including four transistors and two constant current sources. In Patent Document 1, it is necessary to add at least 10 elements in order to increase the slew rate. Therefore, the slew rate can be increased with the number of additional elements which is four elements less in the present embodiment, so that the circuit can be reduced in size.

  As shown in FIG. 2, the operational amplifier 10A configured as described above is connected to the inverting input terminal IN− and the output terminal OUT to form a voltage follower, and the normal rotation in which the low voltage VL is input. The operation when the pulse signal of the high voltage VH is input to the input terminal IN + is shown in FIG. 3 as the time variation of the potential VIN + of the normal input terminal IN +, the potential VIN− of the inverting input terminal IN−, and the output voltage VOUT. This will be described using a change in the slew rate SR of 4 with time. In FIGS. 3 and 4, the solid line represents the characteristic of this embodiment, and the broken line represents the characteristic of the conventional example of FIG.

  First, at times t0 to t1, the input voltages VIN + and VIN− are at the same potential VL. At this time, in the differential pair of the transistors QA1 and QA2, QA1 is in the on state and QA2 is in the off state. All the current I2 flowing from the constant current source CS2 flows to the transistor QA1, and the current I2 is supplied to the emitters of the transistors Q1 and Q2. Not. Similarly, in the differential pair of the transistors QA3 and QA4, the transistor QA3 is on and the transistor QA4 is off. All the current I3 flowing from the constant current source CS3 flows to the transistor QA3, and the current flows to the emitters of the transistors Q1 and Q2. I3 is not supplied. Therefore, the state of the differential amplifier circuit from time t0 to t1 is the same as in the conventional example, and the stability of the operational amplifier 10A is also the same as in the conventional example.

Next, the voltage VH is applied to the normal input terminal IN + at an arbitrary pulse rising speed at time t1, and the potential difference Vdif between the input terminals of the normal input terminal IN + and the inverted input terminal IN− is about 0.5 V at time t2. The state until reaching is explained. This about 0.5 V is a potential difference obtained from the following equation, where the current I2 flowing in the transistor QA1 of the differential amplifier circuit starts flowing in the transistor QA2.

Here, V _BEQ2 is a potential difference between the base and emitter of the transistor Q2, which is about 0.6V, and V _t (= kT / q) is a thermal potential, which is about 0.026V. Between times t1 and t2, the transistor Q1 is turned off, the transistor Q2 is turned on, and all the current I1 flowing from the constant current source CS1 flows to the transistor Q2. Further, the states of the transistors QA1 and QA2, and the transistors QA3 and QA4 are not different from the state from time t0 to t1. Therefore, the collector current IC4 of the transistor Q4 = I1 and the current IC4 is mirrored on the transistor Q3, so that the collector current IC3 of the transistor Q3 is “IC3 = I1”. The slew rate at this time is the same as that of the conventional example as shown in FIG. 4 and is expressed by the equation (1).

When the potential difference Vdif between the input terminals becomes larger than about 0.5 V at time t2, the current I2 starts to flow through the transistor QA2, and the current I2 starts to be supplied to the differential amplifier circuit. Thereafter, when the potential difference Vdif between the input terminals becomes about 0.7 or more, all the current I2 is supplied to the differential amplifier circuit through the transistor QA2. This about 0.7V is a value obtained from the following equation.

On the other hand, there is no change in the state of the differential pair of transistors QA3 and QA4. The transistors Q1 and Q2 are in the off state, while the transistor Q1 is still in the off state, whereas the current I1 and the current 12 supplied from the transistor QA2 flow through the transistor Q2. Therefore, the collector current IC4 of the transistor Q4 is “IC4 = I1 + I2”. Here, since the transistors Q3 and Q4 have a current mirror configuration, the collector current IC3 of the transistor Q3 is also “IC3 = I1 + I2.” The slew rate at this time is expressed by the following equation.

  The slew rate represented by this equation is a value that is larger by I2 / Cc than the slew rate of equation (1), which is a conventional example. Therefore, the rising of the pulse of the output voltage VOUT becomes steep as shown in FIG. 3, and the slew rate increases as shown by the solid line in FIG. On the other hand, as shown by the broken line in FIG. 4, since the current I2 is not supplied in the conventional example, the slew rate is the same as before time t2.

  Next, an operation when the potential difference Vdif between the input terminals becomes smaller than about 0.5 V at time t3 will be described. At this time, in the differential pair of the transistors QA1 and QA2, the transistor QA1 is turned on, the transistor QA2 is turned off, all the current I2 flows to the transistor QA1, and the current I2 is not supplied to the differential amplifier circuit. On the other hand, there is no change in the state of the differential pair of transistors QA3 and QA4. Further, the current I1 flows through the transistor Q2 while the transistor Q1 remains off. Therefore, the collector current IC4 of the transistor Q4 is “IC4 = I1”. The slew rate at this time is the same as that in the conventional example, and is expressed by Expression (1). Thereafter, at time t4, the normal rotation input voltage VIN + and the output voltage VOUT become the same potential VH. On the other hand, since the slew rate does not increase in the conventional example, the normal input voltage VIN + and the output voltage VOUT become the same potential VH at time t5 later than the present example.

Next, an operation when a pulse signal of the low voltage VL is input to the normal input terminal IN + to which the high voltage VH has been input will be described. A state in which the voltage VL is applied to the terminal IN + at an arbitrary pulse falling speed at time t6 and the potential difference Vdif between the input terminals reaches about 0.5 V at time t7 will be described. This about 0.5 V is the potential difference Vdif between the input terminals at which the current I3 begins to flow through the transistor _QA4 , and is expressed by the equation in which the voltage V _BEQ2 in equation (2) is replaced with the potential difference V _BEQ1 between the base and emitter of the transistor Q1. The

  Between times t6 and t7, the transistor Q1 is in the on state and Q2 is in the off state, and all the current I1 flows through the transistor Q1. The states of the transistors QA1 and QA2, and the transistors QA3 and QA4 are not changed from the state at time t3. Here, since the transistor Q2 is in the off state, no current flows through the transistor Q2, and no current flows through the transistor Q4. Since the transistors Q3 and Q4 have a current mirror configuration, no current flows through the transistor Q3, and the collector current IC1 (= I1) of the transistor Q1 flows into the capacitor Cc. As a result, the potential at the point P decreases, and the output voltage VOUT also starts to decrease following the potential at the point P. This state is shown in the waveform of the output voltage VOUT between times t6 and t7 in FIG. The slew rate at this time is the same as that in the conventional example, and is expressed by Expression (1).

When the potential difference Vdif between the input terminals becomes larger than about 0.5 V at time t7, the current I3 starts to flow to the differential amplifier circuit through the transistor QA4. Thereafter, when the potential difference Vdif between the input terminals becomes larger than about 0.7 V, all the current I3 flows through the transistor QA4 to the differential amplifier circuit. This value of about 0.7V is represented by the formula by replacing V _BEQ2 of formula (3) in V _BEQ1. On the other hand, there is no change in the state of the differential pair of transistors QA1 and QA2. Since the current I3 flows through the differential amplifier circuit, the currents I1 and I3 flow through the transistor Q1.

On the other hand, the transistor Q2 remains off and no current flows. Further, the states of the transistors Q3 and Q4 remain unchanged, and no current flows through the transistors Q3 and Q4. Therefore, current “I1 + I3” flows into capacitor Cc, and the slew rate at this time is expressed by the following equation.

  The slew rate represented by this formula is a value that is larger by I3 / Cc than the formula (1) that is the conventional example. Therefore, the trailing edge of the pulse becomes steep as shown in FIG. 3, and the slew rate increases as shown by the solid line in FIG. Further, as indicated by the broken line in FIG. 4, since the conventional example does not supply I3, the slew rate is the same as that before time t7.

Next, an operation when the potential difference Vdif between the input terminals becomes smaller than about 0.5 V at time t8 will be described. At this time, in the differential pair of the transistors QA3 and QA4, the transistor QA3 is turned on and the transistor QA4 is turned off, and all the current I3 flows to the transistor QA3, and the current I3 is not supplied to the differential amplifier circuit. On the other hand, there is no change in the state of the differential pair of transistors QA1 and QA2. Further, the current I1 flows through the transistor Q1, and the transistor Q2 continues to be in the off state, so that no current flows. Therefore, the current I1 flows through the capacitor Cc. Therefore, the slew rate at this time is the same as the conventional example. Thereafter, at time t9, the voltages VIN + and VOUT at the normal rotation input terminal become the same potential VL. On the other hand, since the slew rate does not increase conventionally, the voltages VIN + and VOUT at the normal input terminal become the same potential VL at time t10 later than the present embodiment.

  In addition, when the potential difference Vdif between the input terminals is less than about 0.5 V, the currents I2 and I3 are not additionally supplied to the differential amplifier circuit. Therefore, the current flowing through the differential amplifier circuit is the same as the conventional example. Keep the stability of the same operational amplifier.

  Note that the transistor of the operational amplifier shown in the first embodiment can be reversed between the PNP type and the NPN type. In that case, the constant current sources CS1, CS2, and CS3 are connected to the low voltage power supply line V−. Further, the collectors of the transistors QA1 and QA3 connected to the low voltage power supply line V- are connected to the high voltage power supply line V +.

<Second embodiment>
FIG. 5 shows an operational amplifier 10B of the second embodiment. A circuit configuration of the operational amplifier 10B of the present embodiment will be described. However, the same components as those described in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted. This embodiment is characterized by the addition of NPN transistors QB1, QB2, QB3, QB4 and constant current sources CS2, CS3.

  The transistor QB1 has a base connected to the normal input terminal IN +, a collector connected to the high voltage power supply line V +, and an emitter connected to the constant current source CS2. The transistor QB2 has a base and a collector connected to the constant current source CS1, and an emitter connected to the constant current source CS2. The transistor QB3 has a base connected to the inverting input terminal IN-, a collector connected to the high voltage power supply line V +, and an emitter connected to the constant current source CS3. The transistor QB4 has a base and a collector connected to the constant current source CS1, and an emitter connected to the constant current source CS3. The input stage of the operational amplifier 10B of this embodiment is composed of the transistors Q1, Q2, QB1 to QB4 and the constant current sources CS1 to CS3. Q3 and Q4 function as active loads in the current mirror circuit configuration, and the configuration from the active load to the output terminal OUT is the same as that in FIG.

  The relationship between the third, fourth, ninth and tenth embodiments and the present embodiment is that the differential amplifier circuit corresponds to a circuit comprising transistors Q1 to Q4 and a constant current source CS1, and the first subtracting current supply circuit is the transistor QB1, The second subtracting current supply circuit corresponds to a circuit including transistors QB3 and QB4 and a constant current source CS3.

  The number of additional elements in the present embodiment is a total of six elements including four transistors and two constant current sources. On the other hand, in Patent Document 1, it is necessary to add at least 10 elements in order to increase the slew rate. Therefore, the slew rate can be increased with the number of additional elements which is four elements less in the present embodiment, so that the circuit can be reduced in size.

  The circuit operation of the present embodiment will be described. The operational amplifier 10B of the second embodiment configured as described above is connected as shown in FIG. When the potential difference Vdif between the input terminals is less than about 0.5 V, the sum of the currents flowing through the differential amplifier circuit including the transistors Q1 to Q4 is “I1-I2-I3”. The reason why the currents I2 and I3 are subtracted from the current I1 is that the currents I2 and I3 flow out of the differential amplifier circuit because the transistors QB2 and QB4 are on. A value of about 0.5 V was obtained from equation (2).

  Next, when the potential of the non-inverting input terminal IN + becomes higher than the potential of the inverting input terminal IN− by about 0.5 V or more, a current starts to flow through the transistor QB1. Since the sum of the currents flowing through the transistors QB1 and QB2 is constant at I2, the current flowing out from the differential amplifier circuit through the transistor QB2 starts to decrease. Further, when the potential difference is about 0.7 V or more, current I2 flows through transistor QB1, and therefore current I2 does not flow from the differential amplifier circuit through transistor QB2. Here, the value of about 0.7 V is obtained from the equation (3). Therefore, the sum of the currents flowing through the differential amplifier circuit is “I1-I3”. This is a current value larger by I2 than when the potential difference Vdif between the input terminals is less than about 0.5V. Since the current flowing through the differential amplifier circuit increases in this way, the slew rate increases, and the rise of the pulse becomes steep as shown in FIG.

  Next, the operation when the input pulse falls will be described. When the potential of the non-inverting input terminal IN + becomes lower than the potential of the inverting input terminal IN− by about 0.5 V or more, current starts to flow through the transistor QB3, and thus the current flowing out from the differential amplifier circuit through the transistor QB4 starts to decrease. Further, when this potential difference is about 0.7 V or more, current I3 flows through transistor QB3, so that current I3 does not flow out from the differential amplifier circuit through transistor QB4. Therefore, the sum of the currents flowing through the differential amplifier circuit is “I1−I2”. This is a current value that is I3 more than in the steady state. Since the current flowing through the differential amplifier circuit increases in this way, the slew rate increases, and the falling of the pulse becomes steep as shown in FIG.

  The transistor of the operational amplifier shown in the second embodiment can be reversed between the PNP type and the NPN type. In this case, the constant current source CS1 is connected to the low voltage power supply line V−, and the constant current sources CS2 and CS3 are connected to the high voltage power supply line V +. The collectors of the transistors QB1 and QB3 connected to the high voltage power supply line V + are connected to the low voltage power supply line V-.

<Third embodiment>
FIG. 6 shows an operational amplifier 10C of the third embodiment. The operational amplifier 10C of the third embodiment is a modification of the operational amplifier 10A shown in the first embodiment. The collector of the transistor QA2 is connected to the collectors of the transistors Q2 and Q4, and the collector of the transistor QA4 is connected to the transistors Q1 and Q3. Connect to the collector.

  In the relationship with claims 1, 2, 7, and 8, the differential amplifier circuit corresponds to a circuit comprising transistors Q1 to Q4 and a constant current source CS1, and the first addition current supply circuit includes transistors QA1 and QA2 and a constant current. The second addition current supply circuit corresponds to a circuit including the transistors CSA3 and QA4 and the constant current source CS3.

  With this configuration, it is possible to prevent the currents I2 and I3 additionally supplied to the differential amplifier circuit from flowing out to the input terminals IN + and IN− to increase the slew rate. In the operational amplifier 10A of the first embodiment, the currents I2 and I3 are part of the base currents of the transistors Q1 and Q2, and part of them flow out to the input terminals IN + and IN−, and the current supplied to the capacitor Cc by this outflow There was a slight decrease, and the increase in slew rate was subdued but prevented. The operational amplifier 10C of the third embodiment has an advantage that the current can be prevented from flowing out and the slew rate can be increased by flowing I2 and I3 directly through the collectors of the transistors Q1 and Q2. The tendency of the slew rate increase in the third embodiment is the same as that of the operational amplifier 10A of the first embodiment, and is shown in FIGS.

<Fourth embodiment>
FIG. 7 shows an operational amplifier 10D composed of a field effect transistor according to the fourth embodiment of the present invention. A circuit configuration of the operational amplifier 10D of the present embodiment will be described. However, the same components as those described in FIG. 9 are denoted by the same reference numerals, and detailed description thereof is omitted. In FIG. 7, M1 and M2 are PMOS transistors, M3 and M4 are NMOS transistors, and CS1 is a constant current source. The transistors M1 and M2 and the constant current source CS1 constitute a differential input stage, and the transistors M3 and M4 constitute a current mirror circuit as an active load. The above transistors M1, M2, M3, M4 and the constant current source CS1 constitute a differential amplifier.

  This embodiment is characterized in that PMOS transistors MC1, MC2, MC3, MC4 and constant current sources CS2, CS3 are added to this differential amplifier. The transistor MC1 has a gate connected to the normal input terminal IN +, a drain connected to the low voltage power supply line V-, and a source connected to the constant current source CS2. The transistor MC2 has a gate and a drain connected to the constant current source CS1, and a source connected to the constant current source CS2. The transistor MC3 has a gate connected to the inverting input terminal IN−, a drain connected to the low voltage power supply line V−, and a source connected to the constant current source CS3. The transistor MC4 has a gate and a drain connected to the constant current source CS1, and a source connected to the constant current source CS3. The input stage of the operational amplifier 10D of this embodiment is composed of the above-described transistors M1, M2, MC1 to MC4, and constant current sources CS1 to CS3. The configuration from the active load to the output terminal OUT is the same as that shown in FIG.

  In the relationship with the first, second, fifth, sixth and thirteenth aspects, the differential amplifier circuit corresponds to a circuit including the transistors M1 to M4 and the constant current source CS1, and the first addition current supply circuit includes the transistors MC1 and MC2. The second addition current supply circuit corresponds to a circuit composed of the transistors MC3 and MC4 and the constant current source CS3.

In order to simplify the description of the circuit operation of this embodiment, the gate width W and the gate length L of the transistors MC1, MC2, MC3, and MC4 are unified with the same value, and the transistors MC1 and MC2, and the transistors MC3 and MC4 In each differential circuit, a gate input potential difference Vd at which a transistor through which a current flows is completely switched is set to 0.1V. For reference, this potential difference Vd is expressed by the following equation as a function of L and W using the electron mobility μ _n in the channel and the gate oxide film capacitance C _ox per unit area.

The operational amplifier 10D of the fourth embodiment configured as described above is connected as shown in FIG. 2, and an output when a voltage pulse is applied to the normal input terminal IN + as in the first embodiment. The time changes of the voltage VOUT and the slew rate SR are shown in FIGS. 3 and 4, respectively. In the fourth embodiment, the current I2 flowing from the constant current source CS2 is differentially amplified when the potential difference Vdif between the input terminals exceeds about 0.5 V which is “ _VGSM2−Vd ” at the _{rising edge of the pulse} . As the current drawn from the capacitor Cc starts to flow into the circuit, the current I2 starts to be added in addition to the current I1. Therefore, the slew rate starts to increase. Here, V _GSM2 is a potential difference between the gate and the source of the transistor M2, which is about 0.6V. Further, since Vd is 0.1 V, the potential difference Vdif between the input terminals at this time is “about 0.6-0.1 = about 0.5 V”. When the potential difference Vdif between the input terminals reaches “V _GSM2 + Vd”, that is, “about 0.6 + 0.1 = about 0.7 V”, all of the current I2 flows to the differential amplifier circuit, and from the capacitor Cc. The drawn current becomes “I1 + I2”, and the slew rate increases to the value represented by the equation (4).

In addition, when the pulse falls, when the potential difference Vdif between the input terminals exceeds “ _VGSM1-Vd ”, the current I3 flowing from the constant current source CS3 starts to flow into the differential amplifier circuit, and the capacitor Cc adds the current I1. Since the current I3 starts to be additionally supplied, the slew rate starts to increase. Here, V _GSM1 is a potential difference between the gate and the source of the transistor M1, which is about 0.6V. Since Vd is assumed to be 0.1 V, the potential difference Vdif between the input terminals at this time is “about 0.6−0.1 = about 0.5 V”. When the potential difference Vdif between the input terminals reaches “V _GSM1 + Vd”, that is, “about 0.6 + 0.1 = about 0.7 V”, all the current I3 flows to the transistor M1 and is supplied to the capacitor Cc. Current becomes “I1 + I3”, and the slew rate increases to the value represented by the equation (5). On the other hand, in the conventional example, as indicated by the broken line in FIG. 4, since the currents I2 and I3 are not supplied, the slew rate is expressed by the equation (1).

  In this embodiment, the W / L of the transistor MC2 is larger than the W / L of the transistor MC1, and the W / L of the transistor MC4 is larger than the W / L of the transistor MC3, so that the potential difference Vdif between the input terminals is about 0. It is possible to increase the slew rate even at a value lower than 0.5V. This is because, by increasing these W / L, the gate-source voltage required for flowing current to the transistors MC2 and MC4 decreases.

  In addition, when the potential difference Vdif between the input terminals is less than about 0.5 V, the currents I2 and I3 do not flow into the differential amplifier circuit. Therefore, the state of the differential amplifier circuit of this embodiment is the same as the conventional example. Keep the same operational amplifier stability as the example.

  Note that the MOS transistor of the circuit of FIG. 7 shown in the fourth embodiment can be reversed between PMOS and NMOS. In that case, the constant current sources CS1, CS2, CS3 are connected to the low voltage power supply line V-. The drains of the transistors MC1 and MC3 connected to the low voltage power supply line V− are connected to the high voltage power supply line V +.

<Fifth embodiment>
FIG. 8 shows an operational amplifier 10E that is the fifth embodiment of the present invention. A circuit configuration of the operational amplifier 10E of the present embodiment will be described. In this embodiment, the present invention is applied to an operational amplifier having a sufficiently wide input voltage range capable of inputting an input voltage from a high voltage power supply line potential to a low voltage power supply line potential, a so-called input rail-to-rail operational amplifier. This is an applied example. Here, the same components as those described in FIG. 7 are denoted by the same reference numerals, and detailed description thereof is omitted.

  The input stage of the input rail-to-rail operational amplifier includes a differential circuit composed of PMOS transistors M1 and M2 and a differential circuit composed of NMOS transistors M11 and M12, that is, two differential circuits. A constant current source CS1 is connected to the differential circuit on the PMOS side, a constant current source CS4 is connected to the differential circuit on the NMOS side, and a load resistor is provided at the drain of each differential circuit. This load resistance is constituted by a folded circuit including resistors R1 to R4, NMOS transistors M21 and M22, and PMOS transistors M23 and M24. The resistors R1 to R4 have the same resistance value, and the transistors M21 and M22 and the transistors M23 and M24 have the same shape. Thus, two differential amplifier circuits are configured. The drains of the transistors M21 and M23 serving as load resistors are connected to the voltage amplifier Gm and the phase compensation capacitor Cc. The configuration from the voltage amplifier Gm and the capacitor Cc to the output terminal OUT is the same as that in FIG. Vref is a reference voltage, and applies a gate potential to the transistors M23 and M24 as load resistors.

  This embodiment is characterized in that NMOS transistors MD1 and MD2, PMOS transistors MD3 and MD4, and constant current sources CS2 and CS3 are added to the two differential amplifier circuits. The transistor MD1 has a gate connected to the inverting input terminal IN−, a drain connected to the high voltage power supply line V +, and a source connected to the constant current source CS2. The transistor MD2 has a gate and a drain connected to the constant current source CS4 and a source connected to the constant current source CS2. The transistor MD3 has a gate connected to the inverting input terminal IN−, a drain connected to the low voltage power supply line V−, and a source connected to the constant current source CS3. The transistor MD4 has a gate and a drain connected to the constant current source CS1, and a source connected to the constant current source CS3. The above is the configuration of the input stage of the operational amplifier in this embodiment.

  In relation to claims 11, 12, and 13, the first differential amplifier circuit corresponds to a circuit comprising transistors M1, M2, M21, and M22, resistors R1 and R2, and a constant current source CS1, and the second differential amplifier circuit. The amplifier circuit corresponds to a circuit including transistors M11, M12, M23, and M24, resistors R3 and R4, and a constant current source CS4. The first addition current supply circuit corresponds to a circuit including transistors MD3 and MD4 and a constant current source CS3. The second addition current supply circuit corresponds to a circuit composed of transistors MD1 and MD2 and a constant current source CS2.

  The input rail-to-rail operational amplifier 10E of the present embodiment includes two differential input stages on the PMOS side and the NMOS side, but the number of elements required to amplify the slew rate is from the first to the fourth. As in the embodiment, there are six, and there is an advantage that the slew rate can be increased with a small number of elements.

  In this embodiment, in order to simplify the explanation of the circuit operation, the gate width W and the gate length L of the transistors MD1, MD2, MD3, and MD4 have the same value. In the differential circuit of the transistors MD1 and MD2 and transistors MD3 and MD4, The gate input potential difference Vd at which the transistor through which the current flows is completely switched is set to 0.1V. This potential difference is expressed by equation (6).

  The operational amplifier 10E in the fifth embodiment configured as described above is connected as shown in FIG. 2, and the output when the voltage pulse is applied to the normal input terminal IN + as in the first embodiment. The tendency of the time change of the voltage VOUT and the slew rate SR is the same as that of the fourth embodiment, and is shown in FIGS. 3 and 4, respectively.

ここでＶ_GSM23とＶ_GSM24はトランジスタＭ２３，Ｍ２４のゲートとソース間電位差であり、ＩＤ２４はトランジスタＭ２４に流れる電流である。式(7)では、電流ＩＤ２３とＩＤ２３の関数であるＶ_GSM23以外は変化できない。したがって、電流Ｉ２が追加されることで、電流ＩＤ２３がさらに減少する傾向にある。 In this embodiment, when the potential difference Vdif between the input terminals exceeds “ _VGSM12−Vd ” at the rising _edge of the pulse, the current I2 flowing through the constant current source CS2 starts to flow through the transistor MD2. Here, V _GSM12 is about 0.6 V of the potential difference between the gate and the source of the transistor M12 and Vd is assumed to be 0.1 V. Therefore, the potential difference Vdif between the input terminals at this time is “about 0.6−0.1 = about 0.5V ". Thereafter, when the potential difference Vdif between the input terminals reaches about 0.7 V, all the current I2 flows to the transistor MD2. This about 0.7 V is a value obtained from “V _GSM12 + Vd”. The current I2 flowing through the transistor MD2 passes through the transistor M12 and generates a voltage drop at the resistor R3. At this time, the current ID23 flowing through the transistor M23 decreases based on the equation considered in the closed circuit of the resistors R3 and R4 and the transistors M23 and M24.

Here, V _GSM23 and V _GSM24 are potential differences between the gates and sources of the transistors M23 and M24, and ID24 is a current flowing through the transistor M24. In Expression (7), only V _GSM23 which is a function of current ID23 and ID23 can be changed. Therefore, the current ID23 tends to be further reduced by adding the current I2.

ここで、Ｖ_GSM21とＶ_GSM22はトランジスタＭ２１，Ｍ２２のゲートとソース間電位差であり、ＩＤ２２はＭ２２に流れる電流である。式(8)では電流ＩＤ２１とＩＤ２１の関数であるＶ_GSM21以外変化できない。したがって式(8)を成り立たせるには、電流ＩＤ２１を増加させる必要がある。また、スルーレートの大きさに比例するコンデンサＣｃに流れる電流は、増加傾向にある電流ＩＤ２１と減少傾向にある電流ＩＤ２３の差である。電流Ｉ２が追加されることで、電流ＩＤ２３がさらに減少するため、電流ＩＤ２１とＩＤ２３の差がより大きくなり、コンデンサＣｃから流れ出る電流は増加する。したがって、スルーレートが増大する。 On the other hand, the current ID21 flowing through the transistor M21 is expressed by the following equation based on the equation considered in the closed circuit of the resistors R1 and R2 and the transistors M21 and M22.

Here, V _GSM21 and V _GSM22 are potential differences between the gates and sources of the transistors M21 and M22, and _ID22 is a current flowing through M22. In Expression (8), only V _GSM21 which is a function of current _{ID21 and ID21} can be changed. Therefore, in order to satisfy the equation (8), it is necessary to increase the current ID21. Further, the current flowing through the capacitor Cc proportional to the magnitude of the slew rate is the difference between the current ID21 that tends to increase and the current ID23 that tends to decrease. By adding the current I2, the current ID23 further decreases, so that the difference between the currents ID21 and ID23 becomes larger and the current flowing out of the capacitor Cc increases. Therefore, the slew rate increases.

式(9)では電流ＩＤ２１とＩＤ２１の関数であるＶ_GSM21以外は変化できない。したがって、電流Ｉ３が追加されることで、さらに電流ＩＤ２１が減少する。 When the pulse falls, when the potential difference Vdif between the input terminals exceeds the voltage “V _GSM1 −Vd”, the current I3 flowing from the constant current source CS3 starts to flow to the transistor MD4. Here, V _GSM1 is about 0.6 V of the potential difference between the gate and the source of the transistor M1 and Vd is assumed to be 0.1 V. Therefore, the potential difference Vdif between the input terminals at this time is “about 0.6-0.1 = about 0.5V ". Thereafter, when the potential difference Vdif between the input terminals reaches about 0.7 V, all the current I3 flows to the transistor MD4. This about 0.7 V is a value obtained from “V _GSM1 + Vd”. The current I3 flowing through the transistor MD4 passes through the transistor M1 and generates a voltage drop at the resistor R1. The current ID21 at this time is expressed by the following equation based on the equation considered in the closed circuit of the resistors R1 and R2 and the transistors M21 and M22.

In Expression (9), only the current _{ID21 and VGSM21} which is a function of _ID21 can be changed. Therefore, the current ID21 is further reduced by adding the current I3.

式（10）では電流ＩＤ２３とＩＤ２３の関数であるＶ_GSM23以外は変化できない。したがって、式（10）を成り立たせるには電流ＩＤ２３を増加させる必要がある。また、スルーレートの大きさに比例するコンデンサＣｃに流れる電流は、増加傾向にある電流ＩＤ２３と減少傾向にある電流ＩＤ２１の差である。電流Ｉ３が追加されることで、電流ＩＤ２１がさらに減少するため、電流ＩＤ２１とＩＤ２３の差がより大きくなり、コンデンサＣｃに流れ込む電流は増加する。したがって、スルーレートが増大する。 On the other hand, the current ID23 flowing through the transistor M23 is expressed by the following equation based on the equation considered in the closed circuit of the resistors R3 and R4 and the transistors M23 and M24.

In Expression (10), only V _GSM23 which is a function of current ID23 and ID23 can be changed. Therefore, it is necessary to increase the current ID 23 in order to satisfy the equation (10). Further, the current flowing through the capacitor Cc proportional to the magnitude of the slew rate is the difference between the current ID23 that is increasing and the current ID21 that is decreasing. By adding the current I3, the current ID21 further decreases, so that the difference between the currents ID21 and ID23 becomes larger and the current flowing into the capacitor Cc increases. Therefore, the slew rate increases.

  In this embodiment, the W / L of the transistor MD2 is larger than the W / L of the transistor MD1, and the W / L of the transistor MD4 is larger than the W / L of the transistor MD3, so that the potential difference Vdif between the input terminals can be lower. It is possible to increase the slew rate. This is because by increasing W / L, the gate and source voltage required for flowing current through the transistors MD2 and MD4 is reduced.

  In addition, when the potential difference Vdif between the input terminals is less than 0.5 V, the currents I2 and I3 do not flow into the resistors R3 and R1, so the state of the differential amplifier circuit of this embodiment is the same as the conventional example. Keep the same operational amplifier stability.

<Other examples>
In each of the above embodiments, a bipolar transistor or a MOS transistor is used as a transistor. However, a circuit using a bipolar transistor is changed to a circuit using a MOS transistor, and a circuit using a MOS transistor is changed to a circuit using a bipolar transistor. Is possible. At this time, the base, emitter, and collector of the bipolar transistor correspond to the gate, source, and drain of the MOS transistor.

Gm: Voltage amplifier BF: Buffer circuit 10, 10A, 10B, 10C, 10D, 10E: Operational amplifier M1-M4, M11, M12, M21-M24, Q1-Q4, MC1-MC4, MD1-MD4, QA1-QA4 QB1 to QB4: Transistor Cc: Capacitor for phase compensation V +: High voltage power supply line V-: Low voltage power supply line IN +: Normal input terminal IN-: Inverted input terminal OUT: Output terminal VIN +: Normal input terminal potential VIN-: Inverted input terminal potential VOUT: Output terminal potential CS1 to CS4: Constant current source Vref: Reference voltage

Claims (5)

The emitter of the first transistor having a base connected to the first input terminal and the emitter of the second transistor having the base connected to the second input terminal and the same conductivity type as the first transistor are defined as a first constant. A differential amplifier circuit commonly connected to a current source and having collectors of the first and second transistors connected to a load;
First current when the potential of the first input terminal a first no al a higher than a predetermined value than the potential of the emitter of said first transistor to be subtracted from the current by the first constant current source supplying, it becomes higher when the first predetermined value or more and the first subtraction current supply circuit to stop the supply of the first current,
An operational amplifier comprising: The operational amplifier according to claim 1,
The second the absence et a higher than a predetermined value with respect to the emitter potential of the second potential is the second transistor of the input terminals a second subtracting respect to the current by the first constant current source current supply, a second subtraction current supply circuit to stop the supply of the second predetermined value or more becomes higher when said second current,
An operational amplifier comprising: The operational amplifier according to claim 1,
The first subtracting current supply circuit commonly connects the emitters of two transistors having conductivity types opposite to the first transistor to a second constant current source, and has a base of one of the two transistors. the collector as well as connected to the base of the first transistor connected to a power supply terminal, the other transistor the base and collector of said first operational amplifier, wherein Rukoto such connected to the emitter of the transistor. The operational amplifier according to claim 2 , wherein
The second subtracting current supply circuit is configured to commonly connect emitters of two transistors of opposite conductivity types to the second transistor to a third constant current source, and to connect a base of one of the two transistors. the collector as well as connected to the base of the second transistor connected to a power supply terminal, the other transistor the base and collector of said second operational amplifier, wherein Rukoto such connected to the emitter of the transistor. The operational amplifier according to any one of claims 1 to 4 ,
An operational amplifier , wherein the transistor is replaced with a MOS transistor, the base is replaced with a gate, the emitter is replaced with a source, and the collector is replaced with a drain .

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