JP5406148B2 - Clock reproduction apparatus, clock reproduction method, and control program - Google Patents

Description

  The present invention relates to a clock recovery device. In particular, the present invention relates to a clock recovery apparatus that uses an adaptive clock recovery method for clock synchronization between transmitting and receiving apparatuses in transmission and reception of TDM (Time Division Multiplexer) signals.

  Establish synchronization between transmitting and receiving terminals when transmitting and receiving TDM signals represented by CESoPSN (Circuit Emulation Service over Packet Switched Network) and SAToP (Structure-Agnostic Time Division Multiplexing over Packet) in the packet network One method is an adaptive clock recovery method. In the adaptive clock recovery method, the frequency of the reference clock of the receiving device is adjusted so that the writing speed to the buffer of the receiving device matches the reading speed. The writing speed to the buffer of the receiving device depends on the frequency of the reference clock of the transmitting device, and the reading speed from the buffer depends on the frequency of the reference clock of the receiving device. The transmitting terminal and the receiving terminal can be synchronized.

  A method of obtaining synchronization using the adaptive clock recovery method will be described with reference to FIG. FIG. 6A shows a state where the reading speed and the writing speed match. In this case, the buffer accumulation amount is stable near the center value, and the transmission-side clock that is a reference for the writing speed to the buffer and the reception-side clock that is the reference for the reading speed from the buffer are synchronized.

  Further, FIG. 6B shows a state where the reading speed is faster than the writing speed. In this case, the buffer accumulation amount gradually decreases. When the buffer accumulation amount falls below the lower threshold value, the frequency of the reference clock of the receiving device is adjusted to reduce the reading speed. When the writing speed to the buffer of the receiving apparatus and the reading speed again match, the frequency of the reference clock of the receiving apparatus and the frequency of the reference clock between the transmitting and receiving apparatuses are synchronized.

  Further, FIG. 6C shows a state where the reading speed is slower than the writing speed. In this case, the buffer accumulation amount gradually increases. When the buffer accumulation amount exceeds the upper threshold, the frequency of the reference clock of the receiving device is adjusted to increase the reading speed. When the writing speed to the buffer of the receiving apparatus and the reading speed again match, the frequency of the reference clock of the receiving apparatus and the frequency of the reference clock between the transmitting and receiving apparatuses are synchronized.

  A technique for obtaining synchronization using an adaptive clock recovery method is disclosed in Patent Document 1, for example. In Patent Document 1, when the buffer accumulation amount exceeds the upper threshold, the transmitting terminal and the receiving terminal are synchronized by applying a reading speed faster than usual.

  However, the buffer storage amount also varies greatly due to a fixed delay of a packet generated by a route switch or the like in an IP (Internet Protocol) network. In this case, although the frequency of the reference clock of the receiving device is synchronized with the frequency of the reference clock between the transmitting and receiving devices, the frequency of the reference clock of the receiving device is erroneously adjusted. An erroneous adjustment of the frequency of the reference clock of the receiving apparatus due to the fixed delay of the packet will be described with reference to FIG.

  In FIG. 7A, by receiving a packet whose packet fixed delay is reduced by Ams at time t1, the buffer accumulation amount is increased by the data amount corresponding to the fixed delay Ams. That is, in FIG. 7B, the buffer accumulation amount increases from the central value by Ams.

  When an apparatus to which the adaptive clock recovery method is applied calculates an average value for each period Ta from the buffer accumulation amount and uses the average of the buffer accumulation amount for frequency adjustment, as shown in FIG. In addition, at the time t2 (period Ta4) when the average value of the period Ta3 including the time t1 is applied, the average value of the buffer accumulation amount increases. When the frequency of the reference clock of the receiving device is adjusted based on the average value of the buffer accumulation amount, the average value of the buffer accumulation amount increases as shown in FIG. Is incorrectly adjusted.

  Therefore, as a technique for suppressing erroneous adjustment of the frequency of the reference clock due to the packet fixed delay, for example, in Patent Document 2, when a packet fixed delay occurs, the frequency is excessively corrected and then kept constant, and the buffer is stored. A technique for restoring the frequency after the amount returns to the reference value is disclosed. Patent Document 3 discloses a technique for changing the central value of the buffer accumulation amount according to the packet fixed delay when the packet fixed delay occurs.

JP 2006-49941 A JP 7-46257 A JP 2002-344433 A

  However, when applying the technique disclosed in Patent Document 2, it is difficult to maintain synchronization between the transmission terminal and the reception terminal during a period in which the frequency is excessively corrected. Further, when applying the technique disclosed in Patent Document 3, the central value serving as a reference is changed a plurality of times in a short period of time, and the control may become unstable.

  In view of the above problems, an object of the present invention is to stably synchronize a transmission terminal and a reception terminal even when a packet fixed delay occurs when synchronization is performed using the adaptive clock recovery method. The object is to provide a clock recovery device, a clock recovery method, and a control program.

In order to achieve the above object, a clock recovery device according to the present invention receives a packet, writes it in a buffer, outputs the packet from the buffer in synchronization with the clock received from the clock output means, and outputs the accumulated amount The control means monitors the presence or absence of a delay, and if a delay is detected, the delay detection means calculates and outputs a delay amount, and generates and outputs a clock control value based on the accumulated amount received from the buffer control means comprising a to torque lock control means, and a clock output means for generating and outputting a clock based on the clock control value received from the clock control unit, wherein the buffer control means, the delay detecting means detects a delay If not, the accumulated amount of the buffer is measured and output, and when the delay detecting means detects a delay, it corresponds to the delay amount. And it outputs the predetermined accumulation amount stops the output of the receiving or packet of the packet for the period.

In order to achieve the above object, the clock recovery method according to the present invention receives a packet, writes it to a buffer, outputs the packet from the buffer in synchronization with the output clock, monitors whether there is a delay, If it is not detected, the accumulated amount of the buffer is measured and output, and if a delay is detected, the delay amount is calculated and the reception of the packet or the output of the packet is stopped for a period corresponding to the delay amount and the predetermined accumulation is performed. A clock control value is generated and output based on the output accumulated amount, and the clock is generated and output based on the output clock control value .

In order to achieve the above object, a control program according to the present invention is a control program that can be executed by a computer of a device that outputs a packet from a buffer in synchronization with a clock . Monitors the presence or absence of a delay, and if the delay is not detected, measures and outputs the accumulated amount of the buffer. If the delay is detected, calculates the delay amount and receives a packet or packet during a period corresponding to the delay amount. The output of a predetermined accumulation amount, a function of generating and outputting a clock control value based on the output accumulation amount, and the clock based on the output clock control value. The function of generating and outputting is executed by the computer of the apparatus.

  Normally, a clock is generated using a clock control value generated based on the measured buffer storage amount, and during a period affected by a packet fixed delay, a clock is generated using a predetermined clock control value. Even when a fixed packet delay occurs when synchronization is performed using the adaptive clock recovery method, the transmission terminal and the reception terminal can be stably synchronized.

1 is an example of a block diagram of a clock recovery device 10 according to a first embodiment of the present invention. It is an example of the block diagram of the clock reproduction apparatus 100 which concerns on the 2nd Embodiment of this invention. It is an example of a time chart of (a) packet fixed delay, (b) packet accumulation amount, and (c) first accumulation amount average value of the clock recovery device 100 according to the second embodiment of the present invention. In the clock recovery apparatus 100 according to the second embodiment of the present invention, (a) packet fixed delay, (b) packet accumulation amount, (c) first accumulation amount average value, (d) second accumulation amount It is an example of a time chart of an average value and (e) output frequency. It is an example of the block diagram of the clock reproduction apparatus 200 which concerns on the 3rd Embodiment of this invention. It is the figure which showed an example of the accumulation amount of the buffer for demonstrating an adaptive clock reproduction | regeneration method. It is an example of a time chart for explaining an adaptive clock regeneration method, (a) packet fixed delay, (b) packet accumulation amount, (c) accumulation amount average value, and (d) frequency adjustment value.

(First embodiment)
A clock recovery device according to a first embodiment of the present invention will be described. An example of a block diagram of the clock recovery apparatus according to the present embodiment is shown in FIG. In FIG. 1, the clock recovery apparatus 10 according to the present embodiment includes a buffer control unit 20, a delay detection unit 30, a clock control unit 40, and a clock output unit 50.

  The buffer control unit 20 outputs the packet from the buffer 60 in synchronization with the clock received from the clock output unit 50. Further, the buffer control unit 20 measures the accumulation amount of the buffer 60 and outputs it to the delay detection unit 30 and the clock control unit 40.

The delay detection unit 30 monitors the presence or absence of a delay, and when a delay is detected, calculates a delay amount and outputs the delay amount to the clock control unit 40.
The clock control means 40 generates a clock control value based on the accumulated amount of the buffer 60 received from the buffer control means 20 and outputs it to the clock output means 50. Further, when receiving a delay amount from the delay detection unit 30, the clock control unit 40 outputs a predetermined clock control value to the clock output unit 50 for a period corresponding to the delay amount.

  The clock output means 50 generates a clock based on the clock control value received from the clock control means 40 and outputs it to the buffer control means 20.

  When a delay occurs, a clock is generated based on a predetermined clock control value for a period corresponding to the delay amount, so that the transmission terminal and the reception terminal can be stably synchronized.

(Second Embodiment)
A clock recovery apparatus according to the second embodiment of the present invention will be described. An example of a block diagram of the clock recovery apparatus according to the present embodiment is shown in FIG. 2, the clock recovery device 100 according to this embodiment includes a buffer control unit 101, a buffer accumulation amount observation unit 102, a delay change detection unit 105, a frequency control unit 106, and a voltage controlled oscillator 107.

  The buffer control unit 101 includes a buffer 110. The buffer control unit 101 writes the received packet 104 into the buffer 110. When the accumulated amount of the written packet 104 reaches the center value of the buffer 110, the TDM signal 109 is output from the buffer 110 in synchronization with the clock 108 generated by the voltage controlled oscillator 107. In addition, when receiving a packet fixed delay change notification and a delay change amount from the delay change detection unit 105, the buffer control unit 101 stops receiving the packet 104 or outputting the TDM signal 109 according to the delay change amount. Then, the accumulated amount of the buffer 110 is returned to the center value.

  The buffer accumulation amount observation unit 102 constantly observes the accumulation amount of the packet 104 written in the buffer 110 and outputs the observed accumulation amount to the delay change detection unit 105 and the frequency control unit 106. Furthermore, when the buffer accumulation amount observation unit 102 detects an underrun or overrun of the accumulation amount, the buffer accumulation amount observation unit 102 outputs a notification regarding the underrun or overrun to the frequency control unit 106.

  The delay change detection unit 105 calculates a first accumulation amount average value for each predetermined period Tp from the accumulation amount received from the buffer accumulation amount observation unit 102, and uses the calculated first accumulation amount average value to fix the packet fixed delay. Detect changes. Then, when detecting a packet fixed delay change, the delay change detection unit 105 outputs a packet fixed delay change notification and a delay change amount to the buffer control unit 101 and the frequency control unit 106. Note that a packet fixed delay detection method and a delay change amount acquisition method will be described later.

  The frequency control unit 106 calculates a second accumulation amount average value for each predetermined period Ta from the accumulation amount received from the buffer accumulation amount observation unit 102, and outputs the second accumulation amount average value to the voltage controlled oscillator 107. In addition, when the notification about the underrun or overrun of the storage amount is received from the buffer storage amount observation unit 102, the voltage controlled oscillator 107 is set so that the transmitting terminal and the receiving terminal are synchronized by applying the adaptive clock recovery method. Control. When the frequency control unit 106 receives the packet fixed delay change notification and the delay change amount from the delay change detection unit 105, the frequency control unit 106 sets the second central value as the second accumulated amount average value for a period corresponding to the delay change amount. Is output to the voltage controlled oscillator 107.

  The voltage controlled oscillator 107 generates a clock 108 based on the second accumulated amount average value received from the frequency control unit 106 and outputs the clock 108 to the buffer control unit 101. By using the clock 108 generated based on the second accumulated amount average value, the frequency of the receiving terminal is adjusted to a desired frequency, and the receiving terminal and the transmitting terminal are synchronized.

  Next, a method for detecting a packet fixed delay change and a method for acquiring a delay change amount will be described. FIG. 3A shows the fixed delay of the packet 104, FIG. 3B shows the accumulated amount of the buffer 110, and FIG. 3C shows the first accumulated amount average value calculated by the delay change detecting unit 105.

  In FIG. 3A, when the packet 104 whose packet fixed delay is reduced by Ams is received at time t1, the accumulated amount of the buffer 110 is increased by the data amount corresponding to the fixed delay Ams. (FIG. 3 (b)).

  In FIG. 3C, the first accumulation amount average value C2 (time t2) calculated by the delay change detection unit 105 for the period Tp3 including time t1 is the first accumulation amount average value C1 (center value) before that. Increase from. Furthermore, the first accumulation amount average value C3 (time t3) calculated for the next period Tp4 further increases from the first accumulation amount average value C2 at time t2. Then, the first accumulation amount average value C4 (time t4) calculated for the period Tp5 coincides with the first accumulation amount average value C3 at time t3.

  The delay change detection unit 105 determines that the packet fixed delay has changed when the first accumulation amount average value has stabilized after the change. That is, the delay change detection unit 105 can detect the change in the packet fixed delay within three periods (period Tp × 3) after the packet fixed delay fluctuates. When detecting a variation in the packet fixed delay, the delay change detecting unit 105 detects the first accumulated amount average value C4 after stabilization (time t4) and the first accumulated amount average value C1 before the change (center value). Is calculated as a delay change amount. Here, the delay change amount has a data amount corresponding to the fixed delay Ams.

  Next, the operation of the clock recovery device 100 according to the present embodiment will be described. 4A shows the fixed delay of the packet 104, FIG. 4B shows the accumulated amount of the buffer 110, and FIG. 4C shows the first accumulated amount average value calculated by the delay change detecting unit 105. 4 (d) shows the second accumulated amount average value calculated by the frequency control unit 106, and FIG. 4 (e) shows the output frequency. In FIG. 4, the numbers of time t and period Tp are the same as those in FIG. Further, in the present embodiment, when detecting a packet fixed delay change, the delay change detection unit 105 of the clock recovery device 100 stops calculating the first accumulation amount average value for a period corresponding to the delay change amount, and The first central value is set as the accumulated amount average value of one. Further, when receiving the delay change amount, the frequency control unit 106 stops calculating the second accumulation amount average value for the period corresponding to the delay change amount, and the second central value as the second accumulation amount average value. Set. When the packet fixed delay changes, unnecessary processing can be reduced by stopping the calculation of the first accumulation amount average value and the second accumulation amount average value for the period corresponding to the delay variation amount.

  In FIG. 4A, a packet 104 whose packet fixed delay is reduced by Ams is received at time t1. In FIG. 4B, at time t1, the accumulation amount increases from the center value by a data amount corresponding to the fixed delay Ams. Further, at time t4, the buffer control unit 101 receives the fixed delay change notification and the delay change amount from the delay change detection unit 105, and corresponds to the delay change amount, that is, a period that matches the fixed delay Ams, TDM. Reception of the packet 104 is stopped while the signal 109 is output. As a result, when the period (fixed delay Ams) corresponding to the delay change amount has elapsed from time t4 (time t6), the accumulation amount decreases by the data amount corresponding to the fixed delay Ams and returns to the center value.

  In FIG. 4C, the delay change detecting unit 105 calculates the first accumulated amount average value for each period Tp. Then, the delay change detecting unit 105 detects that the packet fixed delay has changed by the method described with reference to FIG. 3 when three periods have elapsed (time t4) including the period Tp3 including the time t1 when the packet fixed delay fluctuates. It detects and notifies the buffer control unit 101 and the frequency control unit 106 of the packet fixed delay change notification and the delay change amount. Furthermore, in the present embodiment, the delay change detection unit 105 performs the first operation for the period corresponding to the calculated delay change amount, that is, the period until the period that coincides with the fixed delay Ams (period Tp6 to period Tp8). Is stopped, and the first central value is set as the first accumulated amount average value. Then, the delay change detection unit 105 restarts the calculation of the first accumulation amount average value from the period Tp9 after the lapse of the period that coincides with the fixed delay Ams.

  Further, in FIG. 4D, the frequency control unit 106 calculates the second accumulation amount average value for each period Ta. Then, when the frequency control unit 106 receives the packet fixed delay change notification and the delay change amount at time t4, the frequency control unit 106 determines the period (periods Ta2 and Ta3) including the period (fixed delay Ams) corresponding to the delay change amount. The calculation of the accumulated amount average value of 2 is stopped, and the second central value is set as the second accumulated amount average value. Then, the frequency control unit 106 resumes the calculation of the second accumulated amount average value from the period Ta4 after the lapse of the period that coincides with the fixed delay Ams.

  Here, when the frequency control unit 106 receives the packet fixed delay change notification and the delay change amount, the second center value is set as the second storage amount average value because the buffer storage amount is the center value at time t6. This is because the second accumulated amount average value may not return to the second central value even if the process returns to step S2. In this case, when the frequency control unit 106 resumes the control by the adaptive clock regeneration method from time t7, the control is performed according to the average value of the buffer accumulation amount increased from the central value of the buffer accumulation amount. Will be adjusted. Therefore, in the present embodiment, the frequency control unit 106 sets the second central value as the second accumulated amount average value when the notification of the change in the packet fixed delay is received from the delay change detection unit 105.

  Further, in FIG. 4 (e), the second central value is output as the second accumulated amount average value from the frequency control unit 106 to the voltage controlled oscillator 107 at times t5 and t7, whereby the voltage controlled oscillator 107 is output. Adjusts the frequency of the receiving terminal based on the second center value. Further, the frequency control unit 106 resumes the calculation of the second accumulated amount average value from the period Ta4, so that the adjustment based on the adaptive clock regeneration method is resumed from the time t8.

  As described above, in this embodiment, after the detection of the packet fixed delay (time t4), the period (period Ta2, Ta3) until the period matching the fixed delay Ams has elapsed (time t6) is the second accumulation. Since the quantity average value is set to the second center value, unnecessary frequency adjustment is suppressed. Note that, after the period Ta4, the adjustment based on the adaptive clock regeneration method is resumed, but the adaptive clock regeneration method is appropriately applied because the delay variation related to the packet fixed delay has been eliminated.

  Further, in the present embodiment, the packet fixed delay is detected within three periods of the period Tp, which is the calculation period of the first accumulation amount average value. Accordingly, by setting the period Ta, which is the calculation period of the second accumulation amount average value, to be longer than the three periods of the period Tp, which is the calculation period of the first accumulation amount average value, It is possible to suppress unnecessary frequency adjustment from t1) to detection of packet fixed delay (time t4).

  In the above-described embodiment, the case where the packet 104 whose packet fixed delay is reduced by Ams has been described. However, when a packet whose packet fixed delay is increased is received, processing is performed as follows. That is, when receiving a packet whose packet fixed delay increases by A ′ ms, the accumulation amount decreases from the center value by a data amount corresponding to the fixed delay A ′ ms. When the buffer control unit 101 receives the packet fixed delay change notification and the delay change amount from the delay change detection unit 105, the buffer control unit 101 stops outputting the TDM signal while receiving the packet. As a result, the number of packets in the buffer 110 increases, the storage amount increases, and the storage amount before the change of the packet fixed delay is restored. In addition, the second accumulated amount average value is set to the second central value until the period that coincides with the fixed delay A'ms elapses, and then the adjustment based on the adaptive clock regeneration method is resumed. Unnecessary frequency adjustment is suppressed.

  As described above, the clock recovery device 100 according to the present embodiment uses the second accumulated amount average value for adjusting the frequency of the receiving terminal as the second central value for the period that is affected by the variation of the packet fixed delay. By setting to, the frequency is fixed to a predetermined set value. Therefore, even when the packet fixed delay fluctuates, the transmission terminal and the reception terminal can be stably synchronized. Furthermore, the clock recovery device 100 according to the present embodiment sets the period Ta that serves as a reference for frequency adjustment to be longer than the three periods Tp that serves as a reference for detecting the packet fixed delay, thereby changing the packet fixed delay. Can be removed appropriately.

(Third embodiment)
A third embodiment will be described. In the second embodiment, the fluctuation of the packet fixed delay is detected by observing the accumulated amount of the buffer 110. On the other hand, in this embodiment, the fluctuation of the packet fixed delay is detected by observing the arrival time of each received packet 204.

  An example of a block diagram of the clock recovery apparatus according to the present embodiment is shown in FIG. In FIG. 5, the clock recovery apparatus 200 according to the present embodiment includes a buffer control unit 201, a buffer accumulation amount observation unit 202, a packet arrival time observation unit 203, a delay change detection unit 205, a frequency control unit 206, and a voltage control oscillator 207. Prepare.

  The clock recovery device 200 according to the present embodiment is obtained by adding a packet arrival time observation unit 203 to the clock recovery device 100 according to the second embodiment shown in FIG. The operations of the buffer control unit 201, the buffer accumulation amount observation unit 202, the frequency control unit 206, and the voltage control oscillator 207 according to the present embodiment are the same as the buffer control unit 101, the buffer accumulation amount observation unit 102, and the frequency control of the second embodiment. This is almost the same as the unit 106 and the voltage controlled oscillator 107. That is, the buffer accumulation amount observation unit 202 observes the accumulation amount of the packet 204 in the buffer 210 and outputs it to the frequency control unit 206. The frequency control unit 206 calculates an accumulated amount average value for each predetermined period Ta from the received accumulated amount, and outputs it to the voltage controlled oscillator 207. The voltage controlled oscillator 207 generates a clock 208 based on the received accumulated amount average value and outputs the clock 208 to the buffer control unit 201. The buffer control unit 201 outputs a TDM signal 209 from the buffer 210 in synchronization with the received clock 208. By using the clock 208 generated based on the accumulated amount average value, the receiving terminal synchronizes with the transmitting terminal.

  Here, in the present embodiment, the packet arrival time observation unit 203 constantly observes the arrival times of the received packets 204 and outputs the observed arrival times to the delay change detection unit 205.

  The delay change detection unit 205 uses the arrival time received from the packet arrival time observation unit 203 to calculate the difference between the packet arrival time at a certain time point and the packet arrival time before the certain time point in a predetermined period Tq. calculate. When the calculated difference changes greatly, it is determined that the packet fixed delay has changed. Then, the packet fixed delay change notification and the difference in arrival time as the delay change amount are output to the buffer control unit 201 and the frequency control unit 206.

  The operations of the buffer control unit 201 and the frequency control unit 206 when receiving the packet fixed delay change notification and the delay change amount are the same as the operations of the buffer control unit 101 and the frequency control unit 106 described in the second embodiment. It is the same and detailed description is omitted.

  In the present embodiment, the period Ta, which is the interval for calculating the accumulated amount average value, is set longer than the three periods of the period Tq, which is the interval for calculating the difference in packet arrival time, so that the influence of fluctuations in the packet fixed delay can be reduced. Can be removed appropriately.

  Furthermore, in this embodiment, a packet fixed delay is detected from the arrival time of each received packet 204. In this case, the processing related to the buffer accumulation amount (processing related to the adaptive clock regeneration method) and the packet fixed delay detection processing can be separated, and the processing related to the buffer accumulation amount can be avoided from being complicated.

DESCRIPTION OF SYMBOLS 10 Clock reproduction | regeneration apparatus 20 Buffer control means 30 Delay detection means 40 Clock control means 50 Clock output means 60 Buffer 100, 200 Clock reproduction apparatus 101, 201 Buffer control part 102, 202 Buffer accumulation amount observation part 203 Packet arrival time observation part 104, 204 packet 105, 205 delay change detection unit 106, 206 frequency control unit 107, 207 voltage controlled oscillator 108, 208 clock 109, 209 TDM signal 110, 210 buffer

Claims (8)

Buffer control means for receiving a packet and writing to the buffer, outputting the packet from the buffer in synchronization with the clock received from the clock output means, and outputting the accumulated amount;
Delay detection means for monitoring the presence or absence of a delay and detecting and calculating a delay amount; and
A torque lock control means to generate and output a clock control value based on the accumulated amount received from the buffer control unit,
Clock output means for generating and outputting a clock based on the clock control value received from the clock control means;
Equipped with a,
When the delay detection unit does not detect a delay, the buffer control unit measures and outputs the accumulated amount of the buffer. When the delay detection unit detects a delay, the buffer control unit outputs a packet for a period corresponding to the delay amount. Stop receiving or outputting packets, and output a specified amount of accumulation,
Clock recovery device. The delay detection means determines the presence or absence of a delay for each first period,
The clock control means generates the clock control value every second period longer than the first period;
The clock recovery device according to claim 1. The delay detection unit calculates an average value for the accumulated amount received from the buffer control unit for each first period, and a delay occurs when the average value of the calculated accumulation amount becomes constant after the change. It is determined that
The clock recovery device according to claim 2. Provided with a packet arrival time measuring means for measuring the arrival time of the received packet,
The delay detection means determines whether there is a change in the arrival time of the packet for each first period, and determines that a delay has occurred when the arrival time of the packet changes.
The clock recovery device according to claim 2. 5. The clock recovery device according to claim 2, wherein the clock control value is an average value of the delay amount in the second period. 6. When the buffer control means detects an underrun or overrun of the accumulated amount, it outputs a notification regarding the underrun or overrun,
When the clock control means receives a notification about underrun or overrun from the buffer control means, it generates and outputs a clock control value for eliminating the underrun or overrun.
The clock recovery device according to claim 1. Receive the packet, write it to the buffer,
Output the packet from the buffer in synchronization with the output clock,
Monitors the presence or absence of a delay, and if the delay is not detected, measures and outputs the accumulated amount of the buffer. If the delay is detected, calculates the delay amount and receives a packet or packet during a period corresponding to the delay amount. And output a predetermined accumulation amount,
Generate and output a clock control value based on the output accumulated amount,
Generating and outputting the clock based on the output clock control value;
Clock recovery method. A control program executable by a computer of a device that outputs packets from a buffer in synchronization with a clock,
The ability to receive packets and write them to a buffer;
Monitors the presence or absence of a delay, and if the delay is not detected, measures and outputs the accumulated amount of the buffer. If the delay is detected, calculates the delay amount and receives a packet or packet during a period corresponding to the delay amount. A function to stop the output of and output a predetermined accumulation amount,
A function of generating and outputting a clock control value based on the output accumulated amount;
A function of generating and outputting the clock based on the output clock control value;
A control program for causing a computer of the apparatus to execute the above.

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