JP5403973B2 - アウト・オブ・オーダ・プロセッサにおける述語型実行のための方法および装置 - Google Patents
アウト・オブ・オーダ・プロセッサにおける述語型実行のための方法および装置 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 30
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
- G06F9/30087—Synchronisation or serialisation instructions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30094—Condition code generation, e.g. Carry, Zero flag
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
- G06F9/384—Register renaming
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
- G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
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Description
isequal cr7, 0, r10
branch cr7, ELSE
sub r1=r1, r2
load r4=[r1]
jump MERGE
ELSE: add r1=r1, r2
load r3=[r1]
add r5=r3, r4
MERGE: store r5, [r1]
isequal cr7, 0, r10
emaskcr7, 11001b, 5
add r1=r1, r2
load r3=[r1]
sub r1=r1, r2
load r4=[r1]
add r5=r3, r4
MERGE: store r5, [r1]
Claims (11)
- アウト・オブ・オーダ・プロセッサにおいて述語付き命令を処理するための方法であって、
述語付き命令を含む述語付きコード領域に関連した述語定義命令を検出するステップと、
前記述語定義命令の述語が解明されるまで、前記述語付きコード領域内に含まれた述語付き命令のリネーミングをストールするステップと、
前記述語が解明されたという表示を受け取るステップと、
選択されたパスに関連する述語付き命令をリネームするステップと、
選択されなかったパスに関連する述語付き命令を、リネームされた前記述語付き命令を実行する前に、廃棄するステップと、
を含む、方法。 - 前記述語定義命令を検出するステップは、前記述語付きコード領域に関連した述語定義命令を前記アウト・オブ・オーダ・プロセッサのリネーム・ステージにおいて検出するステップを更に含む、請求項1に記載の方法。
- 前記述語定義命令に関連したマスクをマスク・シフト・レジスタに格納するステップと、
前記述語付き命令のうちのどれをリネームおよび実行すべきかを決定するために前記述語および前記格納されたマスクに関して論理機能を遂行するステップと、
を更に含む、請求項2に記載の方法。 - 前記述語は状態レジスタ値に基づいている、請求項1に記載の方法。
- 前記述語定義命令をデコードするステップと、
前記述語付き命令をデコードするステップと、
を更に含む、請求項1に記載の方法。 - 述語付き命令を含む述語付きコード領域に関連した述語定義命令をデコードするように構成されたデコーダと、
前記述語定義命令を検出するように、および、前記述語定義命令の述語が解明されるまで前記述語付き命令のリネーミングをストールするように構成されたパイプライン・ステージと、を含み、
前記パイプライン・ステージは、更に、
前記述語が解明されたという表示を受け取り、
選択されたパスに関連する述語付き命令をリネームし、
選択されなかったパスに関連する述語付き命令を、リネームされた前記述語付き命令を実行する前に、廃棄する、
アウト・オブ・オーダ・プロセッサ。 - 前記パイプライン・ステージはリネーム・ステージに含まれる、請求項6に記載のアウト・オブ・オーダ・プロセッサ。
- 前記リネーム・ステージは、更に、 前記述語定義命令に関連するマスクをマスク・シフト・レジスタに格納し、
前記述語付き命令のうちのどれをリネームおよび実行すべきかを決定するために前記述語および前記格納されたマスクに関して論理機能を遂行する
ように構成される、請求項7に記載のアウト・オブ・オーダ・プロセッサ。 - 前記述語は状態レジスタ値に基づいている、請求項6に記載のアウト・オブ・オーダ・プロセッサ。
- メモリ・サブシステムと、
前記メモリ・サブシステムに接続されたアウト・オブ・オーダ・プロセッサと、を含み、
前記アウト・オブ・オーダ・プロセッサは、
述語付き命令を含む述語付きコード領域に関連した述語定義命令をデコードするように構成されたデコーダと、
前記述語定義命令を検出するように、および、前記述語定義命令の述語が解明されるまで前記述語付き命令のリネーミングをストールするように構成されたリネーム・ステージとを含み、
前記リネーム・ステージは、更に、
前記述語が解明されたという表示を受け取り、
選択されたパスに関連する述語付き命令をリネームし、
選択されなかったパスに関連する述語付き命令を、リネームされた前記述語付き命令を実行する前に、廃棄する、
プロセッサ・システム。 - 前記リネーム・ステージは、更に、
前記述語定義命令に関連したマスクをマスク・シフト・レジスタに格納し、
前記述語付き命令のうちのどれを実行すべきかを決定するために前記述語および前記格納されたマスクに関して論理機能を遂行し、
前記論理機能の結果に基づいて前記述語付き命令の少なくとも1つをリネームする
ように構成される、請求項10に記載のプロセッサ・システム。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/856170 | 2007-09-17 | ||
US11/856,170 US9946550B2 (en) | 2007-09-17 | 2007-09-17 | Techniques for predicated execution in an out-of-order processor |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2009070378A JP2009070378A (ja) | 2009-04-02 |
JP5403973B2 true JP5403973B2 (ja) | 2014-01-29 |
Family
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Family Applications (1)
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JP2008230625A Expired - Fee Related JP5403973B2 (ja) | 2007-09-17 | 2008-09-09 | アウト・オブ・オーダ・プロセッサにおける述語型実行のための方法および装置 |
Country Status (2)
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US (1) | US9946550B2 (ja) |
JP (1) | JP5403973B2 (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8065505B2 (en) * | 2007-08-16 | 2011-11-22 | Texas Instruments Incorporated | Stall-free pipelined cache for statically scheduled and dispatched execution |
US8819399B1 (en) | 2009-07-31 | 2014-08-26 | Google Inc. | Predicated control flow and store instructions for native code module security |
US20110047357A1 (en) * | 2009-08-19 | 2011-02-24 | Qualcomm Incorporated | Methods and Apparatus to Predict Non-Execution of Conditional Non-branching Instructions |
US8433885B2 (en) * | 2009-09-09 | 2013-04-30 | Board Of Regents Of The University Of Texas System | Method, system and computer-accessible medium for providing a distributed predicate prediction |
CN102789377B (zh) | 2011-05-18 | 2015-09-30 | 国际商业机器公司 | 处理指令分组信息的方法和装置 |
US11693883B2 (en) | 2012-12-27 | 2023-07-04 | Teradata Us, Inc. | Techniques for ordering predicates in column partitioned databases for query optimization |
US10719325B2 (en) * | 2017-11-07 | 2020-07-21 | Qualcomm Incorporated | System and method of VLIW instruction processing using reduced-width VLIW processor |
US11042381B2 (en) * | 2018-12-08 | 2021-06-22 | Microsoft Technology Licensing, Llc | Register renaming-based techniques for block-based processors |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0287229A (ja) | 1988-09-24 | 1990-03-28 | Nec Corp | 実行命令の先取り制御方式 |
JPH10283185A (ja) | 1997-04-10 | 1998-10-23 | Matsushita Electric Ind Co Ltd | プロセッサ |
US6367004B1 (en) | 1998-12-31 | 2002-04-02 | Intel Corporation | Method and apparatus for predicting a predicate based on historical information and the least significant bits of operands to be compared |
US6442679B1 (en) | 1999-08-17 | 2002-08-27 | Compaq Computer Technologies Group, L.P. | Apparatus and method for guard outcome prediction |
US6513109B1 (en) | 1999-08-31 | 2003-01-28 | International Business Machines Corporation | Method and apparatus for implementing execution predicates in a computer processing system |
US6883089B2 (en) | 2000-12-30 | 2005-04-19 | Intel Corporation | Method and apparatus for processing a predicated instruction using limited predicate slip |
GB2402510A (en) | 2003-06-05 | 2004-12-08 | Advanced Risc Mach Ltd | Predication instruction within a data processing system |
KR100628573B1 (ko) | 2004-09-08 | 2006-09-26 | 삼성전자주식회사 | 조건부실행명령어의 비순차적 수행이 가능한 하드웨어장치 및 그 수행방법 |
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2007
- 2007-09-17 US US11/856,170 patent/US9946550B2/en not_active Expired - Fee Related
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- 2008-09-09 JP JP2008230625A patent/JP5403973B2/ja not_active Expired - Fee Related
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Publication number | Publication date |
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JP2009070378A (ja) | 2009-04-02 |
US9946550B2 (en) | 2018-04-17 |
US20090077354A1 (en) | 2009-03-19 |
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