JP5401809B2 - Silicon substrate and manufacturing method thereof - Google Patents

Description

  The present invention relates to a silicon substrate and a method for manufacturing the same, and more particularly to a silicon substrate for a solid-state imaging device that exhibits and improves the gettering ability regardless of the heat treatment in the device process and is used for manufacturing a solid-state imaging device. It relates to a suitable technique.

The solid-state imaging device is manufactured by forming a circuit on a silicon substrate sliced from a silicon single crystal pulled up by a CZ (Czochralski) method or the like. When heavy metal is mixed with impurities in the silicon substrate, the electrical characteristics of the solid-state imaging device, such as the occurrence of white scratch defects, are significantly deteriorated.
Causes of heavy metal impurities in the silicon substrate include firstly metal contamination in the manufacturing process of the silicon substrate consisting of single crystal pulling, slicing, chamfering, and surface treatment such as polishing, grinding, and etching, and secondly silicon Heavy metal contamination in the manufacturing process of a solid-state imaging device, which is a device process such as forming a circuit on a substrate, can be mentioned.
Therefore, conventionally, an IG (intrinsic gettering) method for forming oxygen precipitates on a silicon substrate and an EG (exitonic gettering) method for forming gettering sites such as backside damage on the back surface of the silicon substrate have been used. ing.

In order to reduce white scratch defects caused by dark current, which affect the electrical characteristics of the solid-state imaging device, techniques for carbon ion implantation are described in Patent Documents 1 and 2, and the EG method in Patent Document 3 in 0005 stage. An example of this is described, and Patent Document 3 describes a technique related to carbon ion implantation.
JP-A-6-338507 JP 2002-353434 A JP 2006-313922 A

  As described above, as a silicon substrate used in a solid-state imaging device, an intrinsic gettering method in which an oxygen precipitation heat treatment is performed before epitaxial growth to form an oxygen precipitate, or an ion implantation method in which ions such as carbon ions are implanted into a silicon substrate. Is used.

However, in manufacturing high-speed devices such as CCD and CIS, solid-state imaging from an n / n + / n type substrate, that is, a substrate in which an n + type layer and an n type epitaxial silicon layer are stacked on an n type silicon CZ substrate. In the case of manufacturing the element, the portion where the photodiode, which is the heart of the solid-state imaging device, accumulates, that is, the n + type layer becomes a ring getter, and the contaminated heavy metal is biased and the element characteristics are reduced. There was a problem of being lowered.
Here, the n type is a phosphorus (P) concentration of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ atoms / cm ³ , and the n + type is a phosphorus (P) concentration of 1.0 × 10 ^{18 to} 1.0 ×. 10 ²⁰ atoms / cm ³ , n-type means phosphorus (P) concentration of about 1.0 × 10 ^{14 to} 1.0 × 10 ¹⁶ atoms / cm ³ , n + type means resistivity resistivity 8 mΩcm to 10 mΩcm, n The -type corresponds to a resistivity of 0.1 to 100 Ωcm, and the n ++ type corresponds to a resistivity of about 0.1 mΩcm to 0.01 mΩcm.

Furthermore, in the case of the exotic trick gettering method formed by the conventional method described above, backside damage or the like is formed on the back surface, so that metal contamination occurs during such a processing step, thereby causing a defect factor of the device. There are disadvantages.
Further, when a high temperature heat treatment is performed on the carbon implantation substrate as in Patent Document 2, there is a concern that crystal defects (crystal lattice distortion, etc.) formed by carbon implantation are alleviated and the function as a gettering sink is lowered. Is done.

As a silicon substrate used for a solid-state imaging device, an intrinsic gettering method in which an oxygen precipitation heat treatment is performed before epitaxial growth to form an oxygen precipitate, or an ion implantation method in which ions such as carbon ions are ion-implanted into a silicon substrate, Both are concerned about heavy metal contamination during the manufacturing process of the silicon substrate. On the other hand, the exothermic gettering method has a disadvantage in that, since backside damage is formed on the back surface, particles are generated from the back surface during the device process, thereby forming a cause of device failure.
In addition, when a gettering layer is formed by ion implantation of carbon or the like, the concentration of carbon that becomes a gettering sink diffuses due to heat treatment in a subsequent process such as a device process, resulting in sufficient gettering. There was a problem that there was a possibility that it no longer exhibited the ability.

  The present invention has been made in view of the above circumstances, and is intended to reduce manufacturing costs, prevent a decrease in gettering ability in a device process in a solid-state image sensor, and ensure gettering ability in a solid-state image sensor. It is an object of the present invention to provide a silicon substrate and a method for manufacturing the same capable of improving the performance and the improvement thereof, reducing the metal contamination in the solid-state imaging device, and improving the yield in the solid-state imaging device.

In the method for producing a silicon substrate of the present invention, n / n + in which an n + implantation layer and an n epitaxial layer are formed on a substrate having a phosphorus (P) concentration of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ atoms / cm ^3. / N type silicon substrate manufacturing method,
Phosphorus (P) is doped by the CZ method at a concentration of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ atoms / cm ³ and the carbon concentration is 1.0 × 10 ^{16 to} 1.6 × 10 ¹⁷ atoms / cm 3. ^3. A preparation step of pulling up a silicon single crystal in an inert atmosphere containing hydrogen at an initial oxygen concentration of 1.4 × 10 ^{18 to} 1.6 × 10 ¹⁸ atoms / cm ³ and slicing the silicon single crystal;
A gettering revealing heat treatment step of 600 to 800 ° C. and 15 minutes to 4 hours after the preparation step;
An implantation step of ion-implanting an n-type dopant having a concentration of 1.0 × 10 ¹⁸ atoms / cm ³ or more on the surface to form an n + implantation layer;
A recovery heat treatment step of 950 to 1200 ° C. after the implantation step;
Forming an n epitaxial layer doped with an n-type dopant of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁷ atoms / cm ³ on the n + implanted layer;
It is characterized by having.
In the present invention, the n + injection layer may be 0.2 to 0.6 μm from the surface layer.
In the present invention, the n epitaxial layer may have a thickness of 2 to 10 μm.
In the present invention, the pressure of the atmosphere in which hydrogen is added to the inert gas in the step of pulling up the silicon single crystal is 1.33 kPa to 26.7 kPa of reduced pressure, and the hydrogen gas concentration in the atmosphere is 3 volume% to 20 volume. % And
The silicon single crystal can be lifted as a range of pulling speed that does not include COP and dislocation clusters and can pull the single crystal in the interstitial silicon dominant region (PI region).
The silicon substrate of the solid-state imaging device of the present invention is manufactured by any one of the manufacturing methods described above, and can be obtained by forming a gettering sink immediately below the embedded photodiode of the solid-state imaging device.
The silicon substrate of the present invention is doped with phosphorus (P) by the CZ method, has a carbon concentration of 1.0 × 10 ^{16 to} 1.6 × 10 ¹⁷ atoms / cm ³ , and an initial oxygen concentration of 1.4 × 10 ^18. A silicon substrate manufactured from a silicon single crystal grown as ˜1.6 × 10 ¹⁸ atoms / cm ³ ,
An n + implantation layer in which an n-type dopant having a concentration of 10 × 10 ¹⁸ atoms / cm ³ or more is ion-implanted on the surface, and 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁷ atoms / cm ³ on the n + implantation layer. An n epitaxial layer doped with an n-type dopant can be formed .
In the method for manufacturing a silicon substrate of the present invention, phosphorus (P) is doped by the CZ method, the carbon concentration is 1.0 × 10 ^{16 to} 1.6 × 10 ¹⁷ atoms / cm ³ , and the initial oxygen concentration is 1.4. A preparation step of growing a silicon single crystal as × 10 ^{18 to} 1.6 × 10 ¹⁸ atoms / cm ³ and slicing the silicon single crystal;
An implantation step of ion-implanting an n-type dopant having a concentration of 1.0 × 10 ¹⁸ atoms / cm ³ or more on the surface to form an n + implantation layer;
Forming an n epitaxial layer doped with an n-type dopant of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ atoms / cm ³ on the n + implanted layer;
Can have.
The present invention may have a recovery heat treatment step of 950 to 1200 ° C. after the implantation step.
The present invention may have a gettering clarification heat treatment step of 600 to 800 ° C. and 15 minutes to 4 hours after the preparation step.
The silicon substrate of the solid-state imaging device of the present invention is manufactured by any one of the manufacturing methods described above.
Here, the oxygen concentration is based on ASTM F121-1979.

A silicon substrate suitable for manufacturing a solid-state imaging device according to the present invention has a deposit nucleus (heavy metal gettering sink) by carbon addition and a silicon epitaxial layer formed directly thereon.
By using such a silicon substrate for manufacturing a solid-state imaging device, heavy metal is gettered by the substrate portion doped with carbon, and the contaminated heavy metal in the n + implantation layer serving as a ring getter is prevented from being biased. be able to. In addition, since the portion exhibiting gettering is not formed by ion implantation and exists over the entire thickness of the substrate before epi, carbon or the like diffuses due to the heat treatment conditions in the subsequent process, and its concentration decreases and the gettering ability decreases. There is nothing to do. As a result, defects due to heavy metal contamination do not occur in the transistors and embedded photodiodes that make up the solid-state image sensor, and the occurrence of white defects etc. in the solid-state image sensor can be prevented, and the yield of the solid-state image sensor can be reduced. It can be improved.

  Therefore, according to the present invention, it is possible to maintain a high gettering ability, and thus it is possible to provide a silicon substrate capable of reducing the influence of metal contamination, thereby preventing problems such as manufacturing costs and generation of particles in the device process. The effect that it can be solved can be produced.

Hereinafter, an embodiment of a silicon substrate according to the present invention will be described with reference to the drawings.
FIG. 1 is a front sectional view showing a silicon substrate in each step of the method for manufacturing a silicon substrate in the present embodiment, and FIG. 7 is a flowchart showing the method for manufacturing the silicon substrate in the present embodiment. Reference numeral 1 denotes a silicon substrate.

  In the method for manufacturing a silicon substrate in the present embodiment, as shown in FIG. 7, a preparation step S1 for preparing a silicon substrate (silicon wafer) 1, a gettering revealing heat treatment step S2, and an ion implantation step (implantation step). S3, recovery heat treatment step S4, epitaxial step S5, and device step S6 are included.

In the example shown in FIG. 1, first, as a preparatory step S1 shown in FIG. 7, for example, polysilicon as a raw material of silicon crystal is laminated in a quartz crucible, and an appropriate amount of graphite powder is applied on the surface of the polysilicon. At the same time, P (phosphorus) is added as a dopant, and according to the Czochralski method (CZ method), the carbon-added CZ crystal is pulled up as a hydrogen atmosphere as described later.
The CZ crystal is a name of a crystal manufactured by the Czochralski method including a magnetic field applied CZ crystal.

  Here, as an n-type silicon single crystal containing an n-type dopant such as phosphorus, carbon is added at the raw material stage to produce a silicon single crystal from the carbon-added raw material, and the oxygen concentration Oi is controlled and pulled up. . From this carbon-added CZ silicon single crystal, a silicon substrate 1 containing carbon is obtained as shown in FIG.

  The processing method of the silicon substrate 1 is usually followed by slicing with a cutting device such as an ID saw or a wire saw, annealing the obtained silicon wafer, and then performing a surface treatment process such as polishing and cleaning. In addition to these steps, there are various steps such as lapping, cleaning, grinding, mirror finishing, etc., and the steps are changed and used as appropriate according to the purpose, such as changing the order of steps or omitting them.

The silicon substrate 1 thus obtained has a phosphorus (P) concentration corresponding to the n type, carbon having a concentration of 1.0 × 10 ^{16 to} 1.6 × 10 ¹⁷ atoms / cm ³ , and a concentration. Contains 1.4 × 10 ^{18 to} 1.6 × 10 ¹⁸ atoms / cm ³ of oxygen.

  Since carbon is contained in silicon in the form of a solid solution, carbon is introduced into the silicon lattice in the form of replacing silicon. That is, since the atomic radius of carbon is smaller than that of silicon atoms, when carbon is coordinated at the substitution position, the crystal stress field becomes a compressive stress field, and interstitial oxygen and impurities are easily trapped in the compressive stress field. Starting from this substitutional carbon, for example, in a device process, precipitates with oxygen accompanying dislocations are easily developed at high density, and a high gettering effect can be imparted to the silicon substrate 1.

It is necessary to regulate the addition concentration of such carbon within the above range. This is because if the carbon concentration is less than the above range, the formation of carbon / oxygen-based precipitates is not actively promoted, so that the formation of the above-described high-density carbon / oxygen-based precipitates cannot be realized.
On the other hand, if the above range is exceeded, the formation of carbon / oxygen-based precipitates is promoted, and a high-density carbon / oxygen-based precipitate can be obtained. The tendency to become weaker becomes stronger. Therefore, the effect of trapping impurities is reduced because the effect of distortion is weak.

Furthermore, it is necessary to regulate the oxygen concentration in the silicon substrate 1 within the above range. This is because when the oxygen concentration is less than the above range, the formation of carbon / oxygen-based precipitates is not promoted, and thus the above-described high-density precipitates cannot be obtained.
On the other hand, if the above range is exceeded, the size of the oxygen precipitate is reduced, the effect of strain at the interface between the base silicon atom and the precipitate is relaxed, and there is a concern that the gettering effect due to strain is reduced.

  Furthermore, by using such carbon concentration and oxygen concentration, even if a phosphorus-doped n-type substrate is weak in oxygen precipitate formation compared to a p-type substrate doped with boron (B) or the like, Complex defect formation by oxygen can be promoted, and sufficient gettering ability can be obtained.

  Next, as the gettering clarification heat treatment step S2 shown in FIG. 7, this condition is given to the silicon substrate 1 which is a carbon-added CZ crystal in a mixed atmosphere of oxygen and an inert gas such as argon or nitrogen. As a temperature condition at which further precipitation promotion can be expected, a gettering revealing heat treatment is performed as a temperature condition of 600 to 800 ° C. and a heat treatment time of 0.25 to 4 hours, and carbon / oxygen is started from the substitutional position carbon. A system oxygen precipitate 7 is deposited.

As a result, a gettering sink having a high gettering ability against metal contamination in a subsequent process can be formed over the entire thickness of the silicon substrate 1 using the silicon substrate 3 containing solute carbon as a starting material. Therefore, gettering in the adjacent region on the surface of the silicon substrate 1 is realized.
In the present invention, the carbon / oxygen-based precipitate means a precipitate that is a composite (cluster) containing at least carbon.

In order to realize this gettering, the oxygen precipitate 7 which is a carbon / oxygen-based composite has a size of 10 to 100 nm, and 1.0 × 10 ^{6 to} 1.0 × 10 ^{11 in the} silicon substrate 1. Preferably it is present at the number of pieces / cm ³ .
In addition, the BMD size in this case means the diagonal length of the precipitate in the TEM observation image of the cross section in the thickness direction of the silicon substrate, and is represented by the average value of the precipitate in the observation field.

The reason why the size of the oxygen precipitates 7 is not less than the lower limit of the above range is to capture (gettering) interstitial impurities (for example, heavy metals) using the strain effect generated at the interface between the base silicon atoms and the oxygen precipitates. This is to increase the probability of performing. Further, if the size of the oxygen precipitates 7 is not less than the above range, it is not preferable because the substrate strength is lowered or the occurrence of dislocations in the epitaxial layer occurs.
Further, the density of the oxygen precipitates 7 in the silicon substrate is such that the capture (gettering) of heavy metals in the silicon crystal is caused by the strain generated at the interface between the base silicon atom and the oxygen precipitates and the interface state density (volume density). In order to depend, it is preferable to set it as said range.

In addition, in the gettering revealing heat treatment step S2 for providing the IG effect, regardless of the order of the other steps, if this heat treatment is lower than the above temperature range, the formation of the carbon / oxygen complex is insufficient, and the metal of the substrate When contamination occurs, it is not preferable because sufficient gettering ability cannot be expressed, and when it is higher than the above temperature range, oxygen precipitates are excessively aggregated, resulting in insufficient gettering sink density. It is not preferable.
Also, in this heat treatment, the temperature rise and fall and the increase / decrease of the treatment time can be set to different conditions as long as the heat treatment temperature / time is equal to or higher than that at 600 ° C. for 30 minutes. In addition, as long as the heat treatment temperature / time is equal to or lower than that at 800 ° C. for 4 hours, the temperature can be increased and decreased and the treatment time can be increased and decreased.

  Here, the silicon substrate 1 at the end of the preparation step S1 (before the gettering revealing heat treatment step S2) is a CZ crystal containing a dopant and solute carbon, but oxygen precipitation nuclei formed during the crystal growth, or Since the oxygen precipitates shrink due to the heat treatment during the epitaxial growth, no obvious oxide precipitates are observed on the silicon substrate 1 with an optical microscope.

  By the gettering revealing heat treatment step S2, a gettering sink for gettering heavy metals can be secured, and the silicon substrate can have an IG (gettering) effect.

Next, as an ion implantation step (implantation step) S3 shown in FIG. 7, it is inserted into an ion implantation furnace, and n-type dopant ions are implanted into the surface of the silicon substrate 1, and as shown in FIG. An n + implantation layer 2A is formed on the entire surface.
At this time, the thickness of the n + injection layer 2A is preferably in the range of 2 to 10 μm from the setting relating to the spectral sensitivity characteristics of the solid-state imaging device. Further, in the n + implantation layer 2A, the dopant concentration of phosphorus is set to be n + type.
As ion implantation processing conditions at this time,
Implanted ions; P ⁺
Implantation energy; 100-150 keV,
Implantation dose; 4 × 10 ¹⁷ cm ⁻² to 1 × 10 ¹⁷ cm ⁻² ,
Processing substrate temperature: 400 ° C to 600 ° C

  Here, the thickness of the n + injection layer 2A is determined by the spectral sensitivity characteristic of the solid-state imaging device, and as shown in FIG. 6, the wavelength peak detected by the solid-state imaging device is on the short wavelength side indicated by the alternate long and short dash line. From the case of having a characteristic to the case of corresponding to visible light indicated by a broken line, the case corresponding to the infrared side indicated by a solid line, respectively, corresponding to the case of corresponding to the infrared side indicated by a solid line, it is set from the case where the film thickness is thin to the above range preferable.

Next, annealing treatment is performed as a recovery heat treatment step S4 shown in FIG. As a result, the silicon substrate 1 roughened by the ion implantation is cured to recover the bonding state of the silicon single crystal, and the surface state of the silicon substrate 1 is recovered.
As processing conditions at this time,
Treatment time: 950-1200 ° C
Ar atmosphere treatment time: 5 to 10 hours

Next, as an epitaxial step S5 shown in FIG. 7, the wafer is placed in an epitaxial growth furnace and is formed on the n + implantation layer 2A using various CVD methods (chemical vapor deposition methods) as shown in FIG. 1C. , N type epitaxial layer 2B is grown to form silicon substrate 3.
Here, the thickness of the n epitaxial layer 2 </ b> B is preferably in the range of 0.2 to 0.6 μm from the setting regarding the spectral sensitivity characteristics of the solid-state imaging device.
As the epitaxial step S5, before the epitaxial layer is grown, for example, RCA cleaning combining SC1 and SC2 can be performed.

As shown in FIG. 1D, an n / n + / n type silicon substrate 3 on which the n + implantation layer 2A and the n epitaxial layer 2B are formed has an oxide film on the n epitaxial layer 2B as needed. 4. Further, after the nitride film 5 is formed, the nitride film 5 is used in a device process to be described later. In this process, a buried photodiode is formed in the epitaxial layer 2B, whereby the solid-state imaging device 6 is obtained.
Note that the thicknesses of the oxide film 4 and the nitride film 5 are 50 to 100 nm for the oxide film 4 and the polysilicon film 5 in the solid-state imaging device, respectively, due to restrictions in designing the drive voltage of the transfer transistor. The silicon gate film 5 is preferably 1.0 to 2.0 μm.

Next, as a device step S6 shown in FIG. 7, a device such as a solid-state image sensor is formed. In addition, as this device process S6 process, the general manufacturing process of a solid-state image sensor can be employ | adopted. As an example, a CCD device is shown in FIG. 2, but it is not necessary to limit the process to the process shown in the figure.
That is, in the device step S6, first, as shown in FIG. 2A, a semiconductor substrate 3 in which n + type and n type layers 2A and 2B are formed on the silicon substrate 1 shown in FIG. As shown in FIG. 2B, a first p-type well region 11 is formed at a predetermined position of the epitaxial layer 2B. Thereafter, as shown in FIG. 2C, a gate insulating film 12 is formed on the surface, and n-type and p-type impurities are selectively implanted into the first p-type well region 11 by ion implantation. Thus, an n-type transfer channel region 13, a p-type channel stop region 14 and a second p-type well region 15 constituting the vertical transfer register are formed.
Next, as shown in FIG. 2D, the transfer electrode 16 is formed at a predetermined position on the surface of the gate insulating film 12. Thereafter, as shown in FIG. 2E, n-type and p-type impurities are selectively implanted between the n-type transfer channel region 13 and the second p-type well region 15 to thereby form the p-type. A photodiode 19 is formed by laminating the positive charge accumulation region 17 and the n-type impurity diffusion region 18.
Further, as shown in FIG. 2 (f), after forming the interlayer insulating film 20 on the surface, a light shielding film 21 is formed on the surface of the interlayer insulating film 20 except just above the photodiode 19, thereby solid-state imaging. The element 10 can be manufactured.

  In the above device process, for example, in the gate oxide film formation process, the element isolation process, and the polysilicon gate electrode formation, it is usual that a heat treatment at about 600 ° C. to 1000 ° C. is performed. Precipitation 7 can be precipitated and can act as a gettering sink in the subsequent steps. Thereby, it is possible to further prevent the heavy metal from segregating in the n + implantation layer 2A serving as a ring getter and deteriorating the device characteristics.

The heat treatment conditions in these device processes correspond to the conditions shown in FIG.
Specifically, for the silicon substrate 3 on which the n + implantation layer 2A and the n epitaxial layer 2B are formed, each of step1, step2, step3, step4, and step5 from the initial stage shown in FIG. It can be said that this corresponds to the point in time when each step of the transistor forming step is completed.

  Next, the pulling of the carbonized CZ silicon single crystal will be described. Although a wafer having a diameter of 300 mm will be described, the invention is not limited to this.

  FIG. 4 is a longitudinal sectional view of a CZ furnace suitable for explaining the production of a silicon single crystal in the present embodiment. The CZ furnace includes a quartz crucible (crucible) 101 disposed in the center of the chamber and a heater 102 disposed outside the crucible 101. The quartz crucible 101 has a double structure in which the quartz crucible 101 that accommodates the raw material melt 103 is held by an outer graphite crucible 101a, and is rotated and moved up and down by a support shaft 101b called a pedestal. A cylindrical heat shield 107 is provided above the crucible 101. The heat shield 107 has a structure in which an outer shell is made of graphite and graphite felt is filled therein. The inner surface of the heat shield 7 is a tapered surface whose inner diameter gradually decreases from the upper end to the lower end. The upper outer surface of the heat shield 107 is a tapered surface corresponding to the inner surface, and the lower outer surface is formed in a substantially straight surface so as to gradually increase the thickness of the heat shield 107 downward.

In this CZ furnace, for example, a 300 mm single crystal can be grown with a target diameter of 310 mm and a body length of, for example, 1200 mm.
An example of the specification of the thermal shield 107 is as follows. The outer diameter of the portion entering the crucible is, for example, 570 mm, the minimum inner diameter S at the lowermost end is, for example, 370 mm, the radial width W is, for example, 100 mm, and the inclination of the inner surface, which is an inverted frustoconical surface, with respect to the vertical direction is, for example, 21 °. The inner diameter of the crucible 1 is 650 mm, for example, and the height H from the melt surface at the lower end of the heat shield 7 is 60 mm, for example.

Next, a method for setting operating conditions for growing the carbonized CZ silicon single crystal will be described.
First, 250 kg of high-purity silicon polycrystal is charged into the crucible, for example, and n-type dopant phosphorus (P) is added so that the resistivity in the crystal becomes a concentration corresponding to the n-type.

In the present embodiment, the dopant is added to the silicon melt so that the carbon concentration is in the above-described range.
In addition, the crystal rotation speed, the crucible rotation speed, the heating conditions, the applied magnetic field conditions, and the like are controlled so as to achieve the above-described oxygen concentration.

  Then, the inside of the apparatus is inert gas atmosphere, the pressure is reduced to 1.33 to 26.7 kPa (10 to 200 torr), and hydrogen gas is mixed in the inert gas (Ar gas or the like) to 3 to 20% by volume. And let it flow into the furnace. The pressure is 1.33 kPa (10 torr) or more, preferably 4 to 26.7 kPa (30 to 200 torr), and more preferably 4 to 9.3 kPa (30 to 70 torr). As the lower limit of the pressure, since the hydrogen concentration in the melt and the crystal decreases as the partial pressure of hydrogen decreases, the lower limit pressure is defined to prevent this. The upper limit of the pressure is that the gas flow rate on the melt of an inert gas such as Ar decreases as the pressure in the furnace increases, so that the carbon degassed from the carbon heater or carbon member, or the SiO evaporated from the melt As a result, it becomes difficult to exhaust the reactant gas, etc., so that the carbon concentration in the crystal becomes higher than the desired value, and SiO aggregates in the upper part of the melt in the furnace at about 1100 ° C. or at a lower temperature, Since dust is generated and dropped into the melt to cause dislocation of crystals, the upper limit pressure is defined in order to prevent these.

  Next, the silicon is melted by heating with the heater 102 to obtain a melt 103. Next, the seed crystal attached to the seed chuck 105 is immersed in the melt 103, and the crystal is pulled up while rotating the crucible 101 and the pulling shaft 104. The crystal orientation is any one of {100}, {111} or {110}, and after performing the seed squeezing for crystal dislocation, the shoulder portion is formed and the shoulder is changed to a target body diameter of, for example, 310 mm. To do.

  After that, the body part is grown up to 1200 mm, for example, at a constant pulling speed, the diameter is reduced under normal conditions, tail tailing is performed, and then the crystal growth is finished. Here, the pulling speed is appropriately selected according to the resistivity, the silicon single crystal diameter size, the hot zone structure (thermal environment) of the single crystal pulling apparatus to be used, etc., for example, qualitatively within the single crystal plane In this case, the pulling rate including the region where the OSF ring is generated can be adopted, and the lower limit thereof can be set to be higher than the pulling rate at which the OSF ring region is generated in the single crystal plane and the dislocation cluster is not generated.

  Further, the hydrogen concentration in the inert atmosphere can be set in the range of 3% to 20% with respect to the furnace pressure of 4.0 to 9.33 kPa (30 to 70 torr). The furnace pressure is 1.33 kPa (10 torr) or more, preferably 4.0 to 26.7 kPa (30 torr to 200 torr), and more preferably 4.0 to 9.3 kPa (30 torr to 70 torr). The lower limit value is defined as the lower limit pressure described above in order to prevent the hydrogen concentration in the melt and crystal from being lowered when the partial pressure of hydrogen is lowered. The upper limit value is that when the pressure in the furnace increases, the gas flow rate on the melt of an inert gas such as Ar decreases, so that carbon degassed from the carbon heater or carbon member, SiO evaporated from the melt, etc. This makes it difficult for the reactant gas to be exhausted, so that the carbon concentration in the crystal becomes higher than the desired value, and the SiO agglomerates in the upper part of the melt in the furnace at about 1100 ° C. or at a lower temperature. Is generated and dropped into the melt to cause dislocation of the crystal. Therefore, in order to prevent these, the upper limit pressure is defined. The hydrogen partial pressure is preferably 40 pa or more and 400 Pa or less.

The hydrogen concentration in the silicon single crystal during growth in an inert atmosphere containing hydrogen can be controlled by the hydrogen partial pressure in the atmosphere. When hydrogen is introduced into the crystal, hydrogen in the atmosphere is dissolved in the silicon melt to be in a steady (equilibrium) state, and the concentration in the liquid phase and the solid phase is distributed to the crystal by concentration segregation during solidification.
The hydrogen concentration in the melt is determined by Henry's law depending on the hydrogen partial pressure in the gas phase, and the hydrogen concentration in the crystal immediately after solidification is constant in the axial direction of the crystal by controlling the hydrogen partial pressure in the atmosphere. The desired concentration can be controlled.

According to such a silicon single crystal growth method, by pulling up the silicon single crystal in an inert atmosphere containing hydrogen, the COP and dislocation clusters are not included in the entire crystal diameter direction, and the interstitial silicon dominant region (PI) The single crystal can be pulled up by expanding the range of the pulling speed of the PI region, and the single crystal straight body can be made into an interstitial silicon dominant region (PI region) not including dislocation clusters, and at the same time, OSF Due to the reduction in the ring width, when pulling up a grown-in defect-free single crystal, the PI region pulling speed, which had to be set in a very narrow range, has been increased, making it extremely easy. In addition, it is possible to grow a Grown-in defect-free single crystal at a higher pulling speed than in the prior art, and in the crystal plane, When a silicon single crystal is pulled under the conditions in which ring region is generated, it is possible to reduce the influence by reducing the width of the OSF ring.
Here, the PI region pulling speed range is a state in which the value of the axial temperature gradient G in the crystal immediately after solidification described above is constant and does not change when comparing in a hydrogen atmosphere and in an inert atmosphere without hydrogen. Compare with

More specifically, by setting the PI region pulling speed range in which the grown-in defect-free single crystal consisting of the interstitial silicon-type grown-in defect-free region (PI region) can be pulled to be a hydrogen atmosphere, there is no hydrogen. As shown in FIG. 5, it can be pulled up to a margin of 4.5 times or more compared to the time, and the desired single crystal can be pulled up by the pulling speed in such a range. It becomes possible.
At this time, the generation area of the OSF ring can be reduced. Note that the size of the PV region (vacancy type Grown-in defect free region) is not changed by hydrogen addition.

  In this embodiment, by performing hydrogenation as described above, it is easy to pull up the grown-in defect-free single crystal, and by adding carbon, the influence of the OSF ring can be reduced. Due to these synergistic effects, defects caused by the OSF ring can be reduced when an epitaxial layer is grown on this wafer, the above-mentioned single crystal having the desired quality can be pulled up, and work efficiency can be improved. As a result, it is possible to greatly reduce the manufacturing cost of a silicon single crystal or a silicon substrate manufactured from this silicon single crystal.

In the present embodiment, as described above, in the silicon substrate 1 in which the carbon and oxygen concentrations are set, the gettering revealing heat treatment step S2 is performed before the ion implantation step (implantation step) S3 as shown in FIG. In the ion implantation process, which is highly likely to cause heavy metal contamination, the gettering ability can be sufficiently exerted to cope with the occurrence of contamination. At the same time, it is possible to maintain the gettering capability sufficiently to the extent that contamination occurs in a process subsequent to the gettering revealing heat treatment step S2, especially when metal contamination occurs in the device step S6. .
Further, the gettering revealing heat treatment step S2 can be performed in another order as long as it is before the device step S6. In this case, it is possible to continue to maintain the gettering ability sufficiently to cope with the case where metal contamination occurs in the process after the gettering revealing heat treatment process S2.

The method for producing a silicon substrate of the present invention has a concentration corresponding to a resistivity of 8 mΩcm to 10 mΩcm, a carbon concentration of 0.5 × 10 ^{16 to} 1.6 × 10 ¹⁷ atoms / cm ³ , oxygen by CZ method. Pulling up a silicon single crystal having a concentration of 1.4 × 10 ^{18 to} 1.6 × 10 ¹⁸ atoms / cm ³ ;
The above-mentioned problems have been solved by including a heat treatment step for performing a heat treatment for forming oxygen precipitates on a silicon substrate sliced from the pulled silicon single crystal.
In the present invention, the heat treatment for forming the oxygen precipitates may be performed in a mixed atmosphere of oxygen and an inert gas such as argon or nitrogen at a temperature of 600 ° C. to 800 ° C., a treatment time of 0.25 hours to 3 hours. it can.
In another aspect of the present invention, a step of forming a silicon epitaxial layer having an n-type dopant concentration of 0.1 to 100 Ωcm on the sliced silicon substrate surface before heat treatment for forming oxygen precipitates is performed. More preferably.
Furthermore, according to another aspect of the present invention, hydrogen can be added to an inert atmosphere gas when growing the silicon single crystal. At this time, hydrogen is added to the inert gas in the step of pulling up the silicon single crystal. The atmospheric pressure of the added atmosphere can be reduced from 1.33 kPa to 26.7 kPa, and the hydrogen gas concentration in the atmosphere can be from 3% by volume to 20% by volume.
Moreover, the silicon substrate of the present invention is manufactured by any one of the manufacturing methods described above,
Among the BMDs serving as intrinsic gettering sinks, a means in which a density of 10 to 100 nm exists in a density of 1.0 × 10 ^{6 to} 1.0 × 10 ¹¹ pieces / cm ³ can also be employed.
The silicon substrate of the solid-state imaging device of the present invention has a density of 1.0 × 10 ^{6 to} 1.0 × 10 ¹¹ / cm BMD having a size of 10 to 100 nm at a position directly below the embedded photodiode of the solid-state imaging device. ³ is a silicon substrate on which a gettering layer existing in ³ is formed,
A silicon epitaxial layer having an n-type dopant concentration of 0.1 to 100 Ωcm is formed directly on the silicon substrate manufactured by the above manufacturing method,
The gettering layer may be provided immediately below the epitaxial layer.

  The inventors diligently studied a technique capable of preventing heavy metal contamination on a silicon substrate. First, we investigated the gettering method by carbon ion implantation. The gettering effect by carbon ion implantation is mainly due to the oxide deposited from the origin of the distortion (distortion) of the silicon lattice caused by ion implantation through high energy. Such lattice disturbances are concentrated in a narrow ion-implanted region, and the distortion around the oxide is easily released, for example, during high-temperature heat treatment in the device process. It turned out to be scarce.

  Therefore, as a result of a detailed examination of the action of carbon involved in the formation of gettering sinks in a silicon substrate, solid solution is achieved by replacing carbon with silicon in the silicon lattice rather than forcibly introducing carbon by ion implantation. From this substitution position, for example, in the device process, when carbon / oxygen-based precipitates with dislocations are expressed at high density, it is found that the carbon / oxygen-based precipitates have a high gettering effect. did. Furthermore, it has been found that such substitution is introduced for the first time when carbon or oxygen is contained in a silicon single crystal in a solid solution state.

The inventors have analyzed and studied the state and behavior of carbon and oxygen, and as a result, the n-type dopant concentration is equivalent to a resistivity of 8 mΩcm to 10 mΩcm, and the carbon concentration is 0.5 × 10 ^{16 to} 1.6 × 10 ^17. In a silicon single crystal pulled under conditions of atoms / cm ³ and oxygen concentration of 1.4 × 10 ^{18 to} 1.6 × 10 ¹⁸ atoms / cm ³ , an epitaxial layer is formed by processing into a wafer, and 600 to After a heat treatment step of 800 ° C., a gettering sink necessary for heavy metal gettering can be formed as a BMD size and density, and a silicon substrate having sufficient gettering ability can be manufactured. I found out.

Further, in the present invention, when carbon is added to the n-type dopant-added silicon crystal in the range of 0.5 × 10 ^{16 to} 1.6 × 10 ¹⁶ atoms / cm ³ , carbon and oxygen are used as nuclei in the crystal growth process. Gettering sinks are formed, which exist stably even at high temperature heat treatment and may exist after epitaxial growth. Therefore, it acts as a nucleus for oxygen precipitation immediately after epitaxial growth, grows in the device heat treatment step, and effectively acts as a gettering sink against heavy metal contamination in the device heat treatment step.

The silicon substrate of the present invention is suitable for use as a silicon substrate for a solid-state imaging device, but can be applied to any substrate that requires a high gettering capability.
For example, it can be used as a wafer for Multi Chip Package (MCP) such as NAND-FLASH or NOR-FLASH. Also in this case, since the device structure is CMOS, the n-type dopant concentration corresponds to a resistivity of 8 mΩcm to 10 mΩcm, the carbon concentration is 0.5 × 10 ^{16 to} 1.6 × 10 ¹⁷ atoms / cm ³ , and the oxygen concentration is A high gettering capability can be maintained in the range of 1.4 × 10 ^{18 to} 1.6 × 10 ¹⁸ atoms / cm ³ .

Furthermore, the present invention is a silicon substrate of a solid-state image pickup device having a high capture efficiency of heavy metal in which a gettering layer is formed immediately below an embedded photodiode of the solid-state image pickup device, and formed on a CZ crystal added with carbon and directly thereon. The solid-state imaging device silicon substrate manufacturing method is characterized in that the n + implantation layer and the n epitaxial layer are formed, and a gettering sink is formed immediately below the n + implantation layer.
In the present invention, by adding carbon to the CZ crystal, a gettering sink can be formed directly under the n + implantation layer by using a manufacturing process (heat treatment process) of a solid-state imaging device to remove heavy metal contamination in the device process. Quality such as electrical characteristics can be improved.

The present invention is a silicon substrate of a solid-state image sensor having a high capture efficiency of heavy metals, in which a gettering layer is formed immediately below the embedded photodiode of the solid-state image sensor, and carbon is 0.5 × 10 ^{16 to} 1.6 ×. A method of manufacturing a silicon substrate for a solid-state imaging device, characterized in that a gettering sink is formed by carbon and oxygen using a CZ crystal having a resistivity of <10 mΩcm and an n-type dopant concentration added with 10 ¹⁷ atoms / cm ³ as a substrate. be able to.
Further, according to the present invention, sufficient gettering ability can be maintained even in a heat treatment process in which minute oxygen precipitates with high density and secondary dislocations are formed immediately below the epitaxial layer in the image pickup device device process and the temperature is lowered.

This is a silicon substrate of a solid-state image sensor having a high capture efficiency of heavy metals, in which a gettering layer is formed immediately below the embedded photodiode of the solid-state image sensor, and is a CZ crystal added with carbon. Here, a gettering sink with a carbon concentration of 0.5 × 10 ^{16 to} 1.6 × 10 ¹⁷ atoms / cm ³ and an oxygen concentration of 1.4 × 10 ^{18 to} 1.6 × 10 ¹⁸ atoms / cm ³ is formed. A solid-state imaging device silicon substrate manufacturing method can be obtained.
Also in the present invention, particularly when the temperature range of the heat treatment step is 600 ° C. to 700 ° C., high density gettering can be formed immediately below the epitaxial layer and high gettering ability can be expected. Thus, when a solid-state imaging device is manufactured, the electrical characteristics can be improved. Thereby, the yield of a solid-state image sensor can be improved.

The silicon substrate for a solid-state imaging device of the present invention can use a heat treatment process of a manufacturing process in which carbon is contained in a CZ crystal and MCZ crystal having a predetermined n-type dopant concentration / oxygen concentration and a device is mounted on the silicon substrate. By setting appropriate heat treatment conditions, carbon / oxygen precipitates with high gettering ability can be formed.
Therefore, since a gettering sink that extends from directly below the buried photodiode over the entire thickness of the silicon substrate can be formed, the diffusion of heavy metal from the n + implantation layer to the surface device side in the device process is suppressed, and defects in the device are avoided. As a result, it is possible to provide a high-quality solid-state imaging device with good electrical characteristics at a low cost.

It is a front sectional view showing an embodiment of a method for manufacturing a silicon substrate according to the present invention. It is a figure which shows the manufacture procedure of a solid-state image sensor. It is a figure explaining the heat processing in the Example of this invention. It is a longitudinal cross-sectional view of a CZ pulling furnace. It is a schematic diagram which shows the change of the pulling-up speed area | region by hydrogen addition. It is a figure which shows the spectral characteristic of a solid-state image sensor. It is a flowchart which shows one Embodiment of the manufacturing method of the silicon substrate which concerns on this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2A ... n + injection | pouring layer 2B ... n epitaxial layer

Claims (5)

Production of silicon substrate of n / n + / n type in which phosphorus ( P ) has an n + implantation layer and an n epitaxial layer formed on a substrate having a concentration of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ atoms / cm ³ A method,
Phosphorus ( P ) is doped by the CZ method at a concentration of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁸ atoms / cm ³ and the carbon concentration is 1.0 × 10 ^{16 to} 1.6 × 10 ¹⁷ atoms / cm 3. ^3. A preparation step of pulling up a silicon single crystal in an inert atmosphere containing hydrogen at an initial oxygen concentration of 1.4 × 10 ^{18 to} 1.6 × 10 ¹⁸ atoms / cm ³ and slicing the silicon single crystal;
A gettering revealing heat treatment step of 600 to 800 ° C. and 15 minutes to 4 hours after the preparation step;
An implantation step of ion-implanting an n-type dopant having a concentration of 1.0 × 10 ¹⁸ atoms / cm ³ or more on the surface to form an n + implantation layer;
A recovery heat treatment step of 950 to 1200 ° C. after the implantation step;
Forming an n epitaxial layer doped with an n-type dopant of 1.0 × 10 ^{16 to} 1.0 × 10 ¹⁷ atoms / cm ³ on the n + implanted layer;
A method for producing a silicon substrate, comprising: Method for manufacturing a silicon substrate according to claim 1, wherein said n + implanted layer is a 0.2~0.6μm from the surface layer. Method for manufacturing a silicon substrate according to claim 1, wherein the n epitaxial layer is characterized in that it is a film thickness of 2 to 10 [mu] m. The atmospheric pressure of the atmosphere in which hydrogen is added to the inert gas in the step of pulling up the silicon single crystal is 1.33 kPa to 26.7 kPa of reduced pressure, and the hydrogen gas concentration in the atmosphere is 3% to 20% by volume. ,
2. The method of manufacturing a silicon substrate according to claim 1 , wherein the silicon single crystal is pulled up within a pulling speed range that does not include COP and dislocation clusters and can pull up the single crystal in the interstitial silicon dominant region (PI region) . Produced by the method according to any one of claims 1 to 4, a silicon substrate of a solid-state imaging device, characterized in that by forming a gettering sink directly beneath the buried photodiode of the solid-state imaging device.

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