JP2007273959A - Light-detecting device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variations in the electrical characteristics, while enhancing the gettering effect. <P>SOLUTION: A light-detecting device comprises a semiconductor substrate 101 that contains of silicon as a base material and contains carbon at a predetermined concentration; and an epitaxial layer 102 that has silicon as a base material, is grown epitaxially on the semiconductor substrate 101 and is provided with a light-detecting portion (mainly 104), in a region at a predetermined distance from the semiconductor substrate 101. The semiconductor substrate 101 is crystal grown, by using a melt that is obtained by melting a silicon-containing material and a carbon-containing material so that carbon is contained in the semiconductor substrate 101 at a predetermined concentration. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a light detection element, and more particularly to a gettering technique.

  Generally, a gettering technique is applied to a solid-state imaging device which is a kind of light detection device in order to reduce white scratches and dark current. The gettering technique is a technique for removing heavy metal impurities (Fe, Ni, etc.) and crystal defects, which are main causes such as white scratches, from an element formation region of a semiconductor substrate. In IG (Intrinsic Gettering), which is a typical gettering technology, heat treatment is performed to generate BMD ((Bulk Micro Defect) mainly oxygen precipitation defects) inside the semiconductor substrate, and heavy metal impurities and crystal defects due to strain stress caused by this. Trying to capture. As a result, heavy metal impurities are removed from the element formation region of the semiconductor substrate.

In recent years, techniques for further improving the gettering effect have been developed. For example, Patent Document 1 discloses a technique for ion-implanting carbon into a silicon substrate. When carbon is ion-implanted into the silicon substrate, the strain stress increases due to the acceleration of the generation of BMD, and the strain stress is generated due to the difference in atomic radius between silicon and carbon. As a result, the gettering effect is further improved.
JP-A-6-338507 (Patent No. 3384506)

  However, as a result of research and development by the inventors, if carbon is ion-implanted into the silicon substrate, the gettering effect can be improved, but the blooming suppression voltage between the manufactured solid-state imaging devices, It has been found that variations in saturation capacitance, read voltage, etc. (hereinafter referred to as “electrical property variations”) become large. If the variation in the electrical characteristics between the elements increases, it is necessary to increase the various applied voltages in anticipation of this, and this hinders the reduction in power consumption of the solid-state imaging element.

This problem is common not only to solid-state imaging devices but also to photodetection devices (for example, light-receiving devices for photocouplers, optical communications, and optical pickups) to which gettering technology is applied.
Accordingly, an object of the present invention is to provide a photodetection element capable of reducing the variation in electrical characteristics while improving the gettering effect, and a method for manufacturing the same.

  The photodetector according to the present invention uses a first element as a base material, a semiconductor substrate containing a second element of the same family as the first element at a predetermined concentration, and the first element on the semiconductor substrate. And an epitaxial layer having a light detection portion in a region separated from the semiconductor substrate by a predetermined distance, and the semiconductor substrate has a second element contained in the semiconductor substrate as the predetermined element. A material containing the first element and a material containing the second element are crystal-grown from the melted raw material melt so as to have a concentration.

The inventor has confirmed through experiments that according to the above-described configuration, the variation in electrical characteristics of the photodetecting element can be reduced while improving the gettering effect.
As for the reason why the inventor can reduce the variation in the electrical characteristics, (1) the variation in the electrical characteristics is caused by the variation in the distribution of the second element (for example, carbon) in the semiconductor substrate, and (2) By adding the second element to the raw material melt of the semiconductor substrate, variation in the distribution of the second element in the semiconductor substrate can be reduced as compared with the method of ion-implanting the second element. I guess there is.

The above (1) is considered as follows.
BMD tends to occur near the second element. Therefore, the distribution of BMD varies according to the distribution of the second element. Variations in the distribution of BMD induce variations in parasitic capacitance and parasitic resistance in the semiconductor substrate. Then, it is considered that the electrical characteristics in the semiconductor substrate vary.

The above (2) is considered as follows.
If the second element is added to the raw material melt of the semiconductor substrate as described above, the second element is distributed substantially uniformly in the semiconductor substrate during the crystal growth process. On the other hand, when the second element is added by ion implantation, it is difficult to distribute the second element substantially uniformly in the semiconductor substrate. This is mainly due to the fact that the ion beam has a gradient of ion density in the radial direction and that an accuracy error occurs when the ion beam is scanned over the entire area of the semiconductor substrate (wafer). Yes. In consideration of this, the method of adding the second element to the raw material melt reduces the variation in the distribution of the second element in the semiconductor substrate as compared with the method of ion-implanting the second element. It is thought that you can.

The first element is silicon, the second element is carbon, and the predetermined concentration is in the range of 1 × 10 ^{16 to} 2.5 × 10 ¹⁷ atoms / cm ³ . It is good.
According to the above configuration, since the concentration of carbon in the silicon substrate is 1 × 10 ¹⁶ atoms / cm ³ or more, BMDs serving as gettering sites can be formed with high density. As a result, the gettering effect can be improved. Further, since the concentration of carbon in the silicon substrate is 2.5 × 10 ¹⁷ atoms / cm ³ or less, BMD is not excessively formed. Therefore, it is possible to prevent a reduction in the strength of the semiconductor substrate due to the occurrence of dislocations and slips.

The number of BMDs per unit cross-sectional area of the semiconductor substrate may be included in a range of 5 × 10 ^{5 to} 5 × 10 ⁷ pieces / cm ² .
According to the above configuration, since the number of BMDs per unit cross-sectional area of the semiconductor substrate is 5 × 10 ⁵ pieces / cm ² or more, metal impurities and crystal defects existing in the semiconductor substrate can be strongly gettered. . In addition, since the number of BMDs per unit cross-sectional area of the semiconductor substrate is 5 × 10 ⁷ pieces / cm ² or less, it is possible to prevent a reduction in strength of the semiconductor substrate due to the occurrence of dislocations and slips.

The BMD size of the semiconductor substrate may be in the range of 50 to 400 nm.
According to the above configuration, since the size of the BMD is 50 nm or more, it is possible to strongly getter metal impurities and crystal defects present in the semiconductor substrate. Further, since the size of the BMD is 400 nm or less, it is possible to prevent the strength of the semiconductor substrate from being lowered due to the occurrence of dislocations and slips.

The epitaxial layer may have a thickness in the range of 4 μm to 6 μm.
According to the above configuration, it is possible to reduce the electronic shutter voltage while preventing the variation in the impurity concentration in the semiconductor substrate from affecting the electrical characteristics of the epitaxial layer.

Further, the ratio ρ2 / ρ1 between the resistivity ρ1 of the semiconductor substrate and the resistivity ρ2 of the epitaxial layer may be included in the range of 20 or more and 200 or less.
According to the above configuration, it is possible to create a solid-state imaging device that satisfies various electrical characteristics while reducing the electronic shutter voltage.
The photodetector according to the present invention uses a first element as a base material, a semiconductor substrate containing a second element of the same family as the first element at a predetermined concentration, and the first element on the semiconductor substrate. And an epitaxial layer having a light detection portion in a region separated from the semiconductor substrate by a predetermined distance, and the second element is distributed substantially uniformly throughout the semiconductor substrate. ing.

  The inventor has confirmed through experiments that according to the above-described configuration, the variation in electrical characteristics of the photodetecting element can be reduced while improving the gettering effect. The reason why the variation in electrical characteristics can be reduced is as described above. In this specification, “substantially uniform” means that when the concentration of the second element is measured in a plurality of regions in the semiconductor substrate, the ratio of the upper limit value to the lower limit value is within 10. To do.

  The method for manufacturing a photodetecting element according to the present invention includes a preparatory step of preparing a semiconductor substrate having a first element as a base material and containing a second element of the same family as the first element at a predetermined concentration; A stacking step of stacking an epitaxial layer having a first element as a base material on the semiconductor substrate prepared by the preparing step, and a region of the epitaxial layer stacked by the stacking step separated from the semiconductor substrate by a predetermined distance A semiconductor substrate prepared in the preparation step, the first element containing the first element so that the second element contained in the semiconductor substrate has the predetermined concentration And a material containing the second element are grown from a melted raw material melt.

  The inventor has confirmed through experiments that according to the above-described configuration, the variation in electrical characteristics of the photodetecting element can be reduced while improving the gettering effect. The reason why the variation in electrical characteristics can be reduced is as described above. The preparation of the semiconductor substrate may be performed by manufacturing the semiconductor substrate, or may be performed by obtaining the manufactured semiconductor substrate.

Further, the first element is silicon, the second element is carbon,
The predetermined concentration may be included in a range of 1 × 10 ^{16 to} 2.5 × 10 ¹⁷ atoms / cm ³ .
According to the above configuration, it is possible to prevent the strength of the semiconductor substrate from being lowered while forming the BMD at a high density. The reason is as described above.

The manufacturing method of the photodetecting element further includes a heat treatment step of repeatedly performing a heat treatment on the semiconductor substrate after the growth step, and an input temperature when the heat treatment is first performed on the semiconductor substrate is 600 degrees Celsius. It may be 700 degrees or less.
According to the above configuration, since the initial heat treatment temperature is not less than 600 degrees Celsius and not more than 700 degrees Celsius, the precipitation nuclei of oxygen precipitation defects remain without disappearing because they grow to a sufficient size and become gettering sites. BMD can be formed with high density. As a result, the gettering effect can be improved.

The method for manufacturing the photodetector further includes a heat treatment step for heat-treating the semiconductor substrate before forming a gate insulating film on the semiconductor substrate, and the heat treatment has a maximum temperature of 1000 degrees Celsius to 1100 degrees Celsius. The processing time may be included in the range of 60 minutes to 600 minutes.
According to the above configuration, precipitation nuclei of oxygen precipitation defects are sufficiently grown, and BMDs serving as gettering sites can be formed with high density. As a result, the gettering effect can be improved.

The epitaxial layer may have a thickness in the range of 4 μm to 6 μm.
According to the above configuration, it is possible to reduce the electronic shutter voltage while preventing the variation in the impurity concentration in the semiconductor substrate from affecting the electrical characteristics of the epitaxial layer.

Further, the ratio ρ2 / ρ1 between the resistivity ρ1 of the semiconductor substrate and the resistivity ρ2 of the epitaxial layer may be included in the range of 20 or more and 200 or less.
According to the above configuration, it is possible to create a solid-state imaging device that satisfies various electrical characteristics while reducing the electronic shutter voltage.

The best mode for carrying out the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
<Configuration>
FIG. 1 is a diagram showing a schematic configuration of an IT-CCD type solid-state imaging device.
The solid-state imaging device includes a light detection unit 11, a vertical transfer unit 12, a horizontal transfer unit 13, and an amplification unit 14.

  The light detection unit 11 generates and accumulates an amount of charge corresponding to the amount of received light. The light detection units 11 are two-dimensionally arranged in a matrix, and FIG. 1 schematically shows 25 pixels of 5 rows and 5 columns. The vertical transfer unit 12 individually transfers the charges generated and accumulated by the light detection unit 11 to the horizontal transfer unit 13. The horizontal transfer unit 13 transfers the charges transferred from the vertical transfer unit 12 to the amplification unit 14 respectively. The amplifying unit 14 converts the charges transferred from the horizontal transfer unit 13 into voltages and amplifies them.

FIG. 2 is a cross-sectional view of an IT-CCD type solid-state imaging device.
The solid-state imaging device includes a semiconductor substrate 101, an epitaxial layer 102, a gate insulating film 108, a gate electrode 109, an antireflection film 116, a light shielding film 118, an interlayer insulating film 117, and a surface protective film 119. In FIG. 2, only one pixel of the solid-state image sensor is shown.
The semiconductor substrate 101 uses silicon as a base material and contains carbon and phosphorus. The concentration of carbon is included in the range of 1 × 10 ^{16 to} 2.5 × 10 ¹⁷ atoms / cm ³ . Note that carbon is distributed substantially uniformly in the surface direction and the depth direction in the semiconductor substrate 101. Here, “substantially uniform” means that, when the concentration of carbon is measured in a plurality of regions in the semiconductor substrate 101, the ratio of the upper limit value to the lower limit value is within 10.

  The epitaxial layer 102 has a p-type well region 103, n-type regions 104 and 106, and p-type regions 107, 112, 114, and 115. The p-type well region 103 forms an overflow barrier potential ψofb between the n-type region 104 and the semiconductor substrate 101. The n-type region 104 is formed in a region separated from the semiconductor substrate 101 by a predetermined distance. Since the n-type region 104 is surrounded by the p-type well region 103 and the p-type regions 112, 114, and 115, a potential well is formed. The region where the potential well is formed becomes the light detection unit 11. N-type region 106 is surrounded by p-type regions 107, 114, and 112. This forms a potential well. The region where the potential well is formed becomes the vertical transfer unit 12. The p-type region 114 forms a gate potential ψg between the n-type region 104 and the n-type region 106.

The gate insulating film 108, the gate electrode 109, the antireflection film 116, the light shielding film 118, the interlayer insulating film 117, and the surface protective film 119 are general components of a CCD type solid-state imaging device, and are the essential parts of the present invention. Since it is not, description is abbreviate | omitted.
FIG. 3 is a diagram showing a potential distribution inside the semiconductor substrate and the epitaxial layer.
Symbols A to D shown in FIG. 3 correspond to points A to D shown in FIG. 2, respectively. That is, the symbol A corresponds to the vertical transfer unit 12, the symbol B corresponds to the p-type region 114, the symbol C corresponds to the light detection unit 11, and the symbol D corresponds to the semiconductor substrate 101.

A substrate voltage Vsub is applied to the semiconductor substrate 101. The substrate voltage Vsub and the overflow barrier potential ψofb are determined by the substrate voltage Vsub. That is, the higher the substrate voltage Vsub, the higher the substrate potential ψsub and the overflow barrier potential ψofb. The substrate voltage Vsub is determined such that the overflow barrier potential ψofb is higher than the gate potential ψg. By defining in this way, when the photodetection unit 11 generates a charge that exceeds the saturation amount, the overflowing charge can be discharged to the semiconductor substrate 101 instead of the vertical transfer unit 12. With this configuration, the blooming phenomenon can be suppressed.
<Manufacturing method>
4, 5, and 6 are diagrams showing a method for manufacturing a solid-state imaging device.

First, the semiconductor substrate 101 is generated using a pulling method.
A material 23 containing silicon, a material 24 containing carbon, and a material 25 containing phosphorus are put into the crucible 21 (FIG. 4A). Here, the carbon-containing material 24 is introduced so that the semiconductor substrate 101 contains carbon in a concentration range of 1 × 10 ^{16 to} 2.5 × 10 ¹⁷ atoms / cm ³ . As the carbon-containing material 24, for example, graphite or SiC crystal can be considered. Note that the phosphorus-containing material 25 is added so that the semiconductor substrate 101 has a resistivity of 0.25 to 0.5 Ωcm.

  When a specified amount of each material is charged, the raw material of the single crystal ingot is melted using the heater 22 (FIG. 4B), and the seed crystal 28 fixed to the support 27 is brought into contact with the raw material melt 26. Then, the seed crystal 28 is gradually pulled up (FIG. 4C). Then, the single crystal ingot 29 is grown. At this time, carbon is uniformly distributed in the single crystal ingot 29. The semiconductor substrate 101 is obtained by cutting a single crystal ingot 29 so that the plane orientation is <100>.

Next, the semiconductor substrate 101 is processed as follows to form a solid-state imaging device.
A semiconductor substrate 101 is prepared (FIG. 5A). FIG. 5A shows a part of the cross section of the semiconductor substrate 101.
Silicon is epitaxially grown on the prepared semiconductor substrate 101 to deposit an epitaxial layer 102 (FIG. 5B). The thickness of the epitaxial layer 102 is about 6 μm, and the resistivity is 10 to 15 Ωcm.

  After forming a silicon oxide film 120 and a silicon nitride film 121 on the surface of the epitaxial layer 102 and removing portions other than the element formation region, a p-type well region 103 is formed by ion implantation (FIG. 5C). The formation conditions of the silicon oxide film 120 are that the input temperature is 700 degrees Celsius, the maximum temperature is 1000 degrees Celsius, and the holding time at 1000 degrees Celsius is 60 minutes. In a region other than the element formation region of the epitaxial layer 102, a silicon oxide film is formed by a technique called LOCOS. The LOCOS conditions are a maximum temperature of 1000 degrees Celsius and a holding time of 100 minutes.

After the formation of the silicon oxide film, an n-type region 104 is formed in the epitaxial layer 102 by ion implantation (FIG. 5D). After the ion implantation, heat treatment is performed at a maximum temperature of 1000 degrees Celsius and a holding time of 20 minutes.
Next, the silicon oxide film 120 and the silicon nitride film 121 formed on the surface of the epitaxial layer 102 are removed, and a gate insulating film 108 is formed again on the surface of the epitaxial layer 102 (FIG. 6A).

  Thereafter, the p-type regions 112 and 114, the n-type region 106, and the p-type region 107 are formed by ion implantation (FIG. 6B). Further, after forming the gate electrode 109 on the gate insulating film 108, the p-type region 115 is formed, and the antireflection film 116, the interlayer insulating film 117, the light shielding film 118, and the surface protective film 119 are formed (FIG. 6C). )). Moreover, a color filter and a microlens are formed as needed.

In the above-described manufacturing method, the initial heat treatment temperature is set to 700 degrees Celsius, the maximum temperature is set to 1000 degrees Celsius, and the holding time is increased by 180 degrees after the epitaxial layer 102 is deposited and before the gate insulating film 108 is formed. A heat treatment step is performed. Then, the density of BMD (Bulk Micro Defect) per unit cross-sectional area is about 1 × 10 ⁶ pieces / cm ² , and the size of BMD is about 200 nm.

In addition, when a heat treatment step in which the charging temperature is 700 degrees Celsius, the maximum temperature is 1100 degrees Celsius, and the holding time is 300 minutes is performed, the density of BMD per unit cross-sectional area is approximately 5 × 10 ⁶ pieces. / cm ² , and the BMD size is about 300 nm.
In addition, when a heat treatment step is performed in which the input temperature is 600 degrees Celsius, the maximum temperature is 1000 degrees Celsius, and the holding time is 180 minutes, the density of BMD per unit cross-sectional area is approximately 5 × 10 ⁶ pieces. / cm ² , and the BMD size is about 50 nm.
<Performance evaluation>
The inventor created a solid-state imaging device by the three manufacturing methods of Conventional 1, Conventional 2, and the present invention, and performed performance evaluation.

For the solid-state imaging device according to the related art 1, only IG which is a typical gettering technique is applied. That is, heat treatment is performed to generate BMD inside the semiconductor substrate (carbon is not added).
The gettering technique according to Patent Document 1 is applied to the solid-state imaging device according to Conventional 2. That is, carbon is added to the silicon substrate by ion implantation to generate BMD.

The solid-state imaging device according to the present invention is obtained by generating BMD by dissolving carbon in a silicon substrate during crystal growth.
The performance evaluation was performed by measuring the number of white scratches on the solid-state imaging device and the blooming suppression voltage (a kind of electrical characteristic) and comparing the measurement results. The number of pixels of the solid-state image sensor is 5 million pixels, and the number of samples of the solid-state image sensor is 100 each.

FIG. 7 shows a comparison result of the number of white scratches.
In the measurement of the number of white scratches, a pixel whose signal reached a threshold value when a solid-state imaging device in a light-shielded state under an ambient temperature of 60 degrees Celsius was charged for 4 seconds was regarded as a white scratch.
In FIG. 7, the average value of the number of white scratches obtained from the solid-state imaging device according to the conventional 2 is standardized and displayed. The average value of the number of white scratches is 6.38 for Conventional Example 1, 1 for Conventional Example 2, and 0.67 for the present invention. From this result, it can be seen that the number of white flaws can be significantly reduced in Conventional 2 with carbon added and the present invention compared with Conventional 1 with no carbon added. Further, comparing the present invention with the prior art 2, it can be seen that the present invention can reduce the number of white scratches by about 30% compared to the prior art 2.

FIG. 8 shows a comparison result of the blooming suppression voltage.
In the measurement of the blooming suppression voltage, the lower limit value of the substrate voltage at which blooming does not occur when the substrate voltage was changed while irradiating strong light at an ambient temperature of 35 degrees Celsius was regarded as the blooming suppression voltage.
In FIG. 8, the average value of the blooming suppression voltage obtained from the solid-state imaging device according to Conventional 2 is standardized and displayed. The variation in blooming suppression voltage (difference between the maximum value and the minimum value) is 0.09 for Conventional 1, 0.4 for Conventional 2, and 0.12 for the present invention. From this result, it can be seen that the present invention can halve the variation of the blooming suppression voltage as compared with the prior art 2.

Summarizing the above experimental results, according to the configuration of the present invention, it can be said that variations in blooming suppression voltage can be reduced while improving the gettering effect.
The inventor has (1) variations in blooming suppression voltage due to variations in carbon distribution in the semiconductor substrate, and (2) carbon in the raw material melt of the semiconductor substrate. It is presumed that the variation in the distribution of carbon in the semiconductor substrate could be reduced by adding carbon than in the method of ion implantation of carbon.

The above (1) is considered as follows.
BMD tends to occur in the vicinity of carbon. Therefore, the distribution of BMD varies according to the distribution of carbon. Variations in the distribution of BMD induce variations in parasitic capacitance and parasitic resistance in the semiconductor substrate 101. Then, it is considered that the blooming suppression voltage varies.

The above (2) is considered as follows.
If carbon is added to the raw material melt of the semiconductor substrate, the carbon is distributed substantially uniformly in the semiconductor substrate during the crystal growth process. On the other hand, when carbon is added by ion implantation, it is difficult to distribute the carbon substantially uniformly in the semiconductor substrate. This is mainly due to the fact that the ion beam has a gradient of ion density in the radial direction and that an accuracy error occurs when the ion beam is scanned over the entire area of the semiconductor substrate (wafer). Yes. Considering this, it is considered that the method of adding carbon to the raw material melt can reduce the variation in the distribution of carbon in the semiconductor substrate, compared with the method of ion implantation of carbon.

The said model is demonstrated using drawing.
FIG. 9 is a diagram schematically showing a cross section of a wafer.
FIG. 9A shows a wafer according to the present invention, and FIG. The semiconductor substrate 101 according to the present invention has a smaller variation in BMD distribution than the semiconductor substrate 201 according to the related art 2. This is because the semiconductor substrate 101 according to the present invention has a smaller variation in carbon distribution than the semiconductor substrate 201 according to the related art 2. In the semiconductor substrate 101 according to the present invention, BMD is generated substantially uniformly over the entire semiconductor substrate. On the other hand, in the semiconductor substrate 201 according to the related art 2, BMD is mainly generated in the region 203 in which carbon is ion-implanted.

FIG. 10 is a diagram illustrating a potential distribution inside the solid-state imaging device.
FIG. 10A shows the potential distribution of the solid-state imaging device created by the manufacturing method of the present invention, and FIG. 10B shows the potential distribution of the solid-state imaging device created by the conventional manufacturing method 2. Symbols B to D shown in FIG. 10 correspond to points B to D shown in FIG. 2, respectively. That is, the symbol B corresponds to the p-type region 114, the symbol C corresponds to the light detection unit 11, and the symbol D corresponds to the semiconductor substrate 101.

10A, a curve 31 shows a potential distribution when a solid-state image sensor is formed in the P region of FIG. 9A, and a curve 32 shows a solid-state image sensor in the Q region of FIG. The potential distribution when formed is shown.
In FIG. 10B, a curve 33 indicates a potential distribution when a solid-state image sensor is formed in the P region of FIG. 9B, and a curve 34 indicates a solid-state image sensor in the Q region of FIG. 9B. The potential distribution when formed is shown.

  The solid-state imaging device according to the present invention has a smaller variation in the distribution of BMD than the solid-state imaging device according to the second conventional technology. As a result, variations in parasitic capacitance and the like inside the semiconductor substrate are small, and variations in potential distribution are also small. Therefore, since the solid-state imaging device according to the present invention has a smaller variation in overflow barrier potential (difference between ψofbp and ψofbq) than the solid-state imaging device according to the related art 2, the variation in blooming suppression voltage is also reduced.

  In view of the fact that the solid-state image pickup device according to the present invention has a smaller variation in potential distribution than the solid-state image pickup device according to the related art 2 as described above, not only the blooming suppression voltage but also the saturation capacitance and readout of the light detection unit. It is considered that the variation of other electrical characteristics such as voltage can be reduced. Then, it is considered that the solid-state imaging device according to the present invention can also have an effect of reducing deterioration in image quality due to variation in electrical characteristics under weak light.

  When a semiconductor substrate is formed by a pulling method, a concentration of concentric circles is generated in principle in the concentration of impurities (such as phosphorus) in the same plane. When the epitaxial layer is formed on the semiconductor substrate, the impurities in the semiconductor substrate are thermally diffused into the epitaxial layer, and as a result, concentric shades are generated in the impurity concentration even in the same plane in the epitaxial layer. This variation in impurity concentration causes variation in resistivity within the same plane in the epitaxial layer, and is observed as striped image noise called striations in the solid-state imaging device.

The inventors made semiconductor substrates to which the gettering techniques of Conventional 1, Conventional 2, and the present invention were applied, respectively, formed an epitaxial layer on the semiconductor substrate, and varied the resistivity in the same plane in the epitaxial layer. Was measured.
FIG. 14 is a comparison result of variations in resistivity within the same plane in the epitaxial layer.

  According to this, it can be seen that the variation in resistivity in the same plane is small in the order of Conventional 1, Conventional 2, and the present invention. Therefore, according to the gettering technique of the present invention, the occurrence of striation can be suppressed. In fact, the inventors created a solid-state imaging device by applying the gettering techniques of Conventional 1, Conventional 2, and the present invention, and observed an image output from the solid-state imaging device (see FIG. 15). As a result, the occurrence of striation was confirmed in the conventional 1 and the conventional 2, but the occurrence of striation was not confirmed in the present invention (in FIG. 15, the striation is a striped pattern oblique to the image. Appears as shading).

As described above, the gettering technique of the present invention can suppress striation, and the reason is considered as follows.
The striation is generated by thermal diffusion of impurities from the semiconductor substrate to the epitaxial layer. Thermal diffusion of impurities is promoted by silicon atoms that move between lattice points (so-called interstitial silicon) and atomic vacancies that are formed at lattice points by the movement of silicon atoms. In the gettering technique of the present invention, since carbon is introduced into a semiconductor substrate using silicon as a base material, interstitial silicon and atomic vacancies are trapped in carbon. As a result, the thermal diffusion of impurities is suppressed, and the occurrence of striation is suppressed.

Furthermore, in the gettering technique of the present invention, interstitial silicon and carbon trapping atomic vacancies are distributed over the entire area of the semiconductor substrate. Therefore, compared to the conventional gettering technique in which carbon is distributed only in a part of the semiconductor substrate, it can be said that the ability to suppress thermal diffusion of impurities is high and the ability to suppress the occurrence of striation is high.
An effective method for reducing the power consumption of the solid-state imaging device is to reduce the voltage (electronic shutter voltage) applied to the semiconductor substrate when the electronic shutter functions. In order to reduce the electronic shutter voltage, it is effective to reduce the thickness of the epitaxial layer. However, as the epitaxial layer is made thinner, the variation in impurity concentration in the semiconductor substrate is more likely to affect the electrical characteristics of the epitaxial layer, and striations are more likely to occur. According to the gettering technique of the present invention, since the occurrence of striation can be suppressed, the epitaxial layer can be made thinner accordingly. Therefore, the power consumption of the solid-state image sensor can be reduced.

  Specifically, the thickness of the epitaxial layer is desirably 4 μm or more and 6 μm or less. Since the absorption length of red light in silicon is about 3 μm, in order to detect red light efficiently, the photodetection section 11 is designed so that the depletion layer reaches at least about 3 μm deep from the surface of the epitaxial layer. When a voltage is applied to the gate electrode, the depletion layer expands by about 1 μm in the depth direction. Therefore, in order to prevent the depletion layer from reaching the semiconductor substrate, the thickness of the epitaxial layer is preferably 4 μm or more. . Also, if the thickness of the epitaxial layer is greater than 6 μm, it is necessary to increase the electronic shutter voltage, and the effect of reducing power consumption cannot be expected. Therefore, the thickness of the epitaxial layer is desirably 6 μm or less.

The ratio ρ2 / ρ1 between the resistivity ρ1 of the semiconductor substrate and the resistivity ρ2 of the epitaxial layer is preferably 20 or more and 200 or less. In order to produce a solid-state imaging device that satisfies various electrical characteristics, the resistivity ρ2 of the epitaxial layer needs to be increased to about 10 to 50 Ωm. On the other hand, in order to reduce the electronic shutter voltage, it is necessary to reduce the resistivity ρ1 of the semiconductor substrate to about 0.25 to 0.5 Ωm. If the ratio ρ2 / ρ1 of both is set to 20 or more and 200 or less, it is possible to produce a solid-state imaging device that satisfies various electrical characteristics while reducing the voltage of the electronic shutter voltage.
(Embodiment 2)
<Configuration>
FIG. 11 is a diagram illustrating a schematic configuration of an FT-CCD type solid-state imaging device.

The solid-state imaging device includes a light receiving region 41, a storage region 42, a horizontal transfer unit 43, and an amplification unit 46.
The light receiving region 41 has a light detection unit 44. The light detection unit 44 generates an amount of electric charge corresponding to the amount of received light and plays a role as a vertical transfer unit. The accumulation area 42 has an accumulation unit 45. The accumulation unit 45 accumulates the charges transferred from the light detection unit 44 and plays a role as a vertical transfer unit. The light detection unit 44 and the storage unit 45 are two-dimensionally arranged in a matrix, and FIG. 11 schematically shows 66 pixels of 6 rows and 11 columns. The horizontal transfer unit 43 transfers the charges transferred from the storage unit 45 to the amplification unit 46, respectively. The amplifying unit 46 converts the charges transferred from the horizontal transfer unit 43 into voltages and amplifies them.

FIG. 12 is a cross-sectional view of an FT-CCD type solid-state imaging device.
The solid-state imaging device includes a semiconductor substrate 301, an epitaxial layer 302, a gate insulating film 308, a transparent electrode 309, and a planarization film 330. In FIG. 12, only two pixels of the solid-state image sensor are shown.
The semiconductor substrate 301 uses silicon as a base material and contains carbon and phosphorus. Carbon is distributed substantially uniformly in the surface direction and the depth direction in the semiconductor substrate 301. The concentration of carbon is 5 × 10 ¹⁶ atoms / cm ³ .

  The epitaxial layer 302 has a p-type well region 303, an n-type region 304, and a p-type region 312. The p-type well region 303 forms an overflow barrier potential ψofb between the n-type region 304 and the semiconductor substrate 301. The n-type region 304 is formed in a region separated from the semiconductor substrate 301 by a predetermined distance. Since the n-type region 304 is surrounded by the p-type well region 303 and the p-type region 312, a potential well is formed. The region where the potential well is formed becomes the light detection unit 44.

The gate insulating film 308, the transparent electrode 309, and the planarization film 330 are general components of a CCD type solid-state imaging device and are not an essential part of the present invention, and thus description thereof is omitted.
<Manufacturing method>
Compared with the manufacturing method of Embodiment 1, the manufacturing method of Embodiment 2 mainly differs in the temperature of heat processing. Therefore, only matters relating to heat treatment will be described.

  After forming a silicon oxide film and a silicon nitride film on the surface of the epitaxial layer 302 and removing portions other than the element formation region, a p-type well region 303 is formed by ion implantation. The formation conditions of the silicon oxide film at this time are that the input temperature is 600 degrees Celsius, the maximum temperature is 1000 degrees Celsius, and the holding time at 1000 degrees Celsius is 60 minutes. In regions other than the element formation region of the epitaxial layer 302, LOCOS is formed by thermal oxidation. The LOCOS formation conditions are a maximum temperature of 1050 degrees Celsius and a holding time of 100 minutes.

In the above manufacturing method, during the period from the deposition of the epitaxial layer 302 to the formation of the gate insulating film 308, the input temperature of the first heat treatment step is 600 degrees Celsius, the maximum temperature is 1050 degrees Celsius, and the holding time is extended. A heat treatment for 160 minutes is performed. Then, the density of BMD per unit cross-sectional area is about 5 × 10 ⁶ pieces / cm ² , and the size of BMD is about 100 nm.
(Embodiment 3)
<Configuration>
FIG. 13 is a cross-sectional view of a light receiving element for a photocoupler.

The light receiving element includes a semiconductor substrate 401, an epitaxial layer 402, an insulating film 408, a transparent electrode 409, and an antireflection film 416.
The semiconductor substrate 401 uses silicon as a base material and contains carbon and phosphorus. Carbon is distributed substantially uniformly in the surface direction and the depth direction in the semiconductor substrate 401. The concentration of carbon is included in the range of 1 × 10 ^{16 to} 2.5 × 10 ¹⁷ atoms / cm ³ .

  The epitaxial layer 402 has a p-type well region 403 and an n-type region 404. The p-type well region 403 forms an overflow barrier potential ψofb between the n-type region 404 and the semiconductor substrate 401. The n-type region 404 is surrounded by the p-type well region 403 and forms a potential well. The region where the potential well is formed becomes a light detection portion.

The insulating film 408, the transparent electrode 409, and the antireflection film 416 are general constituent elements of the light receiving element, and are not essential parts of the present invention, and thus description thereof is omitted.
As mentioned above, although the photon detection apparatus which concerns on this invention was demonstrated based on embodiment, this invention is not limited to these embodiment. For example, the following modifications can be considered.
(1) In the embodiment, the single crystal ingot is grown by pulling up by the CZ method. However, the present invention is not limited to this, and the MCZ method in which a magnetic field is applied when growing a single crystal may be used.
(2) In the embodiments, IT-CCD type and FT-CCD type solid-state imaging devices are taken as examples. However, the present invention is not limited to this, and can also be applied to MOS-type solid-state imaging devices. In the embodiment, the light receiving element for the photocoupler is taken as an example. However, the present invention is not limited to this, and can be applied to light receiving elements for optical communication, optical pickup, and the like.
(3) Although an example in which carbon is added is given in the embodiment, the present invention is not limited to this as long as it is an element belonging to the same family as silicon. For example, germanium, tin, lead, etc. can be considered.

In the embodiment, a silicon substrate is taken as an example. However, the present invention is not limited to this, and can also be applied to a germanium substrate.
(4) In the embodiment, phosphorus is added to make the conductivity type of the semiconductor substrate N-type, but the present invention is not limited to this.

  The present invention can be used for a solid-state imaging device, a light receiving device, and the like.

It is a figure which shows schematic structure of an IT-CCD type solid-state image sensor. It is sectional drawing of a solid-state image sensor of IT-CCD type. It is a figure which shows the electric potential distribution inside a semiconductor substrate and an epitaxial layer. It is a figure which shows the manufacturing method of a solid-state image sensor. It is a figure which shows the manufacturing method of a solid-state image sensor. It is a figure which shows the manufacturing method of a solid-state image sensor. It is a comparison result of the number of white scratches. It is a comparison result of blooming suppression voltage. It is a figure which shows the cross section of a wafer typically. It is a figure which shows the electric potential distribution inside a solid-state image sensor. It is a figure which shows schematic structure of a FT-CCD type solid-state image sensor. It is sectional drawing of a FT-CCD type solid-state image sensor. It is sectional drawing of the light receiving element for photocouplers. It is a comparison result of the dispersion | variation in the resistivity in the same surface in an epitaxial layer. It is an observation result of striations.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11, 44 Light detection part 12 Vertical transfer part 13, 43 Horizontal transfer part 14, 46 Amplification part 21 Crucible 22 Heater 23 Material containing silicon 24 Material containing carbon 25 Material containing phosphorus 26 Raw material melt 27 Support tool 28 seed crystal 29 single crystal ingot 41 light-receiving region 42 storage region 45 storage part 101, 201, 301, 401 semiconductor substrate 102, 202, 302, 402 epitaxial layer 103, 303, 403 p-type well region 104, 304, 404 n-type Region 106 n-type region 107 p-type region 108, 308 gate insulating film 109 gate electrode 112, 312 p-type region 114 p-type region 115 p-type region 116, 416 antireflection film 117 interlayer insulating film 118 light shielding film 119 surface protective film
120 Silicon oxide film 121 Silicon nitride film 203 Carbon ion-implanted region 309, 409 Transparent electrode 330 Planarizing film 408 Insulating film

Claims (18)

A semiconductor substrate having a first element as a base material and containing a second element of the same family as the first element at a predetermined concentration;
An epitaxial layer that is epitaxially grown using the first element as a base material on the semiconductor substrate, and that has a photodetection portion in a region separated from the semiconductor substrate by a predetermined distance;
The semiconductor substrate is made of a raw material melt in which a material containing the first element and a material containing the second element are melted so that the second element contained in the semiconductor substrate has the predetermined concentration. A photodetection element characterized by being grown as a crystal. The first element is silicon; the second element is carbon;
2. The photodetecting element according to claim 1, wherein the predetermined concentration is in a range of 1 × 10 ^{16 to} 2.5 × 10 ¹⁷ atoms / cm ³ . The number of BMD per unit cross-sectional area which the said semiconductor substrate has is contained in the range of 5 * 10 < ⁵ > thru | or 5 * 10 < ⁷ > piece / cm < ² >. The size of BMD which the said semiconductor substrate has is contained in the range of 50 to 400 nm. The photodetection element according to claim 1 characterized by things. The thickness of the said epitaxial layer is contained in the range of 4 micrometers or more and 6 micrometers or less. The optical detection element of Claim 1 characterized by the above-mentioned. 2. The photodetector according to claim 1, wherein a ratio ρ2 / ρ1 between the resistivity ρ <b> 1 of the semiconductor substrate and the resistivity ρ <b> 2 of the epitaxial layer is included in a range of 20 or more and 200 or less. A semiconductor substrate having a first element as a base material and containing a second element of the same family as the first element at a predetermined concentration;
An epitaxial layer that is epitaxially grown using the first element as a base material on the semiconductor substrate, and that has a photodetection portion in a region separated from the semiconductor substrate by a predetermined distance;
The photodetecting element, wherein the second element is distributed substantially uniformly throughout the semiconductor substrate. The first element is silicon; the second element is carbon;
The photodetection element according to claim 7, wherein the predetermined concentration is included in a range of 1 × 10 ^{16 to} 2.5 × 10 ¹⁷ atoms / cm ³ . The number of BMD per unit cross-sectional area which the said semiconductor substrate has is contained in the range of 5 * 10 < ⁵ > thru | or 5 * 10 < ⁷ > piece / cm < ² >. The photodetection element according to claim 7, wherein a size of BMD included in the semiconductor substrate is included in a range of 50 to 400 nm. The thickness of the said epitaxial layer is contained in the range of 4 micrometers or more and 6 micrometers or less. The optical detection element of Claim 7 characterized by the above-mentioned. The photodetecting element according to claim 7, wherein a ratio ρ2 / ρ1 between the resistivity ρ1 of the semiconductor substrate and the resistivity ρ2 of the epitaxial layer is included in a range of 20 or more and 200 or less. A preparatory step of preparing a semiconductor substrate having a first element as a base material and containing a second element of the same family as the first element at a predetermined concentration;
A stacking step of stacking an epitaxial layer having the first element as a base material on the semiconductor substrate prepared by the preparing step;
Forming a photodetecting portion in a region separated by a predetermined distance from the semiconductor substrate of the epitaxial layer stacked by the stacking step,
In the semiconductor substrate prepared in the preparation step, the material containing the first element and the material containing the second element are melted so that the second element contained in the semiconductor substrate has the predetermined concentration. A method for producing a photodetecting element, wherein the crystal is grown from the raw material melt. The first element is silicon; the second element is carbon;
14. The method of manufacturing a photodetecting element according to claim 13, wherein the predetermined concentration is in a range of 1 × 10 ^{16 to} 2.5 × 10 ¹⁷ atoms / cm ³ . The method for manufacturing the photodetecting element further includes:
A heat treatment step of repeatedly performing a heat treatment on the semiconductor substrate after the growth step;
The manufacturing method of the photodetecting element according to claim 13, wherein an input temperature when first heat-treating the semiconductor substrate is 600 degrees Celsius or more and 700 degrees Celsius or less. The method for manufacturing the photodetecting element further includes:
A heat treatment step of heat-treating the semiconductor substrate before forming a gate insulating film on the semiconductor substrate;
14. The method of manufacturing a light detection element according to claim 13, wherein the heat treatment includes a maximum temperature in a range of 1000 ° C. to 1100 ° C. and a processing time in a range of 60 minutes to 600 minutes. The method of manufacturing a photodetecting element according to claim 13, wherein the thickness of the epitaxial layer is included in a range of 4 μm to 6 μm. 14. The method of manufacturing a photodetecting element according to claim 13, wherein a ratio ρ2 / ρ1 between the resistivity ρ1 of the semiconductor substrate and the resistivity ρ2 of the epitaxial layer is included in a range of 20 or more and 200 or less.