JP5401761B2 - Display substrate defect inspection method, defect inspection apparatus, and display apparatus - Google Patents

Description

  The present invention relates to a defect inspection method for a display substrate before forming an electro-optic element whose luminance changes according to a data signal in a pixel circuit arranged at an intersection of a scanning line and a data line. The present invention relates to a display substrate defect inspection method, a defect inspection device, and a display device, which can easily perform defect inspection of a display substrate without providing wiring dedicated for defect inspection.

  As liquid crystal display panels and organic EL (Organic Light Emitting Diode: OLED) display panels increase in size and definition, there is a problem of yield reduction due to pixel and wiring defects and cost increase due thereto. In order to deal with such a problem, it is conceivable to improve the yield by providing a defect inspection process in the manufacturing process of the display panel to find the defective portion and correcting the defect.

  However, in the case of a defect inspection by a lighting test performed using a completed display panel in the final process of the display panel manufacturing process, there may be a defect that cannot be corrected. When such a defect exists, the manufacturing cost of the display panel is wasted. Therefore, it is desirable to perform defect inspection while the display panel is not completed during the manufacturing process. In this case, as a defect inspection method, there is a method in which the panel surface is photographed with a CCD camera or the like, and a foreign object or a circuit defect is detected by pattern matching. Internal defects cannot be detected. Therefore, in this case, inspection by energization is also necessary.

  In a conventional defect inspection method for energizing a display panel, an organic electroluminescence element (hereinafter referred to as an “organic EL element”), which is an electro-optical element whose luminance is controlled according to a data signal, is a defect in a display substrate that is not mounted. In the inspection method, a switching TFT capable of providing a current path to the driving TFT (Thin Film Transistor) of the organic EL element is added to the pixel circuit of the display substrate even when the organic EL element is not mounted. At the time of defect inspection, the defect is inspected by turning on the switching TFT and observing the drive current flowing through the drive TFT (for example, see Patent Document 1).

Another defect inspection method for a display substrate is that a storage capacitor connected between the gate and source of a drive transistor that drives an organic EL element and a parasitic capacitance formed between the gate and drain of the drive transistor are used. After writing the charge, the charge is read and a defect is detected by the detection output (see, for example, Patent Document 2).
JP 2005-107129 A Japanese Patent No. 3701924

  However, in such a conventional defect inspection method for a display substrate, in particular, the defect inspection method described in Patent Document 1 requires that a switch TFT dedicated to defect inspection and a wiring corresponding thereto be provided in the pixel circuit. In addition, there is a possibility that the TFT elements are crowded and a new defect is generated.

  Further, in the defect inspection method described in Patent Document 2, since the parasitic capacitance is small, it is easily affected by noise and the like, and it is difficult to accurately measure the written charge. In particular, since the pixel circuit of the organic EL display panel is more complicated than the pixel circuit of the liquid crystal display panel, it is difficult to specify the number of parasitic capacitances and the location where they occur, and they have any influence on the measurement results. It is difficult to predict. Therefore, it may be difficult to determine the defect of the pixel circuit.

  Therefore, the present invention addresses such problems and enables a display substrate defect inspection method, a defect inspection apparatus, and a display that can easily perform defect inspection of a display substrate without providing wiring dedicated for defect inspection. An object is to provide an apparatus.

  In order to achieve the above object, a display substrate defect inspection method according to a first aspect of the present invention is an electro-optic that is arranged at an intersection of a plurality of types of scanning lines and signal lines and changes in luminance according to a data signal. A pixel transistor that drives an element; a write transistor that is connected between the signal line and the pixel transistor and is driven by one of the plurality of types of scan lines; and a connection end of the pixel transistor and the write transistor; A defect inspection method for a display substrate having a pixel circuit having an internal capacitor connected between a fixed potential and a matrix, wherein the plurality of types of scanning lines are scanned in the same direction as an image display, The potential of the signal line is kept at a predetermined value, and a predetermined reset scanning signal is supplied to the plurality of types of scanning lines to turn on the write transistor, and the potential across the internal capacitor A reset stage in which the charge is reset to zero at the same level, and a write signal having a predetermined potential is supplied to the signal line, and a predetermined write scan signal is simultaneously applied to the plurality of types of scanning lines. A write stage for sequentially supplying the internal capacitors to store charges so as to exist, and supplying a predetermined read scanning signal to the plurality of types of scanning lines to drive the write transistor on, A reading step of reading out the accumulated charge amount held in the internal capacitor via the signal line, and a determination step of determining the presence or absence of a defect in the pixel circuit based on the read accumulated charge amount. Is what you do.

  With such a configuration, while scanning a plurality of types of scanning lines in the same direction as the video display, the potential of the signal lines is maintained at a predetermined value, and a predetermined reset scanning signal is supplied to the plurality of types of scanning lines. The write transistor connected between the line and the pixel transistor is turned on, and the electric potential at both ends of the internal capacitor connected between the connection end of the pixel transistor and the write transistor and the fixed potential is set to the same level to reset the charge to zero. In addition, a write signal having a predetermined potential is supplied to the signal line, and a predetermined write scan signal is sequentially supplied to a plurality of types of scanning lines so that there is a timing at which the potential simultaneously becomes a high level. Charge is stored in the capacitor, a predetermined scanning signal is supplied to a plurality of scanning lines to turn on the writing transistor, and the amount of stored charge held in the internal capacitor is calculated. Line read through to the determination of presence or absence of a defect of a pixel circuit provided in a matrix on the display substrate based on the accumulated charge amount read out.

  According to a second aspect of the present invention, there is provided a defect inspection method for a display substrate, wherein a pixel transistor is disposed at an intersection of a plurality of types of scanning lines and signal lines and drives an electro-optical element whose luminance changes according to a data signal. A write transistor connected between the signal line and the pixel transistor and driven by one of the plurality of scanning lines, and connected between the pixel transistor and a fixed potential. A pixel circuit comprising: a switching transistor driven by another scanning line among scanning lines; and an internal capacitor connected between a connection end of the pixel transistor and the writing transistor and a connection end of the pixel transistor and the switching transistor. A defect inspection method for a display substrate provided in a matrix, wherein the plurality of types of scanning lines are scanned in the same direction as an image display. The potential of the signal line is maintained at a predetermined value, and a predetermined reset scanning signal is supplied to the plurality of types of scanning lines to simultaneously turn on the writing transistor and the switching transistor. A reset stage in which the charge is reset to zero at the same level, and a write signal having a predetermined potential is supplied to the signal line, and a predetermined write scan signal is simultaneously applied to the plurality of types of scanning lines. A write stage in which charges are accumulated in the internal capacitor so as to exist at a certain timing, and a predetermined read scanning signal is supplied to the plurality of types of scanning lines to simultaneously connect the write transistor and the switching transistor. A reading step of driving on and reading the amount of accumulated charge held in the internal capacitor through the signal line; and A determining step of determining the presence or absence of a defect of the pixel circuit based on the accumulated amount of charge, and performs.

  With such a configuration, while scanning a plurality of types of scanning lines in the same direction as the video display, the potential of the signal lines is maintained at a predetermined value, and a predetermined reset scanning signal is supplied to the plurality of types of scanning lines, The writing transistor connected between the signal line and the pixel transistor and the switching transistor connected between the pixel transistor and the fixed potential are simultaneously turned on, and the connection ends of the pixel transistor and the writing transistor are connected to the pixel transistor and the switching transistor. The electric potential of both ends of the internal capacitor connected to the end is set to the same level to reset the charge to zero, and a write signal having a predetermined potential is supplied to the signal line, and a predetermined write scan is applied to each of the plurality of types of scanning lines. Charge is stored in the internal capacitor by sequentially supplying signals so that there is a timing at which the potentials simultaneously become high. , Supplying a predetermined read scanning signal to a plurality of types of scanning lines to simultaneously turn on the writing transistor and the switching transistor, and reading out and reading out the accumulated charge held in the internal capacitor via the signal line Based on the stored charge amount, it is determined whether or not there is a defect in the pixel circuit provided in a matrix on the display substrate.

  Furthermore, a defect inspection apparatus according to a third aspect of the present invention is a pixel transistor that is disposed at an intersection of a plurality of types of scanning lines and signal lines and that drives an electro-optical element whose luminance changes according to a data signal, and the signal A write transistor connected between a line and a pixel transistor and driven by one of the plurality of scan lines, and an internal capacitor connected between a connection end of the pixel transistor and the write transistor and a fixed potential A display substrate defect inspection apparatus including a pixel circuit having a matrix shape, wherein the plurality of types of scanning lines are scanned in the same direction as or in the opposite direction to the video display, and the plurality of types of scanning lines are scanned. On the other hand, a predetermined reset scanning signal is supplied in the reset stage to turn on the write transistor, and the predetermined write scan signal has the same potential in the write stage. Are sequentially supplied so that there is a high level timing, and a scanning means for supplying a predetermined readout scanning signal in the readout stage to turn on the write transistor, and a potential of the signal line in the reset stage is predetermined. The value is maintained, and a write signal having a predetermined potential is supplied in the write stage to hold the charge in the internal capacitor, and in the read stage, the stored charge amount held in the internal capacitor is detected via the signal line. A reading unit; and a control unit that controls driving of each of the components and determines whether or not the pixel circuit is defective based on an accumulated charge amount read by the writing and reading unit. is there.

  With such a configuration, the scanning unit scans a plurality of types of scanning lines in the same direction or in the opposite direction to the video display, and supplies a predetermined reset scanning signal to the plurality of types of scanning lines at a reset stage. The writing transistor connected between the signal line and the pixel transistor is turned on, and a predetermined scanning signal is sequentially supplied to the writing stage so that there is a timing at which the potential simultaneously becomes a high level, and the reading stage The pixel transistor is supplied with a predetermined scanning signal to turn on the write transistor, and the write / read means maintains the signal line potential at a predetermined value at the reset stage and supplies the write signal with the predetermined potential at the write stage. In addition, the internal capacitor connected between the connection end of the write transistor and the fixed potential holds the charge, and is held in the internal capacitor in the reading stage. The accumulated charge amount is detected via a signal line, and the drive of each of the above components is controlled by the control means, and the display substrate is provided in a matrix based on the accumulated charge amount read by the writing / reading means. It is determined whether there is a defect in the pixel circuit.

  According to a fourth aspect of the present invention, there is provided a defect inspection apparatus including a pixel transistor which is disposed at an intersection of a plurality of types of scanning lines and signal lines and which drives an electro-optical element whose luminance changes according to a data signal, and the signal A write transistor connected between a line and a pixel transistor and driven by one of the plurality of scan lines; and a write transistor connected between the pixel transistor and a fixed potential. A pixel circuit having a switching transistor driven by another scanning line, and an internal capacitor connected between a connection end of the pixel transistor and the write transistor and a connection end of the pixel transistor and the switching transistor is provided in a matrix. A display substrate defect inspection apparatus that scans the plurality of types of scanning lines in the same direction as the video display, and A predetermined reset scanning signal is supplied to a scanning line of a certain type at a reset stage to simultaneously turn on the write transistor and the switching transistor, and the potential of the predetermined write scan signal is simultaneously increased at a writing stage. Sequentially supplied so that there is a level timing, scanning means for supplying a predetermined readout scanning signal in the readout stage to simultaneously drive the write transistor and the switching transistor on, and the potential of the signal line in the reset stage Is maintained at a predetermined value, a write signal having a predetermined potential is supplied in the write stage to hold the charge in the internal capacitor, and the amount of accumulated charge held in the internal capacitor is detected through the signal line in the read stage. The read / write means for controlling the drive of each component and the read / write means for reading. And control means for the determination of the presence or absence of a defect of the pixel circuit based on the accumulated charge amount, those having a.

  With such a configuration, the scanning unit scans a plurality of types of scanning lines in the same direction as the video display, and supplies a predetermined reset scanning signal to the plurality of types of scanning lines at a reset stage. The writing transistor connected between the pixel transistor and the switching transistor connected between the pixel transistor and a fixed potential are simultaneously turned on, and a predetermined writing scanning signal is simultaneously set to the high level in the writing stage. Sequentially supplied so that the timing exists, a predetermined scanning signal is supplied to the read stage to simultaneously turn on the write transistor and the switching transistor, and the potential of the signal line is set to a predetermined value at the reset stage by the write / read means. The write transistor of a predetermined potential is supplied during the write stage to connect the pixel transistor and the write transistor. The charge is held in the internal capacitor connected between the end and the connection end of the pixel transistor and the switching transistor, and the amount of accumulated charge held in the internal capacitor is detected via the signal line in the reading stage, and the control means In addition to controlling the driving of each of the above components, it is determined whether or not there is a defect in a pixel circuit provided in a matrix on the display substrate based on the amount of accumulated charge read by the writing / reading means.

  Further, a display device according to a fifth aspect of the present invention is a pixel transistor that is disposed at an intersection of a plurality of types of scanning lines and signal lines and that drives an electro-optical element whose luminance changes according to a data signal, and the signal lines A write transistor connected between the pixel transistor and the pixel transistor and driven by one of the plurality of types of scan lines, and an internal capacitor connected between a connection end of the pixel transistor and the write transistor and a fixed potential A pixel circuit having a matrix circuit on a substrate, the potential of the signal line is kept at a predetermined value while scanning the plurality of types of scanning lines in the same direction as the video display, and A predetermined reset scanning signal is supplied to a plurality of types of scanning lines to turn on the writing transistor, the potentials at both ends of the internal capacitor are set to the same level, and the charge is reset to zero. A write signal having a predetermined potential is supplied to the signal line, and a predetermined write scan signal is sequentially supplied to the plurality of types of scanning lines so that there is a timing at which the potential simultaneously becomes a high level. Accumulate charges, supply a predetermined readout scanning signal to the plurality of types of scanning lines to drive the write transistor on, and read out the accumulated charge amount held in the internal capacitor via the signal line And a defect inspection device for determining the presence or absence of a defect in the pixel circuit based on the read accumulated charge amount.

  With such a configuration, the defect inspection apparatus scans a plurality of types of scanning lines in the same direction as the video display, while maintaining the potential of the signal lines at a predetermined value, and a predetermined reset scanning signal is applied to the plurality of types of scanning lines. Supply and turn on the write transistor connected between the signal line and the pixel transistor, and charge the both ends of the internal capacitor connected between the connection end of the pixel transistor and the write transistor and the fixed potential at the same level. Is reset to zero, and a write signal having a predetermined potential is supplied to the signal line, and a predetermined write scan signal is sequentially supplied to the plurality of types of scanning lines so that there is a timing at which the potential simultaneously becomes a high level. Then, electric charges are accumulated in the internal capacitor, a predetermined read scanning signal is supplied to a plurality of types of scanning lines to turn on the writing transistor, and the internal capacitance is held in the internal capacitor. It reads the amount of accumulated charge via the signal line, to the determination of the presence or absence of a defect of a pixel circuit provided in a matrix on the substrate based on the read accumulated charge amount.

  According to a sixth aspect of the present invention, there is provided a display device including a pixel transistor which is disposed at an intersection of a plurality of types of scanning lines and signal lines and which drives an electro-optical element whose luminance changes according to a data signal, and the signal lines. A write transistor connected between the pixel transistor and the pixel transistor and driven by one of the plurality of types of scanning lines, and another of the plurality of types of scanning lines connected between the pixel transistor and a fixed potential. A pixel circuit having a switching transistor driven by a scanning line, and an internal capacitor connected between a connection end of the pixel transistor and the write transistor and a connection end of the pixel transistor and the switching transistor on a substrate. A plurality of types of scanning lines are scanned in the same direction as the video display, and the potentials of the signal lines are set. While maintaining a constant value, a predetermined reset scanning signal is supplied to the plurality of types of scanning lines to simultaneously turn on the writing transistor and the switching transistor, so that the potentials at both ends of the internal capacitance are at the same level and the charge is reduced to zero. Reset and supply a write signal with a predetermined potential to the signal line, and sequentially supply a predetermined write scan signal to each of the plurality of types of scanning lines so that there is a timing at which the potential simultaneously becomes a high level. The charge stored in the internal capacitor is stored in the internal capacitor by supplying predetermined scanning signals to the plurality of types of scanning lines to simultaneously turn on the write transistor and the switching transistor. The amount is read through the signal line, and the presence or absence of a defect in the pixel circuit is determined based on the read accumulated charge amount. Recessed those having a testing device.

  With such a configuration, the defect inspection apparatus scans a plurality of types of scanning lines in the same direction as the video display, while maintaining the potential of the signal lines at a predetermined value, and a predetermined reset scanning signal is applied to the plurality of types of scanning lines. The writing transistor connected between the signal line and the pixel transistor and the switching transistor connected between the pixel transistor and the fixed potential are simultaneously turned on, and the connection end of the pixel transistor and the writing transistor, the pixel transistor and the switching are connected. The electric potential of both ends of the internal capacitor connected between the connection ends of the transistors is set to the same level to reset the charge to zero, and a write signal having a predetermined potential is supplied to the signal line. The internal capacitance is supplied by sequentially supplying the write scanning signal so that there is a timing at which the potential simultaneously becomes a high level. Charge is accumulated, a predetermined scanning signal is supplied to a plurality of types of scanning lines to simultaneously turn on the writing transistor and the switching transistor, and the amount of accumulated charge held in the internal capacitor is obtained via the signal line. Based on the read-out stored charge amount, the presence / absence of a defect in a pixel circuit provided in a matrix on the substrate is determined.

  According to the first and ninth aspects of the invention, the pixel transistor that drives the electro-optic element that is arranged at the intersection of the plurality of types of scanning lines and the signal line and changes the luminance according to the data signal, and the signal line A write transistor connected between the pixel transistor and the pixel transistor and driven by one of the plurality of scan lines, and an internal capacitor connected between the pixel transistor and the connection end of the write transistor and a fixed potential. The defect inspection of the display substrate having the pixel circuits arranged in a matrix can be easily performed without providing a dedicated wiring for defect inspection. Therefore, since the defect can be detected before the display substrate is completed, the manufacturing cost of the display substrate can be reduced.

  According to the second aspect of the present invention, defects that cannot be detected when a plurality of types of scanning lines are scanned in the same direction as the video display can be detected by scanning in the reverse direction. Therefore, the defect inspection can be performed more strictly.

  Furthermore, according to the invention of claim 3, when the reset stage, the write stage, and the read stage are executed while scanning a plurality of types of scanning lines, the readout scanning signal is used as a reset scanning signal for the next scan. can do. Therefore, the readout stage and the reset stage of the next scan can be performed simultaneously, and the measurement time can be shortened.

  Furthermore, according to the inventions according to claims 4 and 10, the pixel transistor that is disposed at the intersection of the plurality of types of scanning lines and the signal line and that drives the electro-optical element whose luminance changes according to the data signal, The write transistor connected between the signal line and the pixel transistor and driven by one of the plurality of types of scanning lines, and the plurality of types of scanning connected between the pixel transistor and a fixed potential. A pixel circuit including a switching transistor driven by another scanning line of the lines, and an internal capacitor connected between a connection end of the pixel transistor and the write transistor and a connection end of the pixel transistor and the switching transistor It is possible to easily carry out the defect inspection of the display substrate provided in the shape without providing a dedicated wiring for defect inspection. Therefore, since the defect can be detected before the display substrate is completed, the manufacturing cost of the display substrate can be reduced.

  According to the fifth aspect of the present invention, the scanning signal for the scanning line for driving the switching transistor can be generated by performing a logical operation on the scanning signal for the scanning line for driving the writing transistor and the enable signal.

  According to the sixth aspect of the present invention, the scanning signal of the scanning line that drives the switching transistor can be generated by the scanning line n lines before the scanning line that drives the writing transistor. Therefore, the circuit configuration is simplified.

  Further, according to the inventions according to claims 7 and 12, it is possible to perform a defect inspection of the organic electroluminescence display substrate.

  According to the inventions according to claims 8 and 11, not only the determination of the presence / absence of a defect but also the failure mode can be specified. Therefore, if the defect can be repaired from the specified failure mode, it can be repaired to improve the manufacturing yield.

  According to the thirteenth aspect of the present invention, a pixel transistor that drives an electro-optic element that is arranged at an intersection of a plurality of types of scanning lines and signal lines and whose luminance changes according to a data signal, and a signal line A write transistor connected between the pixel transistor and the pixel transistor and driven by one of the plurality of types of scan lines, and an internal capacitor connected between the connection end of the pixel transistor and the write transistor and a fixed potential. A display device provided with the pixel circuits provided in a matrix on a substrate can be provided with a defect inspection function.

  According to the fourteenth aspect of the present invention, the pixel transistor disposed at the intersection of the plurality of types of scanning lines and the signal line and driving the electro-optical element whose luminance changes according to the data signal, and the signal line And a writing transistor connected between the pixel transistor and driven by one of the plurality of types of scanning lines, and another scanning line of the plurality of types of scanning lines connected between the pixel transistor and a fixed potential. A display device comprising a pixel circuit having a switching circuit driven by the gate electrode, a pixel circuit including a connection terminal between the pixel transistor and the writing transistor and an internal capacitor connected between the connection terminal of the pixel transistor and the switching transistor in a matrix on the substrate Can be provided with a defect inspection function.

  Further, according to the fifteenth aspect of the present invention, even if the luminance is lowered due to a defect, the level of the data signal can be increased to increase the luminance of the electro-optic element, and the defect can be made inconspicuous.

  According to the sixteenth aspect of the present invention, the organic electroluminescence display device can be provided with a defect inspection function.

  Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a block diagram showing a first embodiment of a defect inspection apparatus for a display substrate according to the present invention. This defect inspection apparatus can perform a defect inspection of a display substrate before forming an electro-optic element whose luminance is controlled according to a data signal in a pixel circuit arranged at the intersection of a scanning line and a signal line The scanning means 1, the writing / reading means 2, the control means 3, and the power supply 4 are provided. In the following description, the case where the display substrate is the organic EL display substrate 5 will be described.

Here, the pixel circuit 6 of the organic EL display substrate 5 includes two types of scanning lines WS ₁ , WS ₁ for selecting pixels for one row from a large number of pixels arranged in a matrix of m × n on the substrate. WS ₂ ... WS _n , DS ₁ , DS ₂ ... DS _n and signal lines SG ₁ , SG ₂ ... SG _m for supplying data signals are arranged at the intersections, and as shown in FIG. A holding capacitor C _s for holding a signal, a sub capacitor C _sub for controlling variation of the pixel transistor 8 described later, and a data signal driven by the scanning lines WS _{1 to} WS _n out of the two types of scanning lines. An N-MOS type write transistor 7 held at C _s and an N-MOS type pixel transistor 8 for supplying a current to the organic EL element are included.

More specifically, the writing transistor 7 has a gate connected to the scanning line WS _n , a source connected to the signal line SG _m , and a drain connected to the gate of the pixel transistor 8. Also, the pixel transistor 8 has a drain connected to the scan line DS _n, so that the source is connected to the anode of the organic EL element. Further, the storage capacitor C _s is provided between the gate and the source of the pixel transistor 8, and the sub capacitor C _sub is provided between the source of the pixel transistor 8 and the scanning line DS _(n−1) . Thus, in the pixel circuit 6 of the organic EL display substrate 5, one end of the sub-capacitor _Csub is always fixed at a predetermined potential. In this case, the scanning lines DS _{1 to} DS _n not only function as supply lines for the power source 4 for flowing current to the organic EL elements, but also accumulate in the holding capacitor C _s and the sub capacitor C _sub at the time of defect inspection. has been discharged electric charge, and the charge of the storage capacitor C _s and the sub-capacitor C _sub writing (storage) operation, and the storage capacitor C _s and the sub-capacitor C _sub written driving signal for the amount of charge read operation It also functions as a supply line, and is independent for each line, like the scanning lines WS _{1 to} WS _n . The holding capacitor C _s and the sub capacitor C _sub are internal capacitors of the pixel circuit 6. More specifically, a combined capacitor formed by connecting a holding capacitor C _s and a sub capacitor C _sub in series is an internal capacitor of the pixel circuit 6.

In the defect inspection apparatus of the first embodiment according to the present invention, the scanning means 1, two scanning lines of the organic EL display substrate _{5 WS 1 ~WS n, DS 1} ~DS n image display in the same direction or In addition to scanning in the reverse direction, a predetermined reset scanning signal is supplied to the scanning lines WS _{1 to} WS _n and DS _{1 to} DS _n in the reset stage to drive the writing transistor 7 on, and in the writing stage Are sequentially supplied so that there is a timing at which the potential simultaneously becomes a high level, and a predetermined read scan signal is supplied in the read stage to drive the write transistor 7 on. A driver control circuit 9, a gate driver IC 10, a buffer 11, and a plurality of probes 12 are provided.

  The gate driver control circuit 9 is a control signal for selecting a scanning line to be measured, for example, a clock signal, a pulse width control signal, an output enable control signal, and a shift of a shift register (not shown) provided in the gate driver IC 10 described later. A direction control signal or the like is generated and supplied to the gate driver IC 10.

A gate driver IC 10 is connected to the output terminal of the gate driver control circuit 9. The gate driver IC10 is controlled by a control signal of the gate driver control circuit 9, two scan lines WS ₁ to WS _n as shown in FIG. 3, one clock reset supplied to DS ₁ to DS _n A scanning signal for writing, a writing scanning signal having a pulse width of 2 clocks, and a scanning clock for reading of 1 clock are sequentially generated and output, and controlled by the output enable control signal in the reset stage and reading stage. The scanning lines DS _{1 to} DS ₂ can be set not to output the reset scanning signal and the readout scanning signal. Further, the shift direction control signal the two scan lines are controlled by WS ₁ ~WS _n, DS ₁ ~DS same forward and _{when n} line-sequential scanning of performing the normal image display (see Fig. (A) ) And in the opposite direction (see FIG. 5B).

  Further, a buffer 11 is connected to the output terminal of the gate driver IC 10. This buffer 11 relays between the organic EL display substrate 5 and the gate driver IC 10, and when the output voltage or output current of the gate driver IC 10 is inconsistent with the specifications, voltage conversion or current It is possible to adjust to the specifications by increasing or decreasing the number.

A plurality of probes 12 are provided at the output end of the buffer 11. The plurality of probes 12 is for enabling supplying the scanning signal output from the buffer 11 two scan lines of the organic EL display substrate 5 WS ₁ to WS _n, the DS ₁ to DS _n There, it moved up and down, the organic EL display substrate 5 two scanning lines WS ₁ to WS _n that is formed at the edge, DS ₁ to DS _n two so as to contact each respective terminal electrodes of the The same number of scanning lines WS _{1 to} WS _n and DS _{1 to} DS _n are provided.

The write / read means 2 holds the signal lines SG _{1 to} SG _m of the organic EL display substrate 5 at a low level at the reset stage, and a write signal Visg having a predetermined potential with respect to the signal lines SG _{1 to} SG _m at the write stage. And the stored charge amount stored in the combined capacitor formed by connecting the holding capacitor C _s and the sub-capacitor C _sub in series at the reading stage is read via the signal lines SG _{1 to} SG _m , A writing circuit 13, a changeover switch 14, a reading circuit 15, and a plurality of probes 16 are provided.

  The write circuit 13 amplifies a rectangular wave-like write signal supplied from the control means 3 described later to a predetermined level, and is a voltage amplification circuit.

A changeover switch 14 is provided at the output end of the writing circuit 13. The change-over switch 14 is a switch for switching between the charge writing to the holding capacitor C _s and the sub-capacitor C _sub and the reading operation of the written charge amount, and is controlled by the control means 3 to operate. . The change-over switch 14 connects the signal lines SG _{1 to} SG _m of the organic EL display substrate 5 and the writing circuit 13 in the writing stage, and the signal lines SG _{1 to} SG _m and reading to be described later in the reading stage. a first switch 17 for connecting the circuit 15, to ground the signal line SG ₁ to SG _m is the reset phase, the write and read out the signal line SG ₁ to SG _m and the write circuit 13 and read circuit 15 And a second switch 18 to be connected.

A read circuit 15 is connected to the changeover switch 14. The readout circuit 15 reads out the stored charge amount held in the composite capacitor formed by connecting the storage capacitor C _s and the sub-capacitor C _sub in series via the signal lines SG _{1 to} SG _m. 19 and an A / D converter 20.

Here, the integrating circuit 19 integrates the change of the potential input via the signal lines SG _{1 to} SG _m in the reading stage, and the combined capacitance formed by connecting the holding capacitor C _s and the sub capacitor C _sub in series. The total amount of electric charge accumulated in is detected. Further, the A / D converter 20 performs A / D conversion on the output voltage of the integration circuit 19 so that the control means 3 described later can determine the presence or absence of a defect in the pixel circuit 6 and specify the failure mode. belongs to.

A plurality of probes 16 are connected to the changeover switch 14. The plurality of probes 16 are for allowing the write signal Vsig output from the write circuit 13 to be supplied to the signal lines SG _{1 to} SG _m of the organic EL display substrate 5 and move up and down to display the organic EL display. The same number as the signal lines SG _{1 to} SG _m is provided so as to be in contact with the terminal electrodes of the signal lines SG _{1 to} SG _m formed at the edge of the substrate 5.

  A control means 3 is connected to the scanning means 1 and the writing / reading means 2. This control means 3 controls the supply of various scanning signals by the scanning means 1, controls the supply of write signals by the writing / reading means 2, and the writing and reading operations of the writing / reading means 2. For example, a personal computer is used to determine the presence / absence of a defect in the pixel circuit 6 and specify a failure mode based on the read accumulated charge amount.

Specifically, the control unit 3 causes the scanning unit 1 to supply a scanning signal for resetting one clock to the scanning lines WS _{1 to} WS _n at the reset stage and hold the scanning lines DS _{1 to} DS _n at a low level. is, by the time shift as two scan lines WS ₁ to WS _n to the write step, DS ₁ to DS _n to one clock of each pulse of the write scan signal having a pulse width of two clocks overlap each other Control is performed so that the scanning lines WS _{1 to} WS _n are supplied with a reset scanning signal of one clock and the scanning lines DS _{1 to} DS _n are held at a low level while being sequentially supplied.

Further, the control means 3 drives the changeover switch 14 at the reset stage to hold the signal lines SG _{1 to} SG _m at the low level, and sends a write signal to the write circuit 13 at the write stage. At the same time, the switching switch 14 is switched to supply a write signal to the signal lines SG _{1 to} SG _m , and the switching switch 14 is switched to the reading stage to switch the holding capacitor C _s and subcapacitance C _{sub of the} display substrate 5. Are controlled so as to read out the amount of electric charge accumulated in the combined capacitor formed by serial connection .

  Then, the control means 3 inputs the read accumulated charge amount from the writing / reading means 2, and the accumulation capacity and the defect-free and various failure modes previously created and stored in a storage unit (not shown). Compared with the stored charge amount of a lookup table (hereinafter referred to as “LUT”) that correlates with the corresponding stored charge amount, the presence / absence of a defect is determined and the defective mode is specified, and the defective pixel is also detected. The address information of the circuit 6 is stored in, for example, a storage medium.

  A power supply 4 is connected to the scanning means 1 and the writing / reading means 2. The power source 4 serves as a supply source for supplying a driving voltage to the scanning unit 1 and the writing / reading unit 2. When the drive voltage can be supplied from the control unit 3 to the scanning unit 1 and the writing / reading unit 2, the power source 4 may be omitted.

Next, a defect inspection method performed using the defect inspection apparatus according to the first embodiment configured as described above will be described with reference to the flowchart of FIG.
First, an organic EL display substrate 5 to be measured is installed at a predetermined position, the scan line of the organic EL display substrate _{5 WS 1 ~WS n, DS 1} ~DS n multiple probes of the scanning means 1 to the terminal electrode of the 12 is attached, and a plurality of probes 16 of the writing / reading means 2 are attached to the terminal electrodes of the signal lines SG _{1 to} SG _n of the organic EL display substrate 5.

Next, the power supply 4 is turned on and defect inspection is started.
First, in step S1, the line sequential scanning direction of the organic EL display substrate 5 is selected in order to inspect defects by operating a personal computer which is the control means 3. In this case, it is possible to select one of the same one-way scanning in the forward direction as in normal video display and two-way scanning in the forward direction and the opposite direction. However, in any case, in step S1, first, forward scanning is selected and defect inspection is performed. As will be described later, since there is a failure mode that cannot be detected only by forward scanning, bi-directional scanning is selected to perform failure detection more strictly.

In step S2, a reset stage is executed. In this reset phase, the second switch 18 by the control means 3 changeover switch 14 of the writing reading means 2 is controlled drive is switched to the ground side 18a, the signal line SG ₁ to SG _n are grounded. In addition, a command to perform line sequential scanning in the forward direction is output from the control unit 3 to the scanning unit 1. When this command is received, a scanning signal for reset of one clock is sent from the scanning means 1 as shown in FIG. 3A, for example, scanning line DS _(n-1) , scanning line WS _n , scanning line DS _n. Are supplied with a time shift of one clock, and all the scanning lines of the display substrate 5 are scanned in the forward direction. In this way, both ends of the holding capacitor C _s and the sub capacitor C _sub of all the pixel circuits 6 are fixed at the low level and reset.

In the following description, at the reset stage and the readout stage described later, as shown by hatching in FIG. 3, the enable function of the gate driver IC 10 of the scanning means 1 causes the scanning lines DS ₁ to signal DS _n is zero, description will be given of a case where the potential of the scanning line DS ₁ to DS _n is kept at a low level.

In this case, in the period I shown in FIG. 5, as shown in FIG. 5A, the potentials of the scanning lines DS _(n−1) and DS _n are held at the low level, and one clock is supplied to the scanning line WS _n. The reset scanning signal is supplied. As a result, the potential of the terminal C of the pixel circuit 6 shown in FIG. 2 is fixed at a low level. The write transistor 7 shown in FIG. 2, one clock of the reset signal is turned on is supplied through its gate to the scanning line WS _n. At this time, since the signal lines SG _{1 to} SG _m are grounded as described above, the potential of the source of the write transistor 7 is at a low level. Therefore, the drain of the write transistor 7, that is, the potential of the terminal A is fixed at a low level (see FIG. 5B). As a result, the potentials at both ends of the holding capacitor C _s and the sub capacitor C _sub of the pixel circuit 6 are fixed to the low level, and the reset is completed. At this time, the potential of the terminal B becomes substantially low level due to capacitive coupling.

When the reset phase of step S2 ends, the process proceeds to step S3.
In step S3, the writing stage is executed. In this writing stage, as shown in FIG. 1, the control means 3 drives and controls the changeover switch 14 of the writing / reading means 2 so that the first switch 17 is switched to the writing side 17a and at the same time the second switch 18 is switched. Is switched to the writing / reading side 18b. The write signal supplied from the control means 3 to the write / read means 2 is amplified to a predetermined level by the write circuit 13 of the write / read means 2 and supplied to the signal lines SG _{1 to} SG _m . In addition, a scanning signal for writing having a predetermined pulse width is sequentially supplied from the scanning unit 1 to the two types of scanning lines WS _{1 to} WS _n and DS _{1 to} DS _n to control the organic EL display. All the scanning lines of the substrate 5 are scanned in the forward direction, and charges are accumulated in the holding capacitors C _s and sub capacitors C _sub of all the pixel circuits 6.

Specifically, the writing scanning signal output from the scanning unit 1 in this writing stage is a signal having a pulse width of two clocks as shown in FIG. 3A, for example, and the scanning line DS _{(n -1)} are sequentially supplied to the scanning lines WS _n and the scanning lines DS _n while being time-shifted so that one clock overlaps each other.

Here, in the period II of the write stage shown in FIG. 5, the write signal potential Vsig to the drain of the write transistor 7 through the signal line SG _m as shown in the diagram (a) is supplied, the scan line WS _n and scanning lines DS _(n-1), the potential of the DS _n is the low level. Therefore, when there is no defect in the pixel circuit 6 of the organic EL display substrate 5, the write transistor 7 is turned off, and the potentials of the terminals A to C are maintained at the reset stage, and all are at a low level. .

Then, in the period III, 5 scan lines to the terminal C of the sub-capacitance C _sub shown in Figure 2 the potential becomes high level of the scanning lines DS _(n-1) as shown in (a) DS _{(n The} power supply voltage Vcc is applied through _-1) . As a result, the potential at the terminal C rises to Vcc as shown in FIG. At this time, as shown in FIG. (B), the write transistor 7 and the pixel transistor 8 for the potential of the scanning line WS _n is at a low level is off, the terminal A and terminal B becomes floating state Yes. Therefore, the potentials of the terminal A and the terminal B are pulled to the potential of the terminal C by the capacitive coupling of the storage capacitor C _s and the sub capacitor C _sub and rise to a predetermined level. In this case, the pixel transistor 8 when the potential of the terminal A is raised is turned on, the potential of the terminal B drops are drawn to the low level of the potential of the scan line DS _n. Along with this, the potential at the terminal A also drops. Here, when the potential of the terminal A drops below the on / off threshold potential of the pixel transistor 8, the pixel transistor 8 is turned off and the potential of the terminal A tends to rise. At the same time, the potential at the terminal B is going to rise. As a result, the pixel transistor 8 is turned on again, and the potentials of the terminals A and B drop. By repeating such an operation, the potentials of the terminals A and B stagnate in the vicinity of the threshold potential of the pixel transistor 8.

In the period IV, the potential of the scanning line DS _(n-1) is at a high level as shown in FIG. 5A, so that the potential of the terminal C is maintained at Vcc (see FIG. 5B). ). Further, since the potential of the scanning line WS _n becomes high level, the write transistor 7 is turned on, and the write signal is supplied to the terminal A via the signal lines SG _{1 to} SG _m, and as shown in FIG. Increases to Vsig. Thereby, the pixel transistor 8 is turned on. At this time, as shown in FIG. 6 (a), the potential of the scan line DS _n is at a low level, the potential of the drain of the pixel transistor 8 is at the low level and the terminal B with the ON operation of the pixel transistor 8 The potential drops to a low level (see (b) in the figure).

Further, in the period V, since the potential of the scanning line DS _(n−1) is at a low level as shown in FIG. 5A, the potential of the terminal C drops to the low level (see FIG. 5B). ). The potential of the scanning line WS _n on state of the write transistor 7 in which for remains high is maintained, the potential of the terminal A is Vsig is maintained (see FIG. (B)). Accordingly, the pixel transistor 8 remains on. At this time, since the potential of the scan line DS _n is changed to the high level, the drain of the pixel transistor 8 is the potential of Vcc is applied, the potential of the terminal B rises to the predetermined value (see FIG. (B)).

Further, in the period VI, as shown in FIG. 5A, the potential of the scanning line DS _(n−1) is at the low level, so the potential of the terminal C remains at the low level (FIG. 5B). reference). The potential of the scanning line WS _n is writing transistor 7 is turned off to change to the low level, the state terminal A of floating. As a result, the potential of the terminal A is maintained at Vsig (see FIG. 5B). Accordingly, the pixel transistor 8 remains on. At this time, since the potential of the scan line DS _n has the high level is maintained, the drain potential of the pixel transistor 8 remains Vcc, the potential of the terminal B is the predetermined value is maintained (Fig. ( b)).

In the period VII, as shown in FIG. 5A, all potentials of the scanning line DS _(n−1) , the scanning line WS _n , and the scanning line DS _n are at a low level. Thereby, since the drain potential of the pixel transistor 8 becomes low level, the potential of the terminal B tends to drop toward the low level. Here, since the writing transistor 7 is off, the terminal A is in a floating state, and the potential of the terminal A is lowered by the capacitive coupling while maintaining the potential difference between the terminals AB in the period VI. (See (b) of the same figure). In this case, the potential difference between the terminals AB is equal sufficient to maintain the ON state of the pixel transistor 8, the potential of the terminal B stops by drops to the low level of the scan line DS _n. Accordingly, the charge amounts QCs and QCsub stored (written) in the holding capacitor C _s and the sub capacitor C _sub are determined by the potentials VA, VB, and VC finally held in the terminals A, B, and C, respectively. Cs (VA-VB) and QCsub = Csub (VB-VC).

For example, the scanning line WS _n 25V potential and high level of the signal supplied by the low level 0V, the scanning lines DS _(n-1) and DS _n high level 25V potential of the signal supplied by the low level There 0V, the signal line SG _m 10V potential and high level of the signal supplied by, the low level is 0V, the terminals a, B, When simulating a potential that is ultimately held in C, VA = 5V, VB = 8V, VC = 0V. Therefore, when the pixel circuit 6 is defect-free, the amount of charge accumulated in the storage capacitor C _s and the sub capacitor C _sub by forward scanning is QCs = Cs (VA−VB) = − 3Cs, QCsub = Csub (VB -VC) = 8Csub. Thus, when the writing stage is completed, the process proceeds to step S4.

In step S4, a read stage is performed. In this reading stage, as shown in FIG. 1, the changeover switch 14 of the writing / reading means 2 is driven and controlled by the control means 3, the first switch 17 is switched to the reading side 17b, and the second switch 18 The write / read state is maintained. Further, as shown in FIG. 3A, the signal output from the scanning unit 1 to the scanning lines DS _(n−1) and DS _n is made zero by the enable function of the gate driver IC 10 of the scanning unit 1. 5 only one clock read scanning signal to the scanning lines WS _n to VIII period shown in is supplied. Then, all the lines of the scanning lines of the organic EL display substrate 5 is scanned in the forward direction, load electropneumatic each of the storage capacitor C _s and the sub-capacitance C _sub is accumulated in synthesized capacitances formed by connecting in series the total pixel circuits 6 The quantity is read out via the signal line SG _m and stored in a storage unit (not shown) of the control means 3.

When there is no defect in the pixel circuit 6 of the organic EL display substrate 5, the read charge amount is the charge amount that is stored in the combined capacitor formed by connecting the holding capacitor C _s and the sub capacitor C _sub in series. The value is determined depending on the value of the charge Cs (VA−VB) held by the holding capacitor C _s and the value of the charge Csub (VB−VC) held by the sub capacitor C _sub (see FIG. 26).

  In step S5, it is determined whether the scanning direction for defect inspection is only one-way scanning in the forward direction. In this case, when only one-way scanning is selected by operating the personal computer at the start of the inspection, the determination is “YES” and the process proceeds to step S6.

In step S6, the stored charge amount of the composite capacitor formed by connecting the read storage capacitors C _s and sub capacitors C _{sub of} all the pixel circuits 6 in series is stored in advance in the storage unit of the control means 3, for example, FIG. 26 is compared with the LUT shown in FIG.

In step S7, the control unit 3 determines whether the pixel circuit 6 is defective. In this case, the read accumulated charge amount is a “defect-free” accumulated charge amount in the LUT, for example , a storage capacitor C _s holding charge −3 Cs and a sub-capacitor C _sub holding charge 8 Csub are connected in series. When the amount of charge accumulated in the combined capacitance matches within a predetermined allowable value, the pixel circuit 6 has no defect, and “NO” determination is made, and the defect inspection of the display substrate 5 is completed.

  On the other hand, if the read accumulated charge amount does not coincide with the “no defect” value of the LUT within a predetermined allowable value in step S7, it means that the pixel circuit 6 has a defect. "YES" determination, the process proceeds to step S8.

  In step S8, failure mode analysis is performed. This analysis is performed by comparing the read accumulated charge amount with the total accumulated charge amount indicating various failure modes in the LUT.

  In step S9, the failure mode is specified. Here, based on the analysis result of the failure mode in step S8, the failure mode in which the accumulated charge amount matches within a predetermined allowable value is specified as the failure mode of the pixel circuit 6 in which the defect is detected. Then, the address information and the failure mode of each pixel circuit 6 in which a defect is detected are stored in, for example, a storage medium, and the inspection ends.

On the other hand, if bi-directional scanning is selected as the line sequential scanning direction for defect inspection, step S5 is “NO” and the process proceeds to step S10.
In step S10, a reverse scanning command is output from the control means 3 to the scanning means 1, and reverse scanning is selected. Then, as shown in FIG. 3 (b), the scanning signals similar to the step S2~S4 is supplied in the opposite direction to the two scanning lines DS ₁ to DS _n and the scan line WS ₁ to WS _n The reset stage in step S11, the write stage in step S12, and the read stage in step S13 are executed.

Here, in the reset phase of the step S11, as shown in FIG. 6 (a), the scanning line DS _n, the potential of the DS _(n-1) is held at a low level, one clock reset to the scan line WS _n A scanning signal is supplied. Thereby, the potential of the terminal C is fixed at a low level. On the other hand, the write transistor 7 to the gate is supplied with one clock of the reset signal through the scanning line WS _n of the write transistor 7 shown in FIG. 2 is turned on. At this time, since the signal lines SG _{1 to} SG _m are grounded at the reset stage, the potential of the source of the write transistor 7 is at a low level (see FIG. 6B). Therefore, the drain of the write transistor 7, that is, the potential of the terminal A is fixed at a low level. As a result, the potentials at both ends of the holding capacitor C _s and the sub capacitor C _sub of the pixel circuit 6 are fixed to the low level, and the reset is completed.

In the writing stage of step S12, the potentials of the terminals A to C change as shown in FIG. For example, when simulation is performed under the same conditions as in the case of the forward scanning and the potentials finally held in the terminals A to C are obtained, the terminal A is 14V, the terminal B is 0V, and the terminal C is 0V. The charge QCs written to the storage capacitor C _s is 14 Cs, and the charge QC _sub of the sub capacitor C _sub is 0.

Therefore, accumulated charge amount to be read out by the read out in step S13, the charge amount becomes the sub-capacitance C _sub of the storage capacitor C _s and charge 0 holding a charge 14Cs is accumulated in synthesized capacitances formed by connecting in series, a forward direction In scanning, the accumulated charge amount is read out when there is no defect (see FIG. 26).

  Thereafter, steps S6 to S9 are executed in the same manner as described above, and the presence / absence of a defect is determined and if there is a defect, the failure mode is analyzed and the failure mode is identified. Then, when the specified failure mode is one that can be repaired, the above steps S1 to S9 are executed again after being sent to the repair process to repair the defective portion. Thereby, the manufacturing yield of the display substrate 5 is improved.

  7 to 25 show changes in the potentials of the terminals A to C in the reset stage, the write stage, and the read stage in various failure modes. FIG. 26 shows the final holding potential of each terminal A to C obtained by simulation under the same conditions as in the case of no defect for each defective Ford and the stored charge amount to be read. The LUT is stored in advance in the storage unit.

Here, FIG. 7 shows an example of a failure mode between the short-circuited between the signal line SG _m and the scan line DS _n, shows a change in potential of the terminal A~C by forward scan. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 16V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is , the amount of electric charge sub capacitance C _sub of the storage capacitor C _s and charge 0 holding a charge 16Cs is accumulated in synthesized capacitances formed by connecting in series.

Figure 8 shows an example of failure mode shorted between the signal line SG _m and the scanning lines DS _(n-1), it shows a change in potential of the terminal A~C by forward scan. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 7V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is , the amount of electric charge sub capacitance C _sub of the storage capacitor C _s and charge 0 holding a charge 7Cs is accumulated in synthesized capacitances formed by connecting in series.

Figure 9 is an example of a failure mode shorted between the signal line SG _m and the scan line WS _m, shows a case where the write signal Vsig writing transistor 7 is turned on, by the forward scan of the pin A~C The change in potential is shown. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 24V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is The amount of charge accumulated in the combined capacitor formed by connecting the holding capacitor C _s holding the charge 24 Cs and the sub-capacitor C _sub having the charge 0 in series .

Figure 10 is an example of a failure mode is short-circuited between the signal line SG _m and the scan line WS _m, shows a case where write transistor 7 by the write signal Vsig is not turned on, due to the forward scanning of the terminal A~C The change in potential is shown. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 30V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is , The amount of charge accumulated in the combined capacitor formed by connecting the holding capacitor C _s holding the charge 30 Cs and the sub-capacitor C _sub having the charge 0 in series .

FIG. 11 shows an example of a failure mode in which the scanning line WS _n and the scanning line DS _n are short-circuited, and shows a case where the writing transistor 7 is turned on by the power supply voltage Vcc. The change in potential is shown. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 8V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the stored charge amount to be read is , the amount of electric charge sub capacitance C _sub of the storage capacitor C _s and charge 0 holding a charge 8Cs is accumulated in synthesized capacitances formed by connecting in series.

FIG. 12 shows an example of a failure mode in which the scanning line WS _n and the scanning line DS _(n−1) are short-circuited, and shows a case where the writing transistor 7 is turned on by the power supply voltage Vcc. The change of the electric potential of AC is shown. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 14V for the terminal A, 8V for the terminal B, and 10V for the terminal C, and the accumulated charge amount to be read is The amount of charge stored in a combined capacitor formed by connecting the holding capacitor C _s holding the charge 6Cs and the sub-capacitor C _sub holding the charge −2Csub in series .

Figure 13 shows an example of a failure mode between the short-circuited between the scanning lines DS _n and the scanning line DS _(n-1), it shows a change in potential of the terminal A~C by forward scan. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 1V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is , the amount of electric charge sub capacitance C _sub of the storage capacitor C _s and charge 0 holding charges Cs are stored in the combined capacitance composed are connected in series.

FIG. 14 shows an example of a failure mode in which the gate and source of the write transistor 7 are short-circuited, and shows changes in the potentials of the terminals A to C due to forward scanning. According to this, as shown in FIG. 26, the potential finally held at each of the terminals A to C is 0V for the terminal A, 16V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is The amount of charge stored in a combined capacitor formed by connecting the holding capacitor C _s holding the charge −16 Cs and the sub capacitor C _sub holding the charge 16 Csub in series .

  FIG. 15 shows an example of a failure mode in which the source and drain of the write transistor 7 are short-circuited, and shows changes in the potentials of the terminals A to C due to forward scanning. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 0V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is 0.

Figure 16 shows an example of a failure mode failure modes between the gate and the source are short-circuited, or the holding capacitor C _s leaked pixel transistor 8 shows a change in potential of the terminal A~C by forward scan . According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 5V for the terminal A, 5V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is This is the amount of charge accumulated in a combined capacitor formed by connecting a storage capacitor C _s having a charge 0 and a sub capacitor C _sub holding a charge 5Csub in series .

FIG. 17 shows a failure mode in which the gate and drain of the pixel transistor 8 are short-circuited, and shows changes in the potentials of the terminals A to C due to forward scanning. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 0V for the terminal A, 13V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is The amount of charge accumulated in the combined capacitor formed by connecting the holding capacitor C _s holding the charge −13 Cs and the sub capacitor C _sub holding the charge 13 Csub in series .

FIG. 18 shows a failure mode in which the drain and source of the pixel transistor 8 are short-circuited, and shows changes in the potentials of the terminals A to C due to forward scanning. According to this, as shown in FIG. 26, the potential finally held at each of the terminals A to C is -2V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the amount of stored charge to be read out. Is the amount of charge stored in a combined capacitor formed by connecting the holding capacitor C _s holding the charge −2 Cs and the sub-capacitor C _sub having the charge 0 in series .

Figure 19 shows a defect mode in which while is opened with the drain signal line SG _m and the write transistor 7 shows a change in the potential of the terminal A~C by forward scan. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 5V for the terminal A, 8V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is , The amount of charge accumulated in the combined capacitor formed by connecting the holding capacitor C _s holding the charge −3 Cs and the sub capacitor C _sub holding the charge 8 Csub in series . This value is the same as the accumulated charge amount read when “no defect” in forward scanning. Therefore, the failure mode cannot be detected only by forward scanning. On the other hand, as shown in FIG. 26, the potential finally held in each of the terminals A to C in the backward scanning is 10V for the terminal A, 0V for the terminal B, and 0V for the terminal C. Is the amount of charge stored in the combined capacitor formed by connecting the holding capacitor C _s holding the charge 10 Cs and the sub-capacitor C _sub having the charge 0 in series . This value is the amount of charge accumulated in the combined capacitor formed by connecting the holding capacitor C _s holding the charge 14Cs and the sub-capacitor C _sub having the charge 0 , which are read out in the backward scanning in the case of “no defect”. It is different. As described above, a failure mode that cannot be detected by the forward scanning can be easily detected by additionally executing the backward scanning.

Figure 20 shows a defect mode scanning lines WS _m or the write transistor 7 is open, shows a change in potential of the terminal A~C by forward scan. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 5V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is , the amount of electric charge sub capacitance C _sub of the storage capacitor C _s and charge 0 holding a charge 5Cs is accumulated in synthesized capacitances formed by connecting in series.

Figure 21 shows a defect mode scanning lines DS _n or the pixel transistor 8 is open, shows a change in potential of the terminal A~C by forward scan. According to this, as shown in FIG. 26, the potential finally held at each of the terminals A to C is 13V for the terminal A, 0V for the terminal B, -1V for the terminal C, Is the amount of charge stored in a combined capacitor formed by connecting a holding capacitor C _s holding a charge 13 Cs and a sub capacitor C _sub holding a charge Csub in series .

FIG. 22 shows a failure mode in which the space between the scanning line DS _(n−1) and the sub-capacitor C _sub is open, and shows changes in the potentials of the terminals A to C due to forward scanning. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 8V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the stored charge amount to be read is , the amount of electric charge sub capacitance C _sub of the storage capacitor C _s and charge 0 holding a charge 8Cs is accumulated in synthesized capacitances formed by connecting in series.

FIG. 23 shows a failure mode in which the sub-capacitor C _sub is opened, and shows changes in the potentials of the terminals A to C due to forward scanning. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 4V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is The amount of charge stored in the combined capacitor formed by connecting the holding capacitor C _s holding the charge 4Cs and the sub-capacitor C _sub having the charge 0 in series .

FIG. 24 shows a failure mode in which the sub capacitor C _sub leaks, and shows changes in the potentials of the terminals A to C due to forward scanning. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 12V for the terminal A, 0V for the terminal B, and 0V for the terminal C, and the accumulated charge amount to be read is , the amount of electric charge sub capacitance C _sub of the storage capacitor C _s and charge 0 holding a charge 12Cs is accumulated in synthesized capacitances formed by connecting in series.

FIG. 25 shows a failure mode in which the storage capacitor C _s is opened, and shows changes in the potentials of the terminals A to C due to forward scanning. According to this, as shown in FIG. 26, the potential finally held in each of the terminals A to C is 0V for the terminal A, -7V for the terminal B, and 0V for the terminal C, and the accumulated charge read out. Is the amount of charge stored in a combined capacitor formed by connecting a holding capacitor C _s holding charge −7 Cs and a sub capacitor C _sub holding charge −7 Csub in series .

  In this way, by comparing the accumulated charge amount read by the forward scan and the reverse scan with, for example, the LUT shown in FIG. 26, the read accumulated charge amount matches the LUT within a predetermined allowable range. The corresponding failure mode can be specified from the accumulated charge amount.

In the above description, the reset phase and read, the scanning lines DS _(n-1), the output of the reset scan signal DS _n is zero, only one clock of the reset scan to the scanning lines WS _n Although the case where a signal is supplied has been described, the present invention is not limited to this, and a reset scanning signal of one clock may be sequentially shifted to each scanning line by one clock and sequentially supplied. In this case, at the read stage, only one clock is supplied to the scanning line WS _n by a system different from the above.

FIG. 27 is a block diagram showing a second embodiment of the defect inspection apparatus for the display substrate 5 according to the present invention. The difference from the first embodiment is that three types of scanning lines DS _{1 to} DS _n , WS _{1 to} WS _n , and AZ _{1 to} AZ that can be independently controlled included in the organic EL display substrate 5 to be inspected are provided. _The reset scanning signal, the writing scanning signal, and the reading scanning signal can be sequentially supplied to _n , and the scanning means 1 has the same number of buffers 11 and probes 12 as the scanning lines. Yes. Moreover, so that the output of the gate driver IC10 is connected scan line alternately to one every other via a buffer 11 WS ₁ to WS _n and the scan line DS ₁ to DS _n as shown in FIG. 27. Further, the output of the gate driver IC 10 directed to the scanning lines WS _{1 to} WS _n is branched in the middle and connected to the OR circuit 21, and scanning is performed by performing an OR operation on the scanning signals and enable signals of the scanning lines WS _{1 to} WS _n. Scan signals for the lines AZ _{1 to} AZ _n can be generated. Therefore, although the same pulse signal is output as the scanning signal to the scanning lines WS _{1 to} WS _n and the scanning lines AZ _{1 to} AZ _n (see FIG. 29), the scanning signals of the scanning lines AZ _{1 to} AZ _n are: It may be a scanning signal of the scanning line WS ₁ to WS _n by an enable signal on / off control to differ from the scanning signal of the scanning line WS ₁ to WS _n that (see FIG. 30).

The pixel circuit 6 of the organic EL display substrate 5 that can be inspected by the defect inspection apparatus of the second embodiment includes a storage capacitor C _s that holds a data signal and the scanning lines WS _{1 to} WS among the three types of scanning lines. _The write transistor 7 that is driven by _n and holds the data signal in the holding capacitor C _s , the pixel transistor 8 that supplies current to the organic EL element, and the pixel transistor 8 and the organic EL that are driven by the scanning lines DS _{1 to} DS _n . The first switching transistor 22 for controlling the light emission time of the organic EL element by turning on / off the supply of the drive current to the element, and the source of the pixel transistor 8 driven by the scanning lines AZ _{1 to} AZ _n to a fixed potential. And a second switching transistor 23 to be connected. Each of the transistors is, for example, an N-MOS transistor.

More specifically, as shown in FIG. 28 , the write transistor 7 has a gate connected to the scanning line WS _n , a source connected to the signal line SG _m , and a drain connected to the gate of the pixel transistor 8. Yes. The pixel transistor 8 has a drain connected to the source of the first switching transistor 22 and a source connected to the drain of the second switching transistor 23. Furthermore, the first switching transistor 22 has a gate connected to the scanning line DS _n, and a drain connected to the power supply Vcc. Furthermore, the second switching transistor 23 has a gate connected to the scanning line AZ _n and a source connected to the fixed potential Vini. A holding capacitor C _s is provided between the gate and the source of the pixel transistor 8, and the gate side is the terminal A and the source side is the terminal B. The anode of the organic EL element is connected to the source of the pixel transistor 8.

FIG. 30 is a timing chart of the reset scanning signal supplied to each scanning line in the reset stage in the defect inspection apparatus of the second embodiment. As shown in the figure, the reset scanning signal supplied to each scanning line is generated by latching the start signal STR in synchronization with the rising edge of the clock signal CLK. In this case, since the enable signal AZOE is on during the reset period, the scan lines AZ _{1 to} AZ _n generated by performing an OR operation on the reset scan signal of the scan lines WS _{1 to} WS _n and the enable signal AZOE. The reset scanning signal is the same as the scanning signal of the scanning lines WS _{1 to} WS _n . Therefore, in the reset step, write transistor 7 of the pixel circuit 6 shown in FIG. 28 is turned on by the reset scan signal of the scan line WS _n, and the terminal A and the signal line SG _m lead to electrical. At the same time, the second switching transistor 23 is turned on by the reset scanning signal of the scanning line AZ _n , and the terminal B is connected to the fixed potential Vini via the second switching transistor 23. At this time, if the signal lines SG _m , Vini, and Vcc are set to a common potential, for example, low level, the terminals A and B become both low level, and the charge of the storage capacitor C _s is reset to zero. In the next timing, the reset scan signal is supplied only to the scan line DS _n, although the first switching transistor 22 is turned on, the writing transistor 7, the pixel transistor 8 and the second switching transistor 23 is turned off . Therefore, the reset state of the storage capacitor C _s is maintained.

FIG. 31 is a timing chart of the scanning signal for writing supplied to each scanning line in the writing stage in the defect inspection apparatus of the second embodiment. As shown in FIG. 28 , the combination of two transistors (the write transistor 7 and the second switching transistor 23, the write transistor 7 and the first switching transistor 22) among the plurality of transistors of the pixel circuit 6 shown in FIG. The pulse width of the start signal STR is set to two clocks so that the signals can be turned on simultaneously, and the write scanning signals for the generated scanning lines WS _{1 to} WS _n and the scanning lines DS _{1 to} DS _n have a pulse width of two clocks. I am doing so. Further, the write scanning signals for the scanning lines WS _{1 to} WS _n are controlled by the enable signal AZOE for one clock, and the generated scanning signals for the scanning lines AZ _{1 to} AZ _n have a pulse width for one clock. To have. As a result, the write transistor 7 and the second switching transistor 23 are first turned on by the write scan signals supplied from the three types of scan lines connected to the same pixel circuit 6, and a predetermined amount is applied to both ends of the storage capacitor C _s. The potential is applied, and then the write transistor 7 and the first switching transistor 22 are turned on, and a predetermined charge is written (stored) in the storage capacitor C _s . In this case, when there is a defect in the pixel circuit 6, the terminal A, and changes in the applied voltage and the order of application of B, the accumulated charge amount to be written in the storage capacitor C _s as will be described later are different depending on the failure mode. Therefore, it is possible to determine the presence / absence of a defect and specify the failure mode by detecting the amount of accumulated charge. In the reading stage, the same scanning signal as the reset scanning signal in FIG. 30 is supplied to each scanning line.

FIGS. 32 to 34 are diagrams showing a configuration example of another scanning signal applied to the defect inspection apparatus of the second embodiment, and there are k scanning lines AZ _{1 to} AZ _n (two in the figure). A case where the scanning lines WS _{1 to} WS _n are connected to the previous one is shown. Thereby, since each scanning signal of the scanning line is supplied from the scanning line, it is not necessary to supply the logic operation circuit and the enable signal AZOE as shown in FIG. 28, and the circuit configuration is simplified.

FIG. 32 is a timing chart of a reset scanning signal supplied to each scanning line in the reset stage. As shown in the figure, the reset scanning signal supplied to each scanning line is a one-clock pulse generated by latching the start signal STR in synchronization with the rising edge of the clock signal CLK, and is shifted by one clock. Register operation is performed. Then, the same reset scanning signal as that of the previous two scanning lines WS _{1 to} WS _n is supplied to the scanning lines AZ _{1 to} AZ _n . That is, the scanning line AZ _i is supplied with a signal from the scanning line WS _(i−2) .

FIG. 33 is a timing chart of the writing scanning signal supplied to each scanning line in the writing stage. As shown in the figure, the write scanning signal supplied to each scanning line has a waveform having a pulse width of 2 clocks and a waveform having a pulse width of 1 clock that rises with a delay of 4 clocks from the rise of this waveform. The signal waveform is generated by using a start signal STR that is a combination of and a pulse of 2 clocks and a pulse of 1 clock that rises with a delay of 4 clocks. Each shift register operates for one clock. Accordingly, it is possible to make a timing at which the scanning signal of the scanning line WS _{1 and} the scanning signal of the scanning line DS ₁ are simultaneously turned on by the first two clock pulses. Additionally, the following one clock pulse by the scanning signal of the scanning line WS ₁ are turned on simultaneously two previous scan signal of the scanning line WS _-2 (i.e., the scanning signal of the scanning lines AZ ₁₎ make the timing is turned on be able to. As a result, the write transistor 7 and the second switching transistor 23 are first turned on by the write scan signals supplied from the three types of scan lines connected to the same pixel circuit 6, and a predetermined amount is applied to both ends of the storage capacitor C _s. The potential is applied, and then the write transistor 7 and the first switching transistor 22 are turned on, and a predetermined charge is written (stored) in the storage capacitor C _s .

FIG. 34 is a timing chart of the scanning signal for reading supplied to each scanning line in the reading stage. As shown in the figure, the scanning signal for reading supplied to each scanning line has a waveform having a pulse width of one clock and a waveform having a pulse width of one clock that rises with a delay of four clocks from the rise of this waveform. And a shift register operation of 1 clock. Accordingly, when the scanning signal of the scanning line WS ₁ are turned on simultaneously two previous scan signal of the scanning line WS _-2 (i.e., the scanning signal of the scanning lines AZ ₁₎ can be turned on, the writing transistor 7 and the second The storage transistor written in the storage capacitor Cs can be read by simultaneously turning on the switching transistor 23 of the storage capacitor Cs.

FIGS. 35 to 46 are explanatory diagrams showing changes in the potentials of the terminals A and B of the pixel circuit 6 in the defect inspection of the display substrate 5 using the defect inspection apparatus of the second embodiment. Shown for each. Each signal waveform applied at this time and its supply timing are as shown in FIG. That is, the reset phase, the pulse signal of one clock to the respective scanning lines are sequentially supplied with one cycle shift of the clock signal CLK, the potential Vsig of the signal line SG _m, drain potential Vcc of the first switching transistor 22, The source potential Vini of the second switching transistor 23 is both fixed at a low level.

Further, in the writing stage, each scanning line is sequentially supplied with a shift of one period of the lock signal CLK so that there is a timing at which two pulses divided into two clocks are simultaneously turned on, and the signal line SG _m The potential Vsig, the drain potential Vcc of the first switching transistor 22, and the source potential Vini of the second switching transistor 23 are set to predetermined high level potentials, respectively.

Then, the read phase, two-pulse signal obtained by halving the two clocks to each of the scanning lines are sequentially supplied with one cycle shift of the lock signal CLK so that there is a timing of turning on at the same time, the signal line SG _m The potential Vsig, the drain potential Vcc of the first switching transistor 22, and the source potential Vini of the second switching transistor 23 are all fixed at a low level.

  In the above simulation, assuming that the output of the gate driver IC 10 is controlled by an enable signal and the pulse width of the signal supplied to each scanning line is controlled, a two-pulse signal obtained by dividing two clocks into two However, it may have a pulse width of 2 clocks as shown in FIGS.

FIG. 35 shows a case where the display substrate 5 is not defective, and charges are written in the storage capacitor C _s by the potential difference (VA−VB) of the potential finally held at the terminals A and B of the pixel circuit 6. Here, for example, the potential of the signal supplied by each scanning line WS _n , DS _n , AZ _n is set to the high level of 35 V, the low level of −5 V, and the potential Vcc supplied to the drain of the first switching transistor 22. The high level is 30V, the low level is 0V, the potential Vini supplied to the source of the second switching transistor 23 is 0V, the low level is -3V, and the potential Vsig supplied to the signal line SGm is 20V. When simulating the potential finally held at the terminals A and B when the low level is 0V, VA = 8V and VB = −5V are obtained as shown in FIG. Therefore, when the pixel circuit 6 is defect-free, the amount of charge accumulated in the storage capacitor C _s is Qs = Cs (VA−VB) = − 13 Cs.

  FIG. 36 shows an example of a failure mode in which the gate of the first switching transistor 22 and the signal line are short-circuited. In this case, if a simulation is performed under the same conditions as in the case of no defect described above, a potential of 7 V is held at the terminal A and a potential of −3 V is held at the terminal B. As a result, the amount of stored charge to be read is 10 Cs.

  FIG. 37 shows an example of a failure mode in which the gate of the first switching transistor 22 and the source of the second switching transistor 23 are short-circuited. In this case, a potential of 12V is held at the terminal A and a potential of −3V is held at the terminal B. As a result, the stored charge amount to be read is 15 Cs.

  FIG. 38 shows an example of a failure mode in which the gate and source of the second switching transistor 23 are short-circuited. In this case, a potential of 6V is held at the terminal A and a potential of 6V is held at the terminal B, and as a result, the amount of stored charge to be read is zero.

  FIG. 39 shows an example of a failure mode in which the gate of the second switching transistor 23 and the signal line are short-circuited. In this case, a potential of 4V is held at the terminal A and a potential of −3V is held at the terminal B. As a result, the stored charge amount to be read is 7 Cs.

  FIG. 40 shows an example of a failure mode in which the gate of the write transistor 7 and the drain of the first switching transistor 22 are short-circuited. In this case, a potential of 7V is held at the terminal A and a potential of -5V is held at the terminal B. As a result, the stored charge amount to be read is 12Cs.

  FIG. 41 shows an example of a failure mode in which the gate of the write transistor 7 and the source of the second switching transistor 23 are short-circuited. In this case, a potential of 12V is held at the terminal A and a potential of 12V is held at the terminal B, and as a result, the amount of stored charge to be read is zero.

  FIG. 42 shows an example of a failure mode in which the gate of the write transistor 7 and the signal line are short-circuited. In this case, a potential of 12V is held at the terminal A and a potential of 6V is held at the terminal B, and as a result, the amount of accumulated charge to be read is 18 Cs.

  FIG. 43 shows an example of a failure mode in which the gate of the first switching transistor 22 and the gate of the second switching transistor 23 are short-circuited. In this case, the terminal A holds a potential of 10 V and the terminal B holds a potential of -5 V, and as a result, the amount of stored charge to be read is 15 Cs.

  FIG. 44 shows an example of a failure mode in which the gate of the write transistor 7 and the gate of the second switching transistor 23 are short-circuited. In this case, the terminal A holds a potential of 10 V and the terminal B holds a potential of -5 V, and as a result, the amount of stored charge to be read is 15 Cs.

  FIG. 45 shows an example of a failure mode in which the gate of the write transistor 7 and the gate of the first switching transistor 22 are short-circuited. In this case, a potential of 2V is held at the terminal A and a potential of −6V is held at the terminal B. As a result, the stored charge amount to be read is 8 Cs.

  Then, the calculation results are tabulated as shown in FIG. 46 in association with each failure mode, and are stored in the control means 3 of the inspection apparatus as an LUT. Note that FIGS. 36 to 45 show some defective modes, and the accumulated charge amount can be similarly obtained for other defective modes by simulating. Therefore, if the accumulated charge amount including these other failure modes is obtained and stored in a table (LUT), the accumulated charge amount read by the defect inspection is compared with the LUT, and the predetermined amount is stored. The failure mode can be specified from the accumulated charge amount that is matched within the allowable value.

The third embodiment of the present invention is a display device in which the pixel circuits 6 shown in FIG. 2 are provided in a matrix on a substrate, and two kinds of scanning lines SW _{1 to} SW _n and DS _{1 to} DS _n are displayed as images. while scanning the display in the same direction, supplied with keeping the potential of the signal line SG ₁ to SG _m to a predetermined value, the two scanning lines SW ₁ to SW _n, the DS ₁ to DS _n predetermined reset scanning signals Then, the write transistor 7 is turned on, the potentials at both ends of the internal capacitor (the holding capacitor C _s and the sub capacitor C _sub ) are set to the same level, the charge is reset to zero, and a predetermined potential is applied to the signal lines SG _{1 to} SG _m . A write signal is supplied and a predetermined write scan signal is sequentially supplied to each of the two types of scanning lines SW _{1 to} SW _n and DS _{1 to} DS _n so that there is a timing at which the potential simultaneously becomes a high level. Thus, charges are accumulated in the internal capacitance, and two types of scanning lines S are stored. ₁ to SW _n, the write transistor 7 turns on driving by supplying a scanning signal for a predetermined read DS ₁ to DS _n, the accumulated charge amount signal line SG ₁ to SG _m held in the internal volume And a defect inspection device that determines the presence or absence of a defect in the pixel circuit 6 based on the amount of accumulated charge read out.

The fourth embodiment of the present invention is a display device in which the pixel circuit shown in FIG. 28 is provided in a matrix on a substrate, and includes three types of scanning lines SW _{1 to} SW _n , DS _{1 to} DS _n , While scanning AZ _{1 to} AZ _n in the same direction as the video display, the potentials of the signal lines SG _{1 to} SG _m are maintained at a predetermined value, and the three types of scanning lines SW _{1 to} SW _n , DS _{1 to} DS _n , AZ ₁ is supplied to ～AZ _n predetermined reset scanning signal simultaneously turns on driving the write transistor 8 and the second switching transistor 23, the charge potential across internal capacitance (holding capacitance C _s) in the same level Reset to zero, supply a write signal having a predetermined potential to the signal lines SG _{1 to} SG _m, and apply predetermined signals to the three scanning lines SW _{1 to} SW _n , DS _{1 to} DS _n , and AZ _{1 to} AZ _n , respectively. The potential of the write scan signal becomes high at the same time. Sequentially supplied so that timing exists, charges are accumulated in the internal capacitors, and predetermined scanning signals are supplied to the three scanning lines SW _{1 to} SW _n , DS _{1 to} DS _n , and AZ _{1 to} AZ _n Then, the write transistor 7 and the second switching transistor 23 are simultaneously turned on to read the accumulated charge amount held in the internal capacitor via the signal lines SG _{1 to} SG _m , and the read accumulated charge amount Is provided with a defect inspection apparatus for determining the presence or absence of defects in the pixel circuit 6.

  In the third and fourth embodiments, the defect inspection apparatus increases the level of the data signal corresponding to the organic EL element when the failure mode of the pixel circuit 6 reduces the luminance of the organic EL element. Control is performed to increase the luminance of the organic EL element. As a result, the display device can compensate for a decrease in the luminance of the defective portion and display a uniform display.

  In the above description, the case where the display substrate is the organic EL display substrate 5 has been described. However, the present invention is not limited to this, and the luminance of the electro-optical element such as a liquid crystal display substrate corresponds to the data signal. As long as it changes, it may be anything.

1 is a block diagram showing a first embodiment of a display substrate defect inspection apparatus according to the present invention; FIG. It is a block diagram which shows the example of 1 structure of the pixel circuit of the display substrate used in the said 1st Embodiment. 5 is a timing chart showing examples of scanning signals and writing signals applied to the defect inspection apparatus, where (a) is a timing chart during forward scanning and (b) is a timing chart during backward scanning. It is a flowchart which shows the procedure of the defect inspection method performed using the defect inspection apparatus of the said 1st Embodiment. It is explanatory drawing which shows the change of the both-ends potential of a storage capacity | capacitance and a sub capacity | capacitance in the test | inspection by the forward scanning of a defect-free display board | substrate. It is explanatory drawing which shows the change of the both-ends potential of a storage capacity | capacitance and a sub capacity | capacitance in the test | inspection by reverse scanning of a defect-free display board | substrate. In defective mode between the short-circuited between the signal line SG _m of the display substrate that is applied to the first embodiment and the scanning line DS _n, explanation showing changes in potential across the holding capacitor and the sub-volume by forward scan FIG. In defective mode between the short-circuited in the first display substrate applied to embodiments the signal line SG _m of the scanning lines DS _(n-1), the potential across the storage capacitor and the sub-volume by forward scan It is explanatory drawing which shows a change. Description showing changes in both-end potentials of the storage capacitor and the sub-capacitance due to forward scanning in the failure mode in which the signal line SG _m and the scanning line WS _m of the display substrate applied to the first embodiment are short-circuited. It is a figure and shows the case where a write transistor is turned on by a write signal. Description showing changes in both-end potentials of the storage capacitor and the sub-capacitance due to forward scanning in the failure mode in which the signal line SG _m and the scanning line WS _m of the display substrate applied to the first embodiment are short-circuited. It is a figure and shows the case where a write transistor is not turned on by a write signal. Description showing changes in both-end potentials of the storage capacitor and the sub-capacitance due to the forward scanning in the failure mode in which the scanning line WS _n and the scanning line DS _n of the display substrate applied to the first embodiment are short-circuited. It is a figure and the case where a writing transistor turns on with a power supply voltage is shown. In the failure mode in which the scanning line WS _n and the scanning line DS _(n−1) of the display substrate applied to the first embodiment are short-circuited, the potentials at both ends of the storage capacitor and the sub capacitor by the forward scanning It is explanatory drawing which shows a change, and has shown the case where a writing transistor turns on with a power supply voltage. In the failure mode in which the scanning line DS _n and the scanning line DS _(n−1) of the display substrate applied to the first embodiment are short-circuited, the potentials at both ends of the storage capacitor and the sub-capacitor by the forward scanning are It is explanatory drawing which shows a change. FIG. 7 is an explanatory diagram showing changes in potentials at both ends of a storage capacitor and a sub capacitor due to forward scanning in a failure mode in which a gate and a source of a writing transistor of a display substrate applied to the first embodiment are short-circuited. FIG. 5 is an explanatory diagram showing changes in potentials at both ends of a storage capacitor and a sub capacitor due to forward scanning in a failure mode in which a source and a drain of a writing transistor of a display substrate applied to the first embodiment are short-circuited. In the failure mode in which the gate and the source of the pixel transistor of the display substrate applied to the first embodiment are short-circuited or in the failure mode in which the storage capacitor leaks, the potentials at both ends of the storage capacitor and the sub-capacitor by forward scanning are It is explanatory drawing which shows a change. FIG. 7 is an explanatory diagram showing changes in potentials at both ends of a storage capacitor and a sub-capacitance due to forward scanning in a failure mode in which a gate transistor and a drain of a pixel transistor of a display substrate applied to the first embodiment are short-circuited. FIG. 6 is an explanatory diagram showing changes in potentials at both ends of a storage capacitor and a sub-capacitance due to forward scanning in a failure mode in which a drain and a source of a pixel transistor of a display substrate applied to the first embodiment are short-circuited. A defect mode while is opened with the drain signal line SG _m and the write transistor of the display substrate that is applied to the first embodiment, explanation showing changes in potential across the holding capacitor and the sub-volume by forward scan FIG. In the first embodiment the applied scanning line WS _m or defective mode write transistor is open for display substrate of an explanatory view showing changes in potential across the holding capacitor and the sub-volume by forward scan. In the first embodiment the applied defect mode scanning lines DS _n or the pixel transistor is open for display substrate of an explanatory view showing changes in potential across the holding capacitor and the sub-volume by forward scan. In the failure mode in which the space between the scanning line DS _{(n-1) of the} display substrate and the sub-capacitor applied to the first embodiment is opened, changes in the potentials at both ends of the storage capacitor and the sub-capacitance due to the forward scanning It is explanatory drawing shown. FIG. 6 is an explanatory diagram showing changes in potentials at both ends of a storage capacitor and a sub-capacitance due to forward scanning in a failure mode in which the sub-capacitance of the display substrate applied to the first embodiment is opened. FIG. 6 is an explanatory diagram showing changes in potentials at both ends of a storage capacitor and a sub-capacitance due to forward scanning in a failure mode in which a sub-capacitance of a display substrate applied to the first embodiment leaks. FIG. 6 is an explanatory diagram showing changes in potentials at both ends of a storage capacitor and a sub-capacitance due to forward scanning in a failure mode in which a storage capacitor of a display substrate applied to the first embodiment is opened. It is a look-up table used for determination of the presence or absence of a defect and identification of a defective Ford in the first embodiment. It is a block diagram which shows 2nd Embodiment of the defect inspection apparatus of the display board | substrate by this invention. It is a block diagram which shows one structural example of the pixel circuit of the display substrate used in the said 2nd Embodiment. FIG. 6 is a block diagram illustrating a configuration example of a circuit that generates a scanning signal of a scanning line AZ _n using a scanning signal of a scanning line WS _n . It is a timing chart which shows one structural example of the scanning signal for reset applied to the reset stage in the said 2nd Embodiment. It is a timing chart which shows one structural example of the scanning signal for a writing applied to the writing step in the said 2nd Embodiment. It is a timing chart which shows the other structural example of the scanning signal for reset applied to the reset stage in the said 2nd Embodiment. It is a timing chart which shows the other structural example of the scanning signal for a writing applied to the writing step in the said 2nd Embodiment. 10 is a timing chart illustrating an example of a configuration of a scanning signal for reading applied to a reading stage in the second embodiment. It is explanatory drawing which shows the change of the both-ends potential of the storage capacity at the time of a defect-free in the test | inspection of the display substrate applied to the said 2nd Embodiment. It is explanatory drawing which shows the change of the electric potential of both ends of the storage capacity by forward scanning in the failure mode in which the gate and signal line of the first switching transistor of the display substrate applied to the second embodiment are short-circuited. FIG. 6 shows a change in potential at both ends of the storage capacitor due to forward scanning in a failure mode in which the gate of the first switching transistor and the source of the second switching transistor of the display substrate applied to the second embodiment are short-circuited. It is explanatory drawing. It is explanatory drawing which shows the change of the electric potential of both ends of the storage capacity by forward scanning in the failure mode where the gate and source of the second switching transistor are short-circuited. Explanatory drawing which shows the change of the both-ends potential of the storage capacity by forward scanning in the failure mode in which the gate and the signal line of the second switching transistor 23 of the display substrate applied to the second embodiment are short-circuited. It is. Explanation of change in potential of both ends of the storage capacitor due to forward scanning in a failure mode in which the gate of the writing transistor and the drain of the first switching transistor of the display substrate applied to the second embodiment are short-circuited FIG. Explanation of change in potential between both ends of the storage capacitor due to forward scanning in a failure mode in which the gate of the writing transistor and the source of the second switching transistor of the display substrate applied to the second embodiment are short-circuited FIG. It is explanatory drawing which shows the change of the electric potential of both ends of the storage capacity by a forward scan in the failure mode in which the gate and signal line of the writing transistor of the display substrate applied to the second embodiment are short-circuited. In the failure mode in which the gate of the first switching transistor and the gate of the second switching transistor of the display substrate applied to the second embodiment are short-circuited, the change in the potential across the storage capacitor due to the forward scanning It is explanatory drawing which shows. Explanation of change in potential at both ends of the storage capacitor due to forward scanning in a failure mode in which the gate of the writing transistor and the gate of the second switching transistor of the display substrate applied to the second embodiment are short-circuited FIG. Explanation of change in potential of both ends of the storage capacitor due to forward scanning in a failure mode in which the gate of the writing transistor and the gate of the first switching transistor of the display substrate applied to the second embodiment are short-circuited FIG. It is the look-up table used for determination of the presence or absence of a defect in the said 2nd Embodiment, and identification of defective Ford.

DESCRIPTION OF SYMBOLS 1 ... Scanning means 2 ... Write-out reading means 3 ... Control means 5 ... Organic EL display substrate 6 ... Pixel circuit 7 ... Write transistor 8 ... Pixel transistor 22 ... 1st switching transistor 23 ... 2nd switching transistor (switching transistor)
WS _{1 to} WS _n , DS _{1 to} DS _n , AZ _{1 to} AZ _n ... Scanning line SG _{1 to} SG _m ... Signal line C _s ... holding capacity (internal capacity)
C _sub ... sub capacity (internal capacity)

Claims (16)

A pixel transistor disposed at the intersection of the first and second scanning lines and the signal line and driving an electro-optical element whose luminance changes in accordance with a data signal , the drain of which is connected to the first scanning line And a write transistor connected between the signal line and the pixel transistor and having a gate connected to the second scan line, and one end connected to a connection end of the pixel transistor and the write transistor, A display substrate provided in a matrix with a pixel circuit having a storage capacitor having the other end connected to the source and an internal capacitor composed of a sub-capacitor connected between the other end of the storage capacitor and a fixed potential A defect inspection method,
While scanning the first and second scanning lines in the same direction as the video display,
The potential of the signal line is maintained at a predetermined value, and a predetermined reset scanning signal is supplied to the first and second scanning lines to turn on the writing transistor, so that the potentials at both ends of the internal capacitor are at the same level. Reset stage to reset the charge to zero,
A write signal having a predetermined potential is supplied to the signal line, and a predetermined write scan signal is sequentially supplied to the first and second scan lines so that there is a timing at which the potential simultaneously becomes a high level. A write stage for accumulating electric charge in the internal capacitor;
A reading step of supplying a predetermined reading scanning signal to the first and second scanning lines to turn on the writing transistor, and reading out the accumulated charge held in the internal capacitor via the signal line When,
A determination step of determining whether there is a defect in the pixel circuit based on the read accumulated charge amount;
Defect inspection method rows cormorants display by entering the substrate each process. Said reset step, write step, reading out, after executing the processing of the determination step, the first, while scanning the second scanning line on the video display in the opposite direction, billed said that perform the process again Item 2. A display substrate defect inspection method according to Item 1. In the reset phase and the read phase, the first, second defect inspection method for a display substrate according to 請 Motomeko 1 you output a scanning signal only to the second scan line of the scan lines. A pixel transistor that is disposed at an intersection between the first and second scanning lines and the signal line and drives an electro-optical element whose luminance changes according to a data signal, and is connected between the signal line and the pixel transistor A write transistor having a gate connected to the first scan line; a switching transistor connected between a source of the pixel transistor and a fixed potential; and a gate connected to the second scan line ; A display substrate defect inspection method comprising a pixel circuit having a pixel circuit including a connection end of a pixel transistor and a write transistor and an internal capacitor connected between the source of the pixel transistor,
While scanning the first and second scanning lines in the same direction as the video display,
The potential of the signal line is kept at a predetermined value, and a predetermined reset scanning signal is supplied to the first and second scanning lines to simultaneously turn on the writing transistor and the switching transistor, and both ends of the internal capacitor A reset stage in which the potential is set to the same level and the charge is reset to zero; and
A write signal having a predetermined potential is supplied to the signal line, and a predetermined write scan signal is sequentially supplied to the first and second scan lines so that there is a timing at which the potential simultaneously becomes a high level. A write stage for accumulating electric charge in the internal capacitor;
A predetermined readout scanning signal is supplied to the first and second scanning lines to simultaneously turn on the writing transistor and the switching transistor, and the amount of accumulated charge held in the internal capacitor is passed through the signal line. A readout stage to read out,
A determination step of determining whether there is a defect in the pixel circuit based on the read accumulated charge amount;
Defect inspection method rows cormorants display by entering the substrate each process. The scanning signal of the second scan line, the first scan signal and the enable signal and the defect inspection method for a display substrate according to 請 Motomeko 4 that will be generated by logical operation of the scanning line. The second scanning line, a defect inspection method for a display substrate according to 請 Motomeko 4 that is connected to the first n the previous scan line of the scan lines. The electro-optical element, Ru Oh organic electroluminescence element 請 Motomeko 1 or claim 4 defect inspection method for a display substrate according to. In the determination step, the read accumulated charge amount is compared with a reference table stored in advance in association with the defect-free and various defect modes and the corresponding accumulated charge amounts, and the presence / absence of defect is determined. defect inspection method for a display substrate according to 請 Motomeko 1 or claim 4 you specific mode. A pixel transistor disposed at the intersection of the first and second scanning lines and the signal line and driving an electro-optical element whose luminance changes in accordance with a data signal , the drain of which is connected to the first scanning line And a write transistor connected between the signal line and the pixel transistor and having a gate connected to the second scan line, and one end connected to a connection end of the pixel transistor and the write transistor, A display substrate provided in a matrix with a pixel circuit having a storage capacitor having the other end connected to the source and an internal capacitor composed of a sub-capacitor connected between the other end of the storage capacitor and a fixed potential Defect inspection equipment,
The first and second scanning lines are scanned in the same direction as the video display or in the opposite direction, and a predetermined reset scanning signal is supplied to the first and second scanning lines at a reset stage. The write transistor is turned on, a predetermined write scan signal is sequentially supplied so that there is a timing at which the potential simultaneously becomes a high level in the write stage, and a predetermined read scan signal is supplied in the read stage. Scanning means for driving the writing transistor on;
In the reset stage, the potential of the signal line is kept at a predetermined value, and in the write stage, a write signal having a predetermined potential is supplied to hold the charge in the internal capacitor, and the stored charge amount held in the internal capacitor in the read stage Writing / reading means for detecting via the signal line;
Control means for controlling the driving of each of the constituent elements, and for determining the presence or absence of a defect in the pixel circuit based on the accumulated charge amount read by the writing and reading means;
Defect inspection apparatus display by entering the substrate provided with. A pixel transistor that is disposed at an intersection between the first and second scanning lines and the signal line and drives an electro-optical element whose luminance changes according to a data signal, and is connected between the signal line and the pixel transistor A write transistor having a gate connected to the first scan line; a switching transistor connected between a source of the pixel transistor and a fixed potential; and a gate connected to the second scan line ; A display substrate defect inspection apparatus comprising a pixel circuit having a matrix circuit and an internal capacitor connected between a connection end of a pixel transistor and a write transistor and a source of the pixel transistor,
The writing transistor scans the first and second scanning lines in the same direction as the video display, and supplies a predetermined reset scanning signal to the first and second scanning lines at a reset stage. The switching transistor is simultaneously turned on, and a predetermined scanning signal is sequentially supplied to the writing stage so that there is a timing at which the potential simultaneously becomes a high level, and a predetermined scanning signal is supplied to the reading stage. Scanning means for simultaneously turning on the write transistor and the switching transistor;
In the reset stage, the potential of the signal line is kept at a predetermined value, and in the write stage, a write signal having a predetermined potential is supplied to hold the charge in the internal capacitor, and the stored charge amount held in the internal capacitor in the read stage Writing / reading means for detecting via the signal line;
Control means for controlling the driving of each of the constituent elements, and for determining the presence or absence of a defect in the pixel circuit based on the accumulated charge amount read by the writing and reading means;
Defect inspection apparatus display by entering the substrate provided with. The control unit includes a storage unit that stores in advance a reference table in which the defect-free and various failure modes are associated with the stored charge amount corresponding thereto, and the stored charge amount of the reference table is read by the writing / reading unit. It was accumulated charge amount and the determination of the presence or absence of a defect by comparing and the display defect inspection device for the substrate according to 請 Motomeko 9 or claim 10 you specific failure mode. The electro-optical element, the display defect inspection device for the substrate according to Oh Ru請 Motomeko 9 or claim 10 in an organic electroluminescence device. A pixel transistor disposed at the intersection of the first and second scanning lines and the signal line and driving an electro-optical element whose luminance changes in accordance with a data signal , the drain of which is connected to the first scanning line And a write transistor connected between the signal line and the pixel transistor and having a gate connected to the second scan line, and one end connected to a connection end of the pixel transistor and the write transistor, A pixel circuit including a storage capacitor having the other end connected to the source and an internal capacitor including a sub-capacitor connected between the other end of the storage capacitor and a fixed potential is provided in a matrix on the substrate. A display device,
While the first and second scanning lines are scanned in the same direction as the video display, the potential of the signal line is maintained at a predetermined value, and a predetermined reset scanning signal is supplied to the first and second scanning lines. and the write transistor turns on driven, the potentials at both ends of the internal volume is reset to zero charge in the same level, it supplies a write signal of a predetermined potential to the signal line, the first, the second A predetermined scanning signal for scanning is sequentially supplied to the scanning lines so that there is a timing at which the potential simultaneously becomes a high level, and charges are accumulated in the internal capacitors, and the predetermined scanning lines are stored in the first and second scanning lines. The read scanning signal is supplied to turn on the write transistor, the accumulated charge held in the internal capacitor is read through the signal line, and the read charge amount is based on the read accumulated charge amount. Pixel circuit defects Viewing apparatus comprising a defect inspection apparatus for determining the presence or absence of. A pixel transistor that is disposed at an intersection between the first and second scanning lines and the signal line and drives an electro-optical element whose luminance changes according to a data signal, and is connected between the signal line and the pixel transistor A write transistor having a gate connected to the first scan line; a switching transistor connected between a source of the pixel transistor and a fixed potential; and a gate connected to the second scan line ; A display device comprising a pixel circuit in a matrix on a substrate, the pixel circuit having an internal capacitor connected between a connection end of a pixel transistor and a writing transistor and a source of the pixel transistor,
While the first and second scanning lines are scanned in the same direction as the video display, the potential of the signal line is maintained at a predetermined value, and a predetermined reset scanning signal is supplied to the first and second scanning lines. Then, the write transistor and the switching transistor are simultaneously turned on, the potentials at both ends of the internal capacitor are set to the same level, the charge is reset to zero, a write signal having a predetermined potential is supplied to the signal line, and the first , the second scan line, respectively accumulating charges in the inner capacity and sequentially supplied as the potential scanning signal for a given write is present timing becomes the high level at the same time, the first, the second A predetermined scanning signal is supplied to the scanning line to simultaneously turn on the writing transistor and the switching transistor, and the accumulated charge amount held in the internal capacitor is passed through the signal line. Viewing apparatus having read, a defect inspection apparatus for the determination of the presence or absence of a defect of the pixel circuit based on the read accumulated charge amount Te. The defect inspection apparatus increases the level of a data signal corresponding to the electro-optical element to increase the luminance of the electro-optical element when the defective mode of the pixel circuit reduces the luminance of the electro-optical element. the display device according to 請 Motomeko 13 or claim 14 that controls the. The electro-optical element, a display device according to Oh Ru請 Motomeko 13 or claim 14 in an organic electroluminescence element.

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