JP5396878B2 - Clock synchronization circuit - Google Patents

Description

  The present invention relates to a control circuit for controlling a switching power supply that obtains a predetermined DC voltage output by accumulating energy in a magnetic element by turning on / off a switching element connected to an input power supply, and is synchronized with an internal clock or an external clock. The present invention relates to a switching power supply control circuit system capable of easily configuring a clock input function when operated in the same manner.

  FIG. 6 is a block diagram showing a general configuration of a conventionally known switching power supply. There are various switching power supplies such as an inverter and a converter. Here, a DC-DC converter which is an example of the switching power supply is shown as a typical example. In the DC-DC converter shown in FIG. 6, the output VOUT is fed back to the control circuit 200. The control circuit 200 compares the output VOUT with a target value, and generates and outputs a pulse signal (VCONT) based on the result.

  Here, the operation of the control circuit 200 will be briefly described. In general, the control circuit 200 detects the output VOUT of the DC-DC converter by the detection circuit 210, converts it into a signal VO that can be input to the error amplification circuit 220 at the next stage, and outputs the signal VO. The error amplification circuit 220 amplifies the difference between the signal VO and the reference voltage VREF (230) and outputs an error signal VE. The comparison circuit 250 compares the error signal VE with the output VOSC of the oscillator 240 and outputs a PWM pulse (VCONT). Here, the output waveform VOSC of the oscillator 240 includes a triangular wave, a sawtooth wave, a sine wave, a rectangular wave, and the like. Furthermore, the pulse signal (VCONT) turns on or off the output VOUT by turning on / off a semiconductor switch element represented by a MOSFET (metal-oxide-semiconductor field effect transistor) or a bipolar transistor or a mechanical switch element represented by a relay circuit. I have control.

  In the switching power supplies as described above, those that drive multiple units at the same time or those that are supposed to suppress the influence of noise on the electronic components around the switching power supply, the switching frequency of the switching power supply is fixed to a predetermined frequency. May be required to do.

  In order to fix the frequency, there is a method of mounting a function for switching in synchronization with an external clock. The clock synchronization circuit 300 in the control circuit for the switching power supply in FIG. 6 uses an internal clock when adjusting the frequency to an arbitrary value, and an external clock when switching at the frequency required by the system using the switching power supply. This is an example that operates in synchronization with CK (330).

  However, in the circuit system of FIG. 6, an oscillator 240 is generally mounted inside, and an external component (resistor ROSC in FIG. 6) 310 such as a resistor or a capacitor for arbitrarily adjusting the frequency of the internal oscillator 240 is connected. A terminal (OSC terminal in the figure) 320 and a terminal (CK terminal in FIG. 6) 340 for inputting the external clock CK (330) are required. Further, the oscillator 240 in FIG. 6 needs to have a function of selecting a clock from the outside. This increases the number of terminals of the switching power supply control circuit and complicates the oscillation circuit.

  In Patent Document 1 shown below, a state in which a plurality of switching power supplies are synchronized with an external clock is shown. However, a complicated circuit configuration and an increase in terminals due to a switching function between an internal clock and an external clock are suppressed. It is not touched to do.

JP 2004-357465 A

  In order to solve the above-described problems, an object of the present invention is to provide a clock synchronization circuit that can be synchronized with an internal clock or an external clock in a switching power supply while suppressing circuit complexity and an increase in terminals. It is what.

Clock synchronization circuit of the present invention, a hysteresis inverter having a resistor and a connection terminal, connected to one terminal of the resistor and the input terminal of said hysteresis inverter, between input terminal and the output terminal of said hysteresis inverter, A series circuit of the resistor and a switch is connected, and an input terminal of the hysteresis inverter is connected to the connection terminal, and a capacitor is connected between the connection terminal and the ground so that an output signal of the hysteresis inverter is an internal clock signal. first operation mode in which or the input the external clock signal to the connection terminal to allow selection of the second mode of operation using the output signal of the hysteresis inverter as an external clock signal for synchronization, the input of the hysteresis inverter, A terminal having an input and having a high potential threshold and a low potential threshold. Providing a palater, setting the high potential threshold lower than the high level of the external clock and higher than the high potential threshold of the hysteresis inverter, and further setting the low potential threshold higher than the low level of the external clock, The hysteresis inverter is set lower than the low potential threshold value, and the opening and closing of the switch is controlled based on the output of the comparator .

  According to the present invention, in a switching power supply, it is possible to realize a synchronization function of an internal clock or an external clock while suppressing circuit complexity and an increase in terminals.

It is a figure which shows the structural example of the clock synchronous circuit in the control circuit of the switching power supply which concerns on the 1st Embodiment of this invention. It is a figure which shows the structural example of the clock synchronous circuit in the control circuit of the switching power supply which concerns on the 2nd Embodiment of this invention. It is a figure which shows the operation | movement waveform of the circuit of FIG. FIG. 3 is a diagram illustrating a first specific configuration example of a comparator (COMP1) illustrated in FIG. 2. FIG. 3 is a diagram illustrating a second specific configuration example of the comparator (COMP1) illustrated in FIG. 2. It is a block diagram which shows the general structure of the switching power supply known conventionally.

Hereinafter, embodiments of the present invention will be described in detail.
[Embodiment 1]
FIG. 1 is a diagram illustrating a configuration example of a clock synchronization circuit in a control circuit for a switching power supply according to the first embodiment of the present invention. This synchronization circuit improves the configuration of the clock synchronization circuit 300 in the control circuit of the switching power supply shown in FIG. 6, and the description is omitted because the configuration is the same as the control circuit shown in FIG. 6 except for the synchronization circuit. To do. FIG. 1A shows an example of a first operation mode in which an internal clock is used for a clock synchronization circuit in a control circuit for a switching power supply. FIG. 1B shows an example of a clock synchronization circuit in a control circuit for a switching power supply. This is an example of the second operation mode using an external clock.

  When an internal clock is used for the clock synchronization circuit 30 in the control circuit for the switching power supply shown in FIG. 1A, the hysteresis inverter (INV1) 33, the resistor (R1) 34 and the external capacitor (COSC) in FIG. ) 31 constitutes an oscillator that generates an internal clock, and the oscillation frequency of its output signal (VOSC) 35 is arbitrarily adjusted by the value of the external capacitor (COSC) 31. The external capacitor (COSC) 31 is connected to the input terminal of the hysteresis inverter (INV1) 33 via the connection terminal (input terminal) 32. When the control circuit of the switching power supply is realized by a semiconductor integrated circuit, the connection terminal 32 becomes an external connection terminal of the semiconductor chip on which the semiconductor integrated circuit is integrated, and the capacitor (COSC) 31 is provided outside the semiconductor chip and connected externally. It is connected to the hysteresis inverter (INV1) 33 inside the semiconductor chip via the terminal 32.

  When an external clock is used for the clock synchronization circuit 40 in the switching power supply control circuit shown in FIG. 1B, the external capacitor (COSC) 31 shown in FIG. By applying an external clock (CK) 36 to the input of (INV1) 33, a signal (VOSC) 35 synchronized with the external clock (CK) 36 is obtained.

With the above configuration, it is possible to realize a clock synchronization circuit capable of selecting the first operation mode using the internal clock or the second operation mode using the external clock, and switching between the internal clock and the external clock. Complicating the circuit configuration and increasing the number of terminals due to mounting functions can be suppressed.
[Embodiment 2]
FIG. 2 is a diagram illustrating a configuration example of the clock synchronization circuit in the control circuit for the switching power supply according to the second embodiment of the present invention. In the first embodiment shown in FIG. 1, when the external clock (CK) 36 is used, the external clock (CK) 36 needs a current capacity capable of driving the resistor (R1) 34. That is, since the resistor (R1) 34 is connected between the input and output of the hysteresis inverter (INV1) 33, the voltage | VOSC-VI | is applied to both ends, and a current corresponding thereto flows. Whether the current is sourced or sinked, it must be supplied externally. However, the configuration of FIG. 2 is configured so that such a problem does not occur. That is, in FIG. 2, a comparator (COMP1) 51 and a switch (S1) 55 are added, and the comparator (COMP1) 51 is switched when the input signal (VI) is higher than the reference power supply VH52 and lower than the reference power supply VL53. A signal for turning off the switch (S1) 55 is outputted, and a signal for turning on the switch (S1) 55 is outputted when the input signal (VI) is higher than the reference power supply VL53 and lower than the reference power supply VH52.

  FIG. 3 is a diagram showing operation waveforms of the circuit of FIG. In FIG. 3, VHYS indicates the hysteresis width of the hysteresis inverter (INV1) 51. Here, switch (S1) 55 is on when output VCOM (54) of comparator (COMP1) 51 is high (HIGH), and off when output VCOM (54) of comparator (COMP1) 51 is low (LOW). However, this logic may be inverted. In FIG. 3, when (a) the internal clock signal is used, since the input signal (VI) is always higher than the reference power supply VL53 and lower than the reference power supply VH52, the switch (S1) 55 is always turned on. A clock is generated inside the circuit. On the other hand, when (b) the external clock signal is used, the low level of the external clock signal 36 is lower than the reference power supply VL53, and the high level of the external clock signal 36 is higher than the reference power supply VH52. By setting the clock amplitude so that it becomes and setting the reference power supply VH52 and reference power supply VL53 so that the switch (S1) 55 is always off (that is, the output VCOM (54) is low) To be. As a result, the external clock 36 does not need to drive the resistor (R1) 34, and an external clock signal having a high impedance (low current drive capability) can be used.

  FIG. 4 is a diagram showing a first specific configuration example of the comparator (COMP1) shown in FIG. In the first specific configuration example shown in FIG. 4, the first comparator 512 that receives the input signal (VI) 511 at the (+) end of the comparator input and the input signal (VI) 511 of the comparator input (− ) And a logical sum circuit (OR circuit) 514 that receives the outputs of the first comparator 512 and the second comparator 513, and outputs a comparator (COMP1) from the output terminal of the logical sum circuit 514. ) Output (VCOM) 517 is obtained. In the above, the reference power source VH (515) is connected to the (−) terminal of the comparator input of the first comparator 512, and the reference power source VL is connected to the (+) terminal of the comparator input of the second comparator 513. (516) is connected. In the configuration shown in FIG. 4, when the reference power supply VL (516) <input signal (VI) (511) <reference power supply VH (515), the output (VCOM) 517 of the comparator (COMP1) is at the low level (L), Otherwise, it is high level (H).

  FIG. 5 is a diagram illustrating a second specific configuration example of the comparator (COMP1) illustrated in FIG. In the second specific configuration example shown in FIG. 5, the third comparator 522 that receives the input signal (VI) 521 at the (−) end of the comparator input, and the input signal (VI) 521 of the comparator input (+ ) And a logical comparator circuit (AND circuit) 524 that receives the outputs of the third comparator 522 and the fourth comparator 523, and receives a comparator (COMP1) from the output terminal of the logical product circuit 524. ) Output (VCOM) 527. In the above description, the reference power source VH (525) is connected to the (+) terminal of the comparator input of the third comparator 522, and the reference power source VL is connected to the (−) terminal of the comparator input of the fourth comparator 523. (526) is connected. In the configuration shown in FIG. 5, when the reference power supply VL (526) <input signal (VI) (521) <reference power supply VH (525), the output (VCOM) 527 of the comparator (COMP1) is at the high level (H). Otherwise, it is low level (L).

30 clock synchronization circuit (using internal clock)
31 External capacitor (COSC)
32 Connection terminal (input terminal)
33 Hysteresis inverter
34 Resistance (R1)
35 Output signal of clock synchronization circuit (VOSC)
36 External clock (CK)
40 clock synchronization circuit (using external clock)
50 clock synchronization circuit (using external clock)
51 Comparator (COMP1)
52 Reference power supply 1 (VH)
53 Reference power supply 2 (VL)
54 Comparator output (VCOM)
55 Switch (S1)
511 Input signal (VI)
512 First comparator
513 Second comparator
514 OR circuit (OR circuit)
515 Reference power supply 1 (VH)
516 Reference power supply 2 (VL)
517 VCOM (comparator output)
521 Input signal (VI)
522 Third comparator
523 Fourth comparator
524 AND circuit
525 Reference power supply 1 (VH)
526 Reference power supply 2 (VL)
527 VCOM (comparator output)

Claims (3)

Hysteresis inverter having a resistor and a connection terminal, connected to one terminal of the input terminal of said hysteresis inverter resistance, between the input terminal and the output terminal of said hysteresis inverter, the series circuit of the resistor and the switch And connecting the input terminal of the hysteresis inverter and the connection terminal,
A first operation mode in which a capacitor is connected between the connection terminal and the ground and the output signal of the hysteresis inverter is an internal clock signal, or an external clock signal is input to the connection terminal and the output signal of the hysteresis inverter is The second operation mode used as an external clock synchronization signal can be selected ,
An input terminal of the hysteresis inverter is used as an input, a comparator having a high potential threshold value and a low potential threshold value is provided, and the high potential threshold value is lower than the high level of the external clock and is higher than the high potential threshold value of the hysteresis inverter. Setting the low potential threshold higher than the low level of the external clock and lower than the low potential threshold of the hysteresis inverter, and controlling opening and closing of the switch based on the output of the comparator;
A clock synchronization circuit characterized by the above. The comparator outputs a signal for turning off the switch when the signal applied to the input terminal is higher than the high potential threshold and lower than the low potential threshold, When the signal applied to the input terminal is higher than the low potential threshold and lower than the high potential threshold, a signal for turning on the switch is output, Operating in the second mode,
The clock synchronization circuit according to claim 1, wherein: The clock synchronization circuit according to claim 1 or 2 is provided in a control circuit for a switching power supply that controls a switching power supply that obtains a predetermined DC voltage output by turning on / off a switching element connected to the input power supply. A control circuit for a switching power supply .

Images