JP5394910B2 - Mask pattern drawing method and apparatus - Google Patents

Description

  The present invention relates to a mask pattern drawing method and apparatus for drawing a pattern on a mask with an electron beam (electron beam), and more particularly to a lithography technique for manufacturing a semiconductor device, and a mask pattern drawing method for drawing a pattern on a mask, and Relates to the device.

  In the manufacture of semiconductor devices, in order to form an LSI pattern on a wafer, there is a method in which a mask on which an LSI pattern is formed is prepared, and the pattern formed on the mask is collectively transferred to a resist on the wafer by an optical exposure apparatus. Widely adopted. This mask needs to have an LSI pattern formed accurately. In order to form this LSI pattern, a variable shaped beam type electron beam drawing apparatus in which the beam size and shape are varied by a shaping aperture is used.

  FIG. 5 is a diagram showing a schematic example of a variable shaped electron beam writing apparatus. In the figure, 1 is a CAD system that creates CAD data (original data), 2 is a data conversion computer that converts CAD data into drawing data, and 3 is a control device that controls the variable shaping type electron beam drawing apparatus body 4. .

  The variable shaping type electron beam drawing apparatus body 4 includes an electron gun 5, a blanking electrode 6, an irradiation lens 7, a first shaping aperture plate 8, a shaping deflector 9, a second shaping aperture plate 10, an objective lens 11, and a position deflection. It comprises a vessel 12 and a stage 13. Reference numeral 14 denotes a mask as a drawing material placed on the stage 13.

  The data conversion computer 2 of the variable shaping type electron beam drawing apparatus configured as described above reads CAD data from the CAD system 1, converts the data into drawing data, and sends it to the control device 3. When the control device 3 sends a command to each power source based on the drawing data sent, each power source (not shown) generates a control signal, and the electron gun 5, blanking electrode 6, and shaping deflector 9. To the objective lens 11 and the position deflector 12.

  Then, the electron beam EB emitted from the electron gun 5 passes through the blanking electrode 6, the first shaping aperture plate 8, the shaping deflector 9, the second shaping aperture plate 10, the objective lens 11, and the position deflector 12, and the stage 13. The upper mask 14 is irradiated. A square opening is formed in the first shaped opening plate 8 to form a rectangular beam. When this passes through the opening of the second shaped aperture plate 10, it becomes a small square beam size, and a shot (one exposure operation) is repeated with this small size electron beam to form one line image pattern on the resist on the mask 14. Form. After the drawing, development or the like is performed to etch the light shielding film on the mask surface on which the resist pattern is formed, thereby creating a light exposure mask.

  Using the mask thus created, the pattern of the mask is transferred onto the resist on the wafer by an optical exposure apparatus (for example, a stepper). The semiconductor device is manufactured by repeating development of the mask, transfer, and the like. By the way, in the element region layer of the LSI pattern of the finished semiconductor device, the region overlapping with the gate layer greatly affects the electrical characteristics of the semiconductor device. Therefore, it is important to ensure the dimensional accuracy as compared with other regions.

  FIG. 6A shows a layout in which a strip-like gate layer 21 is overlapped in the vicinity of the corner portion of the L-shaped element region layer 20. 20 is an element region layer pattern on the mask, and 21 is a gate layer pattern on the mask. FIG. 6B shows the positions of the element region layer 22 and the gate layer 23 actually formed by the masks having these layouts. Here, the gate layer refers to a gate layer of an FET (Field Effect Transistor). The broken line in the figure shows the finished state 22 of the shape of the element region layer pattern 20, and the solid line shows the target shape 24 of the element region layer pattern 20.

  When the gate layer 23 is close to the corner portion of the element region layer 24 as shown in FIG. 6B, the in-corner portion C-1 of the finished element region layer 22 is rounded and thickened. The shape of the end portion of the element region layer 22 that overlaps the region (the portion that strongly influences the electrical characteristics of the semiconductor device) is formed to be larger than the target dimension, so that the planned performance cannot be obtained, and the electrical characteristics of the semiconductor device Will deteriorate.

  In view of this, generally, a method in which a concave portion (referred to as an inner serif) having a size not resolving by lithography is provided in a portion corresponding to a corner portion of the pattern on the mask is used for mask pattern formation. This is called OPC (Optical Proximity Correction), and is a technique for adding a pattern much smaller than the design pattern to the mask pattern to bring the pattern shape of the wafer after transfer closer to the design pattern shape.

  A mask using this method is shown in FIG. FIG. 7 is a diagram showing a state in which inner lines are put in the corners of the L-shaped element region layer. As shown in the drawing, concave OPCa (inner serif) is put in the in-corner portion C of the L-shaped element region layer pattern 20a of the mask. Then, as shown in FIG. 7B, the finished resist pattern when exposed to light with an optical exposure apparatus (for example, a stepper) using such a mask can suppress the thickness of the in-corner portion (C-2). Therefore, since the dimension of the shape of the end portion of the element region 22a where the gate layer 23 overlaps can be a value close to the target dimension, the expected electrical characteristics of the semiconductor device can be obtained.

  A conventional apparatus of this type is an L-shaped mask pattern, and a concave portion 7b having a size not to be resolved by lithography is mainly formed in a portion corresponding to a corner portion where the angle of the active region 1 on the mask is 270 °. A pattern formed continuously with the pattern 7a is known (see, for example, Patent Document 1).

Japanese Patent No. 3419603 (paragraphs 0018 to 0020, FIG. 1)

  However, even if exposure is performed with an optical exposure apparatus using such a mask with OPC, the dimensional accuracy of the pattern on the element region layer side overlapping the gate layer of the finished LSI pattern may not be sufficient.

  Now, as described above, the pattern on the mask is formed by patterning with a variable shaping type electron beam drawing apparatus based on drawing data consisting of a collection of a large number of rectangular figures obtained by dividing complicated design data into rectangles. Since the pattern formed on the mask is drawn with a combination of shot sizes having different sizes, each shot is accompanied by variations in position and width due to fluctuations in the electron beam. In particular, when the shot size is large, this variation is reflected in the dimensional accuracy of the pattern on the mask.

  That is, even if the shape and dimensions of the inner serif of the pattern on the mask are optimized to effectively suppress the corner round (thickness of the in-corner portion), the shape, size and position of the inner serif are shifted. As a result, the shape / dimension of the corner round changes, and as a result, the dimension of the end portion of the element region layer that overlaps the gate layer changes.

  For example, when the inner serif portion OPCb at the corner of the pattern 20b on the mask is formed larger than the target as shown in FIG. 8A, the element region layer 22a finished as shown in FIG. 8B. (C-3), the dimension of the end portion of the element region layer that overlaps the gate layer that strongly affects the electrical characteristics of the semiconductor device is made smaller than the target dimension.

  Also, as shown in FIG. 9A, when the inner serif portion OPCc at the corner of the pattern 20c on the mask is formed smaller than the target, the resist pattern finished as shown in FIG. The in-corner portion of the element region layer 22b is thickened (C-4), and the dimension of the end portion of the element region layer that overlaps the gate layer that strongly affects the electrical characteristics of the semiconductor device is completed.

  Also, as shown in FIG. 10 (a), even if the inner serif portion OPCd at the corner of the pattern 20d on the mask is formed with the optimized dimensions, from the in-corner of the element region layer to the region overlapping the gate layer. If the shape of the end of the element region layer is not formed according to the target size when the shot is shifted at the time of drawing, the dimension of the end overlapping the gate layer of the finished element region layer is as shown in FIG. It becomes longer or shorter.

  As described above, if an element region layer mask having a dimensional variation in the shape of the inner serif, the distance from the in-corner to the region overlapping the gate layer, and the size of the end overlapping the gate layer is used in the manufacturing process, A semiconductor device having deteriorated characteristics is manufactured.

  The present invention has been made in view of such problems, and an object thereof is to provide a mask pattern drawing method and apparatus for accurately drawing a pattern on a mask.

In order to solve the above-described problems, the present invention has the following configuration.
(1) The invention described in claim 1 is a semiconductor manufacturing method of a semiconductor manufacturing apparatus including a step of forming a pattern having a corner portion by lithography, wherein the portion corresponding to the corner portion of the pattern on the mask is formed by lithography. In a method of performing exposure using a pattern laid out so as to have an inner serif of a size that does not resolve, when creating a mask pattern composed of an element region layer and a gate layer, an element is formed from the gate layer pattern. A distance D to the in-corner of the region layer pattern is calculated, and when the distance D is shorter than a certain distance, the region F1 from the in-corner of the element region layer pattern to the element region layer overlapping with the gate layer pattern, When the other region is divided from the region F2 and the distance D is longer than a certain distance, the gate layer pattern Region an element region layer pattern overlapping an F1, it other region was divided regions F2, and performing pattern drawn on a mask by changing the maximum shot size shot and the region F1 and the region F2.

  (2) In the invention according to claim 2, the element region layer is L-shaped, the gate layer is band-shaped, the band-shaped gate layer overlaps the L-shaped element region layer, and the gate is formed from the in-corner of the element region layer. The distance D to the layer is calculated and used as a parameter.

  (3) The invention according to claim 3 is a semiconductor manufacturing method of a semiconductor manufacturing apparatus including a step of forming a pattern by lithography, and when a mask pattern composed of an element region layer and a gate layer is created, The distance D from the gate layer pattern to the out corner of the element region layer pattern is calculated, and when the distance D is shorter than a certain distance, the element region layer overlapping the gate layer pattern from the out corner of the element region layer pattern When the distance D is longer than a certain distance, the element region layer pattern overlapping the gate layer pattern is the region F1, and the other region is the region F2. And the pattern is drawn on the mask by changing the maximum shot size to be shot in the area F1 and the area F2.

  (4) In the invention according to claim 4, the element region layer has a rectangular shape, the gate layer has a band shape, the band-shaped gate layer overlaps the rectangular element region layer, and the band shape extends from the out corner of the element region layer. The distance D to the gate layer is calculated and used as a parameter.

  (5) The invention according to claim 5 is characterized in that the area F1 is drawn with a shot having a maximum shot size of 200 nm, and the area F2 is drawn with a shot having a maximum shot size of 2 μm. 5. The mask pattern drawing method according to any one of 1 to 4.

(6) The invention according to claim 6 is characterized in that the pattern drawing is performed directly on a wafer instead of a mask.
(7) The invention according to claim 7 is characterized in that the pattern drawing is performed not on the mask but on the nanoimprint mask.

  (8) The invention according to claim 8 is a semiconductor manufacturing apparatus including a step of forming a pattern having a corner portion by lithography, and does not resolve the portion corresponding to the corner portion of the pattern on the mask by lithography. In an exposure apparatus using a pattern laid out so as to have an inner serif of the size, when creating a mask pattern composed of an element region layer and a gate layer, an element region layer pattern is converted from the gate layer pattern. Means for calculating the distance D to the in-corner, and if the distance D is shorter than a certain distance, the region F1 extends from the in-corner of the element region layer pattern to the element region layer overlapping the gate layer pattern, and the others Means for dividing the area of the area F2 and the gate layer pattern when the distance D is longer than a certain distance. Means for dividing the element region layer pattern overlapping with the region F1, and the other region with the region F2, and means for drawing a pattern on the mask by changing the maximum shot size shot in the region F1 and the region F2. It is characterized by.

  (9) According to the ninth aspect of the present invention, in the semiconductor manufacturing apparatus including a step of forming a pattern by lithography, when creating a mask pattern constituted by an element region layer and a gate layer, the element region is converted from the gate layer pattern. Means for calculating the distance D to the outer corner of the layer pattern, and when the distance D is shorter than a certain distance, the region F1 extends from the outer corner of the element region layer pattern to the element region layer overlapping the gate layer pattern. The means for dividing the other region from the region F2 and, when the distance D is longer than a certain distance, the element region layer pattern overlapping the gate layer pattern is divided into the region F1, and the other region is divided into the region F2. And means for drawing a pattern on a mask by changing the maximum shot size shot in the area F1 and the area F2. Characterized in that it.

The present invention has the following effects.
(1) According to the first aspect of the present invention, when the L-shaped pattern and the gate pattern are drawn, the area F1 for drawing the pattern drawing area at a high resolution and the area F2 for drawing at a normal resolution are obtained. Since beam writing is performed with different dimensional accuracy for each region, high-resolution writing can be performed in the region F1, normal-resolution writing can be performed in the region F2, and the accuracy of the semiconductor pattern can be increased at high speed. Beam drawing can be performed.

  (2) According to the invention of claim 2, the distance D from the in-corner of the element region layer to the gate layer can be calculated and used as a parameter, and the region F1 and the region F2 are drawn with the different dimensional accuracy. be able to.

  (3) According to the invention described in claim 3, in the case of drawing a rectangular pattern and a gate pattern, the area F1 for drawing the pattern drawing area with high resolution and the area F2 for drawing with normal resolution are obtained. Since beam writing is performed with different dimensional accuracy for each region, high-resolution drawing can be performed in the region F1, normal-resolution drawing can be performed in the region F2, beam accuracy can be increased, and beam drawing can be performed at high speed. Can be performed.

  (4) According to the invention of claim 4, the distance D from the out corner of the element region layer to the belt-like gate layer can be calculated and used as a parameter, and the regions F1 and F2 can be defined with the different dimensional accuracy. Can be drawn.

  (5) According to the fifth aspect of the invention, the shot size is set at 200 nm for high resolution drawing, and the shot size is set at 2 μm for normal resolution drawing. Can be done.

(6) According to the invention described in claim 6, it is possible to directly draw on the wafer by using the drawing method according to the present invention, and the wafer can be manufactured with efficiency by skipping the steps.
(7) According to the invention described in claim 7, the pattern drawing according to the present invention can be performed on the nanoimprint mask.

  (8) According to the invention described in claim 8, when the L-shaped element region pattern and the gate layer pattern are drawn, the drawing region is drawn at a high resolution region F1, and the normal resolution is drawn at a region F2. Since the beam is drawn with different dimensional accuracy for each region, high-resolution drawing can be performed in the region F1, normal-resolution drawing can be performed in the region F2, the semiconductor pattern accuracy can be increased, and Beam drawing can be performed at high speed.

  (9) According to the invention of claim 9, when drawing the rectangular element region pattern and the gate layer pattern, the region F1 for drawing the pattern drawing region at a high resolution and the region F2 for drawing at a normal resolution are provided. Since the beam is drawn with different dimensional accuracy for each region, high-resolution drawing can be performed in the region F1, normal-resolution drawing can be performed in the region F2, and the semiconductor pattern accuracy is increased and high speed is achieved. Beam drawing can be performed.

It is a block diagram which shows one Example of this invention. It is process explanatory drawing of this invention. It is process explanatory drawing of this invention. It is process explanatory drawing of this invention. It is a figure which shows one schematic example of a variable shaping type | mold electron beam drawing apparatus. It is the figure which piled up the strip | belt-shaped gate layer in the place close | similar to the corner part of an L-shaped element region layer. It is a figure which shows the state which put the inner serif in the corner part of an L-shaped element area | region layer. It is a figure which shows the state which put the inner serif in the corner part of an L-shaped element area | region layer. It is a figure which shows the state which put the inner serif in the corner part of an L-shaped element area | region layer. It is a figure which shows the state which put the inner serif in the corner part of an L-shaped element area | region layer.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[Example 1]
FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, the same components as those in FIG. 5 are denoted by the same reference numerals. In the figure, 31 is a memory for storing element region layer original data and gate layer original data sent from the CAD system 1, 32 is for reading the element region layer original data from the memory 31, and An extraction unit 33 for extracting a corner portion of the element region layer reads the element region layer original data from the extraction unit 32 and the gate layer original data from the memory 31 and reads the gate layer ( It is a distance calculation part which calculates the distance D to (original data).

  34 is a determination unit that compares the distance D calculated by the distance calculation unit 33 with a predetermined distance D0 that is set in advance. 35 reads element region layer original data from the determination unit 34, and An OPC addition unit 36 adds convex OPC to the portion and adds concave OPC to the corner portion of the element region layer. The determination result of the determination unit 34 and the gate layer original data read from the memory 31 Based on this, the element area layer OPC-added data OPC added by the OPC adding unit 35 is classified into a region F1 that requires high dimensional accuracy and a region F2 that does not require dimensional accuracy.

  Reference numeral 37 denotes a pattern dividing unit that divides the pattern into drawable figures according to the shapes of the element region layer patterns with OPC classified into the regions F1 and F2. A data conversion computer 2 includes a memory 31, an extraction unit 32, a distance calculation unit 33, a determination unit 34, an OPC addition unit 35, a classification division unit 36, and a pattern division unit 37.

  In the data conversion computer 2 configured as described above, the element region layer original data and the gate layer original data in which the gate layer is laid out on the element region layer close to the corner portion of the element region layer from the CAD system 1 are the data conversion computer 2. The memory 31 once stores the element region layer original data and the gate layer original data.

  Next, the extraction unit 32 reads the element region layer original data from the memory 31 to extract the corner portion C of the element region layer 20 ′ shown in FIG. 2A, and the result is the distance calculation unit 33. Send to. Next, the distance calculation unit 33 reads the gate layer original data from the memory 31, and from the side of the corner portion C of the element region layer 20 ′ shown in FIG. 2A to the side edge of the gate layer 21 ′. The shortest distance D is calculated.

Next, when the determination unit 34 determines that the calculated shortest distance D is smaller than a preset setting value D ₀ , for example, 400 nm, the determination unit 34 sends the determination result to the classification unit 36. Next, the OPC addition unit 35 reads the element region layer original data from the determination unit 34 and displays the data in the corners and corners C of the L-shaped element region layer pattern 20 ′ as shown in FIG. (B) of OPC (OP1, OP2, OP3, OP4, OP5) is added to the corner portion, and the OPC (OP6) of the concave portion is added to the corner portion C.

  Next, the classification unit 36 determines the pattern region of the data after adding the element region layer OPC based on the determination result of the determination unit 34 and the gate layer original data read from the memory 31 as the region F1 in which high dimensional accuracy is required. Set to the other region F2.

When the determination unit 34 determines that the distance D from the side of the corner portion C of the element region layer pattern 1 to the end of the gate layer 21 ′ is smaller than the set value D ₀ 400 nm, the classification unit 36 determines that the determination unit 34 On the basis of the determination result of the above, in the pattern with the element region layer OPC, as shown in FIG. 2C, the regions indicated by the oblique lines at both ends of the element region layer pattern 20 ′ overlapping the gate layer 21 ′ and the corners of the element region layer A region indicated by hatching around the inner serif portion OPC6 of the portion C is set as a region F1, and the other region is set as a region F2.

  Then, the pattern dividing unit 37 divides the region F1 requiring high dimensional accuracy into a small shot SS, for example, as shown in FIG. 2D based on the pattern of the data with the element region layer OPC of the classification unit 36. A figure with a maximum shot size of 200 nm is divided, and a pattern F with a large shot LS, for example, a maximum shot size of 2 μm, is performed in a region F2 where high dimensional accuracy is not required.

  As described above, the data conversion computer 2 that has created the drawing data in which the pattern region of the data with the element region layer OPC is divided into the region F1 and the region F2 sends the drawing data to the control device 3. When the control device 3 sends a command to each power supply (not shown) based on the drawing data sent, each power supply (not shown) generates a control signal, and the control signal is sent to the blanking electrode. 6. Send to shaping deflector 9, objective lens 11 and position deflector 12.

  Then, the rectangular beam formed by the electron beam EB emitted from the electron gun 56 passing through the blanking electrode 6, the first shaping aperture plate 8, the shaping deflector 9, and the second shaping aperture plate 10 becomes a mask on the stage 13. 14 are sequentially shot.

On the other hand, when the determination unit 34 determines that the distance D from the side of the corner portion C of the element region layer pattern 20 ′ to the end of the gate layer 21 ′ is greater than the set value D ₀ 400 nm, the classification unit 36 Based on the determination result of the determination unit 34, the region indicated by the oblique lines at both ends of the element region layer 20 ′ overlapping the gate layer 21 ′ as shown in FIG. The other area is set as area F2 in F1.

  Then, the pattern dividing unit 37 generates F1 which requires high dimensional accuracy as shown in FIG. 3D based on the region division of the element region layer pattern 20 ′ of the classification unit 36 as a small shot SS, for example, the maximum A figure division with a shot size of 200 nm is performed, and a large shot LS, for example, a pattern division with a maximum shot size of 2 μm, is performed on the region F2 where high dimensional accuracy is not required.

  The data conversion computer 2 that has created the drawing data in which the L-shaped pattern with the element region layer OPC is divided into the regions F 1 and F 2 sends the drawing data to the control device 3. Based on the drawing data, the variable shaping type electron beam drawing apparatus forms rectangular beams having different sizes, and sequentially shots the rectangular beams onto the resist on the element region layer mask.

  The set value D0 from the in-corner to the gate layer pattern of the element region layer pattern in the above embodiment is 400 nm. However, optimization and change are applied to the applied light exposure process (exposure, development, etc.). Is also possible.

  The starting point of the measurement of the distance D is the in-corner of the element region layer of the original (before the proximity effect correction process) before adding the inner serif. The end point is the edge of the gate layer that is the closest to the start corner (the edge closer to the in corner). The area of the inner serif that is the area 1 is set to be within 400 nm from the inner corner (in the case of a quadruple mask, it is within 1/4 of 100 nm on the wafer).

  According to the first embodiment, when an L-shaped pattern and a gate pattern are drawn, a pattern drawing area is drawn with a high resolution area F1 and an area F2 with a normal resolution is drawn. Since beam drawing is performed with high accuracy, high resolution drawing can be performed in the region F1, and normal resolution drawing can be performed in the region F2, and the beam drawing can be performed at high speed while increasing the accuracy of the semiconductor pattern. it can.

Further, the distance D from the in-corner of the element region layer to the gate layer can be calculated and used as a parameter, and the region F1 and the region F2 can be drawn with the different dimensional accuracy.
Further, since the shot size is set at 200 nm during high resolution drawing and the shot size is set at 2 μm during normal resolution drawing, efficient drawing can be performed with high accuracy.
[Example 2]
In Example 1, the band-shaped gate layer (original pattern) overlaps the L-shaped element region layer, and the distance D from the in-corner of the element region layer to the gate layer is divided as a parameter. In the rectangular element region layer, the distance D1 from the out corner of the element region layer to the band-shaped gate layer can be divided as a parameter.

  When the data conversion computer 2 reads element region layer original pattern data in which the belt-shaped gate layer (original pattern) overlaps the rectangular element region layer, the memory 31 temporarily stores the element region layer original data and the gate layer original data. The extraction unit 32 of the data conversion computer 2 reads the element region layer original data from the memory 31, extracts the out corner AC of the element region layer 20 '' shown in FIG. 4A, and calculates the result as a distance. Send to part 33.

  Next, the distance calculation unit 33 reads the gate layer original data from the memory 31 and, as shown in FIG. 4A, the edge of the gate layer 21 ′ from the side of the out corner portion AC of the element region layer 20 ″. The shortest distance D1 to the part is calculated. Next, when determining that the calculated shortest distance D1 is smaller than a preset setting value D0, for example, 400 nm, the determination unit 34 sends the result to the classification unit 36.

  Next, the OPC adding portion 35 has convex portions at the upper right and lower right corners of the rectangular element region layer 20 '' as shown in FIG. OPC (OP3 ′, OP4 ′) is added. Next, the classification unit 36 determines the pattern region of the data after adding the element region layer OPC based on the determination result of the determination unit 34 and the gate layer original data read from the memory 31 as the region F1 in which high dimensional accuracy is required. , Other region F2 is set.

Next, when the determination unit 34 determines that the distance D1 from the side of the out corner portion AC of the element region layer 20 ″ to the end of the gate layer 21 ′ is smaller than the set value D ₀ 400 nm, the classification unit 36 The element from the region indicated by the oblique lines at both ends of the element region layer 20 ″ overlapping the gate layer 21 ′ as shown in FIG. The area up to the OPC area at the upper right and lower right corners of the area layer is F1, and the other area is the area F2.

On the other hand, when the determination unit 34 determines that the distance D1 from the side of the out corner portion AC of the element region layer pattern 20 ″ to the end of the gate layer 21 ′ is larger than the set value D ₀ 400 nm, the classification unit 36 Based on the determination result of the determination unit 34, the element region layer pattern region is indicated by the hatched region at both ends of the element region layer 20 ″ overlapping the gate layer 21 ′ as shown in FIG. 4B. The other area is set as area F2.

  According to the second embodiment, when drawing a rectangular pattern and a gate pattern, a pattern drawing area is drawn with a high resolution area F1 and a normal resolution drawing area F2 with different dimensional accuracy for each area. Since beam drawing is performed, high-resolution drawing can be performed in the region F1, normal-resolution drawing can be performed in the region F2, and the accuracy of the semiconductor pattern can be increased and beam drawing can be performed at high speed.

Further, the distance D from the out corner of the element region layer to the belt-like gate layer can be calculated as a parameter, and the region F1 and the region F2 can be drawn with the different dimensional accuracy.
[Example 3]
In the first and second embodiments, the present invention is applied to the mask pattern. However, the present invention may be applied to the case where patterning on the wafer at the time of semiconductor device creation is performed by EB direct writing.

According to the third embodiment, it is possible to directly draw on the wafer by using the drawing method according to the present invention, and it is possible to manufacture the wafer with efficiency by skipping the process.
[Example 4]
In the first and second embodiments, the present invention is applied to the mask pattern. However, the present invention may be applied to the case where the nanoimprint mask (mold) is patterned by EB direct writing.

According to the fourth embodiment, the pattern drawing according to the present invention can be performed on the nanoimprint mask.
[Example 5]
In the first and third embodiments, the areas are classified into the two areas F1 and F2. However, the area may be divided into three or more areas and drawn by changing the maximum shot size.

  According to the present invention described above, in the fabrication of the light exposure mask for the element region layer pattern, the distance D from the corner portion of the element region layer pattern to the gate layer pattern is used as a parameter, and high dimensional accuracy is obtained based on this parameter. By dividing into the required region F1 and the other region F2, the pattern dimension accuracy when drawing the light exposure mask of the element region layer pattern in the variable shaping type electron beam drawing apparatus can be improved.

DESCRIPTION OF SYMBOLS 1 CAD system 2 Data conversion computer 3 Control apparatus 31 Memory 32 Extraction part 33 Distance calculation part 34 Determination part 35 OPC addition part 36 Classification part 37 Pattern division part

Claims (9)

A semiconductor manufacturing method of a semiconductor manufacturing apparatus including a step of forming a pattern having a corner portion by lithography, wherein an inner serif having a size not to be resolved by lithography is applied to a portion corresponding to the corner portion of the pattern on the mask. In a method of exposing using a pattern laid out to have,
When creating a mask pattern composed of an element region layer and a gate layer, the distance D from the gate layer pattern to the in corner of the element region layer pattern is calculated,
If the distance D is shorter than a certain distance, the area from the in corner of the element region layer pattern to the element region layer overlapping the gate layer pattern is divided into the region F1, and the other region is divided into the region F2.
When the distance D is longer than a certain distance, the element region layer pattern overlapping the gate layer pattern is divided into the region F1, and the other region is divided into the region F2.
The pattern is drawn on the mask by changing the maximum shot size shot in the area F1 and the area F2.
A mask pattern drawing method characterized by that.   The element region layer is L-shaped, the gate layer is band-shaped, the band-shaped gate layer overlaps the L-shaped element region layer, and a parameter D is calculated by calculating a distance D from the in-corner of the element region layer to the gate layer. The mask pattern drawing method according to claim 1, wherein: In a semiconductor manufacturing method of a semiconductor manufacturing apparatus including a step of forming a pattern by lithography,
When creating a mask pattern composed of an element region layer and a gate layer, the distance D from the gate layer pattern to the out corner of the element region layer pattern is calculated,
When the distance D is shorter than a certain distance, the region F1 is divided from the out corner of the device region layer pattern to the device region layer overlapping the gate layer pattern, and the other region is divided into the region F2.
When the distance D is longer than a certain distance, the element region layer pattern overlapping the gate layer pattern is divided into the region F1, and the other region is divided into the region F2.
The pattern is drawn on the mask by changing the maximum shot size shot in the area F1 and the area F2.
A mask pattern drawing method characterized by that.   The element region layer has a rectangular shape, the gate layer has a band shape, the band-shaped gate layer overlaps the rectangular element region layer, and a parameter D is calculated by calculating a distance D from the out corner of the element region layer to the band-shaped gate layer. The mask pattern drawing method according to claim 3, wherein:   5. The region F1 is drawn with a shot having a maximum shot size of 200 nm, and the region F2 is drawn with a shot having a maximum shot size of 2 [mu] m. Mask pattern drawing method.   3. The mask pattern drawing method according to claim 1, wherein the pattern drawing is drawn directly on a wafer instead of a mask.   3. The mask pattern drawing method according to claim 1, wherein the pattern drawing is performed not on a mask but on a nanoimprint mask. A semiconductor manufacturing apparatus including a step of forming a pattern having a corner portion by lithography, wherein a portion corresponding to the corner portion of the pattern on the mask has an inner serif of a size that does not resolve by lithography. In the exposure apparatus using the patterned pattern,
Means for calculating a distance D from the gate layer pattern to the in-corner of the element region layer pattern when creating a mask pattern composed of the element region layer and the gate layer;
When the distance D is shorter than a certain distance, means for dividing the element region layer pattern from the in corner to the element region layer overlapping the gate layer pattern with the region F1, and the other region with the region F2,
When the distance D is longer than a certain distance, the element region layer pattern overlapping the gate layer pattern is divided into the region F1, and the other region is divided into the region F2,
Means for pattern drawing on a mask by changing the maximum shot size to be shot in the region F1 and the region F2,
A mask pattern drawing apparatus comprising: In a semiconductor manufacturing apparatus including a step of forming a pattern by lithography,
Means for calculating a distance D from the gate layer pattern to the out corner of the element region layer pattern when creating a mask pattern composed of the element region layer and the gate layer;
When the distance D is shorter than a certain distance, means for dividing the area F1 from the out corner of the element region layer pattern to the element region layer overlapping the gate layer pattern, and a region F2 other than that,
When the distance D is longer than a certain distance, the element region layer pattern overlapping the gate layer pattern is divided into the region F1, and the other region is divided into the region F2,
Means for pattern drawing on a mask by changing the maximum shot size to be shot in the region F1 and the region F2,
A mask pattern drawing apparatus comprising:

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