CN115903369A - Method for optimizing virtual pattern before OPC and manufacturing method of mask - Google Patents
Method for optimizing virtual pattern before OPC and manufacturing method of mask Download PDFInfo
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- CN115903369A CN115903369A CN202211527515.8A CN202211527515A CN115903369A CN 115903369 A CN115903369 A CN 115903369A CN 202211527515 A CN202211527515 A CN 202211527515A CN 115903369 A CN115903369 A CN 115903369A
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Abstract
The invention provides a method for optimizing a virtual graph before OPC, which comprises the following steps: providing an original design graph of a polysilicon layer comprising a first polysilicon graph, a second polysilicon graph and a third polysilicon graph which are parallel to each other and are arranged in sequence at intervals along a preset direction; identifying an original design pattern and acquiring size information of the first, second and third polysilicon patterns; and adjusting the size of the second polysilicon pattern and the positions of the first and third polysilicon patterns based on the acquired size information of the first, second and third polysilicon patterns to obtain a corrected pattern. The invention also provides a manufacturing method of the mask, which is realized on the basis of the optimization method. According to the invention, the virtual graph is optimized before OPC and then is properly corrected after the optimized graph is obtained, so that the graph is prevented from being repaired after the OPC is executed and an unsatisfactory graph is found, the operation flexibility is improved, the risk caused by the fact that the OPCV catches the graph in a missing manner is reduced, and the product yield and the performance stability are improved.
Description
Technical Field
The invention belongs to the field of semiconductor manufacturing, and relates to a method for optimizing a virtual pattern before OPC and a method for manufacturing a mask.
Background
The photoetching technology is a vital technology in the semiconductor manufacturing technology, and can realize the transfer of a pattern from a mask plate to the surface of a silicon wafer to form a semiconductor product meeting the design requirement. With the continuous reduction of the characteristic dimension of an integrated circuit, the design dimension of a semiconductor device is more and more precise and is close to the limit of a photoetching imaging system, the diffraction effect of light becomes more and more obvious, so that the optical image degradation is finally generated on the design pattern, the actually formed photoetching pattern is seriously distorted relative to the pattern on a mask plate, so that the deviation problem between the photoetching pattern on a silicon wafer and the pattern on the mask plate is more and more serious, the line width uniformity can be improved through optical proximity effect correction, such as adding a sub-resolution auxiliary pattern, and a photoetching process window is enlarged, so that the consistency between the final pattern on the silicon wafer and the design pattern is ensured, and the photoetching pattern after photoetching is close to a target pattern which a user actually wants to obtain.
However, at the node of 40nm and below, as the gate size decreases, the gate line end shrinkage becomes more serious, and the amount of Correction of the pattern on the mask becomes larger, which results in the overlap of the gate patterns between adjacent patterns, and the Optical Proximity Correction (OPC) method fails. And with the complexity of layout graphs becoming higher and higher, the limitation of photoetching resolution and the defect of OPC model predictability lead OPC not to take all hot spots into account, and the method is difficult to meet the requirements of ever-changing layouts.
Since the line width of the polysilicon layer is the smallest, it is most challenging in the process, and the conventional method is to define the directionality of Fan Bantu in the design rule, and improve the process conditions by increasing the resolution of the light source selecting dipole light source during photolithography, please refer to fig. 1, which shows the polysilicon layer pattern 11 obtained after OPC in the prior art, but in the actual production process, it is found that the selecting dipole light source can increase the resolution, but can obtain an undesirable pattern for some special patterns during OPC correction. Referring to fig. 2, which is a partially enlarged view of the area shown by the dashed line box in fig. 1, the conventional method emphasizes the hot spot area (the area shown by the dashed line box in fig. 1) through Optical Proximity Correction Verification (OPCV), and then repairs the hot spot area, that is, repairs the hot spot area according to the direction shown by the arrow in fig. 2, but this process is a measure taken to find that the actual pattern is not ideal after performing OPC, belongs to post-processing, and only a fixed adjustment value can be found, which is not flexible in practical application, and there is a risk of missed capture when capturing the hot spot area through the OPCV.
Therefore, how to provide a method for optimizing a virtual pattern before OPC and a method for manufacturing a mask to optimize a virtual pattern of a polysilicon layer before OPC, and properly correct the optimized pattern by OPC after the optimized pattern is obtained, so as to avoid repairing the pattern after finding an undesired pattern after performing OPC, improve the flexibility of operation and reduce the risk caused by the missing grab of OPCV, which is an important technical problem to be solved urgently by technical personnel in the field.
It should be noted that the above background description is provided only for the sake of clarity and complete description of the technical solutions of the present application, and for the sake of understanding of those skilled in the art. These solutions are not considered to be known to the person skilled in the art merely because they are set forth in the background section of the present application.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for optimizing a virtual pattern before OPC and a method for manufacturing a mask, which are used to solve the problems in the prior art that some special patterns obtain undesired patterns during OPC correction, and that a hot spot area is forcibly called out by an OPCV for repair, which is a repair measure after OPC is performed, and belongs to post-processing, only a fixed size defect can be found, and the method is not flexible in practical application, and there is a possibility of missing capture when capturing the hot spot area by the OPCV, and there is a certain risk.
To achieve the above and other related objects, the present invention provides a method for optimizing a virtual graphic before OPC, comprising the steps of:
providing an original design pattern of a polysilicon layer, wherein the original design pattern comprises a first polysilicon pattern, a second polysilicon pattern and a third polysilicon pattern which are parallel to each other and are sequentially and alternately arranged along a preset direction;
identifying the original design pattern and acquiring the size information of the first polysilicon pattern, the size information of the second polysilicon pattern and the size information of the third polysilicon pattern;
and adjusting the size of the second polysilicon pattern, the position of the first polysilicon pattern and the position of the third polysilicon pattern based on the acquired size information of the first polysilicon pattern, the size information of the second polysilicon pattern and the size information of the third polysilicon pattern to obtain a corrected pattern.
Optionally, the dimension information includes a width of the polysilicon pattern.
Optionally, the method for obtaining the corrected graph includes the following steps: if the obtained width of the second polysilicon pattern is larger than the width of the first polysilicon pattern and the width of the third polysilicon pattern, the size of the second polysilicon pattern, the position of the first polysilicon pattern and the position of the third polysilicon pattern do not need to be adjusted, and the original design pattern is the corrected pattern.
Optionally, the method for obtaining the corrected graph includes the following steps: if the obtained width of the second polysilicon pattern is equal to the width of the first polysilicon pattern and the width of the third polysilicon pattern, adjusting the edge of the second polysilicon pattern to a direction close to the first polysilicon pattern and a direction close to the third polysilicon pattern by fixed values respectively, moving the first polysilicon pattern to a direction far away from the second polysilicon pattern by corresponding values, and moving the third polysilicon pattern to a direction far away from the second polysilicon pattern by corresponding values to obtain the corrected pattern.
Optionally, the method for obtaining the corrected graph includes the following steps: the method for obtaining the corrected graph comprises the following steps: if the obtained width of the second polysilicon pattern is smaller than the width of the first polysilicon pattern and the width of the third polysilicon pattern, adjusting the edge of the second polysilicon pattern to a fixed value respectively in a direction close to the first polysilicon pattern and a direction close to the third polysilicon pattern, moving the first polysilicon pattern to a direction far away from the second polysilicon pattern by a corresponding value, and moving the third polysilicon pattern to a direction far away from the second polysilicon pattern by a corresponding value to obtain the corrected pattern.
Optionally, the fixed value is determined according to the width of the second polysilicon pattern.
Optionally, the fixed value is determined according to a difference between a width of the second polysilicon pattern and a width of the first polysilicon pattern.
Optionally, the size information of the first polysilicon pattern, the size information of the second polysilicon pattern, and the size information of the third polysilicon pattern are obtained by an EDA tool.
The invention also provides a manufacturing method of the mask, which comprises the following steps:
performing OPC on a corrected graph obtained by the method for optimizing the virtual graph before the OPC to obtain an OPC corrected graph;
obtaining a mask pattern based on the OPC corrected pattern;
and manufacturing the mask plate based on the mask plate pattern.
Optionally, the mask is used for manufacturing a polysilicon layer gate structure.
As described above, according to the method for optimizing the virtual pattern of the polysilicon layer, the virtual pattern of the polysilicon layer is optimized before OPC, and then the optimized pattern is properly corrected through OPC, so that the problem that the pattern is repaired after an unsatisfactory pattern is found after OPC is performed is avoided, the flexibility of operation is improved, the risk caused by the missing capture of the OPCV is reduced, and the yield and the performance stability of the product are improved.
Drawings
Fig. 1 is a diagram illustrating a polysilicon layer in the prior art.
Fig. 2 is an enlarged view of a portion of the area indicated by the dashed line box in fig. 1.
FIG. 3 is a diagram illustrating an original design pattern of a polysilicon layer.
Fig. 4 is a diagram illustrating a polysilicon layer after OPC processing in the prior art.
FIG. 5 is a flowchart illustrating the steps of a method for optimizing virtual graphics before OPC according to the present invention.
FIG. 6 is a data diagram of an adjustment table for a method of optimizing a virtual graphic before OPC according to the present invention.
FIG. 7 is a schematic diagram of a polysilicon layer pattern obtained by adjusting the dimension of a second polysilicon pattern according to the method for optimizing a dummy pattern before OPC of the present invention.
FIG. 8 is a schematic diagram showing a corrected pattern obtained by adjusting the positions of the first polysilicon pattern and the third polysilicon pattern according to the method for optimizing a dummy pattern before OPC in accordance with the present invention.
FIG. 9 is a diagram showing the effect of the actual pattern of the polysilicon layer obtained by the method for optimizing the virtual pattern before OPC of the present invention.
FIG. 10 is a diagram showing the effect of the actual pattern of the polysilicon layer obtained by the method for optimizing the virtual pattern before OPC of the present invention.
Description of the element reference
11. Polysilicon pattern
1. Original design pattern
2. First polysilicon pattern
3. Second polysilicon pattern
4. Second polysilicon pattern
5. Original pattern
6. Actual figure
7. Original pattern
8. Correction pattern
9. Actual figure
S1 to S3
Detailed Description
The following embodiments of the present invention are provided by way of specific examples, and other advantages and effects of the present invention will be readily apparent to those skilled in the art from the disclosure herein. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 3 to 10. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Aiming at the phenomenon that the pattern of the polysilicon layer obtained after OPC is discovered in actual production in the background art, the inventor analyzes the reason for generating the problem that the problem is possibly as follows, generally, both densely distributed patterns (such as 1:1 lines with equal intervals) and sparse patterns (such as independent lines) exist in a layout, and the photoetching process window of the densely distributed patterns is different from the photoetching process window of the sparse patterns, so that the common process window is smaller. The illumination conditions suitable for exposure of dense patterns are not suitable for exposure of sparse patterns. Referring to fig. 3, a schematic diagram of an original design pattern 1 of a polysilicon layer is shown, in which three polysilicon patterns are arranged in parallel at intervals, a middle polysilicon pattern 3 is in a dense distribution state, and a side polysilicon pattern 2 and a side polysilicon pattern 4 are in a semi-dense distribution state, and referring to fig. 4, a polysilicon pattern after OPC in the prior art is shown, so that the polysilicon patterns 2 and 4 on both sides of the middle polysilicon pattern 3 are formed according to a maximum value in a standard size table after illumination, and the middle polysilicon pattern 3 is formed according to a standard value, thereby generating a phenomenon of "large-size-small" as shown in fig. 4. In order to reduce the process difference caused by different pattern densities in an integrated circuit layout, a conventional mode is to insert a sub-resolution pattern into a surrounding area with sparser patterns in a mask pattern so as to improve the focal depth and the uniformity of a process window. The inserted pattern size is smaller than the imaging resolution of the photoetching system, and is a plurality of slender square lines parallel to the mask pattern, so that the inserted pattern size does not form the photoetching pattern during exposure, but influences the photoetching imaging light intensity distribution of the nearby mask pattern.
Example one
The present embodiment provides a method for optimizing a virtual graphic before OPC, please refer to fig. 5, which is a flowchart illustrating steps of the method, and includes the following steps:
s1: providing an original design pattern of a polysilicon layer, wherein the original design pattern comprises a first polysilicon pattern, a second polysilicon pattern and a third polysilicon pattern which are parallel to each other and are sequentially and alternately arranged along a preset direction;
s2: identifying the original design pattern and acquiring the size information of the first polysilicon pattern, the size information of the second polysilicon pattern and the size information of the third polysilicon pattern;
s3: and adjusting the size of the second polysilicon pattern, the position of the first polysilicon pattern and the position of the third polysilicon pattern based on the acquired size information of the first polysilicon pattern, the size information of the second polysilicon pattern and the size information of the third polysilicon pattern to obtain a corrected pattern.
First, referring to fig. 3, step S1 is executed to provide an original design pattern 1 of a polysilicon layer, where the original design pattern 1 includes three first polysilicon patterns 2, second polysilicon patterns 3, and third polysilicon patterns 4 that are parallel to each other and are sequentially and alternately arranged along a predetermined direction.
And step S2 is executed again, the original design graph 1 is identified, and the size information of the first polysilicon graph 2, the size information of the second polysilicon graph 3 and the size information of the third polysilicon graph 4 are obtained. The recognition of the original Design pattern 1 is specifically realized by an Electronic Design Automation (EDA) tool language. Namely, the dimension information of the first polysilicon pattern 2, the dimension information of the second polysilicon pattern 3 and the dimension information of the third polysilicon pattern 4 are obtained by EDA tool.
As an example, the size information includes a width of the polysilicon pattern. In other embodiments, the dimension information may also be the length of the polysilicon pattern and the distance between adjacent polysilicon patterns, and is reasonably selected according to the technical problem to be actually solved.
And S3, adjusting the size of the second polysilicon pattern 3, the position of the first polysilicon pattern 2 and the position of the third polysilicon pattern 4 based on the acquired size information of the first polysilicon pattern 2, the size information of the second polysilicon pattern 3 and the size information of the third polysilicon pattern 4 to obtain a corrected pattern 5.
As an example, the method for obtaining the corrected graph 5 includes the following steps: if the obtained width of the second polysilicon pattern 3 is greater than the width of the first polysilicon pattern 2 and the width of the third polysilicon pattern 4, the size of the second polysilicon pattern 3, the position of the first polysilicon pattern 2 and the position of the third polysilicon pattern 4 do not need to be adjusted, and the original design pattern 1 is the corrected pattern 5.
As an example, the method of obtaining the corrected graph 5 includes the following steps: if the obtained width of the second polysilicon pattern 3 is equal to the width of the first polysilicon pattern 2 and the width of the third polysilicon pattern 4, adjusting the edge of the second polysilicon pattern 3 to a direction close to the first polysilicon pattern 2 and a direction close to the third polysilicon pattern 4 by fixed values respectively, moving the first polysilicon pattern 2 to a direction far away from the second polysilicon pattern 3 by corresponding values, and moving the third polysilicon pattern 4 to a direction far away from the second polysilicon pattern 3 by corresponding values to obtain the corrected pattern 5.
As an example, the fixed value is determined according to the width of the second polysilicon pattern 3.
As an example, the method of obtaining the corrected graph 5 includes the following steps: if the obtained width of the second polysilicon pattern 3 is smaller than the width of the first polysilicon pattern 2 and the width of the third polysilicon pattern 4, adjusting the edge of the second polysilicon pattern 3 to a direction close to the first polysilicon pattern 2 and a direction close to the third polysilicon pattern 4 by fixed values respectively, moving the first polysilicon pattern 2 to a direction far away from the second polysilicon pattern 3 by corresponding values, and moving the third polysilicon pattern 4 to a direction far away from the second polysilicon pattern 3 by corresponding values to obtain the corrected pattern 5.
As an example, the fixed value is determined according to a difference between the width of the second polysilicon pattern 3 and the width of the first polysilicon pattern 2.
Specifically, the adjustment of the size of the second polysilicon pattern 3, the position of the first polysilicon pattern 2, and the position of the third polysilicon pattern 4 may be performed according to an adjustment table prepared based on design rules, please refer to fig. 6, which is a data diagram of the adjustment table, where the content in the adjustment table includes a first width (the width of the second polysilicon pattern 3), a second width (the widths of the first polysilicon pattern 2 and the third polysilicon pattern 4), and a fixed value, and the fixed value is selected according to the value of the first width or the difference between the first width and the second width. The adjustment table shown in fig. 6 is only one example, and in practical applications, the adjustment table is suitably designed based on relevant dimension information of the original design pattern.
Further, when the first width is greater than the second width, that is, the width of the second polysilicon pattern 3 is greater than the widths of the first polysilicon pattern 2 and the third polysilicon pattern 4, the fixed value adjusted in the subsequent steps is zero, that is, the first polysilicon pattern 3 does not need to be adjusted, and the first polysilicon pattern 2 and the third polysilicon pattern 4 do not need to be adjusted, in which case, the originally designed pattern is a corrected pattern, for example, when the first width is 45nm and the second width is 35nm, the fixed value adjusted in the subsequent steps is zero.
Further, when the first width is equal to the second width, that is, the width of the second polysilicon pattern 3 is equal to the widths of the first polysilicon pattern 2 and the third polysilicon pattern 4, please refer to fig. 7, first, the edge of the second polysilicon pattern 3 is adjusted to a fixed value in a direction approaching the first polysilicon pattern 2 and in a direction approaching the third polysilicon pattern 4, respectively, and a difference between the adjusted width of the second polysilicon pattern 3 and the adjusted width of the second polysilicon pattern 3 is twice as large as the fixed value. Referring to fig. 8, the first polysilicon pattern 2 is moved away from the second polysilicon pattern 3 by a corresponding value, and the third polysilicon pattern 4 is moved away from the second polysilicon pattern 3 by a corresponding value, so as to obtain a corrected pattern. In this case, the fixed value is determined according to the first width, and the fixed value ranges from 2% to 4% of the first width value, for example, 1nm when the first width and the second width are both 40 nm. The purpose of adjusting the position of the first polysilicon pattern 2 and the position of the third polysilicon pattern 4 is to reduce the distance between the second polysilicon pattern 3 and the first polysilicon pattern 2 and the third polysilicon pattern 4 due to the proper adjustment of the width of the second polysilicon pattern 3 in the previous step, and to cause partial deviation between the pattern on the original mask and the actual pattern due to the reduction of the distance between adjacent polysilicon patterns in the subsequent photolithography process, so that the first polysilicon pattern 2 and the third polysilicon pattern 4 need to be properly shifted along the adjustment direction of the second polysilicon pattern 3, and the shift value corresponds to the fixed value for adjusting the size of the first polysilicon pattern 3.
Further, when the first width is smaller than the second width, that is, the width of the second polysilicon pattern 3 is smaller than the widths of the first polysilicon pattern 2 and the third polysilicon pattern 4, similarly to the former case, the edge of the second polysilicon pattern 3 is adjusted to a fixed value in a direction approaching the first polysilicon pattern 2 and a direction approaching the third polysilicon pattern 4, and then the first polysilicon pattern 2 is moved to a direction away from the second polysilicon pattern 3 by a corresponding value and the third polysilicon pattern 4 is moved to a direction away from the second polysilicon pattern 3 by a corresponding value, so as to obtain a corrected pattern. In this case, the fixed value is determined based on the difference between the first width and the second width, and the fixed value adjusted in the subsequent step is gradually increased as the difference between the first width and the second width increases, for example, when the first width is 40nm and the second width is 60nm, the fixed value adjusted in the subsequent step is 4nm.
The method for optimizing the virtual graph before the OPC of the embodiment optimizes the virtual graph of the polysilicon layer before the OPC, avoids repairing the graph after finding an unsatisfactory graph after the OPC is executed, improves the flexibility of operation, reduces the risk caused by the missing grab of the OPCV, and improves the yield and the performance stability of the product.
Example two
The embodiment provides a method for manufacturing a mask, and particularly relates to a method for manufacturing a mask on the basis of a method for optimizing a virtual pattern before OPC in the first embodiment, which includes the following steps: performing OPC on a corrected graph obtained by a method for optimizing a virtual graph before OPC in the first embodiment to obtain an OPC corrected graph; obtaining a mask pattern based on the OPC corrected pattern; and manufacturing the mask plate based on the mask plate pattern.
As an example, the mask is used to fabricate a polysilicon layer gate structure.
Specifically, please refer to fig. 9, which shows an actual polysilicon pattern effect diagram obtained without an optimization method, wherein in an actual polysilicon pattern 6 (a pattern shown by dotted filling in fig. 9) obtained after OPC correction is performed on an original pattern 5 (a pattern shown by striped filling in fig. 9), the second polysilicon pattern 3 has a significantly different morphology from the first polysilicon pattern 2 and the third polysilicon pattern 4, and regions adjacent to the second polysilicon pattern 3, the first polysilicon pattern 2 and the third polysilicon pattern 4 are significantly shrunk to show a phenomenon of "large-small-large-size". Please refer to fig. 10, which shows an effect diagram of an actual polysilicon pattern obtained by an optimization method, where an original pattern 7 (a region pattern shown by a dotted line in fig. 10) is optimized to obtain a corrected pattern 8 (shown by a striped filling pattern in fig. 10), and then OPC correction is performed on the corrected pattern 8 to obtain an actual pattern 9 (shown by a dotted filling pattern in fig. 10), and although the first polysilicon pattern in the finally obtained actual pattern is not perfect, compared with the non-optimized pattern shown in fig. 9, the first polysilicon pattern in fig. 10 has a significantly smaller morphology difference from the second polysilicon pattern, so that OPC correction performed after optimization has a significantly improved effect on the condition that the polysilicon pattern is not ideal.
According to the manufacturing method of the mask, the virtual graph of the polycrystalline silicon layer is optimized before the traditional OPC correction to obtain the corrected graph, the OPC correction is carried out on the basis of the corrected graph to obtain the mask graph for manufacturing the mask, and the consistency and the accuracy of the actual graph are obviously improved compared with the actual graph which is not optimized.
In summary, the method for optimizing the virtual pattern before OPC of the present invention optimizes the virtual pattern of the polysilicon layer before OPC, avoids repairing the pattern after finding an unsatisfactory pattern after OPC is performed, improves flexibility of operation, reduces a risk caused by missing capture of the OPCV, can effectively improve integrity and stability of the pattern, and further improves yield and performance stability of the product. According to the manufacturing method of the mask, the virtual graph is optimized before OPC to obtain the corrected graph, OPC is performed to obtain the mask graph to manufacture the mask, and finally, compared with the actual graph which is not optimized, the consistency and accuracy of the actual graph are obviously improved, so that the yield and performance stability of the product can be effectively improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Those skilled in the art can modify or change the above-described embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (10)
- The method for optimizing the virtual graph before OPC is characterized by comprising the following steps of:providing an original design pattern of a polysilicon layer, wherein the original design pattern comprises a first polysilicon pattern, a second polysilicon pattern and a third polysilicon pattern which are parallel to each other and are sequentially and alternately arranged along a preset direction;identifying the original design pattern and acquiring the size information of the first polysilicon pattern, the size information of the second polysilicon pattern and the size information of the third polysilicon pattern;and adjusting the size of the second polysilicon pattern, the position of the first polysilicon pattern and the position of the third polysilicon pattern based on the acquired size information of the first polysilicon pattern, the size information of the second polysilicon pattern and the size information of the third polysilicon pattern to obtain a corrected pattern.
- 2. The method for optimizing virtual graphics before OPC as in claim 1, wherein: the dimension information includes a width of the polysilicon pattern.
- 3. The method for optimizing a virtual pattern before OPC of claim 2, wherein the method for obtaining the corrected pattern comprises the steps of: if the obtained width of the second polysilicon pattern is larger than the width of the first polysilicon pattern and the width of the third polysilicon pattern, the size of the second polysilicon pattern, the position of the first polysilicon pattern and the position of the third polysilicon pattern do not need to be adjusted, and the original design pattern is the corrected pattern.
- 4. The method for optimizing a virtual pattern before OPC of claim 2, wherein the method for obtaining the corrected pattern comprises the steps of: if the obtained width of the second polysilicon pattern is equal to the width of the first polysilicon pattern and the width of the third polysilicon pattern, adjusting the edge of the second polysilicon pattern to a fixed value respectively in the direction close to the first polysilicon pattern and the direction close to the third polysilicon pattern, moving the first polysilicon pattern to a direction far away from the second polysilicon pattern by a corresponding value, and moving the third polysilicon pattern to a direction far away from the second polysilicon pattern by a corresponding value to obtain the corrected pattern.
- 5. The method for optimizing virtual graphics before OPC in claim 2, wherein the method for obtaining the corrected graphics comprises the steps of: if the obtained width of the second polysilicon pattern is smaller than the width of the first polysilicon pattern and the width of the third polysilicon pattern, adjusting the edge of the second polysilicon pattern to a fixed value respectively in a direction close to the first polysilicon pattern and a direction close to the third polysilicon pattern, moving the first polysilicon pattern to a direction far away from the second polysilicon pattern by a corresponding value, and moving the third polysilicon pattern to a direction far away from the second polysilicon pattern by a corresponding value to obtain the corrected pattern.
- 6. The method of optimizing pre-OPC dummy patterns according to claim 4, wherein the fixed value is determined according to the width of the second polysilicon pattern.
- 7. The method of optimizing pre-OPC structures of claim 5, wherein the fixed value is determined by a difference between a width of the second polysilicon pattern and a width of the first polysilicon pattern.
- 8. The method of pre-OPC optimizing a virtual graphic of claim 1, wherein: and acquiring the size information of the first polysilicon pattern, the size information of the second polysilicon pattern and the size information of the third polysilicon pattern through an EDA tool.
- 9. The manufacturing method of the mask is characterized by comprising the following steps:performing OPC on a corrected graph obtained by the method for optimizing the virtual graph before OPC according to any one of claims 1 to 8 to obtain an OPC corrected graph;obtaining a mask pattern based on the OPC corrected pattern;and manufacturing the mask plate based on the mask plate pattern.
- 10. The method for manufacturing the mask according to claim 9, wherein the mask is used for manufacturing a polysilicon layer gate structure.
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| CN118625591A (en) * | 2024-08-09 | 2024-09-10 | 合肥晶合集成电路股份有限公司 | Mask plate, correction method thereof and electronic equipment |
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