JP2009004699A - Method and apparatus of manufacturing semiconductor device - Google Patents

Method and apparatus of manufacturing semiconductor device Download PDF

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JP2009004699A
JP2009004699A JP2007166541A JP2007166541A JP2009004699A JP 2009004699 A JP2009004699 A JP 2009004699A JP 2007166541 A JP2007166541 A JP 2007166541A JP 2007166541 A JP2007166541 A JP 2007166541A JP 2009004699 A JP2009004699 A JP 2009004699A
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electron beam
minute
figures
pattern
plurality
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Kenichi Tokunaga
賢一 徳永
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Nec Electronics Corp
Necエレクトロニクス株式会社
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Abstract

A semiconductor device manufacturing method and a semiconductor manufacturing apparatus in which a desired pattern is formed.
A method of manufacturing a semiconductor device includes a step (S24) of extracting a minute figure smaller than a predetermined size from a plurality of figures constituting a pattern (63), and forming a pattern corresponding to each of the plurality of figures. Irradiating a figure region (52) corresponding to each of a plurality of figures on the substrate (51) with an electron beam (50) (S23). In the extracting step (S24), the size of the minute figure is compared with a predetermined size. In the irradiating step (S23), the irradiation amount per unit area for irradiating the minute figure region (52) corresponding to the minute figure on the substrate (51) with the electron beam (50) shaped so as to correspond to the minute figure is The electron beam (50) shaped so as to correspond to the non-micro figure that was not extracted in the step (S24) of extracting a plurality of figures is a non-micro graphic area (corresponding to the non-micro figure on the substrate (51)). 52) more than the irradiation amount per unit area.
[Selection] Figure 9

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor manufacturing device, and more particularly to a semiconductor manufacturing method and a semiconductor manufacturing device for drawing a mask pattern for lithography by irradiating an electron beam.

  As shown in FIG. 1, a general method for manufacturing a semiconductor device includes a step S1 for designing a circuit pattern (hereinafter referred to as “device pattern”) of a semiconductor device, and a mask having a mask pattern corresponding to the device pattern. Step S2 to be manufactured and Step S3 as a lithography process for transferring a mask pattern to a resist layer on a wafer and forming a circuit corresponding to the transferred pattern are provided. The mask is sometimes called a reticle.

  FIG. 2 shows an example of step S2 when a mask is produced by drawing a mask pattern on a mask substrate using a variable shaping type electron beam exposure apparatus. Step S2 includes step S21, step S22, and step S23.

  Technologies related to step S2 are disclosed in Patent Documents 1 to 4.

  In step S21, optical proximity correction (OPC: Optical Proximity Correction) processing is executed. OPC is one of the super-resolution techniques (RET: Resolution Enhancement Technology) for forming a fine pattern on a wafer. In general, an information processing apparatus that performs OPC processing is called a light intensity simulator.

  OPC called HAT will be described with reference to FIGS. 3 (a) to 3 (c). FIG. 3A shows a designed device pattern 71 as a designed device pattern. The design device pattern 71 is an elongated rectangle. The light intensity simulator calculates a photosensitive device pattern 72 as a pattern to which a resist layer on the wafer is exposed when a pre-OPC mask pattern that is geometrically similar to the designed device pattern 71 is transferred. FIG. 3B shows the photosensitive device pattern 72. The photosensitive device pattern 72 is contracted in the longitudinal direction as compared with the designed device pattern 71 because the light amount at the end portion is insufficient. The light intensity simulator obtains a mask pattern 73 after the OPC process as a mask pattern so that the pattern to which the resist layer is exposed matches the designed device pattern 71. FIG. 3C shows the mask pattern 73 after the OPC process. Comparing the post-OPC mask pattern 73 with the designed device pattern 71, the post-OPC mask pattern 73 has an auxiliary pattern that emphasizes the edge of the post-OPC mask pattern 73 surrounded by a frame. As a result, the pattern that the resist layer on the wafer is exposed to is prevented from shrinking in the longitudinal direction as compared with the designed device pattern 71.

  OPC called serif will be described with reference to FIGS. 4 (a) to 4 (c). FIG. 4A shows a designed device pattern 74 as a designed device pattern. The design device pattern 74 has a bent portion bent in a hook shape. The light intensity simulator calculates a photosensitive device pattern 75 as a pattern to which the resist layer on the wafer is exposed when a pre-OPC mask pattern that is geometrically similar to the designed device pattern 74 is transferred. FIG. 4B shows the photosensitive device pattern 75. The photosensitive device pattern 75 has a rounded bent portion as compared with the designed device pattern 74. The light intensity simulator obtains a mask pattern 76 after the OPC process as a mask pattern so that the pattern to which the resist layer is exposed matches the designed device pattern 74. FIG. 4C shows the mask pattern 76 after the OPC process. When the mask pattern 76 after OPC processing is compared with the designed device pattern 74, the bent portion of the mask pattern 76 after OPC processing surrounded by a frame is emphasized in the mask pattern 76 after OPC processing. As a result, the pattern in which the resist layer on the wafer is exposed is prevented from being rounded at the bent portion as compared with the designed device pattern 74.

  In addition to HAT and serif, OPC includes correction that corrects the size and shape of a pattern constituting a part of a mask pattern based on the distance from an adjacent pattern.

  FIG. 5 is an explanatory diagram of step S21. A mask pattern 62 after OPC processing is obtained from the designed device pattern 61 designed in step S1. Generally, the post-OPC mask pattern 62 is more complicated in shape than the designed device pattern 61.

  FIG. 6 is an explanatory diagram of step S22. By the data conversion process, an electron beam irradiation pattern 63 obtained by dividing the post-OPC mask pattern 62 into a plurality of rectangles is obtained. When the post-OPC mask pattern 62 is complicated, the plurality of rectangles constituting the electron beam irradiation pattern 63 tend to include small rectangles. The data of the electron beam irradiation pattern 63 is used by a variable shaping type electron beam exposure apparatus to draw a mask pattern corresponding to the mask pattern 62 after the OPC process on the mask substrate.

  FIG. 7 shows an optical system of the variable shaping type electron beam exposure apparatus 3 used in step S23. The optical system of the electron beam exposure apparatus 3 includes an electron gun 32, a first aperture 33, a shaping deflector 34, and a second aperture 35. The electron beam 50 emitted from the electron gun 32 is shaped into a rectangle by the first aperture 33, the shaping deflector 34, and the second aperture 35.

  In step S <b> 23, the electron beam exposure apparatus 3 irradiates the electron beam 50 formed into a rectangle in synchronization with the movement of the stage that supports the mask substrate 51, and corresponds to each of the plurality of rectangles of the electron beam irradiation pattern 63. The exposure area 52 on the mask substrate 51 is exposed. In this way, the electron beam exposure apparatus 3 draws the mask pattern 62 after the OPC process on the mask substrate 51. The electron beam exposure apparatus 3 can usually shape the electron beam 50 so that the irradiation field of the electron beam 50 (corresponding to the exposure region 52) is a rectangular region having a side of 1 to 1000 nm. Here, the rectangular area may be a square area or a rectangular area having a longer side and a shorter side.

  The plurality of rectangles constituting the electron beam irradiation pattern 63 include a small rectangle and a large rectangle. When exposing the exposure area 52 corresponding to the large rectangle and the exposure area 52 corresponding to the small rectangle under the common electron beam irradiation conditions, the exposure area 52 corresponding to the large rectangle is sufficiently exposed, but exposure corresponding to the small rectangle. The region 52 may not be sufficiently exposed. When the electron beam 50 is shaped so as to reduce the irradiation field, a phenomenon called blur occurs due to aberration and the Coulomb effect, and the energy intensity received by the exposure region 52 irradiated with such an electron beam 50 is insufficient. .

JP 9-63930 A JP 2000-5131303 gazette JP 2001-296645 A JP 2002-33263 A

  The present inventor recognizes that when the electron beam irradiation pattern includes a figure of a small size, the desired mask pattern may not be formed on the mask substrate, and as a result, the desired device pattern may not be formed on the wafer. did.

  Hereinafter, means for solving the problem will be described using the numbers used in (Best Mode for Carrying Out the Invention). These numbers are added to clarify the correspondence between the description of (Claims) and (Best Mode for Carrying Out the Invention). However, these numbers should not be used to interpret the technical scope of the invention described in (Claims).

  The method of manufacturing a semiconductor device according to the present invention includes a step (S24) of extracting a minute figure smaller than a predetermined size from a plurality of figures constituting the pattern (63), and an electron molded to correspond to each of the plurality of figures. Irradiating a line (50) to a graphic area (52) corresponding to each of a plurality of figures on the substrate (51) (S23). In the extracting step (S24), the size of the minute figure is compared with a predetermined size. In the irradiating step (S23), the irradiation amount per unit area for irradiating the minute figure region (52) corresponding to the minute figure on the substrate (51) with the electron beam (50) shaped so as to correspond to the minute figure is The electron beam (50) shaped so as to correspond to the non-micro figure not extracted in the step (S24) of extracting a plurality of figures is a non-micro figure region (non-micro figure region corresponding to the non-micro figure on the substrate (51)). 52) more than the irradiation amount per unit area.

  The semiconductor manufacturing apparatus (1) according to the present invention corresponds to each of a plurality of figures, and a minute figure extracting unit (23) for extracting a figure smaller than a predetermined size from a plurality of figures constituting the pattern (63). And an electron beam exposure device (3) for irradiating the figure region (52) corresponding to each of a plurality of figures on the substrate (51) with the shaped electron beam (50). The micro graphic extraction unit (23) compares the size of the micro graphic with a predetermined size. The electron beam exposure apparatus (3) irradiates an electron beam (50) shaped so as to correspond to a minute figure onto a minute figure region (52) corresponding to the minute figure on the substrate (51) per unit area. The electron beam (50) formed so as to correspond to the non-micro figure that has not been extracted by the micro figure extraction unit (23) among the plurality of figures is a non-micro figure corresponding to the non-micro figure on the substrate (51) More than the irradiation amount per unit area with which the region (52) is irradiated.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method and semiconductor manufacturing apparatus of a semiconductor device in which a desired pattern is formed are provided.

  With reference to the accompanying drawings, a semiconductor device manufacturing method and a semiconductor manufacturing apparatus according to the present invention will be described below.

(First embodiment)
As shown in FIG. 8, the semiconductor manufacturing apparatus 1 according to the first embodiment of the present invention includes an information processing apparatus 2 and an electron beam exposure apparatus 3. The information processing device 2 includes a storage device and a processing device. The processing device operates as the OPC processing unit 21, the data conversion unit 22, and the minute figure extraction unit 23 according to the program recorded on the recording medium of the storage device. The electron beam exposure apparatus 3 includes a blanking electrode 37, a shaping deflector 34, a stage 36, and a control device 31 that controls them. The stage 36 is an XY stage. As shown in FIG. 7, the optical system of the electron beam exposure apparatus 3 includes an electron gun 32, a first aperture 33, a shaping deflector 34, a second aperture 35, a blanking electrode 37, and a blanking aperture. 38. The first aperture 33, the shaping deflector 34, and the second aperture 35 shape the electron beam 50 emitted from the electron gun 32 into a desired shape. The blanking electrode 37 and the blanking aperture 38 switch between irradiation and non-irradiation of the electron beam 50. The stage 36 moves the mask substrate 51 to which the electron beam 50 is irradiated. As shown in FIG. 1, the manufacturing method of the semiconductor device according to the present embodiment includes a step S1 of designing a device pattern as a circuit pattern of the semiconductor device, and a step S2 of manufacturing a mask having a mask pattern corresponding to the device pattern. And a step S3 as a lithography process for transferring the mask pattern to the resist layer on the wafer and forming a circuit corresponding to the transferred pattern. Step S2 according to this embodiment includes step S21, step S22, step S24, and step S23, as shown in FIG. The information processing apparatus 2 executes Step S21, Step S22, and Step S24. The electron beam exposure apparatus 3 executes step S23.

  In step S21, the OPC processing unit 21 executes the OPC process, and obtains the post-OPC mask pattern data 42 indicating the post-OPC mask pattern 62 from the device pattern design data 41 indicating the designed device pattern 61 designed in step S1. Generate. The device pattern design data 41 is GDS2 data, for example. The device pattern design data 41 may indicate a pattern (mask pattern before OPC processing) that is geometrically similar to the pattern designed in step S1. The designed device pattern 61 and the post-OPC mask pattern 62 are shown in FIG. The mask pattern 62 after the OPC process is obtained by correcting the design device pattern 61 by OPC such as HAT and serif. The OPC processing unit 21 may execute the OPC process on a model basis or a rule basis. In the model-based OPC process, a mask pattern that is geometrically similar to the design device pattern 61 is used as a starting point to simulate a pattern in which the resist layer on the wafer is exposed by the mask pattern, and the simulated pattern becomes the design device pattern 61. The mask pattern 62 after the OPC process is obtained by correcting the mask pattern so as to match. In the rule-based OPC process, the post-OPC mask pattern 62 is obtained by correcting the design device pattern 61 according to a predetermined rule.

  In step S <b> 22, the data conversion unit 22 generates first electron beam irradiation data 43 in a format corresponding to the electron beam exposure apparatus 3 from the post-OPC mask pattern data 42. At this time, the data conversion unit 22 divides the mask pattern 62 after OPC processing into a plurality of figures. The first electron beam irradiation data 43 indicates an electron beam irradiation pattern 63 in which the post-OPC mask pattern 62 is divided into a plurality of figures, for example, rectangles. Therefore, the electron beam irradiation pattern 63 is composed of a plurality of figures as shown in FIG.

  In step S <b> 24, the minute figure extraction unit 23 extracts minute figures from a plurality of figures constituting the electron beam irradiation pattern 63. A micro figure refers to a figure in which one or both of the X and Y dimensions (long side and short side length) are smaller than a predetermined reference dimension. The minute figure extraction unit 23 compares each dimension of a plurality of figures with a reference dimension in order to extract a minute figure. A mask rule check system such as Smart MRC manufactured by SII Nano Technology Co., Ltd. can be used to extract a minute figure. The minute figure extraction unit 23 generates second electron beam irradiation data 44 indicating an electron beam irradiation pattern 64 composed of all the extracted minute figures. The electron beam irradiation pattern 64 is shown in FIG. The data format of the second electron beam irradiation data 44 is the same as the data format of the first electron beam irradiation data 43.

  In step S <b> 23, the electron beam exposure apparatus 3 applies the electron beam 50 formed so as to correspond to each shape of the plurality of figures of the electron beam irradiation pattern 63 based on the first electron beam irradiation data 43 to the mask substrate 51. The exposure region 52 corresponding to each position of the plurality of figures is exposed to light in synchronization with the movement of the stage 36 that supports the substrate. Here, the control device 31 outputs a first control signal 47 to the shaping deflector 34 and outputs a second control signal 48 to the stage 36 corresponding to each of the plurality of figures of the electron beam irradiation pattern 63. A third control signal 49 is output to the blanking electrode 37. The first control signal 47 and the second control signal 48 designate the shape of the electron beam 50 and the position of the stage 36 corresponding to the shape and position of each of the plurality of figures of the electron beam irradiation pattern 63. The third control signal 49 designates the irradiation time of the electron beam 50 based on the irradiation amount information of the electron beam corresponding to each figure.

  In step S <b> 23, the electron beam exposure apparatus 3 applies the electron beam 50 shaped so as to correspond to the shape of each of the plurality of minute figures of the electron beam irradiation pattern 64 based on the second electron beam irradiation data 44 to the stage 36. The exposure area 52 corresponding to each of the plurality of minute figures is exposed to light in synchronization with the movement of the image. Here, the control device 31 outputs a first control signal 47 to the shaping deflector 34 and outputs a second control signal 48 to the stage 36 corresponding to each of the plurality of minute figures of the electron beam irradiation pattern 64. The third control signal 49 is output to the blanking electrode 37.

  Since the exposure area 52 corresponding to the minute figure is doubly exposed, the exposure corresponding to the exposure amount 52 per unit area of the electron beam to the exposure area 52 corresponding to the minute figure is not a minute figure among a plurality of figures. More than the irradiation amount per unit area of the electron beam to the region 52. The exposure area 52 corresponding to the minute figure is compensated for the insufficient intensity of energy received by the electron beam irradiation, so that the size reduction is prevented and a mask pattern that faithfully reproduces the mask pattern 62 after the OPC processing is formed on the mask substrate 51. It is formed. By using the mask manufactured in this way, a device pattern that faithfully reproduces the designed device pattern 61 is formed on the wafer.

  The irradiation amount when the electron beam exposure apparatus 3 irradiates the electron beam 50 based on the second electron beam data 44 is 10 to 100 of the irradiation amount when the electron beam 50 is irradiated based on the first electron beam data 43. % Is preferred. When the acceleration voltage of the electron beam exposure apparatus 3 is 50 kV, the irradiation amount when irradiating the electron beam 50 based on the second electron beam data 44 irradiates the electron beam 50 based on the first electron beam data 43. It is particularly preferable that the irradiation amount is 20%. Specifically, when the electron beam irradiation amount for the standard size pattern on the mask is 15 uC / cm 2, the additional electron beam irradiation amount for the pattern with a size of 50 nm or less on the mask is +3 uC / It is desirable to be about cm2.

(Second Embodiment)
As shown in FIG. 11, the semiconductor manufacturing apparatus 1 according to the second embodiment of the present invention includes an information processing apparatus 2 and an electron beam exposure apparatus 3. The information processing device 2 includes a storage device and a processing device. The processing device operates as an OPC processing unit 21, a data conversion unit 22, a minute figure extraction unit 23, and a difference processing unit (data generation unit) 24 in accordance with a program recorded on a recording medium of the storage device. Similar to the electron beam exposure apparatus 3 according to the first embodiment, the electron beam exposure apparatus 3 according to the present embodiment includes a control device 31, an electron gun 32, a first aperture 33, a shaping deflector 34, A second aperture 35, a stage 36, a blanking electrode 37, and a blanking aperture 38 are provided. As shown in FIG. 1, the method for manufacturing a semiconductor device according to this embodiment includes a step S1 for designing a device pattern as a circuit pattern of the semiconductor device, and a step S2 for producing a mask having a mask pattern corresponding to the device pattern. And a step S3 of transferring the mask pattern to the resist layer on the wafer and forming a circuit corresponding to the transferred pattern. As shown in FIG. 12, step S2 according to the present embodiment includes step S21, step S22, step S24, step S25, and step S23. The information processing apparatus 2 executes Step S21, Step S22, Step S24, and Step S25. The electron beam exposure apparatus 3 executes step S23.

  Step S21, step S22, and step S24 according to the present embodiment are the same as step S21, step S22, and step S24 according to the first embodiment.

  In step S <b> 25, the difference processing unit 24 generates third electron beam irradiation data 45 from the first electron beam irradiation data 43 and the second electron beam irradiation data 44 by difference processing (XOR processing). The data format of the third electron beam irradiation data 45 is the same as the data format of the second electron beam irradiation data 44. The third electron beam irradiation data 45 represents an electron beam irradiation pattern 65. As shown in FIG. 13, the electron beam irradiation pattern 65 is composed of a plurality of non-small figures obtained by removing a plurality of minute figures constituting the electron beam irradiation pattern 64 from a plurality of figures constituting the electron beam irradiation pattern 63. The

  In step S <b> 23, the electron beam exposure apparatus 3 applies the electron beam 50 shaped so as to correspond to the shape of each of the plurality of minute figures of the electron beam irradiation pattern 64 based on the second electron beam irradiation data 44 to the stage 36. The exposure area 52 corresponding to each of the plurality of minute figures is exposed to light in synchronization with the movement of the image. Here, the control device 31 outputs a first control signal 47 to the shaping deflector 34 and outputs a second control signal 48 to the stage 36 corresponding to each of the plurality of minute figures of the electron beam irradiation pattern 64. The third control signal 49 is output to the blanking electrode 37. The first control signal 47 and the second control signal 48 designate the shape of the electron beam 50 and the position of the stage 36 corresponding to the shape and position of each of the plurality of minute figures of the electron beam irradiation pattern 64. The third control signal 49 designates the irradiation time of the electron beam 50 based on the irradiation amount information of the electron beam corresponding to each figure. Here, the irradiation time of the electron beam 50 specified by the third control signal 49 corresponding to each of the plurality of minute figures of the electron beam irradiation pattern 64 is the first time.

  In step S <b> 23, the electron beam exposure apparatus 3 masks the electron beam 50 shaped so as to correspond to each shape of the plurality of non-fine figures of the electron beam irradiation pattern 65 based on the third electron beam irradiation data 45. Irradiation is performed in synchronization with the movement of the stage 36 supporting the substrate 51, and the exposure regions 52 corresponding to the respective positions of the plurality of non-fine figures are exposed. Here, the control device 31 outputs a first control signal 47 to the shaping deflector 34 and outputs a second control signal 48 to the stage 36 corresponding to each of the plurality of non-microscopic figures of the electron beam irradiation pattern 65. Then, the third control signal 49 is output to the blanking electrode 37. The first control signal 47 and the second control signal 48 designate the shape of the electron beam 50 and the position of the stage 36 corresponding to the shape and position of each of the plurality of non-microscopic figures of the electron beam irradiation pattern 65. The third control signal 49 designates the irradiation time of the electron beam 50 based on the irradiation amount information of the electron beam corresponding to each figure. Here, the irradiation time of the electron beam 50 specified by the third control signal 49 corresponding to each of the plurality of non-microscopic figures of the electron beam irradiation pattern 65 is a second time shorter than the first time.

  Since the irradiation time of the electron beam to the exposure region 52 corresponding to the minute figure is longer than the irradiation time of the electron beam to the exposure region 52 corresponding to the non-small figure, the unit area of the electron beam to the exposure region 52 corresponding to the minute figure Is larger than the irradiation amount per unit area of the electron beam with respect to the exposure region 52 corresponding to the non-fine figure. Since the exposure region 52 corresponding to the minute figure is compensated for insufficient energy intensity received by the electron beam irradiation, a reduction in size is prevented, and a mask pattern that faithfully reproduces the mask pattern 62 after the OPC processing is formed on the mask substrate 51. Formed. By using the mask manufactured in this way, a device pattern that faithfully reproduces the designed device pattern 61 is formed on the wafer.

  The irradiation amount when the electron beam exposure apparatus 3 irradiates the electron beam 50 based on the second electron beam data 44 is 110 to 200 of the irradiation amount when the electron beam 50 is irradiated based on the third electron beam data 45. % Is preferred.

  The relationship between the size of the exposure area 52 and the energy intensity that the exposure area 52 receives by electron beam irradiation in the above embodiment will be described with reference to FIGS.

  FIG. 14A shows an exposure area 52 a as the exposure area 52. The exposure region 52a is a square having a side length of 500 nm. In the figure, a straight line A parallel to one side of the exposure region 52a is shown. The straight line A intersects with the outline of the exposure region 52a at points A1 and A2. FIG. 14B shows an exposure area 52 b as the exposure area 52. The exposure region 52b is a square having a side length of 20 nm. In the figure, a straight line B parallel to one side of the exposure region 52b is shown. The straight line B intersects with the outline of the exposure region 52b at points B1 and B2.

  FIG. 15 is a graph showing the energy intensity distribution on the mask substrate 51. The vertical axis indicates the intensity of energy received by the irradiated surface on the mask substrate 51 by electron beam irradiation. The horizontal axis indicates the position on the irradiated surface along the straight line A and the straight line B. For example, when the exposure region 52a is exposed by an electron beam exposure apparatus with an acceleration voltage of 50 kV and a current density of 15 A / cm 2, the energy intensity takes a constant value regardless of the position between the points A 1 and A 2. Outside the point A1, due to aberrations and the Coulomb effect, the energy intensity decreases with increasing distance from the point A1, and the energy intensity becomes zero at a position 20 to 50 nm away. The same applies to the outside of the point A2. The area around the exposure area 52a where the energy intensity decreases as the distance from the exposure area 52a increases as described above is called a blur area. When the exposure region 52b is exposed under the same conditions as the exposure region 52a, between the points B1 and B2 (inside the exposure region 52b), the size of the exposure region 52b (20 nm) is the width of the blur region (20 to 50 nm). ) Is smaller than that between the points A1 and A2 (inside the exposure region 52a).

  FIG. 16 is a graph showing the relationship between the size of the exposure area and the energy intensity inside the exposure area when exposed by an electron beam exposure apparatus with an acceleration voltage of 50 kV and a current density of 15 A / cm 2. The vertical axis represents energy intensity. The horizontal axis indicates the size of the exposure area 52. When the size (side length) of the exposure region 52 is larger than 50 nm, the energy intensity inside the exposure region 52 is constant regardless of the size of the exposure region 52. When the size of the exposure region 52 is smaller than 50 nm, the energy intensity inside the exposure region 52 is lower as the size of the exposure region 52 is smaller.

  FIG. 17 shows exposure areas 53 and 54 on the mask substrate 51. In order to form a mask pattern 55 having a width of 1000 nm, the exposure region 53 and the exposure region 54 are irradiated with an electron beam.

  In FIG. 18, the mask pattern 55 formed when the dimension a of the exposure region 53 on the mask is set in the range of 0 nm to 1000 nm, the size b of the exposure region 54 is set to 1000-a, and the electron beam is irradiated. Dimension c is shown. The vertical axis indicates the dimension c. The horizontal axis indicates the dimension a. When the dimension a or b is 50 nm, the dimension c is minimum. Therefore, the reference dimension in step S24 of the above embodiment is preferably set to a dimension of 100 nm or less. The reference dimension is particularly preferably set in the range of 20 to 50 nm.

  There are cases where the minute figure constitutes a part of the auxiliary pattern added to the design device pattern 61 by the OPC processing and constitutes a part of the design device pattern 61. According to the above-described embodiment, since the minute figure that should increase the amount of electron beam irradiation is selected based on the size of the figure, the mask pattern 62 after OPC processing is faithfully reproduced in either case. A mask pattern is formed on the mask substrate 51.

  Although the case where the plurality of figures constituting the first electron beam irradiation pattern 63 are rectangular has been described, the plurality of figures may be other shapes such as a trapezoid in the above embodiment.

FIG. 1 is a flowchart showing a method for manufacturing a semiconductor device. FIG. 2 is a flowchart showing a mask manufacturing process. FIG. 3 is an explanatory diagram of the HAT process. FIG. 4 is an explanatory diagram of the serif process. FIG. 5 is an explanatory diagram of the OPC process. FIG. 6 is an explanatory diagram of data conversion processing. FIG. 7 is a perspective view showing an optical system of the electron beam exposure apparatus. FIG. 8 is a functional block diagram of the semiconductor manufacturing apparatus according to the first embodiment of the present invention. FIG. 9 is a flowchart showing a mask manufacturing process according to the first embodiment. FIG. 10 is an explanatory diagram of the minute figure extraction process. FIG. 11 is a functional block diagram of a semiconductor manufacturing apparatus according to the second embodiment of the present invention. FIG. 12 is a flowchart showing a mask manufacturing process according to the second embodiment. FIG. 13 is an explanatory diagram of the difference processing. FIG. 14 is a plan view showing an exposure region on the mask substrate. FIG. 15 is a graph showing the energy intensity distribution on the mask substrate. FIG. 16 is a graph showing the relationship between the size of the exposure area and the energy intensity. FIG. 17 is a plan view showing an exposure region on the mask substrate. FIG. 18 is a graph showing the relationship between the size of the exposure area and the size of the mask pattern.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor manufacturing apparatus 2 ... Information processing apparatus 21 ... OPC process part 22 ... Data conversion part 23 ... Minute figure extraction part 24 ... Difference process part 3 ... Electron beam exposure apparatus 31 ... Control apparatus 32 ... Electron gun 33 ... 1st aperture 34 ... Forming deflector 35 ... Second aperture 36 ... Stage 37 ... Blanking electrode 38 ... Blanking aperture 41 ... Device pattern design data (mask pattern data before OPC processing)
42 ... Mask pattern data 43 after OPC processing 43 ... First electron beam irradiation data 44 ... Second electron beam irradiation data 45 ... Third electron beam irradiation data 47 ... First control signal 48 ... Second control signal 49 ... Third control signal 50 ... Electron beam 51 ... Mask substrates 52, 52a, 52b, 53, 54 ... Exposure region 55 ... Mask pattern 61 ... Design device pattern (mask pattern before OPC processing)
62 ... Mask pattern 63, 64, 65 after OPC processing ... Electron beam irradiation pattern 71, 74 ... Design device pattern (mask pattern before OPC processing)
72, 75 ... photosensitive device pattern 73, 76 ... mask pattern after OPC processing

Claims (8)

  1. Extracting a minute figure smaller than a predetermined size from a plurality of figures constituting a pattern;
    Irradiating an electron beam shaped so as to correspond to each of the plurality of figures to a figure area corresponding to each of the figures on a substrate;
    In the extracting step, the size of the minute figure is compared with the predetermined size;
    In the step of irradiating, the irradiation amount per unit area for irradiating the minute figure region corresponding to the minute figure on the substrate with the electron beam shaped to correspond to the minute figure is the number of the plurality of figures. More than the irradiation amount per unit area for irradiating the non-micro graphic region corresponding to the non-micro graphic on the substrate with the electron beam formed so as to correspond to the non-micro graphic not extracted in the extracting step Production method.
  2. The irradiating step comprises:
    Irradiating the figure region with an electron beam shaped to correspond to each based on the first electron beam irradiation data representing the plurality of figures;
    2. The method of manufacturing a semiconductor device according to claim 1, further comprising: irradiating the minute figure region with an electron beam shaped so as to correspond to the minute figure based on second electron beam irradiation data representing the minute figure.
  3. Generating third electron beam irradiation data representing the non-micro figure based on the first electron beam irradiation data representing the plurality of figures and the second electron beam irradiation data representing the micro figures,
    The irradiating step comprises:
    Irradiating the minute region with a first dose by an electron beam shaped to correspond to the minute figure based on the second electron beam irradiation data;
    Irradiating the non-micrographic region with an electron beam shaped so as to correspond to the non-micro figure based on the third electron beam irradiation data by a second irradiation amount smaller than the first irradiation amount. A manufacturing method of a semiconductor device according to Item 1.
  4. Generating the first electron beam irradiation data from pattern data representing the pattern,
    The method of manufacturing a semiconductor device according to claim 2, wherein in the generating step, the pattern is divided into the plurality of figures.
  5. The plurality of figures are a plurality of rectangles;
    5. The method of manufacturing a semiconductor device according to claim 1, wherein in the extracting step, a length of a side of the minute figure is compared with a reference dimension.
  6. A micro figure extraction unit that extracts micro figures smaller than a predetermined size from a plurality of figures constituting a pattern;
    An electron beam exposure apparatus that irradiates a figure region corresponding to each of the electron beams formed on the substrate with an electron beam shaped so as to correspond to each of the plurality of figures;
    The minute figure extraction unit compares the size of the minute figure with the predetermined size,
    The electron beam exposure apparatus is configured to calculate an irradiation amount per unit area for irradiating a minute figure region corresponding to the minute figure on the substrate with an electron beam shaped to correspond to the minute figure among the plurality of figures. More than the irradiation amount per unit area for irradiating the non-micro graphic area corresponding to the non-micro graphic on the substrate with the electron beam shaped to correspond to the non-micro graphic not extracted by the micro graphic extracting unit Semiconductor manufacturing equipment.
  7. The electron beam exposure apparatus comprises:
    Based on the first electron beam irradiation data representing the plurality of figures, the figure region on the substrate is irradiated with the electron beam formed to correspond to each of the figures,
    The semiconductor manufacturing apparatus according to claim 6, wherein an electron beam shaped so as to correspond to the minute figure is irradiated on the minute figure region based on second electron beam irradiation data representing the minute figure.
  8. A data generation unit configured to generate third electron beam irradiation data representing the non-micro figure based on the first electron beam irradiation data representing the plurality of figures and the second electron beam irradiation data representing the minute figure; ,
    The electron beam exposure apparatus comprises:
    Based on the second electron beam irradiation data, the electron beam shaped to correspond to the minute figure is irradiated to the minute region by the first dose,
    7. The semiconductor according to claim 6, wherein, based on the third electron beam irradiation data, an electron beam shaped so as to correspond to the non-microscopic figure is irradiated to the non-micrographic area by a second irradiation amount smaller than the first irradiation amount. Manufacturing equipment.
JP2007166541A 2007-06-25 2007-06-25 Method and apparatus of manufacturing semiconductor device Pending JP2009004699A (en)

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