JP5385722B2 - Interface circuit - Google Patents

Description

  The present invention relates to an interface circuit having a function of automatically switching between two types of standard protocols used in various electronic devices.

FIG. 5 is a block diagram of the electronic device 100 which is a slave device capable of serial communication with a master device (not shown) using a general-purpose SPI interface developed by Motorola.
The slave device 100 is connected to a selection signal line 102, a clock line 106, and a data line 104 as shown in FIG. A selection signal CSB for selecting the slave device 100 from the master device is supplied to the selection signal line 102. A serial clock SCL is supplied to the clock line 106 from the master device. The data line 104 is used for exchanging data SDA when performing bidirectional communication with the master device.

In the slave device 100 having such a configuration, communication is performed at the timing shown in FIG. That is, after the selection signal CSB transitions from “high level” to “low level”, the data SDA is supplied in synchronization with the clock SCL.
FIG. 7 is a block diagram of an electronic device 300 that is a slave device capable of bidirectional communication with a master device (not shown) using a general-purpose I2C interface developed by Philips. .

As shown in FIG. 7, the slave device 300 is connected to a bidirectional bus including a clock line 304 and a data line 302. A serial clock SCL is supplied to the clock line 304 from the master device. Data line 302 is used to exchange data SDA when performing bidirectional communication with the master device.
In the slave device 300 having such a configuration, communication is performed at the timing shown in FIG.

  That is, in this communication, a unique state occurs in which the communication start is the data transfer start “START” and the end is the data transfer end “STOP”. The data transfer start “START” is a transition from the clock SCL to “high level” and the data SDA from “high level” to “low level”. On the other hand, the data transfer completion “STOP” is a transition from the clock SCL to “high level” and the data SDA from “low level” to “high level”. After the start of data transfer “START”, data SDA is supplied in synchronization with the clock SCL.

Here, an electronic apparatus having both functions of an SPI interface and an I2C interface and automatically switching between these functions and an automatic switching method of the functions are known (for example, see Patent Document 1).
FIG. 9 is a block diagram of an electronic device described in Patent Document 1 that automatically switches a conventional interface protocol.
The electronic device 500 is connected to a selection signal line 502, a clock line 506, and a data line 504.

The selection signal line 502 is supplied with a selection signal CSB for selecting the electronic device 500 that is a slave device from the master device. A clock SCL is supplied to the clock line 506 from the master device. The data line 504 is used to exchange data SDA when performing bidirectional communication with the master device.
Such an electronic apparatus 500 is configured to automatically switch the functions of the SPI interface and the I2C interface according to the polarity of the selection signal CSB, in other words, the level of the selection signal CSB. That is, when the selection signal CSB is “low level”, the SPI interface is selected, and when the selection signal CSB is “high level”, the I2C interface is selected.

FIG. 10 is a flowchart of data transmission / reception regarding a method of switching between two protocols described in Patent Document 1, and an operation procedure of the electronic apparatus 500 will be described below.
In step S1, the master apparatus supplies “high level” on the selection signal 502, the data line 504, and the clock line 506, so that the electronic apparatus 500 sets the interface to the I2C mode as a default (standard operation). In step S2, the electronic device 500 monitors the interface for input signals. In step S <b> 3, the electronic apparatus 500 detects whether or not the selection signal CSB on the selection signal line 502 has transitioned from “high level” to “low level”.

  If no transition of the selection signal CSB to “low level” is detected in step S3, the process proceeds to step S8. In step S8, the electronic apparatus 500 determines whether or not there is a transition in the data transfer start “START” for the data SDA on the data line 504. If the result of this determination is that there is no such transition, processing returns to step S2, and if there is such transition, processing proceeds to step S9. In step S9, the electronic apparatus 500 performs a read operation or a write operation in the I2C mode, and returns to step S2 after the end of the execution.

  On the other hand, when the transition of the selection signal CSB to “low level” is detected in step S3, the process proceeds to the next step S4. In step S4, the electronic apparatus 500 sets the interface to operate in the SPI mode. In step S5, the electronic apparatus 500 performs a read operation or a write operation in the SPI mode. When the electronic device 500 detects the transition to “high level” of the selection signal CSB on the selection signal line 502 in step S6, the electronic device 500 sets the interface to the I2C mode in step S7, and returns to step S2.

In a communication system that performs communication with a master device using the electronic device 500 as a slave device as shown in FIG. 9, it is required that one master device controls active / inactive of a large number of electronic devices. FIG. 11 is a block diagram showing an example of such a communication system.
The communication system of FIG. 11 includes one master device 702 and four electronic devices 704, 706, 708, and 710 functioning as slave devices, and the master device 702 is selectively connected to one of the four electronic devices. Two-way communication.

  Therefore, the master device 702 and the four electronic devices 704, 706, 708, and 710 are connected by a common clock line 720 that transfers the clock SCL and a common data line 722 that transfers the data SDA. The master device 702 and the electronic devices 704, 706, 708, and 710 are connected by independent selection signal lines 724, 726, 728, and 730. For the active / inactive control of any of the electronic devices 704, 706, 708, and 710 in communication based on the SPI protocol performed with the master device 702, the selection signals CSB1, CSB2, CSB3, and CSB4 are used. Is used.

FIG. 12 is a block diagram of a communication system in which one master device 802 selectively performs bidirectional communication with two electronic devices 804 and 806.
In this communication system, when the master device 802 transmits / receives data to / from the electronic device 804 according to the SPI protocol, the clock SCL on the clock line 814, the data SDA on the data line 812, and the selection on the selection signal line 810 Signal CSB1 is used. The selection signal CSB1 on the selection signal line 810 is “low level”, and the selection signal CSB2 on the selection signal line 816 is “high level”.
At this time, the SPI interface is set for the electronic device 804, and the I2C interface is set for the electronic device 806. The transmission / reception data SDA on the data line 812 to the electronic device 804 and the clock SCL on the clock line 814 are also input to the electronic device 806.

At this time, when the selection signal CSB2 is “high level”, the clock SCL is “high level”, and the transmission / reception data SDA is changed from “high level” to “low level”, the electronic device 806 has the I2C interface. The data transfer start “START” is recognized (see FIG. 8), and the read operation and the write operation are started in the I2C mode.
As described above, the clock SCL and the transfer data SDA cause a malfunction in which the electronic device 806 starts a read operation or a write operation in the I2C mode. Furthermore, a problem that data transmission / reception to the electronic device 804 is disturbed occurs.

Although FIG. 12 shows an example of data transmission / reception using two electronic devices, such a malfunction is the same when a large number of electronic devices are controlled as shown in FIG.
Such a malfunction occurs, for example, when the electronic device 806 does not recognize the data transfer start “START”, that is, when the clock SCL is “high level” and the transmission / reception data SDA transitions from “high level” to “low level”. This can happen even if the master device 802 issues a signal so that there is no such thing. The reason for this will be described below with reference to the drawings.

FIG. 13 shows an outline of an internal circuit of the electronic device of FIG. 12, and includes an interface core circuit 906 and a start / stop determination circuit 908.
In the electronic device 904 shown in FIG. 13, the start / stop determination circuit 908 recognizes the data transfer start “START” based on the data SDA on the data line 812 and the clock SCL on the clock line 814, and generates a start determination signal. . Using this start determination signal and the selection signal CSB on the selection signal line 810, the determination processing of steps S3 and S8 in the flowchart of FIG. 10 is performed. Based on these determination processes, the interface core circuit 906 performs a read operation or a write operation in the I2C mode or the SPI mode (steps S5 and S9 in FIG. 10).

Here, the clock SCL on the clock line 814 and the data SDA on the data line 812 transferred from the master device 802 to the electronic device 904 are, for example, immediately after the master device 802 is generated, for example, FIG. The timing is as shown in B).
However, the clock SCL and data SDA are delayed from the master device 802 to the start / stop determination circuit 908. The cause of this delay is a delay caused by an internal circuit (in FIG. 13, this delay is represented by resistors 914 and 916) or a delay caused by wiring (in FIG. 13, this delay is represented by resistors 910 and 912). There is.

  When the delay of the data SDA is larger than the delay of the clock SCL (the delay of the data SDA> the delay of the clock SCL), the clock SCL and the data SDA are as shown in FIGS. For this reason, the start / stop determination circuit 908 recognizes the data transfer start “START” and generates a start determination signal. As a result, the electronic device 904 malfunctions to start a read operation or a write operation in the I2C mode.

JP 2002-232508 A

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a slave device when a master device uses a common signal line for data and clocks with a plurality of slave devices and selects one of a plurality of protocols for communication. It is an object of the present invention to provide an interface circuit or the like that can prevent malfunction of the device.

In order to solve the above-described problems and achieve the object of the present invention, each invention has the following configuration.
A first invention is a first mode in which communication based on a first protocol is performed between a master device and a slave device using a clock, data, and a selection signal of the slave device, and the master device and the slave An interface circuit for switching between a second mode in which communication based on a second protocol is performed with a device using a clock and data, wherein the clock is at a high level and the data is switched from a high level to a low level. A determination means for determining a state that changes to a level, and generating a determination signal; detecting a change in a predetermined signal used in the first protocol; and operating when detecting a first protocol operation a movement detecting means for generating a detection signal, when the motion detection signal is generated, irrespective of the generation of the determination signal, said second mode Comprising a limiting means for generating a signal for limiting the transmission and reception of data in the de, a.

In a second aspect based on the first aspect, the operation detection means includes a counter that counts the clock and generates a predetermined signal used in the first protocol based on the count.
According to a third invention, in the first or second invention, the motion detection means includes a flip-flop that generates the motion detection signal using a signal used for the first protocol as a trigger.
A fourth invention is an electronic device including an interface circuit, and the interface circuit is any one of the first to third inventions.

According to a fifth aspect of the present invention, there is provided a first mode for performing communication based on a first protocol using a clock, data, and a selection signal of the slave device between the master device and the slave device, and the master device and the slave. a second mode for performing communication based on a second protocol using a clock and data to and from the device, a method for switching, the presence of transition to Ha Irebe Le Kararo Rebe Le of said selection signals a first step of detecting, in said first step, when it is detected that there is a transition to Ha Irebe Le Kararo Rebe Le of the selection signals, restriction flag for restricting the operation according to the second mode In the first step, the second step in which the slave device executes the operation in the first mode and returns to the first step after the end of the execution. When it is detected that there is no transition to Ha Irebe Le Kararo Rebe Le of the selection signal, and a third step of determining whether the transition of the start of transfer of the data, in the third step, the data If it is determined that there is a transfer start transition, it is determined whether or not the limit flag is set. If it is determined that the limit flag is set, the process returns to the first step, and And a fourth step in which the slave device performs an operation in the second mode and returns to the first step after completion of execution when it is determined that the restriction flag is not set.

  According to the present invention having such a configuration, when a master device uses a common signal line for data and clocks with a plurality of slave devices and selects one of a plurality of protocols for communication. Thus, malfunction of the slave device can be prevented.

It is a block diagram which shows an example of the electronic device to which embodiment of the interface circuit of this invention is applied. It is a flowchart explaining the operation example of embodiment of the interface circuit of this invention. FIG. 2 is a block diagram illustrating a configuration of an electronic device that embodies the configuration of the SPI operation detection circuit of FIG. 1. FIG. 4 is a timing chart for explaining an example of waveforms at various parts during operation of the embodiment of FIG. 3. FIG. It is a block diagram of the electronic device which can send and receive data by SPI protocol. It is a timing chart of transmission / reception of data according to the SPI protocol. It is a block diagram of an electronic device capable of transmitting and receiving data according to the I2C protocol. It is a timing chart of transmission / reception of data according to the I2C protocol. It is a block diagram of the electronic device which switches automatically transmission / reception of both data of SPI and I2C protocol. It is a flowchart which shows the operation | movement of transmission / reception of the data according to both SPI and I2C protocol. It is a block diagram which shows the communication system between a master apparatus and several electronic devices. It is a block diagram which shows the communication system between a master apparatus and two electronic devices. It is a block diagram explaining the internal circuit of an electronic device, the wiring delay etc. which arise in the design of an electronic device, or construction of a communication system. FIG. 14 is a timing chart for explaining a problem caused by a wiring delay according to FIG. 13.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment of interface circuit)
FIG. 1 is a block diagram showing an example of an electronic device to which the interface circuit of the present invention is applied.
The embodiment according to the interface circuit is applied to various electronic devices 1100 that perform bidirectional communication with a master device (not shown).
The electronic device 1100 has an SPI mode for performing communication based on the SPI protocol with a master device (not shown), and an I2C mode for performing communication based on the I2C protocol with the master device. Communication is performed in the two modes, and the two modes are automatically switched by the interface circuit.

Therefore, the electronic device 1100 includes at least an interface core circuit 1102, a start / stop determination circuit 1104, an SPI operation detection circuit 1106, an inverter circuit 1109, and an OR circuit 1108, as shown in FIG. An embodiment of an interface circuit of the present invention is configured.
The interface core circuit 1102 performs various processes and operations as shown in FIG. 2 in order to automatically switch data transmission / reception according to the SPI protocol and the I2C protocol with a master device (not shown).

  The interface core circuit 1102 is connected to a master device (not shown) through a selection signal line 1110, a data line 1112, and a clock line 1114. A selection signal for selecting the electronic device 1100 from the master device is supplied to the selection signal line 1110. The data line 1112 is used for data SDA transfer. A clock CSB is supplied to the clock line 1114 from the master device.

The start / stop determination circuit 1104 monitors the data SDA on the data line 1112 and the clock SCL on the clock line 1114, determines the presence / absence of the data transfer start “START” based on this, generates a start determination signal, and outputs it To do. The start determination signal becomes, for example, “high level” when it is determined that there is a data transfer start “START”.
The SPI operation detection circuit 1106 detects a change in polarity (level change) of a predetermined signal used in the SPI protocol, and outputs an operation detection signal I2CDIS during the SPI protocol operation. The operation detection signal I2CDIS becomes, for example, “high level” during the SPI protocol operation.

The logical value of the start determination signal output from the start / stop determination circuit 1104 is inverted by the inverter circuit 1109, and the inverted signal is input to the OR circuit 1108. The OR circuit 1108 performs a logical OR operation between the output signal of the inverter circuit 1109 and the operation detection signal I2CDIS output from the SPI operation detection circuit 1106, and outputs the result.
As described above, in this embodiment, when the SPI operation detection circuit 1106 detects the access of the SPI protocol, the operation detection signal I2CDIS becomes “high level” and the presence / absence of the start determination signal output from the start / stop determination circuit 1104 Regardless, the limit signal output from the OR circuit 1108 becomes “high level”. Therefore, when the interface core circuit 1102 operates with the SPI protocol, the operation with the I2C protocol is limited.

(Operation example of embodiment)
Next, an operation example of the embodiment having such a configuration will be described with reference to the flowchart of FIG.
In step S21, the master device supplies “high level” on the selection signal line 1110, the data line 1112, and the clock line 1114, so that the interface core circuit 1102 sets the interface to the I2C mode as a default (standard operation). Set. In step S22, the interface core circuit 1102 sets the operation detection signal I2CDIS to “low level”. Thereby, both the SPI protocol and the I2C protocol can be selected at the start of operation.

In step S23, the interface core circuit 1102 monitors the interface for input signals. In step S24, the interface core circuit 1102 detects whether or not the selection signal CSB on the selection signal line 1110 has transitioned from “high level” to “low level”.
If a transition from “high level” to “low level” of the selection signal CSB is detected in step S24, the process proceeds to the next step S25. In step S25, the interface core circuit 1102 sets the interface to operate in the SPI mode. In step S26, the interface core circuit 1102 sets the operation detection signal I2CDIS to “high level”. With this setting, data transfer from the master device to the electronic device 1100 can use only the SPI protocol.

In step S27, the interface core circuit 1102 performs a read operation or a write operation in the SPI mode. When the interface core circuit 1102 detects a rising edge of the selection signal CSB on the selection signal line 1110 in step S28, the interface core circuit 1102 sets the interface to the I2C mode in step S29, and returns to step S23.
On the other hand, when a transition from “high level” to “low level” of the selection signal CSB is not detected in step S24, the process proceeds to step S30. In step S30, the interface core circuit 1102 determines whether or not there is a transition in the data transfer start “START” for the data SDA on the data line 1110. If the result of this determination is that there is no such transition, processing returns to step S23, and if there is such transition, processing proceeds to step S31.

In step S31, the interface core circuit 1102 determines whether or not the operation detection signal I2CDIS is “low level”.
As a result of this determination, when it is determined that the operation detection signal I2CDIS is not “low level”, that is, when it is determined that the operation detection signal I2CDIS is “high level” and data transfer is based on the SPI protocol, The process returns to step S23.
On the other hand, if it is determined in step S31 that the operation detection signal I2CDIS is “low level”, the process proceeds to step S32. In step S32, the interface core circuit 1102 performs a read operation or a write operation in the I2C mode, and returns to step S23 after the end of the execution.

FIG. 3 is a block diagram showing the configuration of the electronic apparatus 1100 that embodies the configuration of the SPI operation detection circuit 1106 of FIG.
The SPI operation detection circuit 1106 assumes an SPI protocol that transmits and receives an 8-bit address and 8-bit data in 16 bits. As shown in FIG. 3, the SPI operation detection circuit 1106 includes a counter 1116 and a flip-flop 1118. I have.
The counter 1116 is a 5-bit counter [4: 0] for changing the state according to the number of edges of the clock SCL supplied to the interface core circuit 1102, that is, a 5-bit counter that performs a counting operation in synchronization with the edges. is there. The flip-flop 1118 uses the value of the MSB bit (most significant bit) of the 5-bit counter 1116 as its clock.
Note that, in the electronic device 1100 in FIG. 3, the configuration of parts other than the counter 1116 and the flip-flop 1118 is substantially the same as the configuration of the electronic device in FIG.

Next, an operation example of the embodiment of the interface circuit shown in FIG. 3 will be described with reference to FIG.
FIG. 4 is a timing chart of the input signal of the SPI protocol.
The counter 1116 performs a counting operation in synchronization with the rising edge of the clock SCL input according to the SPI protocol (see FIGS. 4B and 4D). The value of the MSB bit of the counter 1116 changes from “low level” to “high level” in synchronization with the 16th rising edge of the clock SCL (see FIGS. 4B and 4E). Since the value of the MSB bit of the counter 1116 is input to the flip-flop 1118, the operation detection signal I2CDIS output from the flip-flop 1118 changes from “low level” to “high level” (FIGS. 4E and 4F). See).
The OR circuit 1108 performs an OR operation between the output signal of the inverter circuit 1109 and the operation detection signal I2CDIS output from the flip-flop 1118, and outputs the result. For this reason, the OR circuit 1108 outputs a limiting signal for limiting the operation of the interface core circuit 1102 according to the I2C protocol.

That is, when the counter 1116 and the flip-flop 1118 detect access of the SPI protocol, the operation detection signal I2CDIS output from the flip-flop 1118 becomes “high level”. As a result, the output signal of the OR circuit 1108 becomes “high level” regardless of the presence or absence of the start determination signal output from the start / stop determination circuit 1104. Therefore, when the interface core circuit 1102 operates with the SPI protocol, the operation with the I2C protocol is limited.
As described above, in this embodiment, when the master device wants to send / receive data to / from the electronic device 1100 in accordance with the SPI protocol, the electronic device 1100 automatically performs the reading operation and the writing operation in the I2C mode. Since it becomes invalid, the operation in the SPI mode can be secured.

(Modification of SPI operation detection circuit)
In FIG. 3, the SPI operation detection circuit is configured by the counter 1116 and the flip-flop 1118 and generates the operation detection signal I2CDIS, but is not limited to such a configuration.
The trigger of the flip-flop 1118 uses the MSB bit of the counter 1118, but this is not limited to the MSB bit of the counter 1118, and is not limited to the counter 1118.
As the trigger of the flip-flop 1118, for example, the value of the LSB bit of the counter 1118 or a signal that detects the transition from the “high level” to the “low level” of the selection signal CSB on the selection signal line 1110 can be used. .
In other words, the SPI operation detection circuit only needs to be able to generate the operation detection signal I2CDIS by detecting a predetermined signal whose polarity changes only by SPI access and using it as a trigger for the flip-flop 1118 based on this signal. .

  The interface circuit of the present invention can be applied when connected to, for example, an AD converter, a DA converter, or a communication IC.

DESCRIPTION OF SYMBOLS 1100 ... Electronic device 1102 ... Interface core circuit 1104 ... Start stop determination circuit 1106 ... SPI operation detection circuit 1108 ... OR circuit 1109 ... Inverter circuit 1110 ... Selection signal line 1112- ..Data line 1114 ... clock line 1116 ... counter 1118 ... flip-flop

Claims (5)

A first mode for performing communication based on a first protocol using a clock, data, and a selection signal of the slave device between the master device and the slave device, and a clock between the master device and the slave device And an interface circuit that switches between a second mode for performing communication based on the second protocol using data,
Determination means for determining a state in which the clock is at a high level and the data changes from a high level to a low level, and generating a determination signal;
An operation detection means for detecting a change in a predetermined signal used in the first protocol and generating an operation detection signal when detecting a change in the first protocol operation ;
Limiting means for generating a signal for limiting transmission and reception of data in the second mode regardless of the generation of the determination signal when the operation detection signal is generated ;
An interface circuit comprising: The motion detection means is
The interface circuit according to claim 1, further comprising: a counter that counts the clock and generates a predetermined signal used for the first protocol based on the count. The motion detection means is
The interface circuit according to claim 1, further comprising: a flip-flop that generates the operation detection signal using a signal used for the first protocol as a trigger. An electronic device comprising an interface circuit,
The electronic device according to claim 1, wherein the interface circuit is the interface circuit according to claim 1. A first mode for performing communication based on a first protocol using a clock, data, and a selection signal of the slave device between the master device and the slave device, and a clock between the master device and the slave device And a second mode for performing communication based on the second protocol using data,
A first step of detecting the presence or absence of transition to Ha Irebe Le Kararo Rebe Le of said selection signal,
In the first step, when it is detected that there is a transition to Ha Irebe Le Kararo Rebe Le of the selection signal, to set the restriction flag for restricting the operation according to the second mode, the slave device A second step of performing an operation in the first mode and returning to the first step after completion of execution;
In the first step, when the transition to Ha Irebe Le Kararo Rebe Le of the selection signal is detected that there is no, and the third step determines the presence or absence of transitions of the start of transfer of said data,
In the third step, when it is determined that there is a transition of the data transfer start, it is determined whether or not the limit flag is set, and when it is determined that the limit flag is set, Returning to the first step, if it is determined that the restriction flag is not set, the slave device executes the operation in the second mode, and returns to the first step after the execution is completed. 4 steps,
A method for switching protocols, comprising:

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