JP5384556B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device that performs ion implantation before a silicide process.

  Silicide processing is generally performed on the gate, source, and drain electrodes of MISFETs (Metal Insulator Semiconductor Field Effect Transistors) formed on a semiconductor substrate and contact areas of other wirings to reduce resistance. Is called. As a metal used for silicidation, Co, Ni, or the like is employed.

  For example, in Non-Patent Document 1 below, it is reported that leakage current can be suppressed if fluorine is ion-implanted in advance into a region to be silicided.

M. Tsuchiaki et al., `` Suppression of Thermally Induced Leakage of NiSi-Silicided Shallow Junctions by Pre-Silicide Fluorine Implantation '' Japanese Journal of Applied Physics Vol.44, No.4A, 2005, pp.1673-1681

  In Non-Patent Document 1, it is reported that fluorine implantation into a region to be silicided is effective even when a CMOS (Complementary MOS) structure is formed, and that leakage current can be suppressed. However, as a result of experiments by the inventors of the present application, it was confirmed that the leakage current was increased in the P-channel MISFET, although the leakage current suppression effect was observed in the N-channel MISFET.

  The present invention has been made in view of the above circumstances, and realizes a semiconductor device that performs ion implantation before a silicide process and that can more reliably suppress leakage current in a MISFET.

An aspect of the semiconductor device according to the present invention is a semiconductor device having a CMOS structure including a P-channel MISFET and an N-channel MISFET formed on a semiconductor substrate, wherein the P-channel MISFET is formed on the semiconductor substrate. A first gate insulating film; a first gate electrode formed on the first gate insulating film; and a first insulating film formed on a side surface of the first gate electrode and on the semiconductor substrate. A first sidewall, a second sidewall formed on the side surface of the first gate electrode and on the semiconductor substrate via the first sidewall and made of a second insulating film, and formed on the semiconductor substrate A P-type source region and a P-type drain region formed on the P-type source region and the P-type drain region; The N channel MISFET includes a second gate insulating film formed on the semiconductor substrate, a second gate electrode formed on the second gate insulating film, and the second gate. A third sidewall formed on the side surface of the electrode and on the semiconductor substrate and made of the first insulating film; and on the side surface of the second gate electrode and on the semiconductor substrate via the third sidewall. A fourth sidewall formed of the second insulating film, an N-type source region and an N-type drain region formed on the semiconductor substrate, and on the N-type source region and the N-type drain region. and a formed second silicide regions in said N-channel type MISFET, the height of the third side wall from the semiconductor substrate, from the semiconductor substrate The height of the first sidewall from the semiconductor substrate is higher than the height of the second sidewall from the semiconductor substrate in the P-channel MISFET. In the N-channel MISFET, the maximum distance of the fourth sidewall from the side surface of the second gate electrode and the maximum distance of the third sidewall from the side surface of the second gate electrode The difference Bn is smaller than the difference An between the height of the third sidewall from the semiconductor substrate and the height of the fourth sidewall from the semiconductor substrate. In the P-channel MISFET, the difference Bn is A maximum distance of the second sidewall from a side surface of the first gate electrode; and a first distance from the side surface of the first gate electrode. The difference Bp from the maximum distance of the idwall is smaller than the difference Ap between the height of the first sidewall from the semiconductor substrate and the height of the second sidewall from the semiconductor substrate.

  According to the aspect of the semiconductor device according to the present invention, when silicidation is performed, the silicidation regions in the N-type source region and the N-type drain region do not easily enter the vicinity of the channel, and the leakage current in the MISFET is more reliably suppressed. A semiconductor device capable of achieving the above can be realized.

It is sectional drawing of the semiconductor device which can apply this invention. It is a top view of the semiconductor device which can apply this invention. It is a figure which shows each process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows each process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows each process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows each process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows each process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows each process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a figure which shows each process of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a graph which shows the result of having measured the substrate leakage current about many N channel type MISFET which performed Ni silicide in the source region and the drain region after performing fluorine implantation or silicon implantation beforehand. It is sectional drawing which shows the structure of the semiconductor device based on this invention after washing | cleaning. It is sectional drawing which shows the structure of the semiconductor device after washing | cleaning in case there is no ion implantation. It is a graph which shows the relationship between the implantation amount of a fluorine ion or a silicon ion, and the etching amount of the TEOS oxide film and silicon nitride film at the time of cleaning. It is a graph which shows the result of having measured the sheet resistance of the gate electrode about many N channel type MISFETs which performed silicidation after performing fluorine implantation beforehand. It is a graph which shows the result of having measured the substrate leakage current about many P channel type MISFET which performed Ni silicide in the source region and drain region after performing fluorine implantation beforehand. It is a figure which shows the MISFET manufacturing process in case drain-body off-leakage current Ioffb deteriorates. It is a figure which shows the MISFET manufacturing process in case drain-body off-leakage current Ioffb deteriorates. It is a figure which shows the MISFET manufacturing process in case drain-body off-leakage current Ioffb deteriorates.

  FIG. 15 shows the results of measurement of drain-body off-leakage current (substrate leakage current) Ioffb for a number of P-channel MISFETs in which the source region and the drain region were Ni-silicided after fluorine implantation was performed in advance. It is a graph.

In FIG. 15, the vertical axis represents the quantile (value “0” is the mode value) in the normal distribution measurement result of all P-channel MISFETs, and the horizontal axis represents the substrate leakage current value (arbitrary unit). . In the middle of the three measurement results in the graph, the source region and the drain region are Ni-silicided after performing fluorine implantation under the conditions of 5 [keV] and 1 × 10 ¹⁵ [cm ⁻² ]. The results on the right side of the graph are the results of Ni-silicidation of the source region and the drain region after fluorine implantation under the conditions of 5 [keV] and 6 × 10 ¹⁴ [cm ⁻² ], The leftmost one in the graph shows reference values when the source region and the drain region are Ni-silicided without fluorine implantation.

  As can be seen from FIG. 15, the value of the drain-body off-leakage current (substrate leakage current) Ioffb is obtained when the source region and the drain region are Ni-silicided without performing fluorine implantation (the measurement result on the leftmost side in the graph). Is lower. That is, in the case of a P-channel type MISFET, it can be said that pre-implantation of fluorine into the region to be silicided has an adverse effect on leakage current suppression.

  Further, in the N-channel MISFET, even when fluorine is previously implanted into a region to be silicided, the drain-body off-leakage current Ioffb may increase depending on the structure of the MISFET. 16 to 18 are diagrams showing a MISFET manufacturing process when the drain-body off-leak current (substrate leak current) Ioffb deteriorates.

  As shown in FIG. 16, among the sidewall insulating films SW1 and SW2 formed on the semiconductor substrate SB, the first sidewall insulating film SW1 is a TEOS (tetraethoxysilane) oxide film, and the sidewall insulating film SW2 is silicon. Nitride films are often formed. In the case of this structure, if the vicinity of the silicidation region surface is cleaned with hydrofluoric acid or the like (light wet etching) immediately before silicidation, the first sidewall insulating film SW1 is etched, and the first sidewall insulating film SW1 is exposed. The parts AR1 and AR2 are easily retracted.

  Thereafter, as shown in FIG. 17, a metal film MT of Ni or the like is formed on the entire surface, silicidation is performed, and the first annealing process, the removal of the unreacted portion of the metal film MT, and the second annealing process are performed. In this case, silicidation regions SCs and SCd are formed as shown in FIG. At this time, as shown in FIG. 17, since the metal film MT is formed around the recessed exposed portion AR2, the silicide regions SCs and SCd are formed closer to the channel.

  As a result, the drain-body off-leakage current Ioffb becomes larger as the retraction amount of the exposed portion AR2 increases. Therefore, with the structure as shown in FIG. 18, even if fluorine is previously implanted into the region to be silicided in the N channel MISFET, the effect of suppressing the leakage current is diminished.

  In the embodiment of the present invention, ions are implanted into the N-type source region and the N-type drain region of the N-channel MISFET while covering the P-channel MISFET with the mask layer, and then the N-channel MISFET and the P-channel type. A semiconductor device and a manufacturing method thereof for siliciding each gate electrode, source region, and drain region of a MISFET.

  1 and 2 are a cross-sectional view and a top view of a semiconductor device to which the present invention can be applied. 1 is a cross-sectional view taken along a cutting line II in FIG. FIG. 2 shows a semiconductor device in which each MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a gate electrode GE, a source region SE, and a drain region DE is separated by an element isolation film IS such as a silicon oxide film.

  As shown in FIG. 1, the semiconductor device includes a semiconductor substrate SB such as a silicon substrate, a stacked structure of a gate insulating film (for example, silicon oxide film) GI and a gate electrode (for example, polysilicon film) GE, and a source region. SE and MISFET formed on semiconductor substrate SB including drain region DE are provided. An element isolation film IS is formed outside the source region SE and the drain region DE.

  Silicided regions SCg, SCs, and SCd containing Ni (nickel), Co (cobalt), and the like are formed on the surfaces of the gate electrode GE, the source region SE, and the drain region DE, respectively. A first sidewall insulating film SW1 such as a TEOS oxide film is formed on the side surface of the stacked structure of the gate insulating film GI and the gate electrode GE and on part of the surface of the source region SE and the drain region DE. Has been. In addition, the silicon nitride film faces the side surface of the stacked structure of the gate insulating film GI and the gate electrode GE and part of the surface of the source region SE and the drain region DE through the first sidewall insulating film SW1. A second sidewall insulating film SW2 is formed.

  Note that the semiconductor device shown in FIG. 2 has a CMOS structure and includes both an N-channel MISFET and a P-channel MISFET. The structure of the MISFET shown in FIG. 1 is common to the N-channel MISFET and the P-channel MISFET, and both the channel MISFETs include a well (not shown) formed in the semiconductor substrate SB, a source region SE, The drain region DE has the same structure except that the conductivity type in each region is different. In FIG. 1, the drain-body off-leakage current (substrate leakage current) is indicated by a symbol Ioffb.

  3 to 9 are diagrams showing each step of the manufacturing method of the semiconductor device according to the embodiment of the present invention. A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

  First, as shown in FIG. 3, on the semiconductor substrate SB, a stacked structure of the gate insulating film GI and the gate electrode GE, the first sidewall insulating film SW1, the second sidewall insulating film SW2, and the LDD (Lightly Doped) of the source region. The MISFET including the drain region SE1 and the drain region LDD region DE1 is formed by using a photolithography technique, an etching technique, an ion implantation technique, and the like for each of the P channel type and the N channel type.

Next, as shown in FIG. 4, ion implantation IP1 is performed to form the source region SE2 and the drain region DE2. In forming the N-type source region and the N-type drain region, for example, As (arsenic) ions are used under the conditions of 5 to 50 [keV] and 1 × 10 ¹⁵ to 1 × 10 ¹⁶ [cm ⁻² ]. What is necessary is just to form by inject | pouring into SB. In forming the P-type source region and the P-type drain region, for example, B (boron) ions are applied under the conditions of 1 to 5 [keV] and 1 × 10 ¹⁵ to 1 × 10 ¹⁶ [cm ⁻² ]. What is necessary is just to form by inject | pouring into SB. Of course, since the semiconductor device according to the present invention has a CMOS structure, by using a photoresist as a mask, ion implantation for forming a source / drain of an N-channel MISFET and ions for forming a P-channel source / drain are performed. The injection may be selectively divided.

  Next, as shown in FIG. 5, an anti-silicidation film BL for covering a portion of the semiconductor substrate SB that should be prevented from silicidization covers the surfaces of the P-channel MISFET, the N-channel MISFET, and the semiconductor substrate SB. To form. As this silicidation preventing film BL, a USG (Undoped Silicate Glass) film formed by a CVD (Chemical Vapor Deposition) method at a film forming temperature of 400 ° C. may be employed.

  Then, anisotropic etching (dry etching) is selectively performed on the silicidation preventing film BL by using a photolithography technique and an etching technique, and a portion where the silicidation is to be prevented (for example, a contact region of the wiring) A portion (not shown) that is not desired to be silicided, the side of the stacked structure of the gate insulating film GI and the gate electrode GE of the P-channel type MISFET, and the gate insulating film GI and the gate electrode GE of the N-channel type MISFET An anti-silicidation film BL1 is left on the side of the stacked structure (FIG. 6).

Next, as shown in FIG. 7, a mask layer RM that selectively covers the P-channel MISFET without forming the N-channel MISFET is formed. A photoresist is employed for the mask layer RM, and this photoresist may be patterned. Then, while covering the P-channel MISFET with the mask layer RM, at least the N-type source region and the N-type drain region of the N-channel MISFET have fluorine ions (indicated as “F ⁺ ”) and / or silicon ions (“Si ⁺ ”). Injection IP2 is performed. The ion implantation IP2 may be performed under conditions of about 5 [keV] and about 6 × 10 ¹⁴ to 1 × 10 ¹⁵ [cm ⁻² ] in both cases of fluorine ions and silicon ions.

  The ion implantation IP2 is not limited to fluorine ions and silicon ions, but is at least one of fluorine, silicon, C (carbon), Ge (germanium), Ne (neon), Ar (argon), and Kr (krypton). It may be performed by implanting ions containing.

  Next, in order to remove the silicon oxide film generated on the surface of the semiconductor substrate SB and the surface of the gate electrode GE, a portion to be silicided is cleaned. In this cleaning step, cleaning using hydrofluoric acid may be performed in addition to RCA cleaning. In addition, pre-cleaning may be performed using a device in which a pre-cleaning (chemical dry cleaning) device and a sputtering device are integrated.

  At this time, the remaining silicidation preventing film BL1 and the portion to be silicidized are cleaned. By this cleaning, silicidation left on the side of the stacked structure of the gate insulating film GI and the gate electrode GE of the P-channel MISFET and on the side of the stacked structure of the gate insulating film GI and the gate electrode GE of the N-channel MISFET. The prevention film BL1 is removed. On the other hand, the silicidation preventing film BL1 (not shown) in the other portions is not completely removed by this cleaning, and remains as it is.

  Next, a metal film MT such as Ni is formed by sputtering or the like on the surface of the N channel MISFET, P channel MISFET, semiconductor substrate SB, and the remaining silicidation prevention film BL1 as shown in FIG. . Then, the first RTA (Rapid Thermal Annealing) is performed, and then the unreacted metal film MT is removed, and the second RTA is performed. As a result, silicidation occurs in the gate electrode of the N-channel type MISFET, the N-type source region and N-type drain region into which ions are implanted, and the gate electrode, P-type source region and P-type drain region of the P-channel type MISFET. As shown in FIG. 9, silicided regions SCg, SCs, and SCd are formed on the surfaces of the gate electrode GE, the source region SE, and the drain region DE, respectively.

  In addition to Ni, the metal film MT employs a metal film including at least one of Ni, Ti (titanium), Co (cobalt), Pd (palladium), Pt (platinum), and Er (erbium). May be.

  In the non-patent document 1, it has been reported that leakage current can be suppressed if fluorine is ion-implanted in advance in the region to be silicided, but the inventors of the present application are not limited to fluorine ions, but fluorine, silicon, Even when ions containing at least one of carbon, germanium, neon, argon, and krypton are implanted into the N-type source region and N-type drain region of the N-channel MISFET, the leakage current can be similarly suppressed. I found

  FIG. 10 shows drain-body off-leakage current (substrate leakage current) Ioffb for a number of N-channel MISFETs in which N-type source regions and N-type drain regions are Ni-silicided after fluorine implantation or silicon implantation has been performed in advance. It is a graph which shows the example of the result of having measured.

In FIG. 10, the vertical axis represents the quantile (value “0” is the mode value) in the normal distribution measurement result of all N-channel MISFETs, and the horizontal axis represents the substrate leakage current value (arbitrary unit). . In addition, the measurement result shown as “F, Si implantation” shows that the N-type source region and the N-type drain region are formed after fluorine implantation is performed under conditions of 5 [keV] and 1 × 10 ¹⁵ [cm ⁻² ]. As a result of Ni silicidation, fluorine implantation was performed under the conditions of 5 [keV] and 6 × 10 ¹⁴ [cm ⁻² ], and then the N-type source region and N-type drain region were Ni-silicided. ] And 1 × 10 ¹⁵ [cm ⁻² ] after silicon implantation, the N-type source region and the N-type drain region were Ni-silicided, and 5 [keV] and 6 × 10 ¹⁴ [ cm ⁻² ] shows the result of Ni-silicidation of the N-type source region and N-type drain region after silicon implantation, and the measurement result indicated as “Reference” indicates that N was not implanted with fluorine. Type source area The reference value when the region and the N-type drain region are Ni-silicided is shown.

  As can be seen from FIG. 10, the value of the drain-body off-leakage current (substrate leakage current) Ioffb is higher than that in the case where the source region and the drain region are Ni-silicided (“Reference”) without fluorine implantation. It is lower when the N-type source region and the N-type drain region are Ni-silicided after silicon implantation.

  On the other hand, in the present application, a mask RM is formed in a P-channel type MISFET in which fluorine injection into a region to be silicided has an adverse effect on leakage current suppression. Thereby, ion implantation of fluorine, silicon, or the like in advance into the region to be silicided is not performed.

  That is, according to the present invention, ions are implanted into the N-type source region and the N-type drain region of the N-channel MISFET while covering the P-channel MISFET with the mask layer RM. Thereafter, silicidation is performed on each gate electrode, source region, and drain region of the N-channel type MISFET and the P-channel type MISFET. In other words, in this application, ions are not implanted into the P-type source region and the P-type drain region of the P-channel type MISFET, and ions are implanted into the N-type source region and the N-type drain region of the N-channel type MISFET. Later, silicidation can be performed. As a result, the drain-body off-leakage current (substrate leakage current) Ioffb can be suppressed in the N-channel MISFET without degrading the drain-body off-leakage current Ioffb in the P-channel MISFET. Therefore, it is possible to realize a method for manufacturing a semiconductor device that can more reliably suppress the leakage current in the MISFET.

  Further, according to the present invention, the side of the stacked structure of the gate insulating film GI and the gate electrode GE of the P-channel MISFET and the side of the stacked structure of the gate insulating film GI and the gate electrode GE of the N-channel MISFET. The silicidation prevention film BL1 is left, and the remaining silicidation prevention film BL1 and the portion to be silicided are cleaned. Since the silicidation preventing film BL1 is left on the side of the laminated structure of the gate insulating film GI and the gate electrode GE, when the portion to be silicidized is cleaned, the gate insulating film GI and the gate electrode GE of the N channel MISFET Etching of the side wall insulating films SW1 and SW2 accompanying the laminated structure and the laminated structure of the gate insulating film GI and the gate electrode GE of the P-channel type MISFET is difficult. Accordingly, a method for manufacturing a semiconductor device is realized in which the silicide regions in the source region and the drain region of the N channel MISFET and the P channel MISFET do not easily enter the vicinity of the channel, and the leakage current in the MISFET can be more reliably suppressed. it can.

  FIG. 11 is a cross-sectional view showing the structure of the semiconductor device according to the present invention after cleaning. In FIG. 11, an N-channel MISFET is shown on the right side, and a P-channel MISFET is shown on the left side. In the N-channel MISFET of the structure of FIG. 11, the height of the first sidewall insulating film SW1 from the surface of the semiconductor substrate SB is higher than the height of the second sidewall insulating film SW2 from the surface of the semiconductor substrate SB. small. In the N channel MISFET, the maximum distance of the first sidewall insulating film SW1 from the side surface of the stacked structure of the gate insulating film GI and the gate electrode GE is from the side surface of the stacked structure of the gate insulating film GI and the gate electrode GE. This is smaller than the maximum distance of the second sidewall insulating film SW2. The difference Bn between the maximum distance from the gate side surface of the second sidewall insulating film SW2 and the maximum distance from the gate side surface of the first sidewall insulating film SW1 is the height of the first sidewall insulating film SW1 and the second side. It is smaller than the difference An from the height of the wall insulating film SW2.

  FIG. 12 is a cross-sectional view showing the structure of the N-channel MISFET after cleaning when no ion implantation is performed. In FIG. 12, the difference Bn1 between the maximum distance from the gate side surface of the second sidewall insulating film SW2 and the maximum distance from the gate side surface of the first sidewall insulating film SW1 is the height of the first sidewall insulating film SW1. The difference An1 from the height of the second sidewall insulating film SW2 is approximately the same.

  The inventors consider the difference in size between Bn in FIG. 11 and Bn1 in FIG. 12 as follows.

  That is, in the case of FIG. 11 where ion implantation of fluorine, silicon, or the like is performed, a relatively large amount of ions are implanted into the top of the portion of the first sidewall insulating film SW1 that contacts the side surface of the gate electrode GE. On the other hand, the second sidewall insulating film SW2 is present on the end portion of the first sidewall insulating film SW1 that is in contact with the source region SE and the drain region DE. BL1 remains.

  For this reason, in the present invention, more in the vicinity of the top of the portion in contact with the side surface of the gate electrode GE than in the vicinity of the end of the portion in contact with the source region SE and drain region DE of the first sidewall insulating film SW1. Ions are implanted.

  As shown in the graph of FIG. 13, when ions are implanted into the TEOS oxide film constituting the first sidewall insulating film SW1 and the silicon nitride film constituting the second sidewall insulating film SW2, the dose amount is increased. It has been found that as the amount increases, the amount etched during cleaning immediately before the silicidation step increases.

  Therefore, when the ion implantation process is performed on the N-channel MISFET and the cleaning process and the silicidation process are performed using the semiconductor device manufacturing method according to the present invention, the first sidewall insulation is performed at the time of cleaning immediately before the silicidation process. The vicinity of the top of the portion of the film SW1 in contact with the side surface of the gate electrode GE is etched much, while the vicinity of the end of the portion of the first sidewall insulating film SW1 in contact with the source region SE and drain region DE is relatively It is etched a little. This is because the difference Bn between the maximum distance from the gate side surface of the second sidewall insulating film SW2 and the maximum distance from the gate side surface of the first sidewall insulating film SW1 is the height of the first sidewall insulating film SW1 and the second side. The reason is considered to be smaller than the difference An from the height of the wall insulating film SW2.

  On the other hand, when the ion implantation step is not performed, the etching amount near the top of the portion of the first sidewall insulating film SW1 that contacts the side surface of the gate electrode GE at the time of cleaning immediately before the silicidation step, and the first sidewall There is no difference between the etching amount in the vicinity of the end portion of the insulating film SW1 in contact with the source region SE and the drain region DE. This is because the difference Bn1 between the maximum distance from the gate side surface of the second sidewall insulating film SW2 and the maximum distance from the gate side surface of the first sidewall insulating film SW1 is the height of the first sidewall insulating film SW1 and the second side. This is probably because the difference An1 from the height of the wall insulating film SW2 is approximately the same.

FIG. 14 is a graph showing the result of measuring the sheet resistance of the gate electrode GE for a number of N-channel MISFETs in which the gate electrode GE was silicidized after fluorine implantation was performed in advance. In FIG. 14, the vertical axis represents the quantile (value “0” is the mode value) in the normal distribution measurement result of all N-channel MISFETs, and the horizontal axis represents the sheet resistance value (arbitrary unit). Further, the graph indicated as “F implantation” shows the result of Ni silicide formation of the gate electrode GE after performing fluorine implantation under conditions of 5 [keV] and 1 × 10 ¹⁵ [cm ⁻² ], and 5 [ The result is that the gate electrode GE was Ni-silicided after fluorine implantation under the conditions of keV] and 6 × 10 ¹⁴ [cm ⁻² ], and the graph labeled “Reference” shows the gate without fluorine implantation. Reference values when the electrode GE is Ni-silicided are shown. It can be seen that the sheet resistance value is lower in the N-channel MISFET in which the gate electrode GE is silicided after the fluorine implantation is performed in advance.

  Since no ion implantation is performed in the P-channel type MISFET, the etching amount near the top of the first sidewall insulating film SW1 of the P-channel type MISFET is equal to that of the N-channel type MISFET during cleaning immediately before the silicidation process. The amount of etching near the top of the first sidewall insulating film SW1 is significantly smaller. On the left side of FIG. 11, the height of the first sidewall insulating film SW1 of the P-channel type MISFET is larger than the height of the second sidewall insulating film SW2, and the difference is shown as Ap.

  In the P-channel type MISFET, as in the case of the N-channel type MISFET, the maximum distance of the first sidewall insulating film SW1 from the side surface of the stacked structure of the gate insulating film GI and the gate electrode GE is equal to the gate insulating film GI and the gate. Although it is smaller than the maximum distance of the second sidewall insulating film SW2 from the side surface of the stacked structure of the electrode GE, the maximum distance from the gate side surface of the second sidewall insulating film SW2 in the P-channel MISFET and the first sidewall insulating film The difference Bp between the maximum distance from the gate side surface of SW1 is the maximum distance from the gate side surface of the second sidewall insulating film SW2 of the N-channel MISFET and the maximum distance from the gate side surface of the first sidewall insulating film SW1. It is substantially equal to the difference Bn.

  Thus, according to the structure of the semiconductor device of the present invention, in the N-channel type MISFET, the maximum distance from the gate side surface of the second sidewall insulating film SW2 and the maximum distance from the gate side surface of the first sidewall insulating film SW1. Is smaller than the difference An between the height of the first sidewall insulating film SW1 and the height of the second sidewall insulating film SW2. Therefore, when silicidation is performed, a silicide device in the N-type source region and the N-type drain region is unlikely to enter near the channel, and a semiconductor device that can more reliably suppress leakage current in the MISFET can be realized. The height of the first sidewall insulating film SW1 is smaller than the height of the second sidewall insulating film SW2. Therefore, when silicidation is performed on the gate electrode GE, the gate electrode GE is silicided by entering a portion lower than the height of the second sidewall insulating film SW2, and the resistance value of the gate electrode GE can be further reduced.

  According to the present invention, the difference Bp between the maximum distance from the gate side surface of the second sidewall insulating film SW2 and the maximum distance from the gate side surface of the first sidewall insulating film SW1 in the P-channel type MISFET is N channel. The difference Bn between the maximum distance from the gate side surface of the second sidewall insulating film SW2 of the type MISFET and the maximum distance from the gate side surface of the first sidewall insulating film SW1 is substantially equal. Therefore, when silicidation is performed, the silicidation regions in the P-type source region and the P-type drain region do not easily enter the vicinity of the channel, and a semiconductor device that can more reliably suppress the leakage current in the MISFET can be realized.

  SB semiconductor substrate, SE source region, DE drain region, GE gate electrode, GI gate insulating film, SW1 first sidewall insulating film, SW2 second sidewall insulating film, BL1 silicidation preventing film, SCs, SCd, SCg silicidation region.

Claims (8)

In a semiconductor device having a CMOS structure composed of a P-channel MISFET and an N-channel MISFET formed on a semiconductor substrate,
The P-channel type MISFET is
A first gate insulating film formed on the semiconductor substrate;
A first gate electrode formed on the first gate insulating film;
A first sidewall formed on a side surface of the first gate electrode and on the semiconductor substrate and made of a first insulating film;
A second sidewall formed on the side surface of the first gate electrode and on the semiconductor substrate via the first sidewall and made of a second insulating film;
A P-type source region and a P-type drain region formed in the semiconductor substrate;
A first silicidation region formed on the P-type source region and the P-type drain region;
The N-channel MISFET is
A second gate insulating film formed on the semiconductor substrate;
A second gate electrode formed on the second gate insulating film;
A third sidewall formed on the side surface of the second gate electrode and on the semiconductor substrate and made of the first insulating film;
A fourth sidewall formed on the side surface of the second gate electrode and on the semiconductor substrate via the third sidewall, and made of the second insulating film;
An N-type source region and an N-type drain region formed in the semiconductor substrate;
A second silicidation region formed on the N-type source region and the N-type drain region,
In the N-channel MISFET, the height of the third sidewall from the semiconductor substrate is lower than the height of the fourth sidewall from the semiconductor substrate,
In the P-channel MISFET, the height of the first sidewall from the semiconductor substrate is higher than the height of the second sidewall from the semiconductor substrate,
In the N-channel MISFET, the difference Bn between the maximum distance of the fourth sidewall from the side surface of the second gate electrode and the maximum distance of the third sidewall from the side surface of the second gate electrode is A difference An between a height of the third sidewall from the semiconductor substrate and a height of the fourth sidewall from the semiconductor substrate is smaller than
In the P-channel MISFET, the difference Bp between the maximum distance of the second sidewall from the side surface of the first gate electrode and the maximum distance of the first sidewall from the side surface of the first gate electrode is A semiconductor device, wherein a difference Ap between a height of the first sidewall from the semiconductor substrate and a height of the second sidewall from the semiconductor substrate is smaller. In a semiconductor device having a CMOS structure composed of a P-channel MISFET and an N-channel MISFET formed on a semiconductor substrate,
The P-channel type MISFET is
A first gate insulating film formed on the semiconductor substrate;
A first gate electrode formed on the first gate insulating film;
A first sidewall formed on a side surface of the first gate electrode and on the semiconductor substrate and made of a first insulating film;
A second sidewall formed on the side surface of the first gate electrode and on the semiconductor substrate via the first sidewall and made of a second insulating film;
A P-type source region and a P-type drain region formed in the semiconductor substrate;
A first silicidation region formed on the first gate electrode, on the P-type source region and on the P-type drain region;
The N-channel MISFET is
A second gate insulating film formed on the semiconductor substrate;
A second gate electrode formed on the second gate insulating film;
A third sidewall formed on the side surface of the second gate electrode and on the semiconductor substrate and made of the first insulating film;
A fourth sidewall formed on the side surface of the second gate electrode and on the semiconductor substrate via the third sidewall, and made of the second insulating film;
An N-type source region and an N-type drain region formed in the semiconductor substrate;
A second silicidation region formed on the second gate electrode, on the N-type source region and on the N-type drain region;
In the N-channel MISFET, the height of the third sidewall from the semiconductor substrate is lower than the height of the fourth sidewall from the semiconductor substrate,
In the P-channel MISFET, the height of the first sidewall from the semiconductor substrate is higher than the height of the second sidewall from the semiconductor substrate,
The distance Bn in which the third sidewall recedes from the end of the fourth sidewall in the gate length direction of the N-channel MISFET toward the second gate electrode is the third sidewall from the semiconductor substrate. And the difference An between the height of the fourth sidewall from the semiconductor substrate is smaller,
In the gate length direction of the P-channel type MISFET, the distance Bp that the first sidewall recedes from the end of the second sidewall toward the first gate electrode is the first sidewall from the semiconductor substrate. And a difference An between the height of the second side wall from the semiconductor substrate and the height of the second sidewall. The semiconductor device according to claim 1 or 2, wherein
The value of the Bn is wherein a constant correct that the value of the Bp.
The semiconductor device according to any one of claims 1 to 3,
The semiconductor device, wherein the first insulating film is made of a material different from that of the second insulating film . A semiconductor device according to any one of claims 1 to 4,
The semiconductor device according to claim 1, wherein the first insulating film is made of a silicon oxide film . A semiconductor device according to any one of claims 1 to 5,
The semiconductor device, wherein the second insulating film is made of a silicon nitride film . A semiconductor device according to any one of claims 1 to 6,
The first and second silicidation regions are each made of a metal film containing at least one of nickel, titanium, cobalt, palladium, platinum, and erbium . A semiconductor device according to any one of claims 1 to 7,
The P-type source region and the P-type drain region each include a P-type low-concentration impurity region and a P-type high-concentration impurity region having a higher concentration than the P-type low-concentration impurity region.
The first silicidation region is formed on the P-type high concentration impurity region,
Each of the N-type source region and the N-type drain region includes an N-type low-concentration impurity region and an N-type high-concentration impurity region having a higher concentration than the N-type low-concentration impurity region,
The second silicidation region is a semiconductor device which is characterized that you have been formed on the N-type high concentration impurity region.

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