JP5376705B2 - EL display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decrease resistance of a power supply line, to suppress a voltage drop in the power supply line and to prevent defective display. <P>SOLUTION: A connection terminal portion includes a plurality of connection terminals, each of the connection terminals is provided with a connection pad which is part of the connection terminal. The connection pads include a first connection pad and a second connection pad having a line width different from that of the first connection pad and pitches between the connection pads are equal to each other. <P>COPYRIGHT: (C)2007,JPO&amp;INPIT

Description

The present invention relates to a semiconductor device having a connection terminal. In particular, the present invention relates to a connection terminal structure of a display device having a pixel portion in which pixels are arranged in a matrix, and a connection structure between an external terminal and a connection terminal of a display device.

  The display device has a structure in which a flexible printed circuit is conductively connected to the display panel, and signals and power may be supplied from the flexible printed circuit to the display panel.

For example, a display panel includes a pixel portion and a peripheral driver circuit that drives the pixel portion on a substrate, and the substrate is attached to a counter substrate by a seal material in a seal region. At least the pixel portion is sealed with a substrate, a counter substrate, and a sealing material.

The substrate has a region that does not overlap with the counter substrate, and a connection terminal portion is formed in the region. In the connection terminal portion, electrodes (connection pads) are arranged in a stripe shape. The electrode is connected to a wiring formed to extend outward from the seal region.

In the display panel, in the connection terminal portion, the electrode of the connection terminal (connection pad) and the electrode of the flexible printed circuit terminal (FPC pad) are electrically connected by thermocompression bonding with an anisotropic conductive film or the like.

Then, signals and power supplied from the flexible circuit are supplied to the circuit on the substrate through each connection terminal and wiring.

Here, a power supply line (power supply including a wiring to which a power supply potential serving as a power source of a circuit on the substrate is supplied, a connection portion between the wirings, a connection portion between the FPC terminal and the connection terminal on the substrate, etc. A large amount of current flows through the path) in order to operate the pixels, peripheral drive circuits, and the like.

Therefore, if the resistance in the power supply line is large, the voltage drop in the power supply line becomes large. Then, the power supply potential supplied to the pixel and the peripheral drive circuit becomes lower than the desired power supply potential. Then, the power supply potential input to the pixel and the peripheral drive circuit is lowered, causing a display defect.

Therefore, power is supplied through a plurality of wirings of the flexible printed circuit, and the wirings connected to the connection terminals to which the power supply potential that is the power source of the circuit on the substrate is inputted are connected to each other in the seal region. The configuration is described in Patent Document 1 and Patent Document 2.
JP 2001-109395 A JP 2001-102169 A

However, even with the above-described configuration, if a displacement occurs in the line width direction of the connection pad in bonding the substrate and the FPC, the connection area between the FPC terminal and the connection terminal is reduced, and the contact resistance is increased. End up. In particular, an increase in contact resistance at a connection terminal to which a power supply potential serving as a power supply is input causes a display defect.

Therefore, an object of the present invention is to reduce the resistance of the power supply line, suppress a voltage drop in the power supply line, and prevent display defects.

The configuration of the present invention is shown below.

The semiconductor device of the present invention has a connection terminal portion, the connection terminal portion has a plurality of connection terminals, each of the plurality of connection terminals includes a connection pad forming a part of the connection terminal, The plurality of connection pads include a first connection pad and a second connection pad having a line width different from that of the first connection pad, and the pitch of the plurality of connection pads is equal.

In addition, the semiconductor device of the present invention has a connection terminal portion, and a plurality of connection pads having the same line width are arranged at equal intervals in the connection terminal portion, and two or more connection pads among the plurality of connection pads are arranged. However, it has a connection terminal connected by the wiring routed in the connection terminal portion.

In addition, the semiconductor device of the present invention has a connection terminal portion, and a plurality of connection pads having the same line width are arranged at equal intervals in the connection terminal portion, and two or more connection pads among the plurality of connection pads are arranged. However, the connection terminal portion has a connection terminal connected by a lower electrode through a contact hole.

In the semiconductor device of the present invention having the above structure, a flexible printed circuit is connected to the connection terminal portion.

In the semiconductor device of the present invention having the above structure, at least one of the connection terminal portions is connected to a plurality of terminals of the flexible printed circuit, and the connection terminal and the plurality of terminals of the flexible printed circuit. The contact resistance is 5Ω or less.

The display device of the present invention includes a pixel portion, a peripheral driver circuit, and a connection terminal portion, and the connection terminal portion includes a plurality of connection terminals, each of the plurality of connection terminals being a part of the connection terminal. The plurality of connection pads include a first connection pad and a second connection pad having a line width different from that of the first connection pad. The pitch is equal.

In addition, the display device of the present invention includes a pixel portion, a peripheral drive circuit, and a connection terminal portion, and a plurality of connection pads having the same line width are arranged at equal intervals in the connection terminal portion. Among these, two or more connection pads have connection terminals connected by wiring drawn in the connection terminal portion.

In addition, the display device of the present invention includes a pixel portion, a peripheral drive circuit, and a connection terminal portion, and a plurality of connection pads having the same line width are arranged at equal intervals in the connection terminal portion. Among them, two or more connection pads have connection terminals connected to lower-layer electrodes through contact holes in the connection terminal portions.

In the display device of the invention having the above structure, a flexible printed circuit is connected to the connection terminal portion.

In the display device of the present invention, in the above configuration, at least one of the connection terminal portions is connected to a plurality of terminals of the flexible printed circuit, and the connection terminal and the plurality of terminals of the flexible printed circuit. The contact resistance is 5Ω or less.

In addition, the display device of the present invention includes a pixel portion, a peripheral driver circuit, and a connection terminal portion. The connection terminal portion includes a plurality of connection terminals. A plurality of connection pads having the same pitch, the plurality of connection pads including a first connection pad and a second connection having a line width larger than that of the first connection pad; A plurality of wirings are electrically connected to the second connection pad, and the plurality of wirings are electrically connected to the counter electrode of the display element.

Note that various types of switches can be used as a switch shown in the present invention, and examples thereof include an electrical switch and a mechanical switch. In other words, any device can be used as long as it can control the current flow, and it is not limited to a specific device, and various devices can be used. For example, a transistor, a diode (a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, or the like), or a logic circuit that is a combination thereof may be used. Therefore, when a transistor is used as a switch, the transistor operates as a mere switch, and thus the polarity (conductivity type) of the transistor is not particularly limited. However, when it is desirable that the off-state current is small, it is desirable to use a transistor having a polarity with a small off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region and a transistor having a multi-gate structure. Further, when the transistor operated as a switch operates at a source terminal potential close to a low potential power source (Vss, GND, 0 V, etc.), the N-channel type is used. On the contrary, the source terminal potential is a high potential. When operating in a state close to the side power supply (Vdd or the like), it is desirable to use a P-channel type. This is because the absolute value of the voltage between the gate and the source can be increased, so that it can easily operate as a switch. Note that both N-channel and P-channel switches may be used as CMOS switches. When a CMOS switch is used, the voltage output through the switch (that is, the input voltage to the switch) is high or low with respect to the output voltage, so that the switch operates properly even when the situation changes. I can do it.

Note that in the present invention, the term “connected” includes the case of being electrically connected and the case of being directly connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, other elements (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) that can be electrically connected are arranged. May be. Alternatively, they may be arranged directly connected without interposing another element therebetween. In addition, it is a case where it is connected without interposing other elements that enable electrical connection, and includes only the case where it is directly connected, and does not include the case where it is electrically connected Shall be described as being directly connected. Note that the description of being electrically connected includes the case of being electrically connected and the case of being directly connected.

Note that in the present invention, various types of transistors can be used as a transistor. Thus, there is no limitation on the type of applicable transistor. Therefore, a thin film transistor (TFT) using a non-single crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a MOS transistor formed using a semiconductor substrate or SOI substrate, a junction transistor, a bipolar transistor, ZnO A transistor using a compound semiconductor such as a-InGaZnO, a transistor using an organic semiconductor or a carbon nanotube, or another transistor can be used. Note that the non-single-crystal semiconductor film may contain hydrogen or halogen. In addition, various types of substrates on which the transistor is arranged can be used, and the substrate is not limited to a specific type. Therefore, for example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, or the like can be used. Alternatively, a transistor may be formed using a certain substrate, and then the transistor may be moved to another substrate and placed on another substrate.

In the present invention, one pixel indicates the minimum unit of an image. Therefore, in the case of a full-color display device composed of R (red), G (green), and B (blue) color elements, one pixel is a dot of the R color element, a dot of the G color element, and a B color element. It shall be composed of dots. Note that the color elements are not limited to three colors and may be more than that, for example, RGBW (W is white), or RGB with yellow, cyan, and magenta added. Note that there may be a plurality of dots of a certain color element per pixel. At that time, the plurality of color elements may have different sizes of regions contributing to display. Further, gradation may be expressed by controlling each dot among a plurality of dots of a color element of a certain color. This is called an area gradation method. Alternatively, the viewing angle may be widened by using each dot among a plurality of dots of a color element of a certain color so that the signal supplied to each dot is slightly different.

Note that the arrangement (arrangement) of pixels in a matrix includes the case where the pixels are arranged in a so-called lattice pattern in which vertical stripes and horizontal stripes are combined. When full color display is performed with three color elements (for example, RGB), the case where the dots of the three color elements are arranged in a so-called delta arrangement is also included. Furthermore, the case where a Bayer is arranged is also included. Note that the color elements are not limited to three colors and may be more than that, for example, RGBW (W is white), or RGB with yellow, cyan, and magenta added. In addition, the size of the light emitting area may be different for each dot of the color element.

Note that in the present invention, a semiconductor device refers to a device having a circuit including a semiconductor element (such as a transistor or a diode). In addition, any device that can function by utilizing semiconductor characteristics may be used. A display device refers to a device having a display element (such as a liquid crystal element or a light-emitting element). Note that a display panel body in which a plurality of pixels including a display element such as a liquid crystal element or an EL element and a peripheral driver circuit for driving these pixels are formed over a substrate may be used. Furthermore, a device to which a flexible printed circuit (FPC) or a printed wiring board (PWB) is attached (such as an IC, a resistor, a capacitor, an inductor, or a transistor) may also be included. Furthermore, an optical sheet such as a polarizing plate or a retardation plate may be included. Furthermore, a backlight (which may include a light guide plate, a prism sheet, a diffusion sheet, a reflection sheet, or a light source (such as an LED or a cold cathode tube)) may be included.

Display resistance can be prevented by reducing the resistance of the power supply line and suppressing the voltage drop in the power supply line.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

The semiconductor device of the present invention has a connection terminal portion in which a circuit is formed on a substrate and is connected to an FPC (Flexible Print Circuit). The connection terminal portion has a plurality of connection terminals, and at least one of the connection terminals is connected to the plurality of FPC terminals. Hereinafter, this connection terminal is referred to as a composite connection terminal. In addition, a connection terminal connected to the FPC terminal in a pair is hereinafter referred to as a reference connection terminal.

As described above, the contact resistance can be lowered by connecting the plurality of FPC terminals and the composite connection terminal.

In the connection terminal, a surface electrode connected to the FPC terminal is referred to as a connection pad. That is, the surface electrode that forms part of the connection terminal is referred to as a connection pad. An electrode on the surface of the FPC terminal connected to the connection terminal is referred to as an FPC pad. That is, the electrode on the surface forming a part of the FPC terminal is called an FPC pad. The width between adjacent connection pads is referred to as a connection pitch, and the width between adjacent FPC pads is referred to as an FPC pitch.

Each connection pad in one connection terminal portion of the semiconductor device of the present invention has the same connection pitch, but the present invention is not limited to this.

Therefore, since it is not necessary to change the FPC terminal arrangement, the FPC can be used without changing the specifications of the FPC. Therefore, the FPC can be shared.

Note that although the FPC is used for connection in the connection terminal portion of the semiconductor device, the present invention is not limited to this. For example, an IC (semiconductor integrated circuit) chip, a printed wiring board (Printed Wiring Board: PWB), a programmable logic device board (Field Programmable Gate Array: FPGA), a CPLD (Complex Programmable Logic Device), or the like may be used.

(Embodiment 1)
In this embodiment mode, a case where the present invention is applied to a display panel will be described. In the present embodiment, a configuration in which a composite connection terminal includes a composite connection pad will be described. That is, the composite connection terminal has one connection pad (composite connection pad), and the composite connection pad is electrically connected to the plurality of FPC pads via the anisotropic conductive film.

First, FIG. 1A illustrates a module in which a display panel and an FPC in this embodiment are connected. In this specification, such a module and a display panel main body are referred to as a display device.

A pixel portion 106 and a peripheral driver circuit (a scanning line driver circuit 105 and a signal line driver circuit 104) for driving the pixel portion 106 are formed over the substrate 101. The substrate 101 and the counter substrate 102 are attached to each other. In the pixel portion 106, a plurality of signal lines extending in the column direction from the signal line driver circuit 104 are arranged side by side in the row direction. In the pixel portion 106, a plurality of scanning lines extending in the row direction from the scanning line driving circuit 105 are arranged side by side in the column direction. In the pixel portion 106, a plurality of pixels including display elements are arranged.

Note that various forms of display elements can be used. For example, an EL element (an organic EL element, an inorganic EL element or an EL element including an organic material and an inorganic material), an electron-emitting element, a liquid crystal element, an electronic ink, a light diffraction element, a discharge element, a micro-mirror surface element (DMD: Digital Micromirror Device) ), A display medium whose contrast is changed by an electromagnetic action, such as a piezoelectric element or a carbon nanotube, can be applied. An EL panel type display device using an EL element is used as an EL display, and a display device using an electron-emitting device is used as a field emission display (FED: Field Emission Display) or an SED type flat display (SED: Surface-conduction). Electron-emitter Display) and the like, a liquid crystal panel type display device using a liquid crystal element, a liquid crystal display, a digital paper type display device using electronic ink, an electronic paper, and a display device using an optical diffraction element as a grating. A light bulb (GLV) type display, a plasma display panel (PDP) type display using a discharge element, a plasma display, A DMD panel type display device using a small mirror surface element is a digital light processing (DLP) type display device, a display device using a piezoelectric element is a piezoelectric ceramic display, and a display device using a carbon nanotube is nano. There is a radiation display (NED: Nano Emissive Display).

The substrate 101 is connected to the FPC 103 at the connection terminal portion. Then, signals and power necessary for the scan line driver circuit 105, the signal line driver circuit 104, and the pixel portion 106 are supplied from the FPC 103 to the display panel.

Next, a schematic partial cross-sectional perspective view showing a connection state between the substrate 101 and the FPC 103 in the vicinity of the dotted line 107 is shown in FIG. For easy understanding of the cross-sectional direction, the direction with respect to the line ab in FIG. 1A is shown as the line ab in FIG.

A plurality of connection pads are formed on the substrate 101. The plurality of connection pads include a reference connection pad 112 and a composite connection pad 113. The plurality of connection pads are arranged via partition walls 114 having substantially the same width. Here, the order of arrangement of the reference connection pads 112 and the composite connection pads 113 is not limited to that shown in FIG.

The FPC 103 is provided with FPC pads 111 having approximately the same width at approximately equal intervals. The surface of the substrate 101 where the connection pads (the reference connection pad 112 and the composite connection pad 113) are formed and the surface of the FPC 103 where the FPC pad 111 is formed face each other.

A pair of corresponding FPC pads 111 are provided on the reference connection pad 112 so as to face each other. On the composite connection pad 113, a plurality of corresponding FPC pads 111 are provided to face each other. The connection pads (the reference connection pad 112 and the composite connection pad 113) and the FPC pad 111 are electrically connected by an anisotropic conductive film. Here, the anisotropic conductive film is not shown for easy understanding of the structure.

Next, FIG. 2 shows a schematic diagram of the configuration of the display panel shown in FIG. A scan line driver circuit 105, a signal line driver circuit 104, and a pixel portion 106 are provided over a substrate 101. Further, a connection terminal portion 201 is provided on the substrate 101. The connection terminal portion 201 includes a reference connection pad 112 that forms part of the reference connection terminal and a composite connection pad 113 that forms part of the composite connection terminal. In FIG. 2, the number and arrangement of the reference connection pads 112 and the composite connection pads 113 are not limited to those illustrated.

A plurality of scanning lines 206 are arranged in the row direction from the scanning line driving circuit 105 to the pixel portion 106. A plurality of signal lines 207 extend from the signal line driver circuit 104 to the pixel portion 106 in the column direction. In the pixel portion 106, a plurality of pixels 205 are arranged in a matrix corresponding to the scanning lines 206 and the signal lines 207. Note that the pixels are arranged in a matrix, not only in the case of a stripe type arrangement in which a vertical stripe and a horizontal stripe are combined, but also in a so-called lattice pattern, full color using three color elements (for example, RGB). In the case of performing display, the case of a delta arrangement in which three color elements of the minimum unit constituting an image are arranged in a so-called delta shape is included.

Note that the pixel 205 includes a pixel electrode. A counter electrode 202 is formed so as to cover the pixel portion 106. A display element is formed by sandwiching a display medium between the pixel electrode and the counter electrode 202. Further, the pixel portion 106 includes a power supply line 208, and power is supplied from the power supply line 208 to the pixel electrode of each pixel 205.

Since the display panel of this embodiment includes the composite connection pad 113 that forms part of the composite connection terminal in the connection terminal portion 201, power consumption can be reduced. Therefore, it is desirable that the connection terminal to which the power supply potential of the power supply is input be a composite connection terminal.

Further, when a connection terminal to which a video signal for controlling lighting / non-lighting of the pixel 205 is input is also a composite connection terminal, display defects can be further prevented.

In the display panel of the present embodiment, as shown in FIG. 2, the connection terminal portion 201 may be formed inward from the edge of the substrate, and as shown in FIG. It may be formed so as to be in contact with. Further, as shown in FIG. 7, the connection terminal portion 201 may have composite connection pads 113 at both ends. A plurality of connection terminal portions may be provided. For example, as shown in FIG. 40, a connection terminal portion 4001 and a connection terminal portion 4002 may be provided. Note that different FPCs are connected to the connection terminal portion 4001 and the connection terminal portion 4002, respectively. And either of these connection terminal parts may have a composite connection pad, and may have in either.

Note that although FIG. 1 illustrates a structure in which the scan line driver circuit 105, the signal line driver circuit 104, and the pixel portion 106 are integrally formed over the substrate, the scan line driver circuit 105 and the signal line as illustrated in FIG. The driving circuit 104 may be formed on an IC chip and mounted with COG (Chip On Glass). Note that an IC chip refers to an integrated circuit formed on a substrate cut into chips. In particular, as an IC chip, a single crystal silicon wafer is used as a substrate, a circuit is formed by element isolation or the like, and the single crystal silicon wafer is cut into an arbitrary shape.

Further, a connection structure between the connection pads (the reference connection pad 112 and the composite connection pad 113) and the FPC pad 111 will be described in detail with reference to FIGS. The electrical connection between the reference connection pad 112 and the FPC pad 111 is performed by pressure bonding using an anisotropic conductive film 411. Note that conductive particles 421 may be included in the anisotropic conductive film 411 as illustrated in FIG. The conductive particles 421 are particles having a lower resistance than the anisotropic conductive film 411. Therefore, the contact resistance between the reference connection pad 112 and the FPC pad 111 can be lowered. 4B and 4C show the connection location between the reference connection pad 112 and the FPC pad 111, the same applies to the connection between the composite connection pad 113 and the FPC pad 111.

Further, characteristics of the connection terminal portion on the substrate 101 side will be described with reference to FIG. FIG. 4A is a diagram illustrating a cross section of the connection terminal portion of the substrate 101. The composite connection pads 113a and the composite connection pads 113b having different widths correspond to the composite connection pads 113 illustrated in FIG.

The line width 401 of the reference connection pad 112, the line width 402 of the composite connection pad 113a, the line width 403 of the composite connection pad 113b, and each connection pad (the reference connection pad 112, the composite connection pad 113a, and the composite connection pad 113b) are adjacent to each other. Assuming that the width of the partition wall 114 (also referred to as connection pitch) 404 provided between the matching connection pads 404, the length of the line width 402 is approximately the sum of the two line widths 401 and the width 404. Corresponds to the length. The line width 403 is roughly equivalent to the length of the line width 401 plus three and the width 404 plus two. That is, the length of the line width of the composite connection pad 113 in FIG. 1B is the line width of the n reference connection pads 112 (n is an integer of 2 or more) and (n−1) partition walls. This corresponds to the length of the width (also referred to as connection pitch).

Therefore, although FIG. 1B shows the case where the composite connection pad 113 is electrically connected to the two FPC pads 111, it is needless to say that the present invention is not limited to this. That is, the composite connection pad 113 may be electrically connected to three FPC pads 111, four FPC pads 111, or more FPC pads 111.

That is, when the composite connection pad 113 is electrically connected to the two FPC pads 111, the result is as shown in FIG. The composite connection pad 113a is connected to the two FPC pads 111 through the anisotropic conductive film 411. Further, when the composite connection pad 113b is electrically connected to the three FPC pads 111, the result is as shown in FIG. The composite connection pad 113b is connected to the three FPC pads 111 through the anisotropic conductive film 411. Note that as illustrated in FIG. 4C, the anisotropic conductive film 411 may include conductive particles 421.

Note that in the display panel described in this embodiment, in the connection terminal portion, the contact resistance of the composite connection terminal can be made lower than the contact resistance of the reference connection terminal. Therefore, in the case of supplying power consumption such as a power supply potential that serves as a power supply, it is preferable to supply the display panel with a composite connection terminal connected to a plurality of FPC terminals. That is, a connection terminal to which a power supply potential serving as a power source is input may be a composite connection terminal. By doing so, resistance of the power supply line can be reduced, voltage drop in the power supply line can be suppressed, and display defects can be prevented.

In addition, since the composite connection terminal includes the composite connection pad, even when the display panel and the FPC are bonded to each other, even if the connection terminal and the FPC terminal are displaced in the line width direction, the contact resistance of the composite connection terminal is increased. Does not occur. This will be described below with reference to FIGS.

FIG. 6A illustrates an anisotropic conductive film in which the reference connection pad and the FPC pad are bonded when the display panel and the FPC are bonded to each other in the case where there is no displacement in the line width direction between the connection terminal and the FPC terminal. It is sectional drawing of the place connected via. That is, the centers of the line widths of the reference connection pad 112 and the FPC pad 111 substantially coincide. FIG. 6D corresponds to the top view. The area of the FPC pad 111 that does not overlap with the reference connection pad 112 has a width s.

FIG. 6B illustrates that when the display panel and the FPC are bonded to each other, the reference connection pad and the FPC pad are formed of an anisotropic conductive film in the case where the connection terminal and the FPC terminal are displaced in the line width direction. It is sectional drawing of the place connected via. FIG. 6E corresponds to a top view thereof. As shown in FIGS. 6B and 6E, since the pair of FPC pads 111 corresponding to the reference connection pad 112 are displaced in the line width direction, a non-overlapping region is generated in the reference connection pad 112. The overlapping area has a width g. Note that the non-overlapping area increasing on the FPC pad 111 has a width t. The width g and the width t are substantially equal. Therefore, the connection area is reduced by the width g.

On the other hand, FIG. 6C illustrates that when the display panel and the FPC are bonded to each other, the composite connection pad and the FPC pad are anisotropically conductive when the connection terminal and the FPC terminal are displaced in the line width direction. It is sectional drawing of the place connected through the film | membrane. FIG. 6F corresponds to a top view thereof. In the connection between the composite connection pad 113 and the FPC pad 111 shown in FIG. 6C and FIG. 6F, the occurrence of a non-overlapping region occurs even when a positional shift occurs. Of these FPC pads 111, only one FPC pad 111 is provided. The width of the non-overlapping area is t. Further, when the FPC pad 111 is wider than the reference connection pad 112, the region s that overlaps the partition wall 114 of the FPC pad 111 overlaps with the composite connection pad 113 when there is no misalignment. The area increases. The increasing area is the width s. As the number of FPC pads 111 connected to one composite connection pad 113 increases, the influence of the decrease in connection area due to the generation of the non-overlapping region becomes smaller. Further, in the composite connection pad 113, the connection area may increase. Therefore, even when the position difference in the line width direction between the connection terminal and the FPC terminal occurs in the bonding of the display panel and the FPC, the contact resistance of the composite connection terminal with the FPC terminal can be reduced.

Therefore, the contact resistance between the composite connection terminal and the plurality of FPC terminals described in this embodiment can be 5Ω or less, preferably 1Ω or less.

(Embodiment 2)
In the present embodiment, the connection pads (reference connection pad 112 and composite connection pad 113) that constitute part of the connection terminals (reference connection terminal and composite connection terminal) shown in Embodiment 1 and the bonding pads thereof are used. The structure of the wiring extending into the seal area will be described in detail.

Note that the display panel described in this embodiment is particularly suitable for a display panel having a structure in which a peripheral driver circuit (a scanning line driver circuit or a signal line driver circuit) for driving pixels together with a pixel portion is formed integrally. . In other words, the peripheral driver circuit includes a thin film transistor formed at the same time as the formation of a thin film transistor (also referred to as a TFT) included in the pixel. A schematic diagram of a display panel having such a configuration is shown in FIG. Note that the connection terminal portion 201 is not limited to the one formed inside from the edge of the substrate 101 as in this configuration, but may be formed in contact with the edge of the substrate 101 as shown in FIG.

In the display panel of this structure, the pixel portion 106 and the peripheral driver circuit formed over the substrate 101 are sandwiched between the substrate 101 and the counter substrate, and are sealed with a seal region 901. The sealing may be any of solid sealing, vacuum sealing, gas sealing, liquid sealing, and the like. For example, a resin or the like can be used for solid sealing. For gas sealing, He (helium), Ar (argon), N (nitrogen), or the like can be used. For liquid sealing, liquid paraffin, silicon liquid or the like can be used.

Here, an enlarged view of the region surrounded by the dotted line 902 is shown in FIG. The connection terminal portion includes a reference connection pad 112 and composite connection pads (composite connection pad 113a and composite connection pad 113b). The reference connection pad 112 and the wiring 1001 are formed of a continuous conductive film layer. The line width of the wiring 1001 is narrower than the line width of the reference connection pad 112. Specifically, the line width of the wiring 1001 is less than or equal to half the line width of the reference connection pad 112. More preferably, it is 1/3 or less. Further, the composite connection pad 113a and the wiring 1002 and the composite connection pad 113b and the wiring 1003 are each formed of a continuous layer of conductive film. The wiring 1002 has a line width substantially equal to that of the composite connection pad 113a and the wiring 1003 has a line width substantially equal to that of the composite connection pad 113b.

The composite connection pad 113a has a width obtained by combining the two line widths of the reference connection pad 112 and the width of one connection pitch, but is not limited to this. In addition, the composite connection pad 113b has a width obtained by combining the three line widths of the reference connection pad 112 and the width of the two connection pitches, but is not limited thereto. Moreover, as shown in FIG. 10, you may have a composite connection pad from which line width differs, and you may have multiple composite connection pads of the same line width. Moreover, the composite connection pad of a connection terminal part may be one, and plural may be sufficient as it. Further, the wiring 1001, the wiring 1002, and the wiring 1003 in the wiring portion have line widths around the seal region 901, and may have other line widths inside the pixel portion. Further, the number and arrangement order of the reference connection pads 112, the composite connection pads 113a, and the composite connection pads 113b are not limited thereto.

That is, in the structure of FIG. 10, the wiring formed of the reference connection pad and the continuous conductive film is narrow in the seal region. On the other hand, the wiring formed of the composite connection pad and the conductive film of the continuous layer may be the same as the line width of the composite connection pad in the seal region.

Accordingly, the area of the wiring formed using the reference connection pad 112 and a continuous layer of the conductive film is reduced in the seal region, so that the adhesion between the substrate 101 and the counter substrate to be bonded can be improved. Further, in the composite connection pads (composite connection pad 113a and composite connection pad 113b), the wiring formed of a continuous layer is the same as the line width of the composite connection pad, so that the resistance of the wiring can be reduced. In order to further improve the adhesion, it is desirable that the number of composite connection pads is smaller than the number of reference connection pads 112.

Further, FIG. 11 shows an enlarged view of another configuration of the region surrounded by the dotted line 902. This structure is a structure that can further enhance the adhesion between the substrate 101 and the counter substrate to be bonded.

11 is the same as FIG. 10 in the wiring 1001 formed of the reference connection pad 112 and a continuous layer of conductive film. The composite connection pad 113a includes a narrow wiring portion 1101 and a wide wiring portion 1102 in the wiring portion. The composite connection pad 113b also has a narrow wiring portion 1103 and a wide wiring portion 1104 in the wiring portion.

In other words, the composite connection pads (the composite connection pad 113a and the composite connection pad 113b) are formed with a conductive film of the same layer across the seal region 901. In the seal region 901, the wiring is narrow, and the wiring is wide in the region where the substrate and the counter substrate are bonded to each other. Preferably, the line width of the narrow wiring is not more than one third of the line width of the reference connection pad 112, and the line width of the wide wiring is approximately equal to the line width of the composite connection pad. In addition, the length of the narrow wiring is 3 to 10 times the width of the seal region 901. Therefore, the adhesion between the substrate and the counter substrate is improved. In addition, since the narrow wiring is short, an increase in resistance can be suppressed.

FIG. 12 shows an enlarged view of another configuration of the region surrounded by the dotted line 902. This configuration is a configuration that can increase the adhesion between the substrate 101 and the counter substrate to be bonded while suppressing an increase in wiring resistance.

12 is the same as FIG. 10 in the wiring 1001 formed of the reference connection pad 112 and a continuous layer of conductive film. The composite connection pad 113a has a narrow wiring portion 1201 and a wide wiring portion 1202 in the wiring portion. The composite connection pad 113b also includes a narrow wiring portion 1203 and a wide wiring portion 1204 in the wiring portion.

In other words, the composite connection pads (the composite connection pad 113a and the composite connection pad 113b) are formed by the same layer of conductive film across the seal region 901. A plurality of narrow wirings are formed in the seal region 901, and the plurality of narrow wirings are converged into a wide wiring in the region where the substrate and the counter substrate are bonded to each other. Preferably, each line width of the narrow wiring is not more than one-third of the line width of the composite connection pad, and the line width of the wide wiring is approximately equal to the line width of the composite connection pad. In addition, the length of the narrow wiring is 3 to 10 times the width of the seal region 901. Therefore, the adhesion between the substrate and the counter substrate is improved. In addition, since the narrow wiring is short, an increase in resistance can be suppressed.

In the configuration of FIG. 12, the composite connection pad 113a having a width obtained by combining the line width of two of the reference connection pads 112 and the width of one connection pitch has two narrow portions in the seal region 901. The wiring portion 1201 has a width, but is not limited to this. Further, the composite connection pad 113b having a width obtained by combining the three line widths of the reference connection pad 112 and the width of the two connection pitches becomes three narrow wiring portions 1203 in the seal region 901. However, it is not limited to this. Further, as shown in FIG. 44, in the wiring portion having the same width from the composite connection pad 113a, a part of the wiring straddling the seal region 901 is partially cut out to have a plurality of narrow wiring portions 4401. A wide wiring portion 4402 may be provided. Similarly, in the wiring portion having the same width from the composite connection pad 113b, a part of the wiring straddling the seal region 901 is partially cut out to have a plurality of narrow wiring portions 4403, and the wide wiring portion 4404 is formed in the pixel portion. You may have.

Note that when the display device performs full-color display using RGB color elements, the power supply potential may be changed. In this case, as shown in FIG. 41, the power supply potential of the R color element is supplied to the pixel by the wiring 4101R connected to the composite connection pad 113, the wiring 4201R connected thereto, and the power supply line 208R connected thereto. Further, the power supply potential of the G color element is supplied to the pixel by the wiring 4101G, the wiring 4201G connected thereto, and the power supply line 208G connected thereto. The power supply potential of the B color element is supplied to the pixel by the wiring 4101B, the wiring 4201B connected thereto, and the power supply line 208B connected thereto.

In order to improve the adhesion with the FPC at the connection terminal portion, as shown in FIG. 47, a recess 4701 may be provided in the connection pad (the reference connection pad 112, the composite connection pad 113a, and the composite connection pad 113b). . Note that a plurality of recesses 4701 may be provided for one connection pad. However, the number and shape of the recesses 4701 are not limited to those shown in FIG. Therefore, the shape is not limited to the round shape as shown in FIG. 47, but may be a square or a triangle. As shown in FIG. 50, the recess formed in a stripe shape in the direction perpendicular to the line width direction of the connection pad. 5001 or a recess 5101 formed in a stripe shape in the line width direction of the connection pad as shown in FIG.

Further, the configuration of the composite connection pad is not limited to that described above. For example, as shown in FIG. 36, the composite connection pad may be configured such that a plurality of electrodes having the same shape as the reference connection pad are coupled by an electrode coupling portion 3601. That is, two electrodes having the same line width as that of the reference connection pad 112 are coupled by the electrode coupling portion 3601 to form the composite connection pad 113a. Further, three electrodes having the same line width as that of the reference connection pad 112 are coupled by an electrode coupling portion 3601 to form a composite connection pad 113b. Note that the composite connection pads may be formed continuously by the same layer of conductive film, or the electrode and the electrode coupling portion 3601 may be different conductive films.

In addition, the electrodes that serve as connection pads (reference connection pad 112, composite connection pad 113a, and composite connection pad 113b) that constitute the connection terminals and the wirings extending from the connection terminals may be formed of different conductive films. Good. For example, as shown in FIG. 48, the electrode 4801 in the connection terminal portion is formed of a wiring 4802 extending into the seal region and a continuous conductive film. Over the electrode 4801, an electrode to be a pad is formed. In other words, the reference connection pad 112 is formed on the electrode 4801 constituting the reference connection terminal, and the composite connection pad 113a and the composite connection pad are respectively formed on the plurality of electrodes 4801 serving as the composite connection terminals across the electrodes. 113b is formed.

In such a structure, a connection pad (a reference connection pad 112, a composite connection pad 113a, and a composite connection pad 113b) is formed using a material of a transparent conductive film of a bottom emission display device, and an electrode 4801 and a wiring 4802 are formed using a metal material. To do. Examples of the transparent conductive film include ITO, TZO, and CTO.

Note that the connection pad is not limited to an electrode formed of one layer of a conductive film. That is, as illustrated in FIG. 49, another conductive film 4903 having an area smaller than that of the electrode 4901 may be provided over the electrode 4901, the electrode 4902a, and the electrode 4902b. That is, the reference connection pad includes the electrode 4901 and the conductive film 4903. The composite connection pad includes an electrode 4902a and a conductive film 4903. The composite connection pad includes an electrode 4902b and a conductive film 4903. Thus, the connection pad includes a conductive region that is exposed when the connection terminal portion is viewed from above.

In such a structure, the electrode 4901, the electrode 4902a, and the electrode 4902b are formed using a material for a transparent conductive film of a top emission display device, and the conductive film 4903 is formed using a material for an auxiliary wiring. Examples of the transparent conductive film include ITO, TZO, and CTO.

The connection pad applicable to the present invention and the structure of the wiring connected to the connection pad are not limited to those described above. Further, the above-described ones can be used in combination.

(Embodiment 3)
In this embodiment mode, a structure of a display device is described. In particular, in the present embodiment, description will be given focusing on the configuration of connection between the composite connection pad and the counter electrode.

First, the first configuration of the present embodiment will be described with reference to FIG. 2 that are common to those in FIG. 2 are denoted by common reference numerals and description thereof is omitted. In the first configuration, a wide wiring 1301 forming a part of the counter electrode 202 is formed over the signal line driver circuit 104 and connected to a wiring extending from the composite connection pad 113 through a contact hole 1302. At this time, the wide wiring 1301 is preferably formed wider than the line width of the composite connection pad 113. Then, since the contact hole 1302 can be enlarged, the contact resistance can be reduced. That is, as shown in FIG. 45, the wiring portion 1203 extending from the composite connection pad 113b is connected to the wide wiring 1301 that forms part of the counter electrode 202 through the contact hole 4501 in the pixel portion across the seal region 901. ing. At this time, since the wiring portion 1204 can have the same line width as the composite connection pad 113a, the width of the contact hole 4501 can also be increased. That is, the width of the contact hole 4501 can be made larger than the line width of the reference connection pad 112. Note that portions common to those in FIG. 12 are denoted by common reference numerals and description thereof is omitted. Further, the wiring portion 1204 and the counter electrode 202 may be connected via a plurality of contact holes 4601 as shown in FIG.

Next, a second configuration of the present embodiment will be described with reference to FIG. 2 that are common to those in FIG. 2 are denoted by common reference numerals and description thereof is omitted. In the second configuration, the wiring 1401 extending from the composite connection pad 113 has approximately the same line width as the composite connection pad 113, and has a wider wiring 1402. The width of the wiring 1402 is approximately equal to that of the signal line driver circuit 104. The wiring 1403 connected to the wiring 1402 passes through the signal line driver circuit 104 and is connected to the counter electrode 202 via the contact hole 1404 with a multilayer wiring structure. Note that the contact hole 1404 is formed in a region between the pixel portion 106 and the signal line driver circuit 104. In this manner, the composite connection pad 113, the wiring 1401 having a low wiring resistance, and the wiring 1402 are formed of a continuous conductive film without passing through the contact hole, and thus the line from the composite connection pad 113 to the counter electrode 202 is formed. Resistance can be reduced.

Next, a third configuration of the present embodiment will be described with reference to FIG. 2 that are common to those in FIG. 2 are denoted by common reference numerals and description thereof is omitted. In the third configuration, the signal line driver circuit 104 is formed on the side opposite to the connection terminal portion 201 with the pixel portion 106 interposed therebetween. With such a configuration, the counter electrode 202 is connected to the wiring extending from the composite connection pad 113 through the contact hole 1501 without straddling the signal line driver circuit 104. And since the distance of the line from the composite connection pad 113 to the counter electrode 202 is short, the resistance of this line can be reduced.

Next, a fourth configuration of the present embodiment will be described with reference to FIG. 2 that are common to those in FIG. 2 are denoted by common reference numerals and description thereof is omitted. In the fourth configuration, a wiring 1603 connected to the composite connection pad 113 is connected to a wiring 1601 arranged so as to surround the signal line driver circuit 104. The wiring 1601 is wide at least in a region between the signal line driver circuit 104 and the pixel portion 106, and is connected to the counter electrode 202 through the contact hole 1602 there. Note that when the composite connection pad 113, the wiring 1603, and the wiring 1601 are formed using the same layer of a conductive film, the contact hole is not interposed, and thus the resistance can be further reduced.

Next, a fifth configuration of the present embodiment will be described with reference to FIG. 2 that are common to those in FIG. 2 are denoted by common reference numerals and description thereof is omitted. In the fifth configuration, a wiring 1703 connected to the composite connection pad 113 is connected to a wiring 1701 arranged so as to surround the signal line driver circuit 104 and the pixel portion 106. The wiring 1701 is wide in at least a region sandwiched between the signal line driver circuit 104 and the pixel portion 106 and a region on the opposite side across the region and the pixel portion 106, and there is a counter electrode through the contact hole 1702. 202 is connected. Note that when the composite connection pad 113, the wiring 1703, and the wiring 1701 are formed using the same layer of a conductive film, the contact hole is not interposed, and thus the resistance can be further reduced. According to this structure, since the wiring 1701 is routed around the pixel portion 106, the potential in the surface of the counter electrode 202 can be made uniform by using a conductive film made of a low resistance material for the wiring 1701. it can. Note that the connection between the counter electrode 202 and the wiring 1701 may be performed in another region. For example, as illustrated in FIG. 18, the wiring 1701 is wide at least in a region sandwiched between the scan line driver circuit 105 and the pixel portion 106 and a region opposite to the region sandwiching the pixel portion 106. Therefore, it may be connected to the counter electrode 202 through the contact hole 1702.

Next, a sixth configuration of the present embodiment will be described with reference to FIG. Note that common portions with FIG. 2 are denoted by common reference numerals and description thereof is omitted. In the sixth configuration, the composite connection pads 113 are arranged at both ends of the connection terminal portion 201. In addition, a wide wiring 1901 a is formed between the scan line driver circuit 105 and the pixel portion 106. Further, a wide wiring 1901 b is formed on the opposite side to the wiring 1901 a through the pixel portion 106.

A wiring 1903 connected to one of the composite connection pads 113 formed at both ends is connected to the wiring 1901a. In addition, the wiring 1903 connected to the other of the composite connection pads 113 formed at both ends is connected to the wiring 1901b.

The wiring 1901 a and the wiring 1901 b are connected to the counter electrode 202 through the contact hole 1902. Note that the wiring 1901a and the wiring 1901b are preferably formed using a low-resistance conductive film. Then, the influence of the voltage drop can be reduced, and the potential in the surface of the counter electrode 202 can be made uniform. Although only the wiring 1901a or the wiring 1901b may be provided, the influence of the voltage drop can be further reduced by arranging the wiring 1901a and the wiring 1901b on both sides of the pixel portion 106 as illustrated in FIG. Further, the wiring is not limited to being arranged on both sides like the wiring 1901 a and the wiring 1901 b, and the wiring may be arranged so as to surround the pixel portion 106. In this case, as shown in FIG. 20, in the wiring 2001 surrounding the pixel portion 106, the region between the pixel portion 106 and the signal line driver circuit 104, and the signal line driver circuit 104 with the pixel portion 106 interposed therebetween. Has at least one contact hole 1902 in each of the opposite region, the region sandwiched between the scanning line driver circuit 105 and the pixel portion 106, and the region opposite to the pixel portion 106. Then, the wiring 2001 and the counter electrode 202 are connected through the contact hole 1902.

Note that the configuration of the display device to which the present invention is applicable is not limited to the above-described one.

(Embodiment 4)
In this embodiment mode, a structure of a display device is described. In particular, the present embodiment will be described with attention paid to the configuration of the connection between the composite connection pad and the pixel electrode.

First, the first configuration of the present embodiment will be described with reference to FIG. Note that common portions with FIG. 2 are denoted by common reference numerals and description thereof is omitted. In the first structure, a wiring 2102 is formed so as to surround the signal line driver circuit 104. The wiring 2101 connected to the composite connection pad 113 is further connected to the wiring 2102. In addition, a power line 208 extending to the pixel portion 106 is formed in the wiring 2102. With such a configuration, the influence of the voltage drop can be reduced and the potential of each power supply line 208 can be made uniform. Further, by using a low resistance conductive film for the wiring 2102, the influence of voltage drop can be further reduced. Further, the wiring 2102 may be routed to the periphery of the pixel portion 106 in order to reduce variation in power supply potential supplied to each pixel in each row of the pixel portion 106. In that case, the wiring 2201 in FIG. 22 is obtained. In this case, the wiring 2201 and the power supply line 208 are connected in a region sandwiched between the pixel portion 106 and the signal line driver circuit 104, and the wiring is also provided on the opposite side of the signal line driver circuit 104 across the pixel portion 106. 2201 and the power line 208 are connected. Note that the wiring 2201 is wider than the line width of the power supply line 208. Alternatively, the material used for the wiring 2201 is made to have a lower resistance than the material used for the power supply line 208. Or combine them. By doing so, the influence of the voltage drop can be further reduced.

Next, a second configuration of the present embodiment will be described with reference to FIG. Note that common portions with FIG. 2 are denoted by common reference numerals and description thereof is omitted. In the second configuration, the signal line driver circuit 104 is formed on the side opposite to the connection terminal portion 201 with the pixel portion 106 interposed therebetween. A wide wiring 2301 and a wide wiring 2302 are formed from the composite connection pad 113 as a continuous conductive film of the same layer. The line width of the wide wiring 2301 is approximately equal to the line width of the composite connection pad 113, and the line width of the wide wiring 2302 is approximately equal to the width of the pixel portion 106 in the row direction. A power supply line 208 connected to the wide wiring 2302 is formed to extend to the pixel portion 106. According to this configuration, since the composite connection pad 113 to the power supply line 208 can be formed by a continuous wiring without using a contact hole, the resistance can be reduced. Therefore, the influence of the voltage drop can be further reduced.

(Embodiment 5)
In this embodiment mode, a structure of a display device is described. In particular, in the present embodiment, description will be given focusing on the connection configuration between the composite connection pad, the pixel electrode, and the counter electrode.

First, the first configuration of the present embodiment will be described with reference to FIG. Note that common portions with FIG. 2 are denoted by common reference numerals and description thereof is omitted. In the first configuration, the signal line driver circuit 104 is formed on the side opposite to the connection terminal portion 201 with the pixel portion 106 interposed therebetween. With such a configuration, the counter electrode 202 is connected to the wiring extending from the composite connection pad 113 through the contact hole 1501 without straddling the signal line driver circuit 104. Further, a wide wiring 2301 and a wide wiring 2302 are formed from the composite connection pad 113 as a continuous conductive film of the same layer. The line width of the wide wiring 2301 is approximately equal to the line width of the composite connection pad 113, and the line width of the wide wiring 2302 is approximately equal to the width of the pixel portion 106 in the row direction. A power supply line 208 connected to the wide wiring 2302 is formed to extend to the pixel portion 106. According to this configuration, since the composite connection pad 113 to the power supply line 208 can be formed by a continuous wiring without using a contact hole, the resistance can be reduced.

Next, a second configuration of the present embodiment will be described with reference to FIG. Note that common portions with FIG. 2 are denoted by common reference numerals and description thereof is omitted. The second configuration has at least two composite connection pads 113. Then, a wide wiring 1401 and a wide wiring 1402 are formed from one composite connection pad 113 as a continuous conductive film of the same layer. The wide wiring 1401 is approximately equal to the line width of the composite connection pad 113, and the wide wiring 1402 is approximately equal to the width of the pixel portion 106 in the row direction. The wiring 2101 connected to the other composite connection pad 113 is connected to a wiring 2102 formed so as to surround the signal line driver circuit 104. The wide wiring 1402 is connected to the counter electrode 202 via the contact hole 1404 by a multilayer wiring 1403. The contact hole 1404 is formed between the signal line driver circuit 104 and the pixel portion 106. In addition, a power supply line 208 is formed from the wiring 2102 to the pixel portion 106.

Next, a third configuration of the present embodiment will be described with reference to FIG. Note that common portions with FIG. 2 are denoted by common reference numerals and description thereof is omitted. The third configuration has at least two composite connection pads 113. A wide wiring 1301 forming a part of the counter electrode 202 is formed over the signal line driver circuit 104 and connected to a wiring extending from one composite connection pad 113 through a contact hole 1302. At this time, the wide wiring 1301 is preferably formed wider than the line width of the composite connection pad 113. Then, since the contact hole 1302 can be enlarged, the contact resistance can be reduced. A wiring 2101 connected to the other composite connection pad 113 is connected to a wiring 2102 formed so as to surround the signal line driver circuit 104. In addition, a power supply line 208 is formed from the wiring 2102 to the pixel portion 106.

(Embodiment 6)
In the present embodiment, the cross-sectional structure of the connection terminal will be described in more detail. Note that although a cross-sectional structure of a pixel portion and a connection terminal portion of a display device including an EL element in a pixel is described in this embodiment mode, a display device to which the present invention can be applied is not limited thereto.

In a display device to which the present invention can be applied, a semiconductor layer of a thin film transistor (also referred to as a TFT) formed in a display panel may be a crystalline semiconductor film or an amorphous semiconductor film. Good. For example, polysilicon (p-Si) can be used as the crystalline semiconductor film. As the amorphous semiconductor film, amorphous silicon (a-Si: H) can be used. Furthermore, what is called microcrystalline silicon may be used. As the structure of the thin film transistor, a top gate structure in which a gate electrode is disposed over a semiconductor layer or a bottom gate structure in which a gate electrode is disposed under a semiconductor layer can be used.

First, FIG. 52 shows a cross section of a connection terminal portion and a pixel portion of a display panel having a top-gate transistor when a crystalline semiconductor film is applied to a semiconductor layer.

A base film 5202 is provided over the substrate 5201. As the substrate 5201, a glass substrate, a quartz substrate, a plastic substrate, an insulating substrate such as a ceramic substrate, a metal substrate, a semiconductor substrate, or the like can be used.

The base film 5202 can be formed by a CVD method or a sputtering method. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like formed by a CVD method using SiH ₄ , N ₂ O, or NH ₃ as a raw material can be used. Moreover, you may use these lamination | stacking. Note that the base film 5202 is provided in order to prevent impurities from diffusing from the substrate 5201 to the semiconductor layer, and the base film 5202 is not necessarily provided when a glass substrate or a quartz substrate is used as the substrate 5201.

An island-shaped semiconductor layer is provided over the base film 5202. In the semiconductor layer, a channel formation region 5203 in which a channel is formed and an impurity region 5204 to be a source region or a drain region are formed. A gate electrode 5206 is provided over the channel formation region 5203 with a gate insulating film 5205 interposed therebetween.

As the gate insulating film 5205, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like formed by a CVD method or a sputtering method can be used. As the gate electrode 5206, an aluminum (Al) film, a copper (Cu) film, a thin film mainly containing aluminum or copper, a chromium (Cr) film, a tantalum (Ta) film, a tantalum nitride (TaN) film, titanium ( A Ti) film, a tungsten (W) film, a molybdenum (Mo) film, or the like can be used.

Note that a sidewall may be formed on the side of the gate electrode 5206. After a silicon compound such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed so as to cover the gate electrode 5206, the sidewall can be formed by etching back.

A first interlayer insulating film 5207 is provided over the gate electrode 5206 and the gate insulating film 5205. The first interlayer insulating film 5207 may have an inorganic insulating film as a lower layer and a resin film as an upper layer. As the inorganic insulating film, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a film in which these are stacked can be used. As the resin film, polyimide, polyamide, acrylic, polyimide amide, epoxy, or the like can be used.

In addition, a wiring 5208 is provided over the first interlayer insulating film 5207, and the wiring 5208 is electrically connected to the impurity region 5204 through a contact hole. As the first wiring 5208, a titanium (Ti) film, an aluminum (Al) film, a copper (Cu) film, an aluminum film containing Ti, or the like can be used. More preferably, the wiring 5208 has a three-layer structure in which a titanium (Ti) film is formed as a lower layer, an aluminum (Al) film is formed thereon, and a titanium (Ti) film is formed thereon. By doing so, the wiring resistance and the contact resistance with the impurity region 5204 can also be lowered.

A second interlayer insulating film 5209 is provided over the wiring 5208 and the first interlayer insulating film 5207. As the second interlayer insulating film 5209, an inorganic insulating film, a resin film, or a stacked layer thereof can be used. As the inorganic insulating film, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a film in which these are stacked can be used. As the resin film, polyimide, polyamide, acrylic, polyimide amide, epoxy, or the like can be used. More preferably, a resin film is used for planarization.

A pixel electrode 5210 is provided over the second interlayer insulating film 5209. As a material used for the pixel electrode 5210, a material having a high work function is preferably used. In the case of employing bottom emission in which light is extracted from the substrate 5201 side, a transparent conductive film is used for the pixel electrode 5210. Alternatively, a transparent conductive film and a metal film that is thin enough to transmit light can be stacked and used. In the case of employing top emission in which light is extracted from the side opposite to the substrate 5201, the pixel electrode 5210 may be formed using a metal film that reflects light.

For example, as a material for the transparent conductive film, indium tin oxide (ITO), indium zinc oxide (IZO), tin cadmium oxide (CTO), zinc oxide (ZnO), tin oxide (TO) in which tin oxide is added to indium oxide. Such materials can be used. By using ITO, a low-resistance pixel electrode 5210 can be formed. Further, by using IZO, a uniform film can be formed and dense processing can be performed.

For example, as a metal film having reflectivity, a titanium nitride (TiN) film, a chromium (Cr) film, a tungsten (W) film, a zinc (Zn) film, a platinum (Pt) film, etc., as well as a titanium nitride film For example, a three-layer structure of a titanium nitride film, a film mainly containing aluminum, and a titanium nitride film can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained. By using a metal film that reflects light, an anode that does not transmit light can be formed.

In addition, an insulator 5211 is provided so as to cover an end portion of the pixel electrode 5210. For example, as the insulator 5211, a positive photosensitive acrylic resin film can be used.

In addition, a layer 5212 containing an organic compound is formed over the pixel electrode 5210. In addition, the counter electrode 5213 is provided over the layer 5212 containing an organic compound.

As a material used for the counter electrode 5213, a material having a low work function is preferably used. For example, aluminum (Al), silver (Ag), lithium (Li), calcium (Ca), or an alloy thereof, or a metal thin film such as MgAg, MgIn, AlLi, CaF ₂ , or Ca ₃ N ₂ is used. it can.

In the case of employing bottom injection, aluminum (Al), silver (Ag), lithium (Li), calcium (Ca), or an alloy thereof, MgAg, MgIn, AlLi, CaF ₂ , or Ca ₃ N ₂ or the like The film thickness is such that light is reflected using a metal thin film or the like.
In the case of adopting top emission, the above-described metal thin film is used with a thickness that allows light to pass through, or the metal thin film that has a thickness that allows light to pass through, and a transparent conductive film. You may use it in combination. In this manner, the counter electrode 5213 which can transmit light can be formed.

A light emitting element 5215 is formed in a region where a layer 5212 containing an organic compound is sandwiched between the counter electrode 5213 and the pixel electrode 5210.

In addition, a transistor 5214 including a gate electrode 5206, an impurity region 5204 serving as a source region or a drain region, and a channel formation region 5203 is formed.

Next, the structure of the connection terminal portion will be described. Note that the cross-sectional view of the connection terminal portion illustrated in FIG. 52A illustrates a cross section of the connection terminal in the line width direction.

The connection terminal portion also includes a base film 5202 over the substrate 5201 and a gate insulating film 5205 thereon. However, the base film 5202 and the gate insulating film 5205 are not necessarily provided in the connection terminal portion.

Further, a first electrode 5221, a first electrode 5223, and a first electrode 5225 are provided over the gate insulating film 5205, and the second electrode 5222, the first electrode 5225 are provided over the first electrode 5221. A second electrode 5224 is provided over the electrode 5223, and a second electrode 5226 is provided over the first electrode 5225.

The first electrode 5221, the first electrode 5223, the first electrode 5225, the second electrode 5222, the second electrode 5224, and the second electrode 5226 are formed using the first interlayer insulating film 5207 and the second electrode It is electrically insulated by a partition constituted by an interlayer insulating film 5209.

Note that the first electrode 5221, the first electrode 5223, and the first electrode 5225 are formed using the same material as the gate electrode 5206. The second electrode 5222, the second electrode 5224, and the second electrode 5226 are formed using the same material as the wiring 5208. More preferably, the second electrode 5222, the second electrode 5224, and the second electrode 5226 have a three-layer structure, and an aluminum film is formed over the titanium film, and a titanium film is formed thereon.

The first electrode 5221 and the second electrode 5222 constitute a reference connection terminal 5227. The first electrode 5223 and the second electrode 5224 constitute a composite connection terminal 5228. The first electrode 5225 and the second electrode 5226 form a reference connection terminal 5229. In the case of the structure as shown in FIG. 52A, the second electrode 5222 and the second electrode 5226 correspond to a reference connection pad, and the second electrode 5224 corresponds to a composite connection pad.

52A, the third electrode 5231 is provided over the second electrode 5222, the third electrode 5232 is provided over the second electrode 5224, and the third electrode 5233 is provided over the second electrode 5226. The configuration as shown in FIG. That is, the first electrode 5221, the second electrode 5222, and the third electrode 5231 constitute a reference connection terminal 5234, and the first electrode 5223, the second electrode 5224, and the third electrode 5232 are combined. A terminal 5235 is formed, and the first electrode 5225, the second electrode 5226, and the third electrode 5233 form a reference connection terminal 5236. In the case of the structure shown in FIG. 52B, the third electrode 5231 and the third electrode 5232 correspond to a reference connection pad, and the third electrode 5233 corresponds to a composite connection pad.

Note that the third electrode 5231, the third electrode 5232, and the third electrode 5233 are formed using the same material as the pixel electrode 5210. More preferably, the third electrode 5231, the third electrode 5232, and the third electrode 5233 are indium tin oxide (ITO) in which tin oxide is added to indium oxide, indium zinc oxide (IZO), or cadmium tin oxide. An electrode of an oxide such as (CTO), zinc oxide (ZnO), or tin oxide (TO) is preferable. Since these oxide electrodes are excellent in chemical stability, the electrodes can be protected.

In the structure of FIG. 52A, a semiconductor film 5311 is formed under the first electrode 5222, a semiconductor film 5312 is formed under the first electrode 5223, and a semiconductor film 5313 is formed under the first electrode 5225. Such a configuration may be used. That is, the first electrode 5221, the second electrode 5222, and the semiconductor film 5311 form a reference connection terminal 5314, and the first electrode 5223, the second electrode 5224, and the semiconductor film 5312 form a composite connection terminal 5315. The first electrode 5225, the second electrode 5226, and the semiconductor film 5313 constitute a reference connection terminal 5316.

Further, the connection terminal portion may have a structure as shown in FIG. That is, the first electrode 5301, the first electrode 5303, and the first electrode 5305 are provided over the first interlayer insulating film 5207, and the second electrode 5302, the first electrode 5305 are provided over the first electrode 5301. The second electrode 5304 is provided over the first electrode 5303, and the second electrode 5306 is provided over the first electrode 5305.

The first electrode 5301, the first electrode 5303, the first electrode 5305, the second electrode 5302, the second electrode 5304, and the second electrode 5306 are formed of the second interlayer insulating film 5209. It is electrically insulated by a partition wall.

Note that the first electrode 5301, the first electrode 5303, and the first electrode 5305 are formed using the same material as the wiring 5208. The second electrode 5302, the second electrode 5304, and the second electrode 5306 are formed using the same material as the pixel electrode 5210. More preferably, the second electrode 5302, the second electrode 5304, and the second electrode 5306 are indium tin oxide (ITO) in which tin oxide is added to indium oxide, indium zinc oxide (IZO), or cadmium tin oxide. An electrode of an oxide such as (CTO), zinc oxide (ZnO), or tin oxide (TO) is preferable. Since these oxide electrodes are excellent in chemical stability, the electrodes can be protected.

The first electrode 5301 and the second electrode 5302 constitute a reference connection terminal 5307. The first electrode 5303 and the second electrode 5304 form a composite connection terminal 5308. In addition, the first electrode 5305 and the second electrode 5306 form a reference connection terminal 5309. In the case of the structure shown in FIG. 53A, the second electrode 5302 and the second electrode 5306 correspond to a reference connection pad, and the second electrode 5304 corresponds to a composite connection pad.

Further, the second interlayer insulating film 5209 may not be provided. First, a cross section of the pixel portion is described with reference to FIG. The process up to the point where the wiring 5208 is provided over the first interlayer insulating film 5207 is the same as FIG.

In addition, an insulator 5402 is provided so as to cover an end portion of the pixel electrode 5401. For example, as the insulator 5402, a positive photosensitive acrylic resin film can be used.

A layer 5403 containing an organic compound is formed over the pixel electrode 5401. In addition, the counter electrode 5404 is provided over the layer 5403 containing an organic compound.

Next, the structure of the connection terminal portion will be described. Note that the cross-sectional view of the connection terminal portion illustrated in FIG. 54A illustrates a cross section of the connection terminal in the line width direction.

The connection terminal portion also includes a base film 5202 over the substrate 5201 and a gate insulating film 5205 thereon. However, the base film 5202 and the gate insulating film 5205 are not necessarily provided in the connection terminal portion.

Further, a first electrode 5411, a first electrode 5413, and a first electrode 5415 are provided over the gate insulating film 5205. Further, a second electrode 5412 and a first electrode 5415 are provided over the first electrode 5411. A second electrode 5414 is provided over the electrode 5413, and a second electrode 5416 is provided over the first electrode 5415.

The first electrode 5411, the first electrode 5413, the first electrode 5415, the second electrode 5412, the second electrode 5414, and the second electrode 5416 are electrically connected to each other by the first interlayer insulating film 5207. Insulated.

Note that the first electrode 5411, the first electrode 5413, and the first electrode 5415 are formed using the same material as the gate electrode 5206. The second electrode 5412, the second electrode 5414, and the second electrode 5416 are formed using the same material as the wiring 5208. More preferably, the second electrode 5412, the second electrode 5414, and the second electrode 5416 have a three-layer structure, and an aluminum film is formed over the titanium film, and a titanium film is further formed thereon.

The first electrode 5411 and the second electrode 5412 constitute a reference connection terminal 5421. In addition, the first electrode 5413 and the second electrode 5414 constitute a composite connection terminal 5422. Further, the first electrode 5415 and the second electrode 5416 constitute a reference connection terminal 5423. In the case of the structure shown in FIG. 54A, the second electrode 5412 and the second electrode 5416 correspond to a reference connection pad, and the second electrode 5414 corresponds to a composite connection pad.

54A, the third electrode 5431 is provided over the second electrode 5412, the third electrode 5432 is provided over the second electrode 5414, and the third electrode 5433 is provided over the second electrode 5416. It may be configured as shown in FIG. That is, the first electrode 5411, the second electrode 5412, and the third electrode 5431 constitute a reference connection terminal 5441, and the first electrode 5413, the second electrode 5414, and the third electrode 5432 are combined. A terminal 5442 is formed, and the first electrode 5415, the second electrode 5416, and the third electrode 5433 form a reference connection terminal 5443. 54B, the third electrode 5431 and the third electrode 5432 correspond to a reference connection pad, and the third electrode 5433 corresponds to a composite connection pad.

Note that the third electrode 5431, the third electrode 5432, and the third electrode 5433 are formed using the same material as the pixel electrode 5401. More preferably, the third electrode 5431, the third electrode 5432, and the third electrode 5433 are indium tin oxide (ITO) in which tin oxide is added to indium oxide, indium zinc oxide (IZO), or cadmium tin oxide. An electrode of an oxide such as (CTO), zinc oxide (ZnO), or tin oxide (TO) is preferable. Since these oxide electrodes are excellent in chemical stability, the electrodes can be protected.

Further, the connection terminal portion may have a structure as shown in FIG. In other words, the first electrode 5501, the first electrode 5503, and the first electrode 5505 are provided over the first interlayer insulating film 5207, and the second electrode 5502 and the first electrode 5505 are provided over the first electrode 5501. The second electrode 5504 is provided over the first electrode 5503, and the second electrode 5506 is provided over the first electrode 5505.

The first electrode 5501, the first electrode 5503, the first electrode 5505, the second electrode 5502, the second electrode 5504, and the second electrode 5506 are electrically insulated by an insulator 5402. .

Note that the first electrode 5501, the first electrode 5503, and the first electrode 5505 are formed using the same material as the wiring 5208. The second electrode 5502, the second electrode 5504, and the second electrode 5506 are formed using the same material as the pixel electrode 5401. More preferably, the second electrode 5502, the second electrode 5504, and the second electrode 5506 are indium tin oxide (ITO) in which tin oxide is added to indium oxide, indium zinc oxide (IZO), or cadmium tin oxide. An electrode of an oxide such as (CTO), zinc oxide (ZnO), or tin oxide (TO) is preferable. Since these oxide electrodes are excellent in chemical stability, the electrodes can be protected.

The first electrode 5501 and the second electrode 5502 constitute a reference connection terminal 5511. The first electrode 5503 and the second electrode 5504 form a composite connection terminal 5512. Further, the first electrode 5505 and the second electrode 5506 constitute a reference connection terminal 5513. In the case of the structure shown in FIG. 55A, the second electrode 5502 and the second electrode 5506 correspond to a reference connection pad, and the second electrode 5504 corresponds to a composite connection pad.

Further, as in the structure in FIG. 55B, the structure in which the second electrode 5502, the second electrode 5504, and the second electrode 5506 are not provided in the structure in FIG. That is, the first electrode 5501 forms a reference connection terminal 5521. The first electrode 5503 forms a composite connection terminal 5522. The first electrode 5505 forms a reference connection terminal 5523. In the case of the structure shown in FIG. 55B, the first electrode 5501 and the first electrode 5505 correspond to a reference connection pad, and the first electrode 5503 corresponds to a composite connection pad.

Further, as a transistor structure using polysilicon (p-Si) as a semiconductor layer, a structure in which a gate electrode is sandwiched between a substrate and a semiconductor layer, that is, a bottom gate in which a gate electrode is located under a semiconductor layer. A partial cross section of a display panel to which the transistor 5653 is applied is shown in FIG.

  A base film 5602 is formed over the substrate 5601. Further, a gate electrode 5603 is formed over the base film 5602. As a material for the gate electrode 5603, a metal film or polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

A gate insulating film 5604 is formed so as to cover the gate electrode 5603. As the gate insulating film 5604, a silicon oxide film, a silicon nitride film, or the like is used.

  A semiconductor film is formed over the gate insulating film 5604. The semiconductor film includes a channel formation region 5606 and an impurity region 5605. Note that the channel formation region 5606 may be channel-doped.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 5602, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

A first interlayer insulating film 5600 is formed so as to cover the semiconductor film, and a wiring 5607 is in contact with the impurity region 5605 over the first interlayer insulating film 5600 through a contact hole.

In addition, an opening 5608 is formed in the first interlayer insulating film 5600.

A second interlayer insulating film 5609 is formed so as to cover the first interlayer insulating film 5600, the wiring 5607, and the opening 5608, and a pixel electrode 5610 is formed over the second interlayer insulating film 5609 through a contact hole. ing. In addition, an insulator 5611 is formed to cover an end portion of the pixel electrode 5610. For example, a positive photosensitive acrylic resin film can be used. A layer 5612 containing an organic compound and a counter electrode 5613 are formed over the pixel electrode 5610, and a light-emitting element 5614 is formed in a region where the layer 5612 containing an organic compound is sandwiched between the pixel electrode 5610 and the counter electrode 5613. . An opening 5608 is located below the light emitting element 5614. That is, when light emitted from the light-emitting element 5614 is extracted from the substrate side, the opening 5608 is provided, so that the transmittance can be increased.

Next, the structure of the connection terminal portion will be described. Note that the cross-sectional view of the connection terminal portion illustrated in FIG. 56A illustrates a cross section of the connection terminal in the line width direction.

The connection terminal portion also includes a base film 5602 over the substrate 5601 and a gate insulating film 5604 thereon. However, the base film 5602 and the gate insulating film 5604 are not necessarily provided in the connection terminal portion.

Further, a semiconductor film 5615, a semiconductor film 5617, and a semiconductor film 5619 are provided over the gate insulating film 5604. Further, the first conductive film 5616 is provided over the semiconductor film 5615, and the first conductive film 5617 is provided over the semiconductor film 5617. A first conductive film 5620 is provided over the conductive film 5618 and the semiconductor film 5619.

The semiconductor film 5615, the semiconductor film 5617, the semiconductor film 5619, the first conductive film 5616, the first conductive film 5618, and the first conductive film 5620 are formed of the first interlayer insulating film 5600 and the second interlayer insulating film. 5609 is electrically insulated by a partition wall.

Note that the semiconductor film 5615, the semiconductor film 5617, and the semiconductor film 5619 are formed using the same material as the semiconductor layer of the transistor. The first conductive film 5616, the first conductive film 5618, and the first conductive film 5620 are formed using the same material as the wiring 5607.

The semiconductor film 5615 and the first conductive film 5616 form a reference connection terminal 5621. Further, the semiconductor film 5617 and the first conductive film 5618 constitute a composite connection terminal 5622. Further, the semiconductor film 5619 and the first conductive film 5620 form a reference connection terminal 5623. In the case of the structure illustrated in FIG. 56A, the first conductive film 5616 and the first conductive film 5620 correspond to reference connection pads, and the first conductive film 5618 corresponds to a composite connection pad. .

Note that in the structure in FIG. 56A, a second conductive film 5561 is formed over the first conductive film 5616, a second conductive film 5632 is formed over the first conductive film 5618, and a second conductive film 5620 is formed over the first conductive film 5620. A structure as illustrated in FIG. 56B may include the two conductive films 5633. That is, the semiconductor film 5615, the first conductive film 5616, and the second conductive film 5631 form the reference connection terminal 5541, and the semiconductor film 5617, the first conductive film 5618, and the second conductive film 5632 are combined. A terminal 5642 is formed, and the semiconductor film 5619, the first conductive film 5620, and the second conductive film 5633 form a reference connection terminal 5543. In the case of the structure illustrated in FIG. 56B, the second conductive film 5631 and the second conductive film 5632 correspond to reference connection pads, and the second conductive film 5633 corresponds to a composite connection pad. .

Note that the second conductive film 5631, the second conductive film 5632, and the second conductive film 5633 are formed using the same material as the pixel electrode 5610. More preferably, the second conductive film 5631, the second conductive film 5632, and the second conductive film 5633 are indium tin oxide (ITO) in which tin oxide is added to indium oxide, indium zinc oxide (IZO), An electrode of an oxide such as tin cadmium oxide (CTO), zinc oxide (ZnO), or tin oxide (TO) may be used. Since these oxide electrodes are excellent in chemical stability, the electrodes can be protected.

Alternatively, as in the structure in FIG. 57B, the semiconductor film 5615, the semiconductor film 5617, and the semiconductor film 5619 may be omitted in the structure in FIG. That is, the reference conductive terminal 5711 is formed by the first conductive film 5616 and the second conductive film 5631. The first conductive film 5618 and the second conductive film 5632 form a composite connection terminal 5712. In addition, the first conductive film 5620 and the second conductive film 5633 form a reference connection terminal 5713. In the case of the structure shown in FIG. 57B, the second conductive film 5631 and the second conductive film 5633 correspond to reference connection pads, and the second conductive film 5632 corresponds to a composite connection pad. .

Further, the connection terminal portion may have a structure as shown in FIG. In other words, the first conductive film 5701, the first conductive film 5703, and the first conductive film 5705 are provided over the first interlayer insulating film 5600, and the second conductive film is provided over the first conductive film 5701. A second conductive film 5704 is provided over the film 5702 and the first conductive film 5703, and a second conductive film 5706 is provided over the first conductive film 5705.

The first conductive film 5701, the first conductive film 5703, the first conductive film 5705, the second conductive film 5702, the second conductive film 5704, and the second conductive film 5706 are formed of a second interlayer insulating film. It is electrically insulated by a partition wall made up of the film 5609.

Note that the first conductive film 5701, the first conductive film 5703, and the first conductive film 5705 are formed using the same material as the wiring 5607. The second conductive film 5702, the second conductive film 5704, and the second conductive film 5706 are formed using the same material as the pixel electrode 5610. More preferably, the second conductive film 5702, the second conductive film 5704, and the second conductive film 5706 are indium tin oxide (ITO) in which tin oxide is added to indium oxide, indium zinc oxide (IZO), An electrode of an oxide such as tin cadmium oxide (CTO), zinc oxide (ZnO), or tin oxide (TO) may be used. Since these oxide electrodes are excellent in chemical stability, the electrodes can be protected.

The first conductive film 5701 and the second conductive film 5702 form a reference connection terminal 5707. In addition, the first conductive film 5703 and the second conductive film 5704 form a composite connection terminal 5708. Further, the first conductive film 5705 and the second conductive film 5706 form a reference connection terminal 5709. In the case of the structure shown in FIG. 57A, the second conductive film 5702 and the second conductive film 5706 correspond to reference connection pads, and the second conductive film 5704 corresponds to a composite connection pad. .

Next, the case where an amorphous silicon (a-Si: H) film is used for the semiconductor layer of the transistor will be described.

As shown in FIG. 58A, a base film 5802 is formed over a substrate 5801 as a cross section of a top-gate transistor using amorphous silicon as a semiconductor layer. Further, a pixel electrode 5803 is formed over the base film 5802.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 5802, a single layer such as aluminum nitride (AlN), silicon oxide (SiO ₂ ), or silicon oxynitride (SiO _x N _y ) or a stacked layer thereof can be used.

Further, a wiring 5804 is formed over the base film 5802, and an end portion of the pixel electrode 5803 is covered with the wiring 5804. An N-type semiconductor layer 5806 having an N-type conductivity is formed over the wiring 5804. A semiconductor layer 5805 is formed over the N-type semiconductor layer 5806 and the base film 5802. Note that this semiconductor layer is formed of an amorphous semiconductor film such as amorphous silicon (a-Si: H) or microcrystalline semiconductor (μ-Si: H). In addition, a gate insulating film 5807 is formed over the semiconductor layer 5805. Note that as the gate insulating film 5807, a silicon oxide film, a silicon nitride film, or the like is used.

  A gate electrode 5808 is formed over the gate insulating film 5807. Further, an insulator 5809 is formed so as to cover an end portion of the pixel electrode 5803 and the transistor 5812.

A layer 5810 containing an organic compound and a counter electrode 5811 are formed over the insulator 5809 and the pixel electrode 5803 located in the opening, and the pixel electrode 5803 and the counter electrode 5811 sandwich the layer 5810 containing an organic compound. A light emitting element 5813 is formed.

Next, the structure of the connection terminal portion will be described. Note that the cross-sectional view of the connection terminal portion illustrated in FIG. 58A illustrates a cross section of the connection terminal in the line width direction.

The connection terminal portion also has a base film 5802 over the substrate 5801. However, the base film 5802 is not necessarily provided in the connection terminal portion.

Further, a first conductive film 5814, a first conductive film 5816, and a first conductive film 5818 are provided over the base film 5802, and a second conductive film 5815 is provided over the first conductive film 5814. A second conductive film 5817 is provided over the first conductive film 5816 and a second conductive film 5819 is provided over the first conductive film 5818.

The first conductive film 5814, the first conductive film 5816, the first conductive film 5818, the second conductive film 5815, the second conductive film 5817, and the second conductive film 5819 are electrically connected by an insulator 5809. Is electrically insulated.

Note that the first conductive film 5814, the first conductive film 5816, and the first conductive film 5818 are formed using the same material as the wiring 5804. The second conductive film 5815, the second conductive film 5817, and the second conductive film 5819 are formed using the same material as the gate electrode 5808.

The first conductive film 5814 and the second conductive film 5815 constitute a reference connection terminal 5820. Further, the first conductive film 5816 and the second conductive film 5817 constitute a composite connection terminal 5821. Further, the first conductive film 5818 and the second conductive film 5819 form a reference connection terminal 5822. In the case of the structure shown in FIG. 58A, the second conductive film 5815 and the second conductive film 5819 correspond to a reference connection pad, and the second conductive film 5817 corresponds to a composite connection pad. .

58A, the third conductive film 5823 is below the first conductive film 5814, the third conductive film 5824 is below the first conductive film 5816, and the third conductive film 5818 is below the first conductive film 5818. A structure as shown in FIG. 58B having three conductive films 5825 may be employed. That is, the first conductive film 5814, the second conductive film 5815, and the third conductive film 5823 constitute the reference connection terminal 5820, and the first conductive film 5816, the second conductive film 5817, and the third conductive film are formed. A composite connection terminal 5821 is formed with the film 5824, and a reference connection terminal 5822 is formed with the first conductive film 5818, the second conductive film 5819, and the third conductive film 5825.

FIG. 59 shows a partial cross section of a display panel using a bottom-gate transistor using amorphous silicon as a semiconductor layer.

  A base film 5902 is formed over the substrate 5901. Further, a gate electrode 5903 is formed on the base film 5902. As a material for the gate electrode 5903, polycrystalline silicon to which phosphorus is added can be used. In addition to polycrystalline silicon, silicide which is a compound of metal and silicon may be used.

A gate insulating film 5904 is formed so as to cover the gate electrode 5903. As the gate insulating film 5904, a silicon oxide film, a silicon nitride film, or the like is used.

  A semiconductor layer 5905 is formed over the gate insulating film 5904.

As the substrate, a glass substrate, a quartz substrate, a ceramic substrate, or the like can be used. As the base film 5902, a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), or a stacked layer thereof can be used.

An N-type semiconductor layer 5906 having N-type conductivity is formed over the semiconductor layer 5905.

A wiring 5907 is formed over the N-type semiconductor layer 5906.

One end of the wiring 5907 extends, and a pixel electrode 5908 is formed in contact with the upper portion of the extended wiring 5907.

An insulator 5909 is formed so as to cover the end portion of the pixel electrode 5908 and the transistor 5912.

A layer 5910 containing an organic compound and a counter electrode 5911 are formed over the pixel electrode 5908 and the insulator 5909, and a light-emitting element 5913 is formed in a region where the layer 5910 containing an organic compound is sandwiched between the pixel electrode 5908 and the counter electrode 5911. ing.

Next, the structure of the connection terminal portion will be described. Note that the cross-sectional view of the connection terminal portion illustrated in FIG. 59A illustrates a cross section of the connection terminal in the line width direction.

The connection terminal portion also has a base film 5902 on the substrate 5901. However, the base film 5902 is not necessarily provided in the connection terminal portion.

Further, a first conductive film 5914, a first conductive film 5915, and a first conductive film 5916 are provided over the base film 5902.

The first conductive film 5914, the first conductive film 5915, and the first conductive film 5916 are electrically insulated by an insulator 5909.

Note that the first conductive film 5914, the first conductive film 5915, and the first conductive film 5916 are formed using the same material as the wiring 5907.

The first conductive film 5914 forms a reference connection terminal 5917. In addition, a composite connection terminal 5918 is formed by the first conductive film 5915. In addition, a reference connection terminal 5919 is formed by the first conductive film 5916. In the case of the structure shown in FIG. 59A, the first conductive film 5914 and the first conductive film 5916 correspond to a reference connection pad, and the first conductive film 5915 corresponds to a composite connection pad. .

59A, the second conductive film 5920 is formed over the first conductive film 5914, the second conductive film 5921 is formed over the first conductive film 5915, and the second conductive film 5916 is formed over the first conductive film 5916. A structure shown in FIG. 59B having two conductive films 5922 may be employed. That is, the first conductive film 5914 and the second conductive film 5920 form a reference connection terminal 5923, the first conductive film 5915 and the second conductive film 5921 form a composite connection terminal 5924, and The conductive film 5916 and the second conductive film 5922 constitute a reference connection terminal 5925.

Note that although FIGS. 59A and 59B illustrate an inverted staggered channel-etched transistor, a channel-protected transistor may be used. Note that the case of a transistor with a channel protective structure is described with reference to FIGS.

A transistor 6002 having a channel protection structure illustrated in FIGS. 60A and 60B includes a channel etch transistor 5912 illustrated in FIGS. 59A and 59B and a region where a channel of the semiconductor layer 5905 is formed. The difference is that an insulator 6001 serving as an etching mask is provided above, and the other common points are denoted by the same reference numerals.

By using an amorphous semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, or the like) of a transistor included in the pixel of the present invention, manufacturing cost can be reduced.

The display panel to which the present invention can be applied is not limited to the one described above.
(Embodiment 7)
In the present embodiment, a structure of a composite connection terminal different from that in Embodiment 1 will be described.

First, the first structure of this embodiment will be described with reference to FIGS. The connection pads 3901a, the plurality of connection pads 3902, and the connection pads 3901b are arranged on the connection terminal portion on the substrate 101 at equal intervals. The line widths of these connection pads are almost equal.

In addition, an electrode 3903 is provided below the connection pad 3902 with an insulating film interposed therebetween. The electrode 3903 is formed from the connection pad 3901a to the connection pad 3901b. The connection pad 3901a and the electrode 3903 are electrically connected through the contact hole 3904a, and the connection pad 3901b and the electrode 3903 are electrically connected through the contact hole 3904b. Thus, the connection pad 3901a and the connection pad 3901b are electrically connected. The connection pad 3901a, the connection pad 3901b, and the electrode 3903 constitute a composite connection terminal. And the place where this composite connection terminal is connected to the FPC terminal is a connection pad 3901a and a connection pad 3901b.

In FIG. 39, the connection pads at both ends of the connection terminal portion are electrically connected to form a composite connection terminal. However, the present invention is not limited to this. That is, a composite connection terminal can be configured by electrically connecting arbitrary connection pads of the connection terminal portion. Therefore, the number of connection pads to be electrically connected is not limited to two, and may be three, four, or more. By increasing the number, the contact area with the FPC pad can be increased, so that the contact resistance can be lowered.

Further, according to this configuration, since each connection pad is electrically connected in the lower layer of the connection terminal portion, the connection between the connection pads separated from each other can be achieved without routing the wiring inside the area surrounded by the seal region 901. Is possible.

Note that this structure can be combined with the structure of the connection terminal portion having various structures shown in Embodiment Mode 2. An example is shown in FIG.

In FIG. 61, the composite connection pad 6101a, the composite connection pad 6101b, the composite connection pad 6102, and the reference connection pad 6103 are arranged on the connection terminal portion on the substrate 101 at equal intervals.

In addition, an electrode 6104 is provided below the composite connection pad 6101a and the composite connection pad 6101b with an insulating film interposed therebetween. The electrode 6104 is formed from the composite connection pad 6101a to the composite connection pad 6101b. The composite connection pad 6101a and the electrode 6104 are electrically connected through the contact hole 6105a, and the composite connection pad 6101b and the electrode 6104 are electrically connected through the contact hole 6105b. Thus, the composite connection pad 6101a and the composite connection pad 6101b are electrically connected. The composite connection pad 6101a, the composite connection pad 6101b, and the electrode 6104 constitute a composite connection terminal. The composite connection terminal is connected to the FPC terminal at the composite connection pad 6101a and the composite connection pad 6101b.

In this case, since the width of the contact hole 6105a can be made larger than the line width of the reference connection pad 6103, the contact resistance can be reduced.

In FIG. 61, the composite connection pads at both ends of the connection terminal portion are electrically connected to form a composite connection terminal. However, the present invention is not limited to this. That is, a composite connection terminal can be configured by electrically connecting arbitrary connection pads of the connection terminal portion. Therefore, the number of connection pads to be electrically connected is not limited to two, and may be three, four, or more. By increasing the number, the contact area with the FPC pad can be increased, so that the contact resistance can be lowered.

Further, although the composite connection pads are connected to each other, the composite connection terminal may be configured by electrically connecting the composite connection pad and the reference connection pad.

Further, according to this configuration, since each connection pad is connected in the lower layer of the connection terminal portion, it is possible to connect the connection pads apart from each other without routing the wiring inside the area surrounded by the seal region 901. Become.

Next, a second configuration of the present embodiment will be described with reference to FIG. The connection pads 3701a, the plurality of connection pads 3702, and the connection pads 3701b are arranged on the connection terminal portion on the substrate 101 at equal intervals. The line widths of these connection pads are almost equal.

Further, the connection pad 3701 a and the connection pad 3701 b are connected by a wiring 3703 formed on the edge side of the substrate 101 in the connection terminal portion. Note that since the wiring 3703 is formed of a continuous conductive film with the connection pad 3701a and the connection pad 3701b, the wiring 3703, the connection pad 3701a, and the connection pad 3701b are electrically connected without passing through a contact hole. . Accordingly, the connection pad 3701a, the connection pad 3701b, and the wiring 3703 constitute a composite connection terminal. And the place where this composite connection terminal is connected to the FPC terminal is a connection pad 3701a and a connection pad 3701b.

In FIG. 37, the connection pads at both ends of the connection terminal portion are electrically connected to form a composite connection terminal, but the present invention is not limited to this. That is, a composite connection terminal can be configured by electrically connecting arbitrary connection pads of the connection terminal portion. Therefore, the number of connection pads to be electrically connected is not limited to two, and may be three, four, or more. By increasing the number, the contact area with the FPC pad can be increased, so that the contact resistance can be lowered.

In addition, according to this configuration, since each connection pad is connected without using a contact hole, connection between remote connection pads can be performed without causing an increase in contact resistance. Therefore, the resistance can be reduced.

Note that this structure can be combined with the structure of the connection terminal portion having various structures shown in Embodiment Mode 2. An example is shown in FIG.

In FIG. 38, the composite connection pad 3801a, the composite connection pad 3801b, the composite connection pad 3802, and the reference connection pad 3803 are arranged on the connection terminal portion on the substrate 101 at equal intervals.

Further, the composite connection pad 3801a and the composite connection pad 3801b are connected by a wiring 3804 formed on the edge side of the substrate 101 in the connection terminal portion. Note that the wiring 3804 is formed of a composite conductive pad 3801a and a composite conductive pad 3801b and a continuous conductive film, and thus the wiring 3804, the composite connected pad 3801a, and the composite connected pad 3801b are electrically connected without passing through a contact hole. It is connected. Therefore, a composite connection terminal is configured by the composite connection pad 3801a, the composite connection pad 3801b, and the wiring 3804. The composite connection terminal is connected to the FPC terminal at a composite connection pad 3801a and a composite connection pad 3801b.

In FIG. 38, the composite connection pads at both ends of the connection terminal portion are electrically connected to form a composite connection terminal. However, the present invention is not limited to this. That is, a composite connection terminal can be configured by electrically connecting arbitrary composite connection pads of the connection terminal portion. Therefore, the number of connection pads to be electrically connected is not limited to two, and may be three, four, or more. Further, the composite connection pad and the reference connection pad may be electrically connected by wiring provided on the edge of the substrate. Note that by increasing the number, the contact area with the FPC pad can be increased, so that the contact resistance can be lowered.

(Embodiment 8)
In the present embodiment, a structure that can further improve display defects of a display device will be described.

In this embodiment, a current source circuit in a peripheral driver circuit (such as a scan line driver circuit or a signal line driver circuit) or a wiring connecting the current source circuit and the current source does not overlap with the counter electrode. And

First, FIG. 27 shows a first configuration of the present embodiment. Note that portions common to FIG. 13 are denoted by common reference numerals and description thereof is omitted. In the configuration of FIG. 27, the signal line driver circuit 104 includes a latch circuit 2701 and a shift register 2702. A latch circuit 2701 is arranged at a position farther from the pixel portion 106 than the shift register 2702. In order to effectively use the area of the display panel, the distance between the signal line driver circuit 104 and the pixel portion 106 is reduced. Therefore, the counter electrode 202 protruding from the pixel portion 106 partially overlaps with the shift register 2702. However, the latch circuit 2701 having a current source, a current source circuit, or a wiring connecting them does not overlap the counter electrode 202.

With such a configuration, it is possible to prevent display defects caused by the parasitic capacitance effect formed by the wiring and the counter electrode 202 while effectively using the area of the display panel.

This is because the time for holding the video signal input to the latch circuit 2701 in each stage of the latch circuit is shorter than the time for writing the video signal from the latch circuit 2701 to the pixel. Therefore, when the signal current corresponding to the video signal is small, the influence of the parasitic capacitance is increased, and the video signal is not normally written to the latch circuit 2701.

Here, a configuration example of the signal line driver circuit 104 is shown in FIG. The shift register 2702 includes a plurality of flip-flops 4201 and flip-flops 4202. A clock signal (CLK) and a clock inversion signal (CLKB) are input to the shift register 2702. Then, a start pulse (S_SP) is input to the flip-flop 4201 in the first stage of the shift register 2702. Then, the pulse output from the second-stage flip-flop 4202 is delayed by one start pulse. That is, when the pulse input to the flip-flop 4201 is output from the flip-flop 4202, the output from the flip-flop 4202 is delayed by one pulse. This is a sampling pulse that takes the timing of holding the video signal (Video Data).

The latch circuit 2701 corresponds to each signal line, and a write selection switch 4203a, a write selection switch 4203b, a sampling switch 4204a, a sampling switch 4204b, a current source circuit 4205a, a current source circuit 4205b, a read selection switch 4206a, and a read selection, respectively. A switch 4206b is provided.

One of the write selection switch 4203a and the write selection switch 4203b is turned on, and the other is turned off. When the write selection switch 4203a is on, the write selection switch 4203b is turned off, and the current source circuit 4205a is selected as a current source circuit for writing a video signal. That is, the sampling switch 4204a is turned on in accordance with the timing at which the sampling pulse is input to the latch circuit 2701, and a current corresponding to the video signal is written to the current source circuit 4205a. Similarly, when the write selection switch 4203b is on, the write selection switch 4203a is turned off, and the current source circuit 4205b is selected as a current source circuit for writing a video signal. That is, the sampling switch 4204b is turned on according to the timing at which the sampling pulse is input to the latch circuit 2701, and a current corresponding to the video signal is written to the current source circuit 4205b.

When the write selection switch 4203a is on, the read selection switch 4206b is on and the read selection switch 4206a is off. Then, a current corresponding to the video signal written in the current source circuit 4205b is output to the signal line. Similarly, when the write selection switch 4203b is on, the read selection switch 4206a is on and the read selection switch 4206b is off. Then, a current corresponding to the video signal written in the current source circuit 4205a is output to the signal line.

Here, when the video line 4207 to which the video signal (Video Data) is input overlaps with the counter electrode, parasitic capacitance is generated. When the current value corresponding to the video signal is small, a current flows through the parasitic capacitance, and the video signal is not sufficiently written to the current source circuit. Then, display failure occurs.

However, with the structure shown in FIG. 27 in this embodiment mode, since the counter electrode 202 does not overlap the latch circuit 2701 even when the display panel area is effectively used, display defects can be prevented. .

As the current source circuit, any of the configurations shown in FIGS. 43 (a), (b), and (c) can be applied. The current source circuit in FIG. 43A includes a switch 4304, a transistor 4302, and a capacitor element 4303. Then, the current source 4301 writes the current source circuit. The current source circuit in FIG. 43B includes a switch 4313, a transistor 4311, and a capacitor 4312. Then, the current source 4301 writes the current source circuit. The current source circuit in FIG. 43C includes a switch 4324, a transistor 4321, a transistor 4322, a capacitor 4323, and a switch 4325. Then, the current source 4301 writes the current source circuit.

Next, FIG. 28 shows a second configuration of the present embodiment. Note that portions common to those in FIG. 14 are denoted by common reference numerals and description thereof is omitted. Also in this configuration, the signal line driver circuit 104 includes a latch circuit 2701 and a shift register 2702. A latch circuit 2701 is arranged at a position farther from the pixel portion 106 than the shift register 2702. In order to effectively use the area of the display panel, the distance between the signal line driver circuit 104 and the pixel portion 106 is reduced. Therefore, the counter electrode 202 protruding from the pixel portion 106 partially overlaps with the shift register 2702. However, the latch circuit 2701 having a current source, a current source circuit, or a wiring connecting them does not overlap the counter electrode 202.

In this structure, the wiring 1403 and the counter electrode 202 are connected to each other through the contact hole 1404 in the shift register 2702.

Next, FIG. 29 shows a third configuration of the present embodiment. Note that portions common to those in FIG. 15 are denoted by common reference numerals and description thereof is omitted. Also in this configuration, the signal line driver circuit 104 includes a latch circuit 2701 and a shift register 2702. A latch circuit 2701 is arranged at a position farther from the pixel portion 106 than the shift register 2702. In order to effectively use the area of the display panel, the distance between the signal line driver circuit 104 and the pixel portion 106 is reduced. Therefore, the counter electrode 202 protruding from the pixel portion 106 partially overlaps with the shift register 2702. However, the latch circuit 2701 having a current source, a current source circuit, or a wiring connecting them does not overlap the counter electrode 202.

Further, in this structure, the latch circuit 2701 is arranged on the opposite side of the pixel portion 106 with respect to the connection terminal portion 201 to which signals and power are supplied, so that wiring that causes parasitic capacitance is latched. It does not straddle the circuit 2701. Therefore, it is possible to prevent display defects.

Next, FIG. 30 shows a fourth configuration of the present embodiment. Note that portions common to those in FIG. 16 are denoted by common reference numerals and description thereof is omitted. Also in this configuration, the signal line driver circuit 104 includes a latch circuit 2701 and a shift register 2702. A latch circuit 2701 is arranged at a position farther from the pixel portion 106 than the shift register 2702. In order to effectively use the area of the display panel, the distance between the signal line driver circuit 104 and the pixel portion 106 is reduced. Therefore, the counter electrode 202 protruding from the pixel portion 106 partially overlaps with the shift register 2702. However, the latch circuit 2701 having a current source, a current source circuit, or a wiring connecting them does not overlap the counter electrode 202. Therefore, display defects can be prevented.

Next, FIG. 31 shows a fifth configuration of the present embodiment. Note that portions common to those in FIG. 17 are denoted by common reference numerals and description thereof is omitted. Also in this configuration, the signal line driver circuit 104 includes a latch circuit 2701 and a shift register 2702. A latch circuit 2701 is arranged at a position farther from the pixel portion 106 than the shift register 2702. In order to effectively use the area of the display panel, the distance between the signal line driver circuit 104 and the pixel portion 106 is reduced. Therefore, the counter electrode 202 protruding from the pixel portion 106 partially overlaps with the shift register 2702. However, the latch circuit 2701 having a current source, a current source circuit, or a wiring connecting them does not overlap the counter electrode 202. Therefore, display defects can be prevented.

Next, FIG. 32 shows a sixth configuration of the present embodiment. Note that portions common to those in FIG. 18 are denoted by common reference numerals and description thereof is omitted. Also in this configuration, the signal line driver circuit 104 includes a latch circuit 2701 and a shift register 2702. A latch circuit 2701 is arranged at a position farther from the pixel portion 106 than the shift register 2702. In order to effectively use the area of the display panel, the distance between the signal line driver circuit 104 and the pixel portion 106 is reduced. Therefore, the counter electrode 202 protruding from the pixel portion 106 partially overlaps with the shift register 2702. However, the latch circuit 2701 having a current source, a current source circuit, or a wiring connecting them does not overlap the counter electrode 202. Therefore, display defects can be prevented.

Next, FIG. 33 shows a seventh configuration of the present embodiment. Note that portions common to those in FIG. 19 are denoted by common reference numerals and description thereof is omitted. Also in this configuration, the signal line driver circuit 104 includes a latch circuit 2701 and a shift register 2702. A latch circuit 2701 is arranged at a position farther from the pixel portion 106 than the shift register 2702. In order to effectively use the area of the display panel, the distance between the signal line driver circuit 104 and the pixel portion 106 is reduced. Therefore, the counter electrode 202 protruding from the pixel portion 106 partially overlaps with the shift register 2702. However, the latch circuit 2701 having a current source, a current source circuit, or a wiring connecting them does not overlap the counter electrode 202. Therefore, display defects can be prevented.

Next, an eighth configuration of the present embodiment is shown in FIG. Note that portions common to those in FIG. 20 are denoted by common reference numerals and description thereof is omitted. Also in this configuration, the signal line driver circuit 104 includes a latch circuit 2701 and a shift register 2702. A latch circuit 2701 is arranged at a position farther from the pixel portion 106 than the shift register 2702. In order to effectively use the area of the display panel, the distance between the signal line driver circuit 104 and the pixel portion 106 is reduced. Therefore, the counter electrode 202 protruding from the pixel portion 106 partially overlaps with the shift register 2702. However, the latch circuit 2701 having a current source, a current source circuit, or a wiring connecting them does not overlap the counter electrode 202. Therefore, display defects can be prevented.

In this example, FIG. 35A shows a preferable magnitude relationship among the line width of the reference connection pad, the line width of the composite connection pad, the connection pitch, the line width of the FPC pad, and the FPC pitch shown in Embodiment Mode 1. This will be described with reference to (B) and (C).

FIG. 35A illustrates a state where the substrate 101 over which a circuit is formed and the FPC 103 are connected. FIG. 35B shows a partially enlarged view of the region surrounded by the dotted line 3501. A cross section thereof is shown in FIG.

First, description will be made with reference to FIG. On the substrate 101, connection pads (reference connection pads 112 and composite connection pads 113) are provided, and partition walls 114 are formed between the connection pads. The partition 114 has an insulating property and maintains insulation between the connection pads. The connection pads (the reference connection pad 112 and the composite connection pad 113) are connected to the corresponding FPC pads 111 through the anisotropic conductive film 411, respectively. In addition, although the structure in case the composite connection pad 113 connects with the two FPC pads 111 is shown here, it is not limited to this. As shown in FIG. 4C, conductive particles 421 may be mixed in the anisotropic conductive film 411. By doing so, the contact resistance can be lowered.

When the FPC 103 and the substrate 101 are bonded together, if there is no positional deviation in the line width direction of the pad, the central axis of the reference connection pad 112 and the central axis of the FPC pad 111 are coincident, and FIG. B) and (C).

Next, description will be made with reference to FIG. Line 3502 represents the edge of the FPC.

The line width L1 of the reference connection pad 112 is configured to be smaller than the connection pitch L3. Further, the line width L2 of the FPC pad 111 is configured to be larger than the FPC pitch L4. Further, the line width L 1 of the reference connection pad 112 is configured to be smaller than the line width L 2 of the FPC pad 111. That is, by configuring each pad so as to satisfy the conditions of L1 <L3, L2> L4, and L1 <L2, a slight positional deviation occurs in the line width direction of the pad when the FPC 103 and the substrate 101 are bonded together. In addition, electrical connection between corresponding pads can be made, and occurrence of a short circuit with an adjacent pad can be reduced.

Furthermore, according to this configuration, the line width L5 of the composite connection pad 113 is approximately equal to the total size of the line width L2 of the FPC pad 111, the line width L1 of the reference connection pad 112, and the FPC pitch L4. That is, L5 = L2 + L1 + L4. The line width of the connection region between the composite connection pad 113 and the two FPC pads 111 is L2 + L1. Then, since L2> L1, the connection area of the composite connection pad 113 connected to the two FPC pads 111 is more than twice the connection area of the reference connection pad 112 and the FPC pad 111. Therefore, the contact resistance at the composite connection pad 113 can be greatly reduced. In the case where the composite connection pad 113 is connected to three or more FPC pads 111, the connection area is also greatly increased, so that the contact resistance can be reduced.

In this embodiment, a structure of a display panel in the case where a light emitting element is used as a display element will be described.

In this embodiment, a display panel applicable to the display device of the present invention will be described with reference to FIG. 66A is a top view illustrating the display panel, and FIG. 66B is a cross-sectional view taken along line a-a ′ in FIG. 66A. A signal line driver circuit 6601, a pixel portion 6602, a second scan line driver circuit 6603, and a first scan line driver circuit 6606 indicated by dotted lines are included. Further, a sealing substrate 6604 and a sealing material 6605 are provided, and an inner side surrounded by the sealing material 6605 is a space 6607.

  Note that the wiring 6608 is a wiring for transmitting a signal input to the second scan line driver circuit 6603, the first scan line driver circuit 6606, and the signal line driver circuit 6601, and is an FPC (flexible) that serves as an external input terminal. Print circuit) 6609 receives a video signal, a clock signal, a start signal, and the like. An IC chip (semiconductor chip on which a memory circuit, a buffer circuit, or the like is formed) 6619 is mounted on a joint portion between the FPC 6609 and the display panel using COG (Chip On Glass) or the like. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to the FPC. The display device in this specification includes not only a display panel body but also a state in which an FPC or a PWB is attached thereto. In addition, it is assumed that an IC chip or the like is mounted.

  Next, a cross-sectional structure is described with reference to FIG. A pixel portion 6602 and its peripheral driver circuits (a second scan line driver circuit 6603, a first scan line driver circuit 6606, and a signal line driver circuit 6601) are formed over the substrate 6610. Here, signal lines A driver circuit 6601 and a pixel portion 6602 are shown.

  Note that the signal line driver circuit 6601 forms a CMOS circuit using an N-channel TFT 6620 and a P-channel TFT 6621. In this embodiment, a display panel in which peripheral drive circuits are integrally formed on a substrate is shown. However, this is not always necessary, and all or part of the peripheral drive circuits are formed on an IC chip and mounted by COG or the like. May be.

  The pixel portion 6602 includes a plurality of circuits included in a pixel including the TFT 6611 and the TFT 6612. Note that the source electrode of the TFT 6612 is connected to the first electrode 6613. An insulator 6614 is formed so as to cover an end portion of the first electrode 6613. Here, a positive photosensitive acrylic resin film is used.

  In order to improve the coverage, a curved surface having a curvature is formed at the upper end portion or the lower end portion of the insulator 6614. For example, in the case where positive photosensitive acrylic is used as a material for the insulator 6614, it is preferable that only the upper end portion of the insulator 6614 have a curved surface with a curvature radius (0.2 μm to 3 μm). As the insulator 6614, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

  Over the first electrode 6613, a layer 6616 containing an organic compound and a second electrode 6617 are formed. Here, as a material used for the first electrode 6613 which functions as an anode, a material having a high work function is preferably used. For example, ITO (Indium Tin Oxide) film, Indium Zinc Oxide (IZO) film, Titanium nitride film, Chromium film, Tungsten film, Zn film, Pt film, etc., as well as titanium nitride and aluminum as main components And a three-layer structure of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained.

  The layer 6616 containing an organic compound is formed by an evaporation method using an evaporation mask or an inkjet method. For the layer 6616 containing an organic compound, an element periodic group 4 metal complex is used as a part thereof, and other materials that can be used in combination include high molecular weight materials even if they are low molecular weight materials. It may be. In addition, as a material used for a layer containing an organic compound, an organic compound is usually used in a single layer or a stacked layer. However, in this embodiment, an inorganic compound is used for a part of a film made of an organic compound. Include. Further, a known triplet material can be used.

Further, as a material used for the second electrode (cathode) 6617 formed over the layer 6616 containing an organic compound, a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof MgAg, MgIn, AlLi, or the like) , CaF ₂ , or Ca ₃ N ₂ ) may be used. Note that in the case where light generated in the layer 6616 containing an organic compound transmits the second electrode 6617, the second electrode (cathode) 6617 can be formed using a thin metal film and a transparent conductive film (ITO ( A stack of an indium tin oxide alloy), an indium oxide zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), or the like) is preferably used.

  Further, the sealing substrate 6604 is attached to the substrate 6610 with the sealant 6605, whereby the light-emitting element 6618 is provided in the space 6607 surrounded by the substrate 6610, the seal substrate 6604, and the sealant 6605. Note that the space 6607 includes a structure filled with a sealant 6605 in addition to a case where the space 6607 is filled with an inert gas (nitrogen, argon, or the like).

  Note that an epoxy-based resin is preferably used for the sealant 6605. Moreover, it is desirable that these materials are materials that do not transmit moisture and oxygen as much as possible. In addition to a glass substrate and a quartz substrate, a plastic substrate formed of FRP (Fiberglass-Reinforced Plastics), PVF (polyvinyl fluoride), Mylar, polyester, acrylic, or the like can be used as a material used for the sealing substrate 6604.

  A display panel can be obtained as described above.

Further, an example of an EL element applicable to the light-emitting element 6618 is shown in FIG.

An anode 7202 over a substrate 7201, a hole injection layer 7203 made of a hole injection material, a hole transport layer 7204 made of a hole transport material, a light emitting layer 7205, an electron transport layer 7206 made of an electron transport material, and an electron In this element structure, an electron injection layer 7207 made of an injection material and a cathode 7208 are stacked. Here, the light emitting layer 7205 may be formed of only one kind of light emitting material, but may be formed of two or more kinds of materials. Further, the structure of the element of the present invention is not limited to this structure.

  In addition to the stacked structure in which the functional layers illustrated in FIG. 72A are stacked, an element using a polymer compound, a high-efficiency element using a triplet light-emitting material that emits light from a triplet excited state in a light-emitting layer, or the like There are a wide variety of variations. The present invention can also be applied to a white display element obtained by controlling the carrier recombination region by the hole blocking layer and dividing the light emitting region into two regions.

  In the element manufacturing method of the present invention illustrated in FIG. 72A, first, a hole injecting material, a hole transporting material, and a light emitting material are sequentially deposited on a substrate 7201 having an anode 7202. Next, an electron transport material and an electron injection material are vapor-deposited, and finally a cathode 7208 is formed by vapor deposition.

  Next, materials suitable for the hole injection material, the hole transport material, the electron transport material, the electron injection material, and the light emitting material are listed below.

As the hole injection material, porphyrin compounds, phthalocyanine (hereinafter referred to as “H ₂ Pc”), copper phthalocyanine (hereinafter referred to as “CuPc”), and the like are effective as long as they are organic compounds. In addition, any material that has a smaller ionization potential than the hole transport material used and has a hole transport function can also be used as the hole injection material. There is also a material obtained by chemically doping a conductive polymer compound, and examples thereof include polyethylenedioxythiophene (hereinafter referred to as “PEDOT”) doped with polystyrene sulfonic acid (hereinafter referred to as “PSS”), polyaniline, and the like. An insulating polymer compound is also effective in terms of planarization of the anode, and polyimide (hereinafter referred to as “PI”) is often used. In addition, inorganic compounds are also used. In addition to metal thin films such as gold and platinum, there are ultra thin films of aluminum oxide (hereinafter referred to as “alumina”).

  The most widely used hole transport material is an aromatic amine-based compound (that is, a compound having a benzene ring-nitrogen bond). As widely used materials, 4,4′-bis (diphenylamino) -biphenyl (hereinafter referred to as “TAD”) and its derivative 4,4′-bis [N- (3-methylphenyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “TPD”), 4,4′-bis [N- (1-naphthyl) -N-phenyl-amino] -biphenyl (hereinafter referred to as “α-NPD”) ). 4,4 ′, 4 ″ -tris (N, N-diphenyl-amino) -triphenylamine (hereinafter referred to as “TDATA”), 4,4 ′, 4 ″ -tris [N- (3-methylphenyl) And starburst aromatic amine compounds such as —N-phenyl-amino] -triphenylamine (hereinafter referred to as “MTDATA”).

As an electron transport material, a metal complex is often used, and Alq ₃ , BAlq, tris (4-methyl-8-quinolinolato) aluminum (hereinafter referred to as “Almq”), bis (10-hydroxybenzo [h] -quinolinato And metal complexes having a quinoline skeleton or a benzoquinoline skeleton such as beryllium (hereinafter referred to as “Bebq”). Further, bis [2- (2-hydroxyphenyl) -benzoxazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”), bis [2- (2-hydroxyphenyl) -benzothiazolate] zinc (hereinafter referred to as “Zn (BOX) ₂ ”) There is also a metal complex having an oxazole-based or thiazole-based ligand such as “Zn (BTZ) ₂ ”). In addition to metal complexes, 2- (4-biphenylyl) -5- (4-tert-butylphenyl) -1,3,4-oxadiazole (hereinafter referred to as “PBD”), OXD-7, and the like An oxadiazole derivative of TAZ, 3- (4-tert-butylphenyl) -4- (4-ethylphenyl) -5- (4-biphenylyl) -1,2,4-triazole (hereinafter referred to as “p-EtTAZ”) ) And other phenanthroline derivatives such as bathophenanthroline (hereinafter referred to as “BPhen”) and BCP have electron transport properties.

The electron transport material described above can be used as the electron injection material. In addition, an ultra-thin film of an insulator such as a metal halide such as calcium fluoride, lithium fluoride, or cesium fluoride, or an alkali metal oxide such as lithium oxide is often used. In addition, alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as “Li (acac)”) and 8-quinolinolato-lithium (hereinafter referred to as “Liq”) are also effective.

As the luminescent material, various fluorescent dyes are effective in addition to the metal complexes such as Alq ₃ , Almq, BeBq, BAlq, Zn (BOX) ₂ , Zn (BTZ) _{2 described} above. As fluorescent dyes, blue 4,4′-bis (2,2-diphenyl-vinyl) -biphenyl and red-orange 4- (dicyanomethylene) -2-methyl-6- (p-dimethylaminostyryl)- 4H-pyran. A triplet light emitting material is also possible, and is mainly a complex having platinum or iridium as a central metal. As the triplet light emitting material, tris (2-phenylpyridine) iridium, bis (2- (4′-tolyl) pyridinato-N, C ^{2 ′} ) acetylacetonatoiridium (hereinafter referred to as “acacIr (tpy) ₂ ”), 2,3,7,8,12,13,17,18-octaethyl-21H, 23H porphyrin-platinum and the like are known.

A highly reliable display element can be manufactured by combining the materials having the functions described above.

In addition, as shown in FIG. 72B, a display element in which layers are formed in the reverse order of FIG. 72A can be used. That is, a cathode 7218 on the substrate 7211, an electron injection layer 7217 made of an electron injection material, an electron transport layer 7216 made of an electron transport material, a light emitting layer 7215, a hole transport layer 7214 made of a hole transport material, In this element structure, a hole injection layer 7213 made of a hole injection material and an anode 7212 are laminated.

Further, in order to extract light emission from the display element, at least one of the anode and the cathode only needs to be transparent. Then, a TFT and a display element are formed on the substrate, and a top emission that extracts light emission from a surface opposite to the substrate, a bottom emission that extracts light emission from a surface on the substrate side, and a surface opposite to the substrate side and the substrate. The pixel structure of the present invention can be applied to a display element having any emission structure.

A light-emitting element having a top emission structure will be described with reference to FIG.

A TFT 7301 is formed over a substrate 7300, a first electrode 7302 is formed in contact with a source electrode of the TFT 7301, and a layer 7303 containing an organic compound and a second electrode 7304 are formed thereover.

The first electrode 7302 is an anode of the light emitting element. The second electrode 7304 is a cathode of the light emitting element. That is, a region where the layer 7303 containing an organic compound is sandwiched between the first electrode 7302 and the second electrode 7304 is a light-emitting element.

Here, as a material used for the first electrode 7302 functioning as an anode, a material having a high work function is preferably used. For example, in addition to a single layer film such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, or a Pt film, a stack of titanium nitride and a film containing aluminum as a main component, a film containing a titanium nitride film and aluminum as a main component A three-layer structure of titanium nitride film and the like can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained. By using a metal film that reflects light, an anode that does not transmit light can be formed.

As a material used for the second electrode 7304 functioning as a cathode, a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or Ca ₃ N ₂ ) is used. It is preferable to use a laminate of a metal thin film made of a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), or the like). Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

Thus, light from the light-emitting element can be extracted from the top surface as indicated by an arrow in FIG. That is, when applied to the display panel of FIG. 71, light is emitted to the substrate 7145 side. Accordingly, in the case where a light-emitting element having a top emission structure is used for a display device, the substrate 7145 is a light-transmitting substrate.

  In the case of providing an optical film, the substrate 7145 may be provided with an optical film.

Note that in the case of the pixel structure described in Embodiment 7, a metal film made of a material having a low work function such as MgAg, MgIn, or AlLi that functions as the cathode of the first electrode 7302 can be used. For the second electrode 7304, a transparent conductive film such as an ITO (indium tin oxide) film or indium zinc oxide (IZO) can be used. Therefore, according to this configuration, it is possible to increase the transmittance of top emission.

A light-emitting element having a bottom emission structure will be described with reference to FIG. Since the light-emitting element has the same structure as that in FIG. 73A except for the emission structure, the description will be made using the same reference numerals.

Here, as a material used for the first electrode 7302 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

As a material used for the second electrode 7304 functioning as a cathode, a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or Ca ₃ N ₂ ) is used. A metal film made of can be used. Thus, by using a metal film that reflects light, a cathode that does not transmit light can be formed.

In this manner, light from the light-emitting element can be extracted to the bottom surface as indicated by an arrow in FIG. That is, when applied to the display panel of FIG. 71, light is emitted to the substrate 7100 side. Therefore, in the case where a light-emitting element having a bottom emission structure is used for a display device, the substrate 7100 is a light-transmitting substrate.

  In the case of providing an optical film, the substrate 7100 may be provided with an optical film.

A light-emitting element having a dual emission structure will be described with reference to FIG. Since the light-emitting element has the same structure as that in FIG. 73A except for the emission structure, the description will be made using the same reference numerals.

Here, as a material used for the first electrode 7302 functioning as an anode, a material having a high work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode capable of transmitting light can be formed.

As a material used for the second electrode 7304 functioning as a cathode, a material having a low work function (Al, Ag, Li, Ca, or an alloy thereof such as MgAg, MgIn, AlLi, CaF ₂ , or Ca ₃ N ₂ ) is used. It is preferable to use a laminate of a metal thin film made of the above and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), etc.). Thus, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

In this manner, light from the light-emitting element can be extracted from both surfaces as indicated by arrows in FIG. That is, when applied to the display panel in FIG. 71, light is emitted to the substrate 7100 side and the substrate 7145 side. Therefore, in the case where a light-emitting element having a dual emission structure is used for a display device, the substrate 7100 and the substrate 7145 are both light-transmitting substrates.

  In the case where an optical film is provided, the optical film may be provided on both the substrate 7100 and the substrate 7145.

In addition, the present invention can be applied to a display device that realizes full color display using a white light emitting element and a color filter.

As shown in FIG. 74, a TFT 7401 is formed over a substrate 7400, a first electrode 7403 is formed in contact with the source electrode of the TFT 7401, and a layer 7404 containing an organic compound and a second electrode 7405 are formed thereover. ing.

The first electrode 7403 is an anode of the light emitting element. The second electrode 7405 is a cathode of the light emitting element. That is, a region where the layer 7404 containing an organic compound is sandwiched between the first electrode 7403 and the second electrode 7405 is a light-emitting element. In the configuration of FIG. 74, white light is emitted. A red color filter 7406R, a green color filter 7406G, and a blue color filter 7406B are provided above the light-emitting element, so that full color display can be performed. Further, a black matrix (also referred to as BM) 7407 for separating these color filters is provided.

  The structures of the light-emitting elements described above can be used in combination and can be used as appropriate for the display panel of the present invention. Further, the light-emitting element is an example, and a light-emitting element having another structure can be applied.

The display panel of the present invention can be applied to various electronic devices. Specifically, it can be applied to a display portion of an electronic device. Such electronic devices include video cameras, digital cameras, goggles-type displays, navigation systems, sound playback devices (car audio, audio components, etc.), computers, game devices, portable information terminals (mobile computers, mobile phones, portable games) And an image reproducing device (specifically, a device having a light emitting device capable of reproducing a recording medium such as a digital versatile disc (DVD) and displaying the image). It is done.

FIG. 65A illustrates a light-emitting device, which includes a housing 65001, a support base 65002, a display portion 65003, a speaker portion 65004, a video input terminal 65005, and the like. The display device of the present invention can be used for the display portion 65003. The light emitting devices include all information display light emitting devices such as for personal computers, for receiving television broadcasts, and for displaying advertisements. A light emitting device using the display panel of the present invention for the display portion 65003 can prevent display defects.

FIG. 65B shows a camera, which includes a main body 65101, a display portion 65102, an image receiving portion 65103, operation keys 65104, an external connection port 65105, a shutter 65106, and the like.

A camera using the display panel of the present invention for the display portion 65102 can prevent display failure.

  FIG. 65C illustrates a computer, which includes a main body 65201, a housing 65202, a display portion 65203, a keyboard 65204, an external connection port 65205, a pointing mouse 65206, and the like. A computer using the display panel of the present invention for the display portion 65203 can prevent display defects.

  FIG. 65D illustrates a mobile computer, which includes a main body 65301, a display portion 65302, a switch 65303, operation keys 65304, an infrared port 65305, and the like. A mobile computer using the display panel of the present invention for the display portion 65302 can prevent display defects.

FIG. 65E shows a portable image reproducing device (specifically, a DVD reproducing device) provided with a recording medium, which includes a main body 65401, a housing 65402, a display portion A 65403, a display portion B 65404, a recording medium (such as a DVD). A reading unit 65405, an operation key 65406, a speaker unit 65407, and the like are included. The display portion A 65403 can mainly display image information, and the display portion B 65404 can mainly display character information. An image reproducing device using the display panel of the present invention for the display portion A 65403 or the display portion B 65404 can prevent display defects.

  FIG. 65F illustrates a goggle type display which includes a main body 65501, a display portion 65502, and an arm portion 65503. A goggle type display using the display panel of the present invention for the display portion 65502 can prevent display defects.

  FIG. 65G illustrates a video camera, which includes a main body 652001, a display portion 652002, a housing 652003, an external connection port 652004, a remote control receiving portion 652005, an image receiving portion 652006, a battery 652007, an audio input portion 652008, operation keys 652009, and the like. . A video camera using the display panel of the present invention for the display portion 652002 can prevent a display defect.

  FIG. 65H shows a cellular phone, which includes a main body 65701, a housing 65702, a display portion 65703, an audio input portion 65704, an audio output portion 65705, operation keys 65706, an external connection port 65707, an antenna 65708, and the like. A mobile phone using the display panel of the present invention for the display portion 65703 can prevent display defects.

  Thus, the display panel of the present invention can be applied to any electronic device.

In this embodiment, a structural example of a mobile phone having the display panel of the present invention in a display portion will be described with reference to FIG.

  The display panel 6410 is incorporated in the housing 6400 so as to be detachable. The shape and dimensions of the housing 6400 can be changed as appropriate in accordance with the size of the display panel 6410. A housing 6400 to which the display panel 6410 is fixed is fitted into a printed board 6401 and assembled as a module.

  The display panel 6410 is connected to the printed circuit board 6401 through the FPC 6411. A signal processing circuit 6405 including a speaker 6402, a microphone 6403, a transmission / reception circuit 6404, a CPU, a controller, and the like is formed over the printed board 6401. Such a module, the input means 6406, and the battery 6407 are combined and housed in a housing 6409. The pixel portion of the display panel 6410 is arranged so as to be visible from an opening window formed in the housing 6412.

  Further, the configuration shown in this embodiment is an example of a mobile phone, and the display device of the present invention is not limited to the mobile phone having such a configuration, and can be applied to mobile phones having various configurations.

  FIG. 62 shows an EL module in which a display panel 6201 and a circuit board 6202 are combined. A display panel 6201 includes a pixel portion 6203, a scan line driver circuit 6204, and a signal line driver circuit 6205. On the circuit board 6202, for example, a control circuit 6206, a signal dividing circuit 6207, and the like are formed. The display panel 6201 and the circuit board 6202 are connected by a connection wiring 6208. An FPC or the like can be used for the connection wiring.

      With this EL module, an EL television receiver can be completed. FIG. 63 is a block diagram showing the main configuration of an EL television receiver. A tuner 6301 receives a video signal and an audio signal. The video signal includes a video signal amplifying circuit 6302, a video signal processing circuit 6303 that converts a signal output from the video signal into a color signal corresponding to each color of red, green, and blue, and the video signal as input specifications of the drive circuit. Processing is performed by a control circuit 6206 for conversion. The control circuit 6206 outputs a signal to each of the scan line side and the signal line side. In the case of digital driving, a signal dividing circuit 6207 may be provided on the signal line side so that an input digital signal is divided into m pieces and supplied.

  Of the signals received by the tuner 6301, the audio signal is sent to the audio signal amplifier circuit 6304, and the output is supplied to the speaker 6306 through the audio signal processing circuit 6305. The control circuit 6307 receives control information on the receiving station (reception frequency) and volume from the input unit 6308 and sends a signal to the tuner 6301 and the audio signal processing circuit 6305.

  As shown in FIG. 65A, the television set can be completed by incorporating the EL module shown in FIG. 62 into a housing 65001. A display portion 65003 is formed by the EL module. Further, a speaker portion 65004, a video input terminal 65005, and the like are provided as appropriate.

  Of course, the present invention is not limited to a television receiver, and is applied to various uses as a display medium of a particularly large area such as a monitor of a personal computer, an information display board in a railway station or airport, an advertisement display board in a street, etc. can do.

In this embodiment, a preferable configuration of a display panel having a composite connection pad in a connection terminal portion will be described.

First, the configuration of connection pads (reference connection pads and composite connection pads) in the connection terminal portion of the display panel will be described with reference to FIG.

A continuous conductive film is formed over the substrate 6701. The conductive film in the connection terminal region functions as a connection pad, and the conductive film in the wiring region functions as a wiring. In FIG. 67, the reference connection pad 6703 and the wiring 6706 are formed of a continuous conductive film. The composite connection pad 6704, the wiring 6707, and the wiring 6708 are formed of a continuous conductive film. The composite connection pad 6705, the wiring 6709, the wiring 6710, and the wiring 6711 are formed using a continuous conductive film.

In the seal region 6702, a counter substrate provided so as to face the substrate 6701 is bonded to the substrate with a sealant.

Note that the composite connection pad 6704 is connected to two FPC pads, and the composite connection pad 6705 is connected to three FPC pads.

Here, the line width of the reference connection pad 6703 is W, the line width of the composite connection pad 6704 is W ′, and the line width of the composite connection pad 6705 is W ″. Further, the distance between the centers of the line widths of adjacent reference connection pads is L.

Here, the distance between the line width center of the composite connection pad 6704 and the line width center of the reference connection pad is 1.5 times L, and the distance between the line width center of the composite connection pad 6705 and the line width center of the reference connection pad Is twice L. Therefore, since it is not necessary to change the FPC terminal arrangement, the FPC can be used without changing the specifications of the FPC.

The line width W ′ of the composite connection pad 6704 is preferably larger than the distance L between the line width centers of adjacent reference connection pads. Further, the line width W ″ of the composite connection pad 6705 is preferably larger than twice L. By doing so, the contact resistance between the connection pad and the FPC pad can be reduced.

Next, the role of a plurality of wirings electrically connected to the composite connection pad in the display panel will be described.

For example, in a display panel having two scan line driver circuits, the wiring 6707 in FIG. 67 is electrically connected to one scan line driver circuit, and the wiring 6708 in FIG. 67 is electrically connected to the other scan line driver circuit. Has been. That is, each wiring for supplying a common signal or a common power supply to the two scanning line driving circuits is electrically connected to one connection pad. Therefore, it is possible to prevent malfunction of the two scanning line driving circuits.

As another structure, in a display panel including a pixel portion and a peripheral driver circuit that drives the pixel, and the peripheral driver circuit includes a shift register and a buffer circuit, the wiring 6707 in FIG. 67 is electrically connected to the shift register. The wiring 6708 in FIG. 67 is electrically connected to the buffer circuit. That is, each wiring for supplying a common power to the shift register and the buffer circuit is electrically connected to one connection pad. That is, as illustrated in FIG. 68B, the wiring 6804 is a wiring for supplying power to the shift register 6801 and is electrically connected to the wiring 6707 in FIG. A wiring 6805 is a wiring for supplying power to the buffer circuit 6802 and is electrically connected to the wiring 6708 in FIG. Here, when power is supplied from the wiring 6803 to the shift register 6801 and the buffer circuit 6802 as shown in FIG. 68A, the power supply potential of the wiring 6803 decreases when a large current is output from the buffer circuit 6802. End up. Therefore, the shift register 6801 does not operate normally. Therefore, by operating as shown in FIG. 68B, malfunction of the shift register 6801 can be prevented.

As another structure, in a liquid crystal display panel including a liquid crystal element in a pixel, the wiring 6707 and the wiring 6708 in FIG. 67 are electrically connected to the counter electrode. That is, each wiring for supplying a power source potential as a power source to the counter electrode is electrically connected to one connection pad. Particularly in a liquid crystal display panel, the potential of the counter electrode is changed in order to extend the life of the liquid crystal element by reversing the polarity of the voltage applied to the liquid crystal element. Therefore, low power consumption can be achieved by reducing the resistance of the power supply line as in this configuration.

As another structure, in an EL display panel including an EL element in a pixel, the wiring 6707 and the wiring 6708 in FIG. 67 are electrically connected to a power supply line or a counter electrode. That is, each wiring for supplying a power supply potential as a power supply to the counter electrode or the power supply line is electrically connected to one connection pad. In particular, in an EL display panel, a large amount of current flows through the EL element. Therefore, if the resistance of the power supply line is large, a desired power supply potential cannot be obtained due to a voltage drop. Therefore, display resistance can be prevented by reducing the resistance of the power supply line as in this configuration.

As another structure, in a display panel including a light-emitting element in a pixel, the wiring 6707 in FIG. 67 is electrically connected to the counter electrode, and the wiring 6708 in FIG. 67 is a wiring (auxiliary wiring) provided in contact with the counter electrode. Are electrically connected to each other. That is, each wiring that supplies a common power source to the counter electrode and the auxiliary wiring is electrically connected to one connection pad. Note that a cross-sectional structure of the structure of the display panel in this case will be described with reference to FIGS.

A base film 7502 is provided over the substrate 7501. As the substrate 7501, a glass substrate, a quartz substrate, a plastic substrate, an insulating substrate such as a ceramic substrate, a metal substrate, a semiconductor substrate, or the like can be used. The base film 7502 can be formed by a CVD method or a sputtering method. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like formed by a CVD method using SiH ₄ , N ₂ O, or NH ₃ as a raw material can be used. Moreover, you may use these lamination | stacking. Note that the base film 7502 is provided to prevent impurities from diffusing from the substrate 7501 to the semiconductor layer, and the base film 7502 is not necessarily provided when a glass substrate or a quartz substrate is used for the substrate 7501.

An island-shaped semiconductor layer is provided over the base film 7502. In the semiconductor layer, a channel formation region 7505 of the transistor 7503, an impurity region 7506 to be a source region or a drain region and a low concentration impurity region (LDD region) 7507, and a channel formation region 7508 of the transistor 7504, an impurity region to be a source or drain region 7509, a low concentration impurity region (LDD region) 7510 is formed. Then, a gate electrode 7512 and a gate electrode 7513 are provided over the channel formation region 7505 and the channel formation region 7508 with a gate insulating film 7511 interposed therebetween. As the gate insulating film 7511, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or the like formed by a CVD method or a sputtering method can be used. As the gate electrode 7512 and the gate electrode 7513, an aluminum (Al) film, a copper (Cu) film, a thin film mainly containing aluminum or copper, a chromium (Cr) film, a tantalum (Ta) film, or a tantalum nitride (TaN) A film, a titanium (Ti) film, a tungsten (W) film, a molybdenum (Mo) film, or the like can be used.

A side wall 7514 is formed beside the gate electrode 7512, and a side wall 7515 is formed beside the gate electrode 7513. A silicon compound such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed so as to cover the gate electrode 7512 and the gate electrode 7513, and then etched back to form the sidewalls 7514 and 7515. .

Note that the low-concentration impurity regions 7507 and the low-concentration impurity regions 7510 are located below the sidewalls 7514 and 7515, respectively. That is, the low concentration impurity region 7507 and the low concentration impurity region 7510 are formed in a self-aligning manner. Note that the sidewall 7514 and the sidewall 7515 are provided in order to form the low-concentration impurity region 7507 and the low-concentration impurity region 7510 in a self-aligned manner, and are not necessarily provided.

A first interlayer insulating film is provided over the gate electrode 7512, the gate electrode 7513, the sidewall 7514, the sidewall 7515, and the gate insulating film 7511. The first interlayer insulating film has an inorganic insulating film 7516 in the lower layer and a resin film 7517 in the upper layer. As the inorganic insulating film 7516, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a film in which these are stacked can be used. As the resin film 7517, polyimide, polyamide, acrylic, polyimide amide, epoxy, or the like can be used.

A wiring 7518, a wiring 7519, and a wiring 7520 are provided over the first interlayer insulating film. The wiring 7518 has an impurity region 7506 through a contact hole, and the wiring 7519 has an impurity region 7506 and an impurity region 7509 through the contact hole. The wiring 7520 is electrically connected to the impurity region 7509 through a contact hole. As the wiring 7518, the wiring 7519, and the wiring 7520, a titanium (Ti) film, an aluminum (Al) film, a copper (Cu) film, an aluminum film containing Ti, or the like can be used. Note that in the case where a wiring such as a signal line is provided in the same layer as the wiring 7518, the wiring 7519, and the wiring 7520, low resistance copper may be used.

A second interlayer insulating film 7521 is provided over the wiring 7518, the wiring 7519, the wiring 7520, and the first interlayer insulating film. As the second interlayer insulating film 7521, an inorganic insulating film, a resin film, or a stacked layer thereof can be used. As the inorganic insulating film, a silicon nitride film, a silicon oxide film, a silicon oxynitride film, or a film in which these are stacked can be used. As the resin film, polyimide, polyamide, acrylic, polyimide amide, epoxy, or the like can be used.

A pixel electrode 7522 and a wiring 7523 are provided over the second interlayer insulating film 7521. The pixel electrode 7522 and the wiring 7523 are formed of the same material. That is, they are simultaneously formed in the same layer. As a material used for the pixel electrode 7522 and the wiring 7523, a material having a high work function is preferably used. For example, in addition to a single layer film such as a titanium nitride (TiN) film, a chromium (Cr) film, a tungsten (W) film, a zinc (Zn) film, or a platinum (Pt) film, a film containing titanium nitride and aluminum as main components. Or a three-layer structure of a titanium nitride film, a film containing aluminum as its main component, and a titanium nitride film can be used. Note that with a stacked structure, resistance as a wiring is low, good ohmic contact can be obtained, and a function as an anode can be obtained. By using a metal film that reflects light, an anode that does not transmit light can be formed.

An insulator 7524 is provided so as to cover end portions of the pixel electrode 7522 and the wiring 7523. For example, as the insulator 7524, a positive photosensitive acrylic resin film can be used.

A layer 7525 containing an organic compound is formed over the pixel electrode 7522, and part of the layer 7525 containing an organic compound overlaps with the insulator 7524. Note that the layer 7525 containing an organic compound is not formed over the wiring 7523.

A counter electrode 7526 is provided over the layer 7525 containing an organic compound, the insulator 7524, and the wiring 7523. As a material used for the counter electrode 7526, a material having a low work function is preferably used. For example, aluminum (Al), silver (Ag), lithium (Li), calcium (Ca), or an alloy thereof, or a metal thin film such as MgAg, MgIn, AlLi, CaF ₂ , or Ca ₃ N ₂ is used. it can. Thus, by using a thin metal thin film, a cathode capable of transmitting light can be formed.

In a region where the layer 7525 containing an organic compound is sandwiched between the counter electrode 7526 and the pixel electrode 7522, a light-emitting element 7527 is formed.

In a region where the layer 7525 containing an organic compound is isolated by the insulator 7524, a bonding portion 7528 is formed, and the counter electrode 7526 and the wiring 7523 are in contact with each other. Therefore, the wiring 7523 functions as an auxiliary electrode of the counter electrode 7526, and the resistance of the counter electrode 7526 can be reduced. Therefore, the thickness of the counter electrode 7526 can be reduced and the transmittance can be increased. Therefore, higher luminance can be obtained in a display panel having a structure in which light obtained from the light-emitting element 7527 is extracted from the top surface.

Note that in order to further reduce the resistance of the counter electrode 7526, a stack of a metal thin film and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), or the like) may be used. Good. Thus, a cathode capable of transmitting light can also be formed by using a thin metal thin film and a transparent conductive film having transparency.

Note that the impurity region 7506 and the impurity region 7509 are doped with N-type impurities. Thus, the transistor 7503 and the transistor 7504 are N-channel transistors.

Note that the display panel described with reference to FIGS. 75A and 75B can reduce the thickness of the film of the counter electrode 7526 and can transmit light emitted from the top surface. Therefore, the luminance from the upper surface can be increased. In addition, the resistance of the counter electrode 7526 can be reduced by connecting the wiring 7523 to the counter electrode 7526. Therefore, power consumption can be reduced. Note that the wiring 7523 is an auxiliary wiring.

Next, the configuration of the display panel will be described with reference to schematic views 76 (a) and (b) of the display panel as viewed from above. A signal line driver circuit 7601, a scan line driver circuit 7602, and a pixel portion 7603 are formed over the substrate 7600. Note that the substrate 7600 is connected to an FPC (flexible printed circuit) 7604 and receives signals such as a video signal, a clock signal, and a start signal input to the signal line driver circuit 7601 and the scan line driver circuit 7602 from the FPC 7604. An IC chip (a semiconductor chip on which a memory circuit, a buffer circuit, or the like is formed) 7605 is mounted on a joint portion between the FPC 7604 and the substrate 7600 by COG (Chip On Glass) or the like. Although only the FPC 7604 is illustrated here, a printed wiring board (PWB) may be attached to the FPC 7604. The display device in this specification includes not only a display panel body but also a state in which an FPC or a PWB is attached thereto. In addition, it is assumed that an IC chip or the like is mounted.

Pixels are arranged in a matrix in the pixel portion 7603 of the display panel illustrated in FIG. And it is a pixel row for each color element. A layer 7607 containing an organic compound is provided over one column of pixels for each color. In the pixel portion, in a region 7606 where the layer 7607 containing an organic compound is not provided, a joint portion between a wiring formed using the same material as the pixel electrode and the counter electrode is formed. That is, the joint portion 7528 in the cross-sectional view of FIG. 75 is formed in the region 7606 in FIG. FIG. 77 shows a schematic diagram of the upper surface of the pixel portion. In FIG. 77, a wiring 7702 is formed using the same material as the pixel electrode 7701. The pixel electrode 7701 corresponds to the pixel electrode 7522 in FIG. 75, and the wiring 7702 corresponds to the wiring 7523 in FIG. A layer containing an organic compound is formed over the pixel electrode 7701 for one column, and a light emitting element is formed in each region sandwiched between the pixel electrode 7701 and the counter electrode. In addition, since the wiring 7702 is in contact with the counter electrode at the joint, the resistance of the counter electrode can be reduced. That is, the wiring 7702 functions as an auxiliary electrode of the counter electrode. Note that with the structure of the pixel portion as shown in FIG. 77, a display panel with a high aperture ratio and a reduced resistance of the counter electrode can be provided.

Pixels are arranged in a matrix in the pixel portion 7603 of the display panel illustrated in FIG. And it is a pixel row for each color element. A layer 7617 containing an organic compound is provided for each column of pixels for each color. In the pixel portion, in a region 7616 where the layer 7617 containing an organic compound is not provided, a joint portion between a wiring formed using the same material as the pixel electrode and the counter electrode is formed. That is, the joint portion 7528 in the cross-sectional view of FIG. 75 is formed in the region 7616 in FIG. FIG. 78 shows a schematic diagram of the upper surface of the pixel portion. In FIG. 78, a wiring 7802 is formed using the same material as the pixel electrode 7801. The pixel electrode 7801 corresponds to the pixel electrode 7522 in FIG. 75, and the wiring 7802 corresponds to the wiring 7523 in FIG. A layer containing an organic compound is formed on each of the pixel electrodes 7801, and light emitting elements are formed in regions sandwiched between the pixel electrode 7801 and the counter electrode. In addition, since the wiring 7802 is in contact with the counter electrode at the joint, the resistance of the counter electrode can be reduced. That is, the wiring 7802 functions as an auxiliary electrode for the counter electrode. Note that a display panel in which the resistance of the counter electrode is further reduced can be provided by using the structure of the pixel portion as shown in FIG.

In the display panel described in this embodiment, the counter electrode has high translucency and the aperture ratio of the pixel is high; thus, the required light intensity can be obtained even when luminance is low. Thus, the reliability of the light emitting element can be improved. Further, since the resistance of the counter electrode can be reduced, power consumption can be reduced.

Further, a description will be given with reference to a schematic view of a display panel.

The display panel in FIG. 69 includes a signal line driver circuit 6903, a first scan line driver circuit 6904, a second scan line driver circuit 6905, a pixel portion 6906, and a connection terminal portion 6907 on a substrate 6901. Have. Then, the substrate 6901 and the counter substrate are attached to each other in the seal region 6902, and the signal line driver circuit 6903, the first scan line driver circuit 6904, and the second scan line driver circuit 6905 are sealed.

The connection terminal portion 6907 has a plurality of connection pads. Among the plurality of connection pads, the reference connection pad 6908 is electrically connected to the wiring 6910. The composite connection pad 6909 is electrically connected to the wiring 6911 and the wiring 6912. In addition, the wiring 6911 and the wiring 6912 are electrically connected to the signal line driver circuit 6903. For example, as illustrated in FIG. 68B, one of the wiring 6911 and the wiring 6912 is electrically connected to a wiring for supplying power to the shift register in the signal line driver circuit 6903, and the other is connected to the signal line driver circuit 6903. It is electrically connected to a wiring for supplying power to the buffer circuit in the inside.

70 includes a signal line driver circuit 7003, a first scan line driver circuit 7004, a second scan line driver circuit 7005, a pixel portion 7006, a connection terminal over a substrate 7001. Part 7007. Then, the substrate 7001 and the counter substrate are attached to each other in the seal region 7002, and the signal line driver circuit 7003, the first scan line driver circuit 7004, and the second scan line driver circuit 7005 are sealed.

The connection terminal portion 7007 has a plurality of connection pads. Among the plurality of connection pads, the reference connection pad 7008 is electrically connected to the wiring 7010. The composite connection pad 7009 is electrically connected to the wirings 7011 and 7012. The wiring 7011 is electrically connected to the first scan line driver circuit 7004 and the wiring 7012 is electrically connected to the second scan line driver circuit 7005.

In this embodiment, another structure that can be applied to the light-emitting element of the present invention will be described with reference to FIGS.

A light-emitting element utilizing electroluminescence is distinguished depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The former has an electroluminescent layer in which particles of a luminescent material are dispersed in a binder, and the latter has an electroluminescent layer made of a thin film of luminescent material, but is accelerated by a high electric field. This is common in that it requires more electrons. Note that the obtained light emission mechanism includes donor-acceptor recombination light emission using a donor level and an acceptor level, and localized light emission using inner-shell electron transition of a metal ion. In general, the dispersion-type inorganic EL element often has donor-acceptor recombination light emission, and the thin-film inorganic EL element often has localized light emission.

A light-emitting material that can be used in the present invention includes a base material and an impurity element serving as a light emission center. By changing the impurity element to be contained, light emission of various colors can be obtained. As a method for manufacturing the light-emitting material, various methods such as a solid phase method and a liquid phase method (coprecipitation method) can be used. Also, spray pyrolysis method, metathesis method, precursor thermal decomposition method, reverse micelle method, method combining these methods with high temperature firing, liquid phase method such as freeze-drying method, etc. can be used.

The solid phase method is a method in which a base material and an impurity element or a compound containing the impurity element are weighed, mixed in a mortar, heated and fired in an electric furnace, reacted, and the base material contains the impurity element. The firing temperature is preferably 700 to 1500 ° C. This is because the solid phase reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state. Although firing at a relatively high temperature is required, it is a simple method, so it has high productivity and is suitable for mass production.

The liquid phase method (coprecipitation method) is a method in which a base material or a compound containing the base material and an impurity element or a compound containing the impurity element are reacted in a solution, dried, and then fired. The particles of the luminescent material are uniformly distributed, and the reaction can proceed even at a low firing temperature with a small particle size.

As a base material used for the light-emitting material, sulfide, oxide, or nitride can be used. Examples of the sulfide include zinc sulfide (ZnS), cadmium sulfide (CdS), calcium sulfide (CaS), yttrium sulfide (Y ₂ S ₃ ), gallium sulfide (Ga ₂ S ₃ ), strontium sulfide (SrS), sulfide. Barium (BaS) or the like can be used. As the oxide, for example, zinc oxide (ZnO), yttrium oxide (Y ₂ O ₃ ), or the like can be used. As the nitride, for example, aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), or the like can be used. Furthermore, zinc selenide (ZnSe), zinc telluride (ZnTe), and the like can also be used, such as calcium sulfide-gallium sulfide (CaGa ₂ S ₄ ), strontium sulfide-gallium (SrGa ₂ S ₄ ), barium sulfide-gallium (BaGa). _It may be a ternary mixed crystal such as ₂ S ₄ ).

  As emission centers of localized emission, manganese (Mn), copper (Cu), samarium (Sm), terbium (Tb), erbium (Er), thulium (Tm), europium (Eu), cerium (Ce), praseodymium (Pr) or the like can be used. Note that a halogen element such as fluorine (F) or chlorine (Cl) may be added as charge compensation.

  On the other hand, a light-emitting material containing a first impurity element that forms a donor level and a second impurity element that forms an acceptor level can be used as the emission center of donor-acceptor recombination light emission. As the first impurity element, for example, fluorine (F), chlorine (Cl), aluminum (Al), or the like can be used. For example, copper (Cu), silver (Ag), or the like can be used as the second impurity element.

In the case where a light-emitting material for donor-acceptor recombination light emission is synthesized using a solid-phase method, a base material, a first impurity element or a compound containing the first impurity element, a second impurity element, or a second impurity element Each compound containing an impurity element is weighed and mixed in a mortar, and then heated and fired in an electric furnace. As the base material, the above-described base material can be used, and examples of the first impurity element or the compound containing the first impurity element include fluorine (F), chlorine (Cl), and aluminum sulfide (Al ₂ S). ₃ ) or the like, and examples of the second impurity element or the compound containing the second impurity element include copper (Cu), silver (Ag), copper sulfide (Cu ₂ S), and silver sulfide (Ag). ₂ S) or the like can be used. The firing temperature is preferably 700 to 1500 ° C. This is because the solid phase reaction does not proceed when the temperature is too low, and the base material is decomposed when the temperature is too high. In addition, although baking may be performed in a powder state, it is preferable to perform baking in a pellet state.

  In addition, as an impurity element in the case of using a solid phase reaction, a compound including a first impurity element and a second impurity element may be used in combination. In this case, since the impurity element is easily diffused and the solid-phase reaction easily proceeds, a uniform light emitting material can be obtained. Further, since no extra impurity element is contained, a light-emitting material with high purity can be obtained. As the compound including the first impurity element and the second impurity element, for example, copper chloride (CuCl), silver chloride (AgCl), or the like can be used.

  Note that the concentration of these impurity elements may be 0.01 to 10 atom% with respect to the base material, and is preferably in the range of 0.05 to 5 atom%.

  Alternatively, a light-emitting material containing a third impurity element may be used as a light-emitting material having a donor-acceptor recombination-type light emission center. In this case, the concentration of the third impurity element is preferably 0.05 to 5 atom% with respect to the base material. The light emitting material having such a configuration can emit light at a low voltage. Therefore, a light-emitting element that can emit light at a low driving voltage can be obtained, and a light-emitting element with reduced power consumption can be obtained. Further, an impurity element which becomes a light emission center of the above-described localized light emission may be included.

  As such a light emitting material, for example, ZnS is used as a base material, Cl is used as a first impurity element, Cu is used as a second impurity element, Ga and As are used as a third impurity element, and light emission of localized light emission is further performed. It is also possible to use a light emitting material containing Mn as the center. In order to form such a light emitting material, the following method can be used. Mn is added to the light-emitting material (ZnS: Cu, Cl), and baked in vacuum for about 2 to 4 hours. The firing temperature is preferably 700 to 1500 ° C. The fired product is pulverized to a particle size of 5 to 20 μm, GaAs having a particle size of 1 to 3 μm is added and stirred. A luminescent material can be obtained by baking this mixture at about 500 to 800 ° C. for 2 to 4 hours in a nitrogen stream containing sulfur gas. By using this luminescent material and forming a thin film by vapor deposition or the like, it can be used as a light emitting layer of a light emitting element.

In the case of a thin-film inorganic EL element, the electroluminescent layer is a layer containing the above-described luminescent material, and is a physical vapor deposition method such as a resistance vapor deposition method, a vacuum vapor deposition method such as an electron beam vapor deposition (EB vapor deposition) method, or a sputtering method. (PVD), metal organic chemical vapor deposition (CVD), chemical vapor deposition (CVD) such as hydride transport low pressure CVD, atomic layer epitaxy (ALE), or the like.

FIGS. 79A to 79C illustrate an example of a thin-film inorganic EL element that can be used as a light-emitting element. 79A to 79C, the light-emitting element includes a first electrode layer 50, an electroluminescent layer 51, and a second electrode layer 53.

The light-emitting element illustrated in FIGS. 79B and 79C has a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. 79A. The light-emitting element illustrated in FIG. 79B includes an insulating layer 54 between the first electrode layer 50 and the electroluminescent layer 52, and the light-emitting element illustrated in FIG. 79C includes the first electrode layer 50. And an electroluminescent layer 52, and an insulating layer 54 b is provided between the second electrode layer 53 and the electroluminescent layer 52. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Further, the insulating layer may be a single layer or a stacked layer including a plurality of layers.

79B, the insulating layer 54 is provided so as to be in contact with the first electrode layer 50. However, the order of the insulating layer and the electroluminescent layer is reversed so as to be in contact with the second electrode layer 53. An insulating layer 54 may be provided.

In the case of a dispersion-type inorganic EL element, a particulate light emitting material is dispersed in a binder to form a film-like electroluminescent layer. Process into particles. When particles having a desired size cannot be obtained sufficiently by the method for manufacturing a light emitting material, the particles may be processed into particles by pulverization or the like in a mortar or the like. A binder is a substance for fixing a granular light emitting material in a dispersed state and maintaining the shape as an electroluminescent layer. The light emitting material is uniformly dispersed and fixed in the electroluminescent layer by the binder.

In the case of a dispersion-type inorganic EL element, the electroluminescent layer can be formed by a droplet discharge method capable of selectively forming an electroluminescent layer, a printing method (screen printing, offset printing, etc.), a coating method such as a spin coating method, A dipping method, a dispenser method, or the like can also be used. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm. In the electroluminescent layer including the light emitting material and the binder, the ratio of the light emitting material may be 50 wt% or more and 80 wt% or less.

80A to 80C illustrate examples of a dispersion-type inorganic EL element that can be used as a light-emitting element. A light-emitting element in FIG. 80A has a stacked structure of a first electrode layer 60, an electroluminescent layer 62, and a second electrode layer 63, and a luminescent material 61 held by a binder in the electroluminescent layer 62. Including.

As a binder that can be used in this embodiment, an insulating material can be used, an organic material or an inorganic material can be used, and a mixed material of an organic material and an inorganic material may be used. As the organic insulating material, a polymer having a relatively high dielectric constant such as a cyanoethyl cellulose resin, or a resin such as polyethylene, polypropylene, polystyrene resin, silicone resin, epoxy resin, or vinylidene fluoride can be used. Alternatively, a heat-resistant polymer such as aromatic polyamide, polybenzimidazole, or siloxane resin may be used. Note that a siloxane resin corresponds to a resin including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent. Moreover, resin materials such as vinyl resins such as polyvinyl alcohol and polyvinyl butyral, phenol resins, novolac resins, acrylic resins, melamine resins, urethane resins, and oxazole resins (polybenzoxazole) may be used. Further, for example, a photocurable resin material or the like can be used. The dielectric constant can be adjusted by appropriately mixing fine particles of high dielectric constant such as barium titanate (BaTiO ₃ ) and strontium titanate (SrTiO ₃ ) with these resins.

Examples of the inorganic insulating material contained in the binder include silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon containing oxygen and nitrogen, aluminum nitride (AlN), aluminum containing oxygen and nitrogen, or aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), BaTiO ₃ , SrTiO ₃ , lead titanate (PbTiO ₃ ), potassium niobate (KNbO ₃ ), lead niobate (PbNbO ₃ ), tantalum oxide (Ta ₂ O ₅ ), tantalum Formed with a material selected from materials including barium oxide (BaTa ₂ O ₆ ), lithium tantalate (LiTaO ₃ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), ZnS and other inorganic insulating materials. can do. By including an inorganic material having a high dielectric constant in the organic material (by addition or the like), the dielectric constant of the electroluminescent layer made of the light emitting material and the binder can be further controlled, and the dielectric constant can be further increased. .

In the manufacturing process, the light-emitting material is dispersed in a solution containing a binder, but as a solvent for the solution containing a binder that can be used in this embodiment, a method of forming an electroluminescent layer by dissolving the binder material (various types) A solvent capable of producing a solution having a viscosity suitable for a wet process) and a desired film thickness may be appropriately selected. For example, when a siloxane resin is used as a binder, propylene glycol monomethyl ether, propylene glycol monomethyl ether acetate (also referred to as PGMEA), 3-methoxy-3-methyl-1-butanol (also referred to as MMB) can be used. Etc. can be used.

The light-emitting element illustrated in FIGS. 80B and 80C has a structure in which an insulating layer is provided between the electrode layer and the electroluminescent layer in the light-emitting element in FIG. The light-emitting element illustrated in FIG. 80B includes an insulating layer 64 between the first electrode layer 60 and the electroluminescent layer 62, and the light-emitting element illustrated in FIG. 80C includes the first electrode layer 60. And an electroluminescent layer 62, and an insulating layer 64 b between the second electrode layer 63 and the electroluminescent layer 62. Thus, the insulating layer may be provided only between one of the pair of electrode layers sandwiching the electroluminescent layer, or may be provided between both. Further, the insulating layer may be a single layer or a stacked layer including a plurality of layers.

In FIG. 80B, the insulating layer 64 is provided so as to be in contact with the first electrode layer 60; however, the order of the insulating layer and the electroluminescent layer is reversed so as to be in contact with the second electrode layer 63. An insulating layer 64 may be provided on the substrate.

Insulating layers such as the insulating layer 54 in FIG. 79 and the insulating layer 64 in FIG. 80 are not particularly limited, but preferably have high insulation resistance, a dense film quality, and a high dielectric constant. It is preferable. For example, silicon oxide (SiO ₂ ), yttrium oxide (Y ₂ O ₃ ), titanium oxide (TiO ₂ ), aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), tantalum oxide (Ta ₂ O ₅ ), Barium titanate (BaTiO ₃ ), strontium titanate (SrTiO ₃ ), lead titanate (PbTiO ₃ ), silicon nitride (Si ₃ N ₄ ), zirconium oxide (ZrO ₂ ), etc., a mixed film thereof, or two or more kinds thereof A laminated film can be used. These insulating films can be formed by sputtering, vapor deposition, CVD, or the like. The insulating layer may be formed by dispersing particles of these insulating materials in a binder. The binder material may be formed using the same material and method as the binder contained in the electroluminescent layer. The film thickness is not particularly limited, but is preferably in the range of 10 to 1000 nm.

The light-emitting element described in this embodiment can emit light by applying a voltage between a pair of electrode layers sandwiching an electroluminescent layer, but can operate in either DC driving or AC driving.

Note that the light-emitting element described in this embodiment can be applied to the light-emitting element in this specification. For example, the light-emitting element in the display panel of Embodiment 2 can also be applied. In that case, the electroluminescent layer of this example corresponds to the layer 6616 containing an organic compound in FIG.

In this embodiment, a structure of a display panel in the case where a liquid crystal element is used as a display element will be described.

FIG. 71A illustrates a liquid crystal display panel in which a signal line driver circuit 7130, a scan line driver circuit 7138, and a pixel portion 7131 are formed over a first substrate 7100.

FIG. 71B is a cross-sectional view taken along the line AA ′ of the liquid crystal display panel. The signal line driver circuit 7130 includes a CMOS circuit having an n-channel TFT 7121 and a p-channel TFT 7122 on the first substrate 7100. Indicates. The n-channel TFT 7121 and the p-channel TFT 7122 are preferably formed so as to have a crystalline semiconductor film. The TFT forming the signal line driver circuit 7130 and the scan line driver circuit 7138 may be formed of a CMOS circuit, a PMOS circuit, or an NMOS circuit.

  The pixel portion 7131 includes a TFT 7123 and a capacitor 7158. The TFT 7123 is preferably formed so as to have a crystalline semiconductor film. The capacitor 7158 includes a gate insulating film sandwiched between a semiconductor film to which an impurity is added and a gate electrode.

  Note that the TFT of the pixel portion 7131 is not required to have high crystallinity as compared with the signal line driver circuit 7130 and the scan line driver circuit 7138.

  The pixel portion 7131 includes a pixel electrode 7111 connected to one electrode of the TFT 7123. A third insulating film 7109 is provided so as to cover the n-channel TFT 7121, the p-channel TFT 7122, the pixel electrode 7111, the TFT 7123, and the like.

In addition, a second substrate 7145 which is a counter substrate is prepared. The second substrate 7145 is provided with a black matrix 7151 at least at a position corresponding to the signal line driver circuit 7130, a color filter 7152 at least at a position corresponding to the pixel portion, and a counter electrode 7153. . In the present invention, the second substrate 7145 is not necessarily provided with a black matrix, a color filter, or a counter electrode, and may be provided on the first substrate 7100 side. Thereafter, a spacer 7156 may be formed for maintaining the substrate interval. Further, a protrusion 7150 for preventing convection of the liquid crystal material may be formed at the same time for the purpose of preventing uneven distribution of the organic ferroelectric fine particles mixed with the liquid crystal material. As the spacer 7156, a spherical one may be used, or a so-called columnar spacer formed by etching an insulating film can be used. Further, the height of the protrusion 7150 may be the same as the thickness of the liquid crystal layer 7154 so that the protrusion 7150 has the same function as the spacer 7156. Whether the spacer 7156 and the protrusion 7150 are separate or the same is appropriately selected.

Next, the second substrate 7145 is subjected to an alignment treatment and attached to the first substrate 7100 using a sealant 7143. The sealant 7143 is preferably made of an epoxy resin. Alternatively, part of the third insulating film 7109 may be left at a position where the sealant 7143 is formed. As a result, the adhesion area is increased and the adhesion strength can be increased. Note that the spacer 7156 for maintaining the distance between the substrates may be formed after performing alignment treatment on the alignment film.

A liquid crystal layer 7154 is injected between the first substrate 7100 and the second substrate 7145. In the case of injecting the liquid crystal layer 7154, it may be performed in a vacuum. Alternatively, the second substrate 7145 may be attached after the liquid crystal layer is dropped onto the first substrate 7100. In particular, for a large substrate, it is preferable to drop the liquid crystal layer rather than injecting it.

  In addition, a polarizing plate or a circular polarizing plate may be provided as appropriate for the first substrate 7100 or the second substrate 7145 to increase contrast.

  In addition, a flexible printed circuit (FPC) 7146 is connected to the conductive film 7108 provided in the first adhesion region 7132 by an anisotropic conductive film (ACF). Then, a video signal and a clock signal which are external input signals are received via the FPC 7146. Although only the FPC is shown here, a printed wiring board (PWB) is attached via the FPC. An external signal generation circuit is mounted on the printed wiring board.

  Also, when the ACF is bonded by pressurization or heating, care should be taken not to cause cracks due to the flexibility of the substrate and softening due to heating. For example, a substrate having high rigidity may be provided as an auxiliary at least below the first bonding region 7132.

  In this embodiment, a driver-integrated light-emitting device in which a signal line driver circuit 7130 and a scan line driver circuit 7138 are provided over a first substrate 7100 is shown; however, the signal line driver circuit and the scan line driver circuit are formed using an IC. However, it may be connected to a signal line, a scanning line, or the like by an SOG method or a TAB method.

  As described above, a liquid crystal display panel can be manufactured.

FIG. 4A illustrates a display panel of the present invention. (B) The figure explaining a connection terminal part. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The schematic diagram of the display apparatus of this invention. FIG. 6 illustrates a display panel of the present invention. The schematic diagram of the display apparatus of this invention. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The schematic diagram of the display apparatus of this invention. The schematic diagram of the display apparatus of this invention. FIG. 6 illustrates a signal line driver circuit. FIG. 6 illustrates a current source circuit. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. The figure explaining a connection terminal part. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. Sectional drawing of the display apparatus of this invention. The figure explaining a connection terminal part. An example of an EL module. The block diagram which shows the main structures of EL television receiver. 4 is an example of a mobile phone to which the present invention can be applied. Examples of electronic devices. (A) The schematic diagram which shows the structure of the display panel of this invention. (B) The schematic diagram which shows the structure of the display panel of this invention. The figure explaining a connection terminal part. 10A and 10B illustrate power supply to a shift register and a buffer circuit. FIG. 6 illustrates a display panel of the present invention. FIG. 6 illustrates a display panel of the present invention. FIG. 6 illustrates a display panel of the present invention. FIG. 11 illustrates a light-emitting element. Sectional drawing of a display apparatus. Sectional drawing of a display apparatus. Sectional drawing of a display apparatus. FIG. 6 illustrates a display panel of the present invention. The elements on larger scale of the display panel of this invention. The elements on larger scale of the display panel of this invention. An example of a light emitting element. An example of a light emitting element.

Claims (1)

A pixel portion having a light emitting element;
A drive circuit unit having a latch circuit and a shift register;
A connection terminal portion having a plurality of connection pads,
It said plurality of single multiple wire to the connection pad are electrically connected,
The plurality of wirings are electrically connected to a counter electrode of the light emitting element,
The EL display panel, wherein the counter electrode overlaps the shift register and does not overlap the latch circuit.

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