JP5375114B2 - Processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To effectively use a register when data of data size which is odd to the bit width of the register continue. <P>SOLUTION: This processor has: an arithmetic part executing calculation to input data; a plurality of first registers storing the data; and an input data extraction part. For example, the input data extraction part reads an input bit string from the first registers storing the input bit string including the data of an arithmetic target. The input data extraction part extracts data of an arithmetic target from the read input bit string based on preset first position information, and extends the extracted data of the arithmetic target to a bit width of the arithmetic part. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a processor.

  The processor includes an arithmetic logic unit (hereinafter also referred to as ALU (Arithmetic Logic Unit)) that performs four arithmetic operations, logical operations, and the like, and a register. Generally, the bit length (bit width) of a register is 32 bits or 64 bits. For example, in a processor having a 32-bit register, when data with a data size (bit width) of less than 32 bits is stored in the register, the upper bits of the register are filled with “0” or sign extension. Therefore, the register is not used effectively when the data size is small. A processor has been proposed in which data having a data size that is a multiple of 8 (e.g., 8 bits or 16 bits) is continuously arranged and stored in a register, and each piece of continuous data is processed.

  For devices that handle variable bit length data, a configuration has been proposed in which a bit string composed of a plurality of variable bit length data is read from a data memory, and the read bit string is logically shifted by an arbitrary number of bits with a barrel shifter and input to an arithmetic unit. (For example, refer to Patent Document 1). In the configuration of Patent Document 1, the bit width of the bit string read from the data memory is at least twice (for example, 32 bits) the maximum bit length (for example, 16 bits) of the variable bit length data. The number of bits shifted by the barrel shifter is calculated by an arithmetic unit.

  A configuration has been proposed in which an ALU composed of a plurality of arithmetic units is divided by an arbitrary bit width, and a plurality of sets of data are respectively calculated by the divided ALU arithmetic units (see, for example, Patent Document 2).

  Data having a data size that is a multiple of 8 (such as 8 bits or 16 bits) is stored in a register in a register, and the processor that processes each piece of continuous data has an odd data size such as 7 bits or 9 bits. Is expanded to a data size that is a multiple of 8. In this case, the upper bits of the expanded data are filled with “0” or sign extension. Therefore, the register is not used effectively when data having an odd data size other than a multiple of 8 continues.

  An object of the present invention is to effectively use a register when data having a data size that is odd with respect to the bit width of the register continues.

  The processor includes an operation unit that performs an operation on input data, a plurality of first registers that store data, and an input data extraction unit. For example, the input data extraction unit reads the input bit string from the first register in which the input bit string including the operation target data is stored. The input data extraction unit extracts data to be calculated from the read input bit string based on the first position information set in advance, and expands the extracted data to be calculated to the bit width of the calculation unit.

  The register can be used effectively when data having an odd data size with respect to the bit width of the register continues.

It is a figure which shows the outline | summary of the processor in one Embodiment. It is a figure which shows an example of the control part shown in FIG. It is a figure which shows an example of operation | movement of the update part shown in FIG. It is a figure which shows an example of the data stored in the register | resistor shown in FIG. It is a figure which shows the outline | summary of the input data extraction part shown in FIG. It is a figure which shows the outline | summary of the output data generation part shown in FIG. It is a figure which shows the outline | summary of the processor in another embodiment. It is a figure which shows an example of the control part shown in FIG. It is a figure which shows an example of operation | movement of the update part shown in FIG. FIG. 10 is a diagram showing a continuation of the operation shown in FIG. 9. It is a figure which shows an example of operation | movement of the conversion part shown in FIG. It is a figure which shows the outline | summary of the input data extraction part shown in FIG. It is a figure which shows the outline | summary of the output data generation part shown in FIG. It is a figure which shows an example of the relationship between a load command and the state of a register. It is a figure which shows an example of the data stored in the register | resistor shown in FIG. It is a figure which shows an example of operation | movement of the input data extraction part shown in FIG. FIG. 17 is a diagram showing a continuation of the operation shown in FIG. 16. It is a figure which shows an example of operation | movement of the output data generation part shown in FIG. It is a figure which shows the continuation of the operation | movement shown in FIG. FIG. 20 is a diagram showing a continuation of the operation shown in FIG. 19.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows an embodiment of the present invention. The processor 10 includes an execution unit 20, a register file 30, control registers 40, 41 and 42, and a control unit 50. For example, the processor 10 is a 32-bit processor, and has a 32-bit wide general-purpose register R (R0-R9) in the register file 30. Note that general-purpose registers R4, R6, and R8 surrounded by broken lines in the figure are registers for storing data, and control registers 40, 41, and 42 are provided corresponding to the general-purpose registers R4, R6, and R8, respectively. ing. Hereinafter, the general-purpose registers R (R0 to R9) are also referred to as registers R (R0 to R9).

  The execution unit 20 reads the data from the register file 30, receives the data from the two input data extraction units 22 that output the data to the instruction execution unit 24, the instruction execution unit 24 that executes the instructions, and the instruction execution unit 24, And an output data generation unit 28 for writing data to the register file 30. For example, the instruction execution unit 24 includes an arithmetic logic unit (hereinafter also referred to as ALU (Arithmetic Logic Unit)) 25 that executes four arithmetic operations, logical operations, and the like, and a load / store unit 26 that executes a load / store instruction. Have. The execution unit 20 may have an input data extraction unit that combines the input data extraction units 22 shown in the figure.

  For example, when the registers R4, R6, and R8 are accessed by an instruction, the control registers 40, 41, and 42 are referred to by the control unit 50, respectively. For example, the control register 40 has an enable EN indicating whether or not to enable the control register 40, a bit length LN indicating the bit length of the access target data stored in the register R4, and the access target data in the register R4. It has an offset OF indicating an offset value (data position). For example, when enabling the control register 40, the enable EN is set to “1”. Further, the offset OF is updated during operation to indicate a data position to be used next, as shown in FIG. 3 described later.

  Similarly, for example, the control register 41 has an enable EN indicating whether or not to enable the control register 41, a bit length LN indicating the bit length of the access target data stored in the register R6, and a register R6 of the access target data. It has an offset OF indicating an offset value inside. Also, for example, the control register 42 is an enable EN that indicates whether the control register 41 is enabled, a bit length LN that indicates the bit length of the access target data stored in the register R6, and the access target data in the register R6. It has an offset OF indicating an offset value at. That is, the control registers 41 and 42 are the same as the control register 40 except for the corresponding registers R (R6 and R8).

  For example, the control unit 50 receives a register number RN1 indicating the register R accessed by the instruction and an instruction type TP indicating the instruction type from the decoder (not shown), and updates the offset OF of the control registers 40, 41, and 42. To do. In this embodiment, the registers RS1 and RT1 with the register number RN1 indicate the source register R, and the register RD1 with the register number RN1 indicates the destination register R. The instruction type TP indicates the type of instruction to be executed (such as a load instruction).

  For example, the control unit 50 outputs the register number RN1 and the control information RINF 10, 20, and 30 read from the control registers 40, 41, and 42 to the execution unit 20. For example, each control information RINF 10, 20, 30 is information including an enable EN, a bit length LN, and an offset OF of each control register 40, 41, 42. In FIG. 1, description of a control signal (for example, an initial value INT1 shown in FIG. 2 described later) for setting initial values of the control registers 40, 41, and 42 is omitted.

  FIG. 2 shows an example of the control unit 50 shown in FIG. The control unit 50 (the portion surrounded by the broken line in the figure) has an update unit 51 and a selector 52A. 2 shows the update unit 51 and the selector 52A for updating the offset OF of the control register 40, and the description of the update unit 51 and the selector 52A for updating the offset OF of the control registers 41 and 42 is omitted. ing. For example, the update unit 51 and the selector 52A for updating the offset OF of the control registers 41 and 42 are the same as those in FIG. 2 except for the control registers 41 and 42 to be controlled.

  For example, the control unit 50 receives the initial value INT1, and sets the values of the enable EN, the bit length LN, and the offset OF of the control register 40 to the initial value INT1. In this case, the selector 52A selects the value of the initial value INT1 (more specifically, the initial value of the offset OF) as a value to be set in the control register 40. Here, for example, the control registers 40, 41, and 42 are allocated on the address map. As a result, the values (initial values, etc.) of the control registers 40, 41, and 42 can be set by a load instruction or a store instruction. In the example shown in the figure, the control registers 40, 41, and 42 are constituted by flip-flops (hereinafter also referred to as FFs).

  For example, the update unit 51 updates the offset OF based on the register number RN1 and the instruction type TP. For example, when an instruction for accessing the register R4 is executed, the updating unit 51 calculates a bit position in the register R4 of data to be used next, and updates the offset OF. Details of the operation of the updating unit 51 will be described later with reference to FIG. When updating the offset OF, the selector 52A selects a value received from the updating unit 51 as a value to be set in the control register 40.

  FIG. 3 shows an example of the operation of the update unit 51 shown in FIG. 3 shows the operation of the update unit 51 (update unit 51 for the control register 40) for updating the offset OF of the control register 40. That is, FIG. 3 illustrates the operation of the update unit 51 for the control register 40. Each operation of the updating unit 51 (updating unit 51 for the control registers 41 and 42) for updating the offset OF of the control registers 41 and 42 is explained by replacing the register R4 with the registers R6 and R8, respectively. Note that the selector 52A shown in FIG. 2 described above selects the value received from the update unit 51 as the value to be set in the control register 40.

  First, in process 60, the updating unit 51 determines whether or not an access to the register R4 occurs based on the register number RN1. When the register R4 is accessed (Yes in process 60), the operation of the update unit 51 proceeds to process 61. When the register R4 is not accessed (No in process 60), the update unit 51 does not update the offset OF. The process ends. The update unit 51 for the control registers 41 and 42 determines whether or not access to the registers R6 and R8 occurs in the process 60, respectively.

  In the process 61, the update unit 51 determines whether or not the enable EN is set to “1”. That is, it is determined whether or not the control register to be updated (control register 40 in the example in the figure) is valid. When the enable EN is “1” (Yes in process 61), the operation of the update unit 51 proceeds to process 62. When the enable EN is not “1” (No in process 61), the update unit 51 sets the offset OF. The process ends without updating.

  In process 62, the update unit 51 determines whether the instruction is a load instruction based on the instruction type TP. If it is not a load instruction (No in process 62), the operation of the update unit 51 proceeds to process 63. If it is a load instruction (Yes in process 62), the update unit 51 ends the process without updating the offset OF. .

  In process 63, the update unit 51 determines whether the instruction is a store instruction based on the instruction type TP. If it is not a store instruction (No in process 63), the operation of the update unit 51 proceeds to process 64. If it is a store instruction (Yes in process 63), the update unit 51 ends the process without updating the offset OF. .

  In process 64, the updating unit 51 determines whether or not the addition result of the value obtained by doubling the bit length LN and the offset OF is equal to or greater than the bit width of the register R (32 in this embodiment). When the addition result is 32 or more (Yes in process 64), the operation of the update unit 51 proceeds to process 65. When the addition result is 31 or less (No in process 64), the operation of the update unit 51 proceeds to process 66. Move.

  In processing 65, the updating unit 51 sets the offset OF to 0. In process 66, the update unit 51 updates the offset OF to a value obtained by adding the bit length LN to the current offset OF. As a result, the offset OF is sequentially updated to the position of the next data to be used.

  Note that the offset OF may be set to “0” after the load instruction and the store instruction are executed. In this case, for example, in Yes in process 62 and Yes in process 63, the operation of the update unit 51 proceeds to process 65 (set the offset OF to “0”).

  FIG. 4 is a diagram illustrating an example of data stored in the registers R4, R6, and R8. FIG. 4A shows an example of a program for adding continuous data DS0, DS1, and DS2 and continuous data DT0, DT1, and DT2, respectively. FIG. 4B shows an outline of the states of the registers R4, R6, and R8 when the program of FIG. 4A is executed. Addresses adr1, adr2, and adr3 in FIG. 4A indicate addresses of a memory (not shown), and a shaded portion in FIG. 4B indicates an area in which valid data is not stored. In the illustrated registers R4, R6, and R8, the right side is the lower bits.

  The bit length of data DS0, DS1, DS2, DT0, DT1, DT2 is 9 bits, and the bit length of data DD0, DD1, DD2 is 10 bits. Therefore, the bit lengths LN of the control registers 40, 41, and 42 shown in FIG. 1 are set to “9”, “9”, and “10”, respectively. Further, the initial value of the offset OF of the control registers 40, 41, 42 is set to “0”.

  In the program of FIG. 4A, first, the processor 10 loads the data DS0, DS1, and DS2 stored continuously at the address adr1 into the register R4 (FIGS. 4A1 and 4B1). Next, the processor 10 loads data DT0, DT1, and DT2 continuously stored at the address adr2 into the register R6 (FIGS. 4A2 and 4B1). In the example of the figure, the area that is not effectively used for the registers R4 and R6 is 5 bits, and the register R is compared with the configuration in which the data is stored in one register R for each of the data DS0, DS1, DS2, DT0, DT1, and DT2. Can be used effectively. Furthermore, in this embodiment, since the ALU 25 shown in FIG. 1 described above does not need to perform a shift operation or the like in order to extract the data to be calculated, it is possible to process the calculation of continuous data at high speed.

  Then, the processor 10 adds the data DS0 stored in the register R4 and the data DT0 stored in the register R6, and stores the data DD0 as the addition result in the register R8 (FIG. 4 (a3), ( b2)). At this time, the offset OF of the control registers 40, 41, and 42 is updated to “9”, “9”, and “10” by the operation shown in FIG. Next, the processor 10 adds the data DS1 stored in the register R4 and the data DT1 stored in the register R6, and stores the data DD1 as the addition result in the register R8 (FIG. 4 (a4)). (B3)). At this time, the offsets OF of the control registers 40, 41, and 42 are updated to “18”, “18”, and “20”, respectively, by the operation shown in FIG. Thereafter, the processor 10 adds the data DS2 stored in the register R4 and the data DT2 stored in the register R6, and stores the data DD2 as the addition result in the register R8 (FIG. 4 (a5), ( b4)).

  As described above, the area of the register R8 that is not used effectively is 2 bits, and the register R can be used more effectively than the configuration in which the data is stored in one register R for each of the data DD0, DD1, and DD2. Furthermore, in this embodiment, it is not necessary for the ALU 25 to execute a shift operation or the like in order to continuously arrange a plurality of operation result data, so that the operation of continuous data can be processed at high speed. Finally, the processor 10 stores the data DD0, DD1, DD2 stored in the register R8 at the address adr3 (FIG. 4 (a6)). Thus, in this embodiment, it is not necessary to expand the data DS0, DS1, DS2, DT0, DT1, DT2, DD0, DD1, DD2 to 32 bits and store them in the memory, so that the memory can be used effectively. .

  FIG. 5 shows an overview of the input data extraction unit 22 shown in FIG. The shaded portion in the figure indicates a portion that is not valid data. Note that the states of the data DS0, DS1, and DS2 in the figure correspond to the states when the above-described instruction of FIG. 4 (a4) is executed. In the data DS0, DS1, DS2 in the figure, the right side is the lower bit. The input data extraction unit 22 includes a left logical shift unit 220, a right arithmetic shift unit 221, and a selector 222.

  The left logical shift unit 220 logically shifts the data RDATA read from the register R to the left by the shift amount LSL. In the example of the figure, the data RDATA is data including invalid data (shaded part in the figure), data DS2, DS1, and DS0. The shift amount LSL is a value obtained by subtracting the added value of the bit length LN and the offset OF of the control register (for example, the control register 40) corresponding to the read register R from 32 which is the bit width of the register R. For example, the operation target data DS1 is shifted to the leftmost side of the 32-bit width data by the left logical shift unit 220.

  The right arithmetic shift unit 221 right-shifts the output data (32-bit width data) of the left logical shift unit 220 by the shift amount ASR. That is, an empty bit on the left side of 32-bit width data is filled with the sign extension SE. As a result, the input data extraction unit 22 can handle signed data. The shift amount ASR is a value obtained by subtracting the bit length LN of the control register (for example, the control register 40) corresponding to the read register R from 32 which is the bit width of the register R. By the right arithmetic shift unit 221, for example, the data DS1 to be calculated is shifted to the rightmost side of 32-bit width data.

  Based on the selection signal SEL, the selector 222 outputs one of the data S1 and S2 as the data IDATA to the instruction execution unit 24 shown in FIG. For example, when the data RDATA is read from any of the registers R4, R6, and R8, the selector 222 sets the enable EN of the control registers 40, 41, and 42 corresponding to the registers R4, R6, and R8 from which the data RDATA is read to “1”. When “(the control register is valid)”, the data S2 (the output data of the right arithmetic shift unit 221) is output to the instruction execution unit 24 as data IDATA. Under other conditions, the selector 222 outputs the data RDATA (data S1) read from the register R to the instruction execution unit 24 as data IDATA.

  For example, when the data RDATA is read from the registers R other than the registers R4, R6, and R8, the selector 222 outputs the data RDATA (data S1) read from the register R to the instruction execution unit 24 as data IDATA. That is, in this embodiment, the selection signal SEL is generated by, for example, the register number RN1 indicating the register R from which the data RDATA is read and the enable EN of the control registers 40, 41, and 42.

  FIG. 6 shows an overview of the output data generation unit 28 shown in FIG. Note that the states of the data DD0 and DD1 in the figure correspond to the state when the above-described instruction of FIG. 4 (a4) is executed. The right side of the data DD0 and DD1 in the figure is the lower bit. The output data generation unit 28 includes a left logical shift unit 280, a right logical shift unit 281, an FF 282, an OR circuit (hereinafter also referred to as OR) 283, and a selector 284.

  The left logical shift unit 280 logically shifts the data (for example, the operation result of the ALU 25) EDATA received from the instruction execution unit 24 shown in FIG. 1 to the left by the shift amount LSL. In the example of the figure, the data EDATA is 32-bit width data composed of the sign extension SE and the data DD1. The shift amount LSL is a value obtained by subtracting the bit length LN of the control register (for example, the control register 42) corresponding to the register R storing the calculation result from 32, which is the bit width of the register R. For example, the operation result data DD1 is shifted to the leftmost side of the 32-bit width data by the left logical shift unit 280.

  The right logical shift unit 281 right-shifts the output data (32-bit width data) of the left logical shift unit 280 by the shift amount LSR. Note that empty bits of 32-bit width data are filled with “0”. Further, the shift amount LSR is a value obtained by subtracting the added value of the bit length LN and the offset OF of the control register (for example, the control register 42) corresponding to the register R storing the calculation result from the bit width 32 of the register R. is there. For example, the operation result data DD1 is shifted by the right logical shift unit 281 to a position where the least significant bit of the data DD1 matches the position of the offset OF in the 32-bit width data.

  The OR circuit 283 outputs the OR of the output data of the right logical shift unit 281 and the data read from the FF 28 to the selector 284 and the FF 282. In addition, in the FF 282, output data of the OR circuit 283 when the previous arithmetic instruction (for example, FIG. 4 (a3)) is executed (in the example of the figure, data DD0 and “0” are arranged in order from the lower bit). 32 bits wide data) is stored. Then, according to the current operation instruction (for example, FIG. 4 (a4)), the FF 282 stores data DD0, data DD1, and data of 32 bits in which “0” is arranged in order from the lower bit.

  Based on the selection signal SEL, the selector 284 outputs one of the data S1 and S2 as data ODATA to the register R indicated by the register number RN1. For example, when the selector 284 stores the data ODATA in any of the registers R4, R6, and R8, the enable EN of the control registers 40, 41, and 42 corresponding to the registers R4, R6, and R8 in which the data ODATA is stored is “ When 1 ″ (the control register is valid), data S2 (output data of the OR circuit 283) is output to the register R as data ODATA. Under other conditions, the selector 222 outputs the data EDATA (data S1) received from the instruction execution unit 24 as data ODATA to the register R indicated by the register number RN1.

  For example, when storing the data ODATA in the register R other than the registers R4, R6, and R8, the selector 284 outputs the data EDATA (data S1) received from the instruction execution unit 24 to the register R as the data ODATA. That is, in this embodiment, the selection signal SEL is generated by, for example, the register number RN1 indicating the register R in which the data ODATA is stored and the enable EN of the control registers 40, 41, and 42.

  As described above, in this embodiment, the input data extraction unit 22 sequentially reads data having an arbitrary bit length from one of the registers R4, R6, and R8 based on the control registers 40, 41, and 42. Furthermore, in this embodiment, the output data generation unit 28 sequentially stores a plurality of data having an arbitrary bit length in one of the registers R4, R6, and R8 based on the control registers 40, 41, and 42. Therefore, in this embodiment, the register R can be used more effectively than the configuration in which data is stored in one register R for each data. That is, in this embodiment, the register can be used effectively even when data having a data size that is odd with respect to the bit width of the register (for example, a data size other than a multiple of 8) is continuous.

  FIG. 7 shows an overview of a processor in another embodiment. The processor 11 of this embodiment includes an execution unit 21, control registers 43, 44, 45, and a control unit 54 instead of the execution unit 20, control registers 40, 41, and 42 and the control unit 50 shown in FIG. Each is provided. Other configurations are the same as those of the processor 10 described with reference to FIGS. The same elements as those described in FIGS. 1 to 6 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  For example, the processor 11 is a 32-bit processor, and includes an execution unit 21, a register file 30, control registers 43, 44, 45 and a control unit 54. It should be noted that control registers 43, 44, and 45 are provided corresponding to the groups of registers R (R4 and R5, R6 and R7, R8 and R9) surrounded by a broken line in the drawing. That is, the control registers 43, 44, 45 are provided corresponding to the groups of registers R (R4 and R5, R6 and R7, R8 and R9) surrounded by a broken line in the drawing.

  The execution unit 21 is provided with an input data extraction unit 23 and an output data generation unit 29 instead of the input data extraction unit 22 and the output data generation unit 28 shown in FIG. The input data extraction unit 23 is configured to be able to read data stored across both registers of a set of registers R (for example, R4 and R5, R6 and R7, R8 and R9). For example, when data is read from a register group including registers R4 and R5, the input data extraction unit 23 can read data stored across the registers R4 and R5. Details of the input data extraction unit 23 will be described later with reference to FIG.

  The output data generation unit 29 is configured to store data across both registers of the set of registers R (for example, R4 and R5, R6 and R7, R8 and R9). For example, when storing two 20-bit data in a register group composed of the registers R4 and R5, the output data generation unit 29 stores the lower 12 bits of the second data in the register R4. The upper 8 bits of the data are stored in the register R5. Details of the output data generation unit 29 will be described later with reference to FIG.

  The control register 43 is provided corresponding to a register group including the registers R4 and R5. For example, when the registers R4 and R5 are accessed by an instruction, the control register 43 is referred to. For example, the control register 43 has an enable EN, a bit length LN, an offset OF, register numbers RPT, WPT, empty EMP, and full FUL. The enable EN, the bit length LN, and the offset OF are the same as the enable EN, the bit length LN, and the offset OF described with reference to FIG. For example, when enabling the control register 43, the enable EN is set to “1”. The offset OF is set with an offset value (data position) in the register R4 of the data to be accessed when accessing the register R4. When accessing the register R5, the offset OF is stored in the register R5 of the data to be accessed. The offset value is set.

  A register number indicating the register R from which data is read is set in the register number RPT, and a register number indicating the register R in which the data is written is set in the register number WPT. The empty EMP indicates a state in which valid data is not stored in either of the registers R4 and R5 (both registers R4 and R5 are empty). For example, in a state where valid data is not stored in either of the registers R4 and R5, the empty EMP is set to “1”. Full FUL indicates a state in which valid data is stored in both the registers R4 and R5. For example, in a state where valid data is stored in both the registers R4 and R5, the full FUL is set to “1”. The control registers 44 and 45 are the same as the control register 43 except for the corresponding register group (R6 and R7, R8 and R9).

  The control unit 54 receives the register number RN1 and the instruction type TP from a decoder (not shown), reads the control information RINF 10, 11, 20, 21, 30, 31 from the control registers 43, 44, 45, The offsets OF of 44 and 45 are updated. Here, for example, each control information RINF11, 21, 31 is information including the register numbers RPT, WPT, empty EMP, and full FUL of each control register 43, 44, 45.

  For example, the control unit 54 outputs the control information RINF10, 20, and 30 read from the control registers 43, 44, and 45 to the execution unit 21, and outputs the register number RN2 to the execution unit 21 instead of the register number RN1. . In this embodiment, the registers RS2 and RT2 with the register number RN2 indicate the source register R, and the register RD2 with the register number RN2 indicates the destination register R. In FIG. 7, the description of a control signal (for example, an initial value INT2 shown in FIG. 8 described later) for setting the initial values of the control registers 43, 44, and 45 is omitted.

  FIG. 8 shows an example of the control unit 54 shown in FIG. The control unit 54 (portion surrounded by a broken line in the figure) includes a selector 52 (52A, 52B, 52C, 52D, 52E), an update unit 55, and a conversion unit 56. FIG. 8 shows the selector 52 and the update unit for the control register 43, and the description of the selector 52 and the update unit 55 for the control registers 44 and 45 is omitted. For example, the selector 52 and the update unit 55 for the control registers 44 and 45 are the same as those in FIG. 8 except for the control registers 44 and 45 to be controlled. Further, in FIG. 8, the description of the control registers 44 and 45 is omitted.

  For example, the control unit 54 receives the initial value INT2, and sets each value (such as enable EN) in the control register 43 to the initial value INT2. In this case, the selector 52 selects the value of the initial value INT2 as a value to be set in the control register 43. Here, for example, the control registers 43, 44, and 45 are allocated on the address map. As a result, the values (such as initial values) of the control registers 43, 44, and 45 can be set by a load instruction or a store instruction. In the example shown in the figure, the control registers 43, 44, and 45 are configured by flip-flops.

  For example, the update unit 55 receives the register number RN1 and the instruction type TP, reads the control information RINF10 and 11 from the control register 43, and updates the offset OF, register number RPT, WPT, empty EMP, and full FUL. Details of the operation of the updating unit 55 will be described with reference to FIGS. When the value of the control register 43 is updated, the selector 52 selects the value received from the update unit 55 as a value to be set in the control register 43.

  For example, the conversion unit 56 receives the register number RN1 and the instruction type TP, reads the register numbers RPT, WPT, and enable EN from the control registers 43, 44, and 45 corresponding to the register R indicated by the register number RN1, and sets the register number RN2. Set. When the register R specified by the register number RN1 is a register R that does not correspond to the control registers 43, 44, and 45, the conversion unit 56 sets the register numbers RPT, WPT, and enable EN to the control registers 43, 44, It is not necessary to read from 45. Then, the converting unit 56 outputs the register number RN2 instead of the register number RN1 to the execution unit 21 shown in FIG. Details of the operation of the conversion unit 56 will be described later with reference to FIG.

  9 and 10 show an example of the operation of the update unit 55 shown in FIG. 9 and 10 show the operation of the update unit 55 for updating the offset OF, the register numbers RPT, WPT, empty EMP, and full FUL of the control register 43. That is, in FIGS. 9 and 10, the operation of the update unit 55 for the control register 43 will be described. The operation of the update unit 55 for the control register 44 is explained by replacing the registers R4 and R5 with the registers R6 and R7, and the operation of the update unit 55 for the control register 45 is changed to the registers R8 and R9. It is explained by replacing it. Further, the selector 52 shown in FIG. 8 described above selects the value received from the updating unit 55 as the value to be set in the control register 43. Note that the sign% in FIG. 10 indicates a remainder operator.

  First, as shown in FIG. 9, in the process 70, the update unit 55 determines whether or not an access to any of the registers R4 and R5 occurs based on the register number RN1. When one of the registers R4 and R5 is accessed (Yes in process 70), the operation of the update unit 55 proceeds to process 72. When neither of the registers R4 and R5 is accessed (No in process 70), the update unit 55 terminates the process without updating the control register 43.

  In process 72, the update unit 55 determines whether or not the enable EN is set to “1”. That is, it is determined whether or not the control register 43 is valid. When the enable EN is “1” (Yes in process 72), the operation of the update unit 55 proceeds to process 74. When the enable EN is not “1” (No in process 72), the update unit 55 The process is terminated without updating. For example, when the registers R4 and R5 are handled in the same manner as the registers R0 to R3 shown in FIG. 7 described above, the updating unit 55 ends the process without updating the control register 43. That is, when the register R4 and the register R5 are not used as a register group including the registers R4 and R5, the update unit 55 ends the process without updating the control register 43.

  In process 74, the update unit 55 determines whether the instruction is a load instruction based on the instruction type TP. In the case of a load instruction (Yes in process 74), the operation of the update unit 55 proceeds to process 76. In the case of no load instruction (No in process 74), the operation of the update unit 55 proceeds to process 84.

  In process 76, the updating unit 55 updates the register number WPT. For example, when the register number WPT before update indicates the register R4, the update unit 55 updates the register number WPT to the register number indicating the register R5. For example, when the register number WPT before update indicates the register R5, the update unit 55 updates the register number WPT to the register number indicating the register R4. For example, if the register number WPT after the update has a constant number of 4 (a value indicating the register R4), the result obtained by adding 1 to the value obtained by subtracting the constant number from the register number WPT before the update is used as the dividend. It is calculated by adding the remainder when dividing by 2 to the constant number. When the constant number is 5 (value indicating the register R5), the updated register number WPT is obtained by adding 1 to the value obtained by subtracting the register number WPT before update from the constant number, and the dividend is It is calculated by subtracting the remainder when dividing by 2 from the constant number.

  In process 78, the updating unit 55 determines whether or not the register number WPT updated in process 76 is the same as the register number RPT. When the register numbers WPT and RPT are the same (Yes in process 78), the update unit 55 indicates that the full FUL is “1” in process 80 (valid data is stored in both the registers R4 and R5). Information). On the other hand, when the register numbers WPT and RPT are different from each other (No in process 78), the operation of the update unit 55 proceeds to process 82. In process 82, the updating unit 55 sets the empty EMP to “0” (information indicating that valid data is stored in at least one of the registers R4 and R5).

  In process 84 (when it is determined in process 74 that the instruction is not a load instruction), the update unit 55 determines whether the instruction is a store instruction based on the instruction type TP. In the case of a store instruction (Yes in process 84), the operation of the update unit 55 proceeds to process 86. In the case of no store instruction (No in process 84), the operation of the update unit 55 proceeds to process A shown in FIG.

  In process 86, the updating unit 55 updates the register number RPT. For example, when the register number RPT before update indicates the register R4, the update unit 55 updates the register number RPT to the register number indicating the register R5. For example, when the register number RPT before update indicates the register R5, the update unit 55 updates the register number RPT to the register number indicating the register R4. For example, the updated register number RPT is calculated by the same calculation as the updating of the register number WPT in the process 76.

  In process 88, the update unit 55 determines whether or not the register number WPT is the same as the register number RPT updated in process 86. When the register numbers WPT and RPT are the same (Yes in process 88), the update unit 55 sets the empty EMP to “1” in process 90 (no valid data is stored in any of the registers R4 and R5). Information). On the other hand, when the register numbers WPT and RPT are different from each other (No in process 88), the operation of the update unit 55 proceeds to process 92. In process 92, the update unit 55 sets the full FUL to “0” (information indicating that at least one of the registers R4 and R5 is empty).

  As shown in FIG. 10, in the process 94 (when it is determined in the process 84 of FIG. 9 that the instruction is not a store instruction), the update unit 55 registers a group of registers R4 and R5 based on the register number RN1. Determine whether the access to the destination is a destination. For example, when the register RD1 with the register number RN1 is the register R4, the access to the register group including the registers R4 and R5 is the destination. When the access to the register group is the destination (Yes in process 94), the operation of the update unit 55 proceeds to process 96. When the access to the register group is the source (No in process 94), the operation of the update unit 55 is performed. Moves to processing 108.

  In process 96, the update unit 55 determines whether or not the addition result of the offset OF and the bit length LN is equal to or greater than the bit width of the register R (32 in this embodiment). When the addition result is 32 or more (Yes in process 96), the operation of the update unit 55 proceeds to process 98. The processes 98, 100, 102, and 104 are the same as the processes 76, 78, 80, and 82. By the processes 96 and 98, the output data generation unit 29 shown in FIG. 7 described above can store data across the registers R4 and R5. On the other hand, when the addition result is 31 or less (No in process 96), the operation of the update unit 55 proceeds to process 104.

  In processing 106, the update unit 55 updates the offset OF. For example, the updated offset OF is calculated by the remainder when the result obtained by adding the bit length LN to the offset OF before update is the dividend and the dividend is divided by the bit width of the register R (32 in this embodiment). The

  In process 108 (when it is determined in process 94 that the access to the register group is the source), the update unit 55 updates the offset OF. For example, the updated offset OF is calculated by the same calculation as the update of the offset OF in the process 106.

  In processing 109, the updating unit 55 determines whether or not the offset OF updated in processing 108 is zero. If the offset OF is 0 (Yes in process 109), the operation of the update unit 55 proceeds to process 112. If the offset OF is not 0 (No in process 109), the operation of the update unit 55 proceeds to process 110.

  In processing 110, the updating unit 55 determines whether or not the addition result of the offset OF and the bit length LN is larger than the bit width of the register R (32 in this embodiment). When the addition result is larger than 32 (Yes in process 110), the update unit 55 updates the register number RPT in process 112. When the addition result is 32 or less (No in process 110), the update unit 55 The number RPT is not updated. The processes 112, 114, 116, and 118 are the same as the processes 86, 88, 90, and 92. Through the processes 108, 109, 110, and 112, the input data extraction unit 23 illustrated in FIG. 7 can read the data stored across the registers R4 and R5.

  FIG. 11 shows an example of the operation of the conversion unit 56 shown in FIG. FIG. 11 shows the operation of the conversion unit 56 when setting one of the register numbers RN2 (one of the registers RD2, RS2, and RT2). When there are a plurality of registers R specified by the register number RN1 (that is, when there are a plurality of registers R set in the register number RN2), the processing of FIG. 11 is performed for each register R that is accessed. .

  First, in the process 120, the conversion unit 56 determines whether or not an access to any of the registers R4-R9 occurs based on the register number RN1. When any of the registers R4-R9 is accessed (Yes in process 120), the operation of the conversion unit 56 proceeds to process 122, and when the register R4-R9 is not accessed (No in process 120), the conversion unit 56 In process 138, the registers (RD2, RS2, RT2) having the register number RN2 are set to the registers (RD1, RS1, RT1) having the register number RN1.

  For example, when the registers RD1, RS1, and RT1 with the register number RN1 are the registers R3, R4, and R6, the conversion unit 56 sets the register RD2 with the register number RN2 to the register R3 and the register RS2 with the register number RN2 in processing 138. , Process 122 is performed to set RT2.

  In process 122, the conversion unit 56 determines whether or not the enable EN of the control registers 43, 44, and 45 corresponding to the register R specified by the register number RN1 is set to “1”. That is, it is determined whether or not the control registers 43, 44, and 45 corresponding to the register R designated by the register number RN1 are valid. Through the process 122, the register R designated by the register number RN1 is used as a register group composed of two registers R, or as a single register R in the same manner as the registers R0 to R3 shown in FIG. It is determined whether to use it.

  When the enable EN is “1” (Yes in processing 122), the operation of the conversion unit 56 proceeds to processing 124. When the enable EN is not “1” (No in processing 122), the conversion unit 56 performs processing in step 138. The registers (RD2, RS2, RT2) with register number RN2 are set to the registers (RD1, RS1, RT1) with register number RN1. For example, the registers RD1, RS1, and RT1 of the register number RN1 are the registers R8, R4, and R6, and the enable EN of the control registers 43, 44, and 45 are set to “1”, “1”, and “0”, respectively. If so, the conversion unit 56 performs the process 124 to set the registers RS2 and RT2 of the register number RN2. Further, in the process 138, the conversion unit 56 sets the register RD2 of the register number RN2 to the register RD1 (register R8) of the register number RN1.

  In process 124, the conversion unit 56 determines whether the instruction is a load instruction based on the instruction type TP. In the case of a load instruction (Yes in process 124), the conversion unit 56 sets the register RT2 of the register number RN2 to the register R indicated by the register number WPT in the process 126. On the other hand, if the instruction is not a load instruction (No in process 124), the operation of the conversion unit 56 proceeds to process 128.

  In process 128, the conversion unit 56 determines whether the instruction is a store instruction based on the instruction type TP. In the case of a store instruction (Yes in process 128), the conversion unit 56 sets the register RT2 of the register number RN2 to the register R indicated by the register number RPT in process 130. On the other hand, if it is not a store instruction (No in process 128), the operation of the conversion unit 56 proceeds to process 132.

  In process 132, the conversion unit 56 determines whether or not the access to the register group including the register R specified by the register number RN1 is a destination based on the register number RN1. When the access to the register group is the destination (Yes in process 132), the conversion unit 56 sets the register RD2 of the register number RN2 to the register R indicated by the register number WPT in process 134. On the other hand, when the access to the register group is the source (No in process 132), the conversion unit 56 sets the register with the register number RN2 (for example, registers RS2 and RT2) to the register R indicated by the register number RPT in process 136. To do.

  For example, in the process 136, when the register RS1 with the register number RN1 is one of the registers R4 and R5, the conversion unit 56 converts the register RS2 with the register number RN2 into the register R (R4 or R5) indicated by the register number RPT in the control register 43. ). Further, for example, when the register RT1 with the register number RN1 is one of the registers R4 and R5, the conversion unit 56 registers the register RT2 with the register number RN2 in the process 136 by the register R (R4) indicated by the register number RPT of the control register 43. Or set to R5).

  FIG. 12 shows an overview of the input data extraction unit 23 shown in FIG. The shaded portion in the figure indicates a portion that is different from the input data extraction unit 22 shown in FIG. 5 described above. Also, the sign% in FIG. 12 indicates a remainder operator. The input data extraction unit 23 includes an FF 224, a left logical shift unit 226, a right arithmetic shift unit 221, and a selector 222.

  For example, the FF 224 stores the data RDATA read from the register R when the write enable WE is “1”. For example, the write enable WE may be generated based on the bit length LN and the offset OF of the control register (control register 43 or the like) corresponding to the read register R, and may be generated by the input data extraction unit 23. It may be generated by the control unit 54 shown in FIG. In this embodiment, the write enable WE is “1” when the addition result of the value obtained by doubling the bit length LN and the offset OF is larger than the bit width of the register R (32 in this embodiment). If the result is 32 or less, it is “0”.

  In other words, the FF 224 stores data RDATA including a part of the data stored across the two registers R before the instruction using the data stored across the two registers R is executed. Is done. The FF 224 may store the data RDATA every time the data RDATA is read from the register R without using the write enable WE.

  The left logical shift unit 226 receives data having a bit width (64 in this embodiment) that is twice the bit width of the register R, and logically shifts the received data to the left by the shift amount LSL. The 64-bit width data received by the left logical shift unit 226 is the data RDATA read from the register R on the upper 32 bits and the data read from the FF 224 on the lower 32 bits. The shift amount LSL is a value obtained by subtracting the added value of the bit length LN and the offset OF of the control register (for example, the control register 43) corresponding to the read register R from 64 (twice the bit width of the register R). This is the remainder when the dividend is divided by 32 (bit width of register R). Thereby, for example, the data to be calculated is shifted to the leftmost side of the 64-bit width data.

  The right arithmetic shift unit 221 receives the upper 32 bits of the output data (64-bit width data) of the left logical shift unit 226 and right-arithmizes the received data (32-bit width data) by the shift amount ASR. shift. The shift amount ASR is a value obtained by subtracting the bit length LN of the control register (for example, the control register 43) corresponding to the read register R from 32 (bit width of the register R). The right arithmetic shift unit 221 shifts, for example, data to be calculated to the rightmost side of 32-bit width data.

  Based on the selection signal SEL, the selector 222 outputs one of the data S1 and S2 as data IDATA to the instruction execution unit 24 shown in FIG. For example, when the data RDATA is read from any of the registers R4 to R9, the selector 222 receives the data when the enable EN of the control registers 43, 44, and 45 corresponding to the register R from which the data RDATA is read is “1”. S2 is output to the instruction execution unit 24 as data IDATA. Under other conditions, the selector 222 outputs the data S1 (data RDATA read from the register R) to the instruction execution unit 24 as data IDATA.

  For example, when the data RDATA is read from the registers R other than the registers R4-R8, the selector 222 outputs the data RDATA (data S1) read from the register R to the instruction execution unit 24 as data IDATA. That is, in this embodiment, the selection signal SEL is generated by, for example, the register number RN2 indicating the register R from which the data RDATA is read and the enable EN of the control registers 43, 44, and 45.

  FIG. 13 shows an overview of the output data generation unit 29 shown in FIG. A shaded portion in the figure indicates a portion different from the output data generation unit 28 shown in FIG. 6 described above. Detailed descriptions of the left logical shift unit 280, the FF 282, the OR circuit 283, and the selector 284 described in FIG. 6 are omitted. The output data generation unit 29 includes a left logical shift unit 280, a right logical shift unit 285, a selector 286, an FF 282, an OR circuit 283, and a selector 284.

  The right logical shift unit 285 receives data having a bit width (64 in this embodiment) that is twice the bit width of the register R, and right-shifts the received data by the shift amount LSR. The 64-bit width data received by the right logical shift unit 285 is the output data (32-bit width data) of the left logical shift unit 280 on the upper 32 bits side, and the lower 32 bits are filled with “0”. Yes. Further, the shift amount LSR is obtained by subtracting the added value of the bit length LN and the offset OF of the control register (for example, the control register 43) corresponding to the register R storing the operation result from 64 (twice the bit width of the register R) Value. Thereby, for example, the operation result data is shifted to a position where the least significant bit of the operation result data matches the position of the offset OF in the 32-bit width data.

  The selector 286 outputs one of the data S3 and S4 to the FF 282 based on the selection signal SEL2. For example, when the addition result of the bit length LN and the offset OF of the control register (control register 43 or the like) corresponding to the register R storing the operation result is 32 (bit width of the register R) or more, the selector 286 selects the data S3 Is output to FF282. Under other conditions (when the addition result is smaller than 32), the selector 286 outputs the data S4 to the FF 282. Here, the data S3 is the upper 32 bits of the output data (64-bit width data) of the right logical shift unit 285, and the data S4 is the output data of the OR circuit 283 (32-bit width data). . As a result, when storing operation result data across both registers of the register R pair (for example, R4 and R5, R6 and R7, R8 and R9), a part of the operation result is stored in one of the register R pairs. , The remainder of the calculation result can be stored in the FF 282.

  The OR circuit 283 outputs the OR result of the lower-order 32-bit data IN2 of the output data (64-bit width data) of the right logical shift unit 285 and the data IN1 read from the FF 282 to the selector 284 and the selector 286.

  Based on the selection signal SEL, the selector 284 outputs one of the data S1 and S2 as data ODATA to the register R indicated by the register number RN2. In this embodiment, the selection signal SEL is generated by, for example, the register number RN2 indicating the register R in which the data ODATA is stored and the enable EN of the control registers 43, 44, and 45. The selection operation of the selector 284 is described by replacing the register R from which the data RDATA is read out with the register R in which the data ODATA is stored in the selection operation of the selector 222 shown in FIG.

  FIG. 14 shows an example of the relationship between the load instruction and the register state. FIG. 14 shows an example of the states of the registers R4 and R5 when the 9-bit data DS is continuously loaded from the memory MEM to the registers R4 and R5. FIG. 14A shows an example of a program for continuously loading the data at the address adr1 into the register R4, and FIG. 14B shows the register R4 when the program of FIG. 14A is executed. , R6 is shown. Note that the right side of the memory MEM and registers R4 and R5 in the figure are the lower bits. In this embodiment, the address adr1 is automatically incremented (for example, +4).

  In the first load instruction (FIG. 14 (a1)), the processor 11 stores the data DS (the lower 5 bits of the data DS0, DS1, DS2, and data DS3) stored in the address “0x0000” of the memory MEM in the register R4. (Fig. 14 (b2)). In the second load instruction (FIG. 14 (a2)), the load destination register is converted from the register R4 to the register R5 by the processing shown in FIG. 9-11, and the processor 11 is stored in the address “0x0004”. The loaded data DS is loaded into the register R5 (FIG. 14 (b3)).

  In the third load instruction (FIG. 14 (a3)), the load destination register is set in the register R4 by the processing shown in FIG. 9-11, and the processor 11 stores the data DS stored in the address “0x0008”. The data is loaded into the register R4 (FIG. 14 (b4)). In the fourth load instruction (FIG. 14 (a4)), the load destination register is converted from the register R4 to the register R5 by the processing shown in FIGS. 9-11, and the processor 11 is stored in the address “0x000C”. The loaded data DS is loaded into the register R5 (FIG. 14 (b5)). As described above, when data is continuously loaded from the memory MEM into the register group including the registers R4 and R5, the loaded data is alternately stored in the registers R4 and R5.

  FIG. 15 is a diagram illustrating an example of data stored in the registers R4-R9. FIG. 15A shows an example of a program for adding a plurality of continuous 9-bit data DS and a plurality of continuous 9-bit data DT. FIG. 15B shows an example of the state of the registers R4-R9 when the program loop of FIG. 15A is repeated twice. The shaded portion in FIG. 4B indicates an area where no valid data is stored. In the illustrated registers R4 to R9, the right side is the lower bits. Addresses adr1, adr2, and adr3 in FIG. 15A are addresses of a memory (for example, the memory MEM shown in FIG. 14 described above), and are automatically incremented (for example, +4).

  The instruction BREQ_full is executed when the full FUL of the control register (for example, the control registers 43 and 44) assigned to the address A (for example, the addresses A4 and A5) is “1” (for example, the label Label1). Is an instruction to branch to. The instruction BREQ_emp branches to a specified label (for example, label Label3) when the empty EMP of the control register (for example, control register 45) assigned to the address A (for example, address A8) is “1”. It is an instruction to do.

  That is, in the program shown in FIG. 15A, when the processor 11 does not store valid data in at least one of the registers R4 and R5, the processor R does not store valid data (one of R4 and R5). Then, the data DS stored at the address adr1 is loaded (FIGS. 15A2 and 15A3). Next, when valid data is not stored in at least one of the registers R6 and R7, the processor 11 stores the valid data in the register R (one of R6 and R7) at the address adr2. Data DT is loaded (FIG. 15 (a5), (a6)).

  Then, the processor 11 adds one of the plurality of data DS stored in the registers R4 and R5 and one of the plurality of data DT stored in the registers R6 and R7, and adds the data DD as a result of the addition. It is stored in either one of the registers R8 and R9 (FIG. 15 (a8)). Furthermore, the processor 11 performs the same addition processing twice as in FIG. 15A8 (FIGS. 15A9 and 15A10). When valid data is stored in at least one of the registers R8 and R9, the processor 11 stores the data DD stored in either the register R8 or R9 at the address adr3 (FIG. 15 (a11 ), (A12)). Note that the operation of the processor 11 returns to the top of the loop processing when valid data is not stored in either of the registers R8 and R9 (FIGS. 15 (a11), (a13), and (a14)).

  When the program loop of FIG. 15A is repeated twice, a plurality of 9-bit data DS (for example, data DS0 to DS6) are stored in the registers R4 and R5, and a plurality of 9-bit data DT (for example, data DT0 to DT6) is stored in the registers R6 and R7 (FIG. 15 (b1)), and a plurality of data DS (for example, data DS0 to DS6) and a plurality of data DT (for example, data DT0). -DT6) and a plurality of 10-bit data DD (for example, data DD0 to DD6) are stored in the registers R8 and R9 (FIG. 15 (b2)).

  As described above, in this embodiment, data stored across two registers R can be handled, and data can be stored across two registers R. Thereby, in this embodiment, the register R and the memory (for example, the memory MEM shown in FIG. 14) can be used more effectively. Further, in this embodiment, since the ALU 25 shown in FIG. 7 described above does not need to perform a shift operation or the like, it is possible to process continuous data operations at high speed.

  16 and 17 show an example of the operation of the input data extraction unit 23 shown in FIG. 16 and 17 show an example of one operation of the input data extraction unit 23 when the program shown in FIG. 15 is executed. The other operation of the input data extraction unit 23 will be described by replacing the data DS, register RS2, registers R4, R5 and control register 43 with data DT, register RT2, registers R6, R7 and control register 44, respectively.

  The shaded portion in the figure indicates a portion that is not valid data, and the symbol SE indicates code extension. In the example shown in the figure, the right side is the lower bit. Further, the portion surrounded by a broken line in the figure indicates the value of the control register 43 (the values of OF, RPT, WPT, EMP, and FUL) when the instruction is executed, the register R indicated by the register RS2 of the register number RN2, and the write The values of the enable WE and the shift amounts LSL and ASR are shown. The register numbers RPT, WPT, etc. in parentheses in the figure indicate the value of the control register 43 updated when the instruction is executed.

  Note that the initial values of the enable EN, bit length LN, offset OF, register number RPT, WPT, empty EMP, and full FUL of the control register 43 are “1” before the program shown in FIG. “9”, “0”, “value indicating the register R4 (hereinafter also simply referred to as R4)”, “R4”, “0”, “1” are set. The register number WPT and empty EMP are stored in the register R4 from “R4” and “1” by the operation shown in FIG. 9 when the data at the address adr1 is loaded into the register R4 (FIG. 15A3). The values indicating R5 (hereinafter also simply referred to as R5) "and" 0 "are updated.

  As shown in FIG. 16, first, in the first addition instruction (FIG. 15 (a8)), the input data extraction unit 23 reads RDATA stored in the register R4 (register R indicated by the register number RPT), Data DS0 is extracted (FIG. 16 (a)). For example, the left logical shift unit 226 receives 64-bit width data (data RDATA on the upper 32 bits side and data on FF 224 on the lower 32 bits side) (FIG. 16 (a1)), and receives the received data as a shift amount LSL (23 bits). ) Shift logically to the left. The right arithmetic shift unit 221 receives the upper 32 bits of the output data of the left logical shift unit 226 (FIG. 16 (a2)), and right-shifts the received data by the shift amount ASR (23 bits). . The offset OF is updated from “0” to “9” by the operations shown in FIGS. 9 and 10 described above.

  In the second addition instruction (FIG. 15 (a9)), the input data extraction unit 23 reads RDATA stored in the register R4 and extracts data DS1 based on the offset OF (OF = 9) (FIG. 15). 16 (b)). The operation of the input data extraction unit 23 is the same as that of the first addition instruction (FIG. 16A) except for the shift amount LSL (14 bits) of the left logical shift unit 226. The offset OF is updated from “9” to “18” by the operation shown in FIGS.

  In the third addition instruction (FIG. 15 (a10)), the input data extraction unit 23 reads RDATA stored in the register R4 and extracts data DS2 based on the offset OF (OF = 18) (FIG. 15). 16 (b)). The operation of the input data extraction unit 23 is the same as that of the first addition instruction (FIG. 16A) except for writing the data RDATA to the FF 224 and the shift amount LSL (5 bits) of the left logical shift unit 226. The same. For example, since the addition result of the value obtained by doubling the bit length LN and the offset OF is larger than 32 (WE = 1), the data RDATA including the data DS3a is stored in the FF 224. The data DS3a is data of lower 5 bits of the data DS3.

  Also, the offset OF, register number RPT, and empty EMP are updated from “18”, “R4”, and “0” to “27”, “R5”, and “1”, respectively, by the operations shown in FIGS. Is done. Since the empty EMP has been updated to “1”, in the second loop, the processor 11 loads the data DS stored in the address adr1 into the register R5 indicated by the register number WPT (FIG. 15 (a2)). (A3)). At this time, the register number WPT and empty EMP are updated from “R5” and “1” to “R4” and “0”, respectively, by the operation shown in FIG.

  As shown in FIG. 17, in the first addition instruction (FIG. 15 (a8)) in the second loop, the input data extraction unit 23 is stored in the register R5 (register R indicated by the register number RPT). RDATA is read and data DS3 is extracted (FIG. 17 (d)). For example, the left logical shift unit 226 receives 64-bit data (the upper 32 bits side is data RDATA and the lower 32 bits side is FF224 data (FIG. 17 (d1)), and receives the received data as a shift amount LSL (28 bits). ) Shift logically to the left. The lower 4 bits of the data RDATA are data DS3b, and the upper 5 bits of the data of the FF 224 are data DS3a. The data DS3b is the upper 4 bits of data DS3.

  That is, the 64-bit width data received by the left logical shift unit 226 includes the data DS3. The right arithmetic shift unit 221 receives the upper 32 bits of the output data of the left logical shift unit 226 (FIG. 17 (d2)), and right shifts the received data by the shift amount ASR (23 bits). . In this way, the input data extraction unit 23 can extract the data DS3 stored across the registers R4 and R5. In this case, for example, since the addition result of the value obtained by doubling the bit length LN and the offset OF is larger than 32 (WE = 1), the data RDATA read from the register R5 is stored in the FF 224. The offset OF is updated from “27” to “4” by the operations shown in FIGS. 9 and 10 described above.

  In the second addition instruction (FIG. 15 (a9)) in the second loop, the input data extraction unit 23 reads RDATA stored in the register R5, and performs data based on the offset OF (OF = 4). DS4 is extracted (FIG. 16 (e)). The operation of the input data extraction unit 23 is the first addition instruction in the second loop except that the data RDATA is not written to the FF 224 and the shift amount LSL (19 bits) of the left logical shift unit 226 is ( This is the same as FIG. The offset OF is updated from “4” to “13” by the operation shown in FIGS.

  In the third addition instruction (FIG. 15 (a10)) in the second loop, the input data extraction unit 23 reads RDATA stored in the register R5, and performs data based on the offset OF (OF = 13). DS5 is extracted (FIG. 17 (f)). The operation of the input data extraction unit 23 is the same as that of the second addition instruction in the second loop (FIG. 17E) except for the shift amount LSL (10 bits) of the left logical shift unit 226. . As described above, in this embodiment, continuous data having an arbitrary bit length can be sequentially read.

  18, 19, and 20 show an example of the operation of the output data generation unit 29 shown in FIG. 18-20 shows an example of the operation of the output data generation unit 29 when the program shown in FIG. 15 is executed. In the example of the figure, the right side is the low-order bit, and the code SE indicates code extension. Further, the portion surrounded by a broken line in the figure indicates the value of the control register 45 (the values of OF, RPT, WPT, EMP, and FUL) when the instruction is executed, the register R indicated by the register RD2 of the register number RN2, and the shift The values of the quantities LSL and LSR and the data S (S3, S4) selected by the selector 286 shown in FIG. 13 described above are shown. The register numbers RPT, WPT, etc. in parentheses in the figure indicate the values of the control register 45 updated when the instruction is executed.

  The initial values of the control register 45 enable EN, bit length LN, offset OF, register numbers RPT, WPT, empty EMP, and full FUL are “1” and “10”, respectively, before the program shown in FIG. 15 is executed. "0", "value indicating the register R8 (hereinafter also simply referred to as R8)", "R8", "0", "1". The FF 282 stores “0” as an initial value.

  As shown in FIG. 18, in the first addition instruction (FIG. 15 (a8)), the output data generation unit 29 receives data (for example, the operation result of ALU 25) EDATA from the instruction execution unit 24 shown in FIG. The valid data DD0 in the data EDATA is stored in the register R8 (register R indicated by the register number WPT) (FIG. 18A). For example, the left logical shift unit 280 receives the data EDATA (FIG. 18 (a1)), and shifts the data DD0 to the left by the shift amount LSL (22 bits). Then, the right logical shift unit 285 receives 64-bit width data (data in which the upper 32 bits are output from the left logical shift unit 280 and the lower 32 bits are padded with “0”) (FIG. 18 (a2)). The received data is logically shifted to the right by the shift amount LSR (54 bits) (FIG. 18 (a3)).

  The OR circuit 283 receives the lower 32-bit data IN2 of the output data (64-bit width data) of the right logical shift unit 285 and the data IN1 read from the FF 282 (FIG. 18 (a4)), and receives the data IN1 and IN2. The OR result is output to the selector 284 and the selector 286 (FIG. 18 (a5)).

  The selector 286 receives the upper 32 bits of data S3 of the output data of the right logical shift unit 285 and the output data S4 (S2) of the OR circuit 283, and stores the output data S4 (S2) of the OR circuit 283 in the FF 282 ( FIG. 18 (a6)). For example, since the addition result of the bit length LN and the offset OF is smaller than 32, the data S4 is output to the FF282. Further, the selector 284 outputs the data S2 including the data DD0 as data ODATA to the register R8 (FIG. 18 (a6)). The offset OF is updated from “0” to “10” by the operation shown in FIGS. 9 and 10 described above.

  In the second addition instruction (FIG. 15 (a9)), the output data generation unit 29 receives the data EDATA from the instruction execution unit 24, and registers the data DD1 in the data EDATA based on the offset OF (OF = 10) in the register R8. (FIG. 18B). The operation of the output data generation unit 29 is the same as that for the first addition instruction (FIG. 18A) except for the shift amount LSR (44 bits) of the right logical shift unit 285.

  Here, since the data IN1 read from the FF 282 is output data of the OR circuit 283 at the time of the first addition instruction, it is data including the data DD0 (FIG. 18 (b4)). Further, the lower 32 bits of data IN2 of the output data of the right logical shift unit 285 is data including data DD1 (FIG. 18 (b4)). Therefore, the output data S2 of the OR circuit 283 is data including the data DD0 and DD1 (FIG. 18 (b5)). That is, the register R8 stores data ODATA including data DD0 and DD1 (FIG. 18 (b6)). The offset OF is updated from “10” to “20” by the operation shown in FIGS.

  As shown in FIG. 19, in the third addition instruction (FIG. 15 (a10)), the output data generation unit 29 receives the data EDATA from the instruction execution unit 24 and offsets the data DD2 in the data EDATA by the offset OF (OF = 20), the data is stored in the register R8 (FIG. 19 (c)). The operation of the output data generation unit 29 is the same as that of the first addition instruction (FIG. 18A) except for the shift amount LSR (34 bits) of the right logical shift unit 285. Since the data IN1 read from the FF 282 is data including the data DD0 and DD1 (FIG. 19 (c4)), the output data S2 and the data ODATA of the OR circuit 283 are data including the data DD0, DD1, and DD2. (FIG. 19 (c5), (c6)). Further, the offset OF is updated from “20” to “30” by the operations shown in FIGS.

  In the first addition instruction (FIG. 15 (a8)) in the second loop, the output data generation unit 29 receives the data EDATA from the instruction execution unit 24, and offsets the data DD3a in the data EDATA by an offset OF (OF = 30). ) And the data DD3b in the data EDATA is stored in the FF 282 (FIG. 19D). The data DD3a is the lower 2 bits of the data DD3, and the data DD3b is the upper 8 bits of the data DD3.

  The operation of the output data generation unit 29 is the same as that of the first addition instruction (FIG. 18A) except for the operation of the selector 286 and the shift amount LSR (34 bits) of the right logical shift unit 285. . The data IN1 read from the FF 282 is data including data DD0, DD1, and DD2, and the lower 32 bits of data IN2 of the output data of the right logical shift unit 285 is data including data DD3a (FIG. 19 ( d4)). Therefore, the output data S2 and data ODATA of the OR circuit 283 are data including data DD0, DD1, DD2, DD3a (FIGS. 19 (d5) and (d6)).

  The selector 286 receives the upper 32 bits of data S3 of the output data of the right logical shift unit 285 and the output data S4 (S2) of the OR circuit 283, and stores the data S3 including the data DD3b in the FF 282 (FIG. 18). (D3), (d6)). For example, since the addition result of the bit length LN and the offset OF is 32 or more, the data S3 is output to the FF282. The offset OF, the register number WPT, and the empty EMP are “30”, “R8”, “1” to “8”, “values indicating the register R9 (hereinafter simply referred to as“ register R9 ”). R9) ”and“ 0 ”, respectively.

  As shown in FIG. 20, in the second addition instruction (FIG. 15 (a9)) in the second loop, the output data generation unit 29 receives the data EDATA from the instruction execution unit 24 and receives the data DD4 in the data EDATA. Is stored in the register R9 (register R indicated by the register number WPT) based on the offset OF (OF = 8) (FIG. 20 (e)). The operation of the output data generation unit 29 is the same as that of the first addition instruction (FIG. 18A) except for the register R9 for storing the data ODATA and the shift amount LSR (46 bits) of the right logical shift unit 285. The same. The offset OF is updated from “8” to “18” by the operation shown in FIGS.

  Here, the data IN1 read from the FF 282 is data including data DD3b (data DD3 excluding data DD3a stored in the register R8), and lower 32 bits of data IN2 output from the right logical shift unit 285 are: Data including data DD4 (FIG. 20 (e4)). Therefore, the output data S2 and the data ODATA of the OR circuit 283 are data including the data DD3b and DD4 (FIGS. 20 (e5) and (e6)). Thus, in this embodiment, data DD3 of data DD having a continuous arbitrary bit length (for example, 10 bits) can be stored across the two registers R8 and R9.

  In the third addition instruction in the second loop (FIG. 15 (a10)), the output data generation unit 29 receives the data EDATA from the instruction execution unit 24, and offsets the data DD5 in the data EDATA to the offset OF (OF = 18). ) To store in the register R9 (FIG. 20 (f)). The operation of the output data generation unit 29 is the same as that of the second addition instruction in the second loop (FIG. 20E) except for the shift amount LSR (36 bits) of the right logical shift unit 285. .

  The data IN1 read from the FF 282 is data including data DD3b and DD4, and the lower 32 bits of data IN2 output from the right logical shift unit 285 is data including data DD5 (FIG. 20 (f4)). ). For this reason, the output data S2 and the data ODATA of the OR circuit 283 are data including the data DD3b, DD4, and DD5 (FIG. 20 (f5) and (f6)). Further, the offset OF is updated from “18” to “28” by the operations shown in FIGS.

  In the second loop, because empty EMP is updated to “0” at the time of the first addition instruction, the processor 11 addresses the data DD0, DD1, DD2, DD3a in the register R8 indicated by the register number RPT. Store in adr3 (FIG. 15 (a11), (a12)). At this time, the register number RPT and empty EMP are respectively updated from “R8” and “0” to “R9” and “1” by the operation shown in FIG.

  As described above, also in this embodiment, the same effect as that of the embodiment described with reference to FIGS. 1 to 6 can be obtained. Furthermore, in this embodiment, data stored across two registers R can be handled, and data can be stored across two registers R. As a result, in this embodiment, the register R can be used more effectively. Further, in this embodiment, the register number RN2 is changed by the operation shown in FIGS. 9 to 11 described above, so that a register group composed of two registers (for example, R4 and R5, R6 and R7, R8). And R9) can be controlled like FIFO (First-In First-Out). Furthermore, in this embodiment, execution of conditional execution instructions (load instruction, store instruction, etc.) can be controlled by using empty EMP and full FUL.

  In the above-described embodiment, the example in which the present invention is applied to the 32-bit processors 10 and 11 has been described. The present invention is not limited to such an embodiment. For example, the present invention may be applied to a 64-bit processor. In this case, for example, the register file 30 includes general-purpose registers R (R0 to R9) having a 64-bit width. Further, the present invention may be applied to, for example, a processor (SIMD (Single Instruction Multiple Data) processor, superscalar processor, etc.) capable of processing a plurality of instructions and data simultaneously. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiment, the example in which the input data extraction units 22 and 23, the instruction execution unit 24, and the output data generation units 28 and 29 operate in a single cycle has been described. The present invention is not limited to such an embodiment. For example, the input data extraction units 22 and 23, the instruction execution unit 24, and the output data generation units 28 and 29 may divide the pipeline stage and operate in multiple cycles. That is, the input data extraction units 22 and 23, the instruction execution unit 24, and the output data generation units 28 and 29 may be configured to operate by pipeline processing. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the above-described embodiments illustrated in FIGS. 7 to 20, the example in which the registers R <b> 4 to R <b> 9 are used as a register group has been described. The present invention is not limited to such an embodiment. For example, when the registers R4-R9 are not used as a register group, they may be used like the registers R4, R6, R8 shown in FIG. In this case, for example, the use of the registers R4-R9 can be controlled by configuring the enable EN of the control registers 43, 44, 45 with 2 bits. For example, the registers R4 and R5 are respectively used as the register R4 shown in FIG. 4 and the register R0 shown in FIG. 1 when the enable EN is “01”, and when the enable EN is “10”. These are used like the register R0 shown in FIG. 1 and the register R4 shown in FIG. Further, for example, the registers R4 and R5 are used like the registers R4 and R5 shown in FIG. 12 when the enable EN is “11”, and when the enable EN is “00”, Used as shown in register R0. Also in this case, the same effect as the above-described embodiment can be obtained.

  In the embodiment described with reference to FIGS. 7 to 20 described above, the example in which the control registers 43, 44, and 45 have empty EMP and full FUL has been described. The present invention is not limited to such an embodiment. For example, the control registers 43, 44, and 45 may be configured by omitting empty EMP and full FUL. Also in this case, the same effect as that of the above-described embodiment can be obtained except for the control of the conditional execution instruction. Further, the control registers 43, 44, 45 may be configured by omitting the register numbers WPT, RPT, empty EMP, and full FUL. Also in this case, the same effects as those of the above-described embodiment can be obtained except for control like a FIFO and control of a conditional execution instruction.

  As mentioned above, although this invention was demonstrated in detail, said embodiment and its modification are only examples of this invention, and this invention is not limited to this. Obviously, modifications can be made without departing from the scope of the present invention.

  DESCRIPTION OF SYMBOLS 10, 11 ... Processor; 20, 21 ... Execution unit; 22, 23 ... Input data extraction part; 24 ... Instruction execution part; 25 ... ALU; 26 ... Load / store unit; 28, 29 ... Output data generation part; Register file; 40-45 Control register; 50, 54 Control unit

Japanese Patent Laid-Open No. 11-68579 Japanese Patent Laid-Open No. 6-19683

Claims (7)

An arithmetic unit that performs an operation on the input data;
A plurality of first registers for storing data;
A control register provided for each of the first registers, including offset information indicating a bit position to be accessed by the first register and length information indicating a bit length of data;
Based on the offset information and the length information of the control register corresponding to the first register from which the input bit string is read out from the first register in which the input bit string including a plurality of data is stored. Extracting an operation target data from the plurality of pieces of data of the read input bit string, extending the extracted operation target data to a bit width of the operation unit, and inputting the input data to the operation unit ;
A controller that updates the offset information based on the length information each time the calculation target data is extracted, with respect to the control register corresponding to the first register from which the calculation target data is extracted; A processor comprising: The processor of claim 1, wherein
Said offset information and based rather positions on the length information of the control registers corresponding to the first register having an output bit string that contains the data of the operation result of the arithmetic unit is stored, the calculation result of the arithmetic unit An output data generation unit for generating an output bit string in which data is located ;
The control unit stores the calculation result data of the calculation unit for the control register corresponding to the first register in which the output bit string including the calculation result data of the calculation unit is stored. And updating the offset information based on the length information . The processor of claim 2, wherein
A first buffer for storing the output bit string each time the output bit string is stored in the first register;
The output data generation unit arranges the output bit string to be stored in the first register and the first buffer by arranging the operation result data at the arrangement position of the data read from the first buffer. A processor characterized by generating. The processor according to any one of claims 1 to 3 ,
The processor according to claim 1, wherein the offset information and the length information of the control register are independent of each other in the plurality of control registers . An arithmetic unit that performs an operation on the input data;
A plurality of first registers for storing data;
Register information indicating the first register to be accessed in the first register group, and an access target of the first register, provided corresponding to each first register group configured by the two first registers. A control register including offset information indicating a bit position of
Based on the offset information of the control register corresponding to the first register group in which the input bit string is stored, reading the input bit string from the first register group in which the input bit string including the operation target data is stored, An input data extraction unit that extracts the calculation target data from the read input bit string and extends the extracted calculation target data to the bit width of the calculation unit;
An output bit string in which an arrangement position is calculated based on the offset information of the control register corresponding to the first register group in which the calculation result data of the calculation unit is stored, and the calculation result data is located at the arrangement position An output data generation unit for generating
A control unit that updates the offset information of the control register in response to access to the first register group;
A first buffer storing at least a part of the data of the operation result;
A second buffer in which the input bit string read by the input data extraction unit is stored;
When the data to be calculated is stored across the two first registers of the first register group, the input data extraction unit uses the second buffer to extract the data from the two first registers. Read the data to be calculated,
The output data generation unit stores the operation result data in one of the first registers using the first buffer when the operation result data is stored across the two first registers of the first register group. The partial data that is part of the operation result data is arranged in the output bit string, and the operation result data excluding the partial data is arranged in the output bit string stored in the other first register. A processor characterized by that. The processor of claim 5, wherein
The processor, wherein the control unit updates the register information and the offset information of the control register in response to access to the first register group . The processor of claim 6, wherein
The control register includes the register information, the offset information, empty information indicating that data to be transferred is not stored in any of the two first registers of the register group, and 2 of the register group. Full information indicating that data to be transferred is stored in both of the first registers,
The processor updates the register information, the offset information, the empty information, and the full information of the control register in response to access to the first register group .

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