JPH02204833A - Computer system - Google Patents

Abstract

PURPOSE:To attain the access of variable length data by allowing one address of a memory device to store the variable length data, and recognizing a processor and the data size of its variable length data. CONSTITUTION:The memory device 2 is provided with a storage space which can store the data of the size of variable length in one address, and in each address, data (i) stored in its address, and the data size (i) for holding the effective size of its data are stored. When a processor 1 reads-in the data stored in the memory device 2, first of all, the memory device 2 outputs the data stored in the designated address and an effective data size to a data bus 3 and a data size bus 4. In this state, the processor 1 reads in data length on the data size bus 4, and reads in the data from the data bus 3 in accordance with its data length. In such a manner, the access can be executed at high speed without being aware of the data length of the data to which the processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer system having a storage device capable of storing variable length data at one address.

[Conventional technology]

Conventionally, regarding storage devices, published by Gouha Shoten, written by Shuzo Yajima, Gouha Lecture, Information Science 14 Functions and Structure of Computers (19
1982), pages 193 to 211, the data size of one address in the memory address space is all the same (for example, 8 bits), and the data is divided into 8-bit (1-byte) units for each address. It is read and written in . Although it may be read and written in 16-bit or 32-bit units, the data size (number of bits) is fixed.

Therefore, when processing only 1 byte data.

Processing is possible by simply specifying the address. Furthermore, when reading and writing data of different sizes, such as 2-byte data, data at multiple addresses is read and written and processed as 2-byte data.

In this way, processing when all data is of the same size is extremely simple, and data on the storage device can be accessed at high speed.

[Problems to be Solved by the Invention] Although the above-mentioned conventional technology does not take into account such cases, even though the data length handled by the processor is often not constant, for example, the length of data handled by the processor is not fixed, There are some instruction words where the length of the operand is not constant. In this case, since the size of the operand can only be determined by reading the operation code (instruction code) and analyzing the operation code, there is a problem that it takes time to read the -instruction. Furthermore, the data size of the data to be processed may not be constant.

For example, if a mixture of 1-byte and 2-byte data is stored in a storage device, the program that processes these data will recognize the data size,
There is a problem in that it is necessary to process according to the data size, and such a processing program becomes complicated.

An object of the present invention is to provide a method and apparatus that can uniformly handle variable length data whose data length is not constant.

Another object of the present invention is to provide a method and apparatus for accessing data whose size is not constant regardless of the data size.

[Means to solve the problem]

In order to achieve the above object, variable length data can be stored in one address of a storage device. Also, the processor can recognize the data size of the variable length data.
As described above, variable length data can be accessed by a processor.

[Effect]

In order to store variable length data, a memory capable of storing the maximum size of variable length data and the data size is allocated to one address. Alternatively, variable length data can be stored by connecting any number of fixed length memories with link fields.

In order to recognize the data size, when writing data to a storage device, the data and data size are stored. When reading data, by outputting the data stored in the storage device and its data size from the storage device, the processor recognizes the data size and can access variable length data.

【Example〕

First, as an embodiment, an outline of a processor and a storage device to which the present invention is applied will be explained using FIG.

The processor 1 includes an ALU 102 which executes calculations and an instruction execution control unit 101 which controls the execution of a program. Storage device! 2 has a storage space that can store data of variable length at one address, and each address has a storage space that can store data of variable length size.
The data i stored at that address and the data size i that holds the effective size of the data are stored.

A case will be described in which processor l reads data stored in storage device Wt2. First, the storage device 2 outputs the data stored at the designated address and the effective data size to the data bus 3 and data size bus 4. The processor 1 reads the data length on the data size bus 4, and reads data from the data bus 3 according to the data length.In this way, the processor 1 reads the data size according to the size of the data stored at a certain address. Load.

When processor 1 writes data to storage device 2,
Processor 1 outputs the data to be stored and its data size to storage device 2 through data bus 3 and data size bus 4. The storage device 2 stores the data size and data. With such a comb, data of any size can be stored in one address.

Next, the operation of the processor and storage device in this embodiment will be explained in detail using FIGS. 2 to 5.

FIG. 2 is a diagram showing the detailed configuration of the processor 1 and the storage device W12.

Processor 1 has four registers 103. A register selector 111 for selecting a register. ALUIO2 that performs calculations
, a data output register 1 that outputs data to the storage device 2
06. A data input register 107 that inputs data from the storage device 2. Data input/output switchers 108 to 109 that switch between reading and writing data, and an address register 105 that specifies data input/output addresses. Consisting of an instruction execution control unit 101 that controls program execution,
These receive and transfer data via an internal data bus 120 and an internal data size bus 121.

The storage device 2 uses 24 bits for address selection, and allows access from 0 to 16M (mega) addresses by the address decoder 201. Also, register 10, data input register 12 . The data output register 11 and the storage unit 13 of the storage device 2 have a data field for storing data and a size field for storing the effective data size in bytes.

In this embodiment, the data that can be stored at one address is up to 4 bytes, and 3 bits are required to represent 0 to 4 bytes. Therefore, one address consists of a size field of 3 bits and a data field of 32 bits.

Figure 3 is a diagram showing the instruction format of one processor.
The instructions provided by this processor are classified into one type shown below depending on the addressing method.

(1) r format Specify the effective address of the operation using a register.

(2) x format As the effective address of an operation, the source address is specified by a register and an offset to the contents of that register, and the destination is specified by a register.

(3) Format a The source address is specified as an absolute address, and the destination is specified as a register.

Figure 3 (a) for (1) above, Figure 3 (b) for (2) above
FIG. 3(d) corresponds to (c) and (3), respectively.

Opcodes 310 to 313 are expressed using the upper 4 bits of the first byte of the instruction. The registers to be operated on or the registers used for addressing to specify the source and destination addresses of the operation are:
The lower 4 bits of the 1st byte are divided into two and each two bits are used.

Instruction format (2) uses operands 311 and 332 as offsets to the index register of the source address. Instruction format (3) uses operand 333 as an absolute source address. Further, if the instruction is a branch instruction, the source address is used as the branch destination address. In this way, the length of an instruction in this processor is 1 to 4 bytes.

First, regarding the operation when processor 1 reads and writes data on a storage device, 1o is executed by processor 1.
This will be explained using the ad command. The 1oad instruction is an instruction to read data on a storage device and store it in the register 10. The size of the data to be operated on is held in the size field 104 in the register and the size field 211 in the storage device, so there is no need to specify it in the instruction.

The assembler mnemonic for the r-format 1oad instruction is:

1oacf rag, addr rag,
reg specifies the register number that stores the data read from the storage device, and addr rag specifies the register number containing the address to read. The processor uses two bits for register selection, and a register selector 111 selects a register from four registers.

First, the contents of the register specified by addr rag are sent to address register 1 through internal data bus 120.
Next, the contents of the address register 105 are output to the storage device 2 via the address bus 5. Storage device! 2, the address decoder 201 converts the data and size data stored at the specified address,
It is output via the data bus 3 and data size bus 4.

In the processor 1, size data and data are sent to the data field 107 and its size field 117 of the data input register 12 by input/output data switchers 108-109, respectively. Finally, the data and size data read into the data input register 12 are transferred through the internal data bus 120 and the internal data size bus 121.
It is stored in the register 10 specified by ag.

Through the above processing, the data in the storage device is stored in the register.

Next, regarding the processing of operations using the size field,
This will be explained using the cap instruction.

The cap instruction is an instruction that compares the contents of two registers, and its assembler mnemonic is cp rag
1 rag 2, which is an instruction to compare the contents of register rag 1 and register reg 2 and set the condition code register 110 in the processor. Processor 1 sends regl and reg 2 data and size data to ALU 102. The ALU 102 first compares the size fields of rag 1 and rag 2.

Now if the size field values are different.

Assuming that data of different sizes have been compared, a size mismatch flag in the condition code register is set. If the sizes are equal, a comparison is made and the condition code register 110 is set according to the result.

Next, the add instruction will be explained.

The add instruction adds the values of two specified registers and stores the result in the register. In assembler mnemonic.

Add ragl rag2 and add the contents of regl and rag 2 to reg
This is an instruction to store in 1. The processor is reg
1 and rag2, data and data size in ALU10
Send to 2. In ALU102, first, rag 1 and ra
Compare the two size fields sent from g2.

If the data sizes are different, the data in the register with the shorter data size is sign-extended within the ALU to make the data sizes of the two data equal.

Next, addition is performed and the result is stored in reg 1 , but the result of addition may not be able to be stored with the data size of rag 1 at that time. Therefore, in addition to an instruction that sets an overflow flag in the condition code to indicate that the operation result did not fit in the register without changing the data size of the register that stores the result, the data size of the register that stores the result An instruction is provided to expand and store the .

In this way, according to this embodiment, the size of each data is held in the size field by the data itself, so there is no need to specify the size in the instruction. It becomes possible to perform calculations. This has the effect of reducing the number of types of processor instructions and shortening the instruction length.

In the cap and add instructions mentioned above, if the data sizes of the two registers to be operated on are different, a size mismatch flag is set and sign extension is performed.
It is also possible to transfer control to exception handling even if data with different data sizes are specified.

The processor has two execution modes: fixed mode and extended mode. In other words, control is transferred to exception handling only in cases where it is impossible to continue processing, such as an operation on a register with a data size of O. There is an extended mode that adjusts the data size, and a fixed mode that transfers control to exception processing as a data size mismatch even when the data size of the calculation target is different. These modes identify the current execution mode by an execution mode identification flag provided in the condition code register 110. This allows common use in cases where one instruction is treated as an error and a mismatch in data size is treated as an error, and when data sizes are different but are sign-extended to the same size and an operation is performed. Furthermore, it is also possible to dynamically switch execution modes during instruction execution.

Next, the join instruction provided by this processor will be explained. The Join instruction is an instruction that successively converts variable length data stored at consecutive addresses into variable length data at one address. The assembler mnemonic is join adr,n, from the address specified by (adr) to (adr+n
-1) Concatenate variable length data up to address and store as one variable length data at address adr.

The operation of the 0-order join instruction will be described below, in which the data other than the adr address does not change, and if the result of concatenation exceeds 4 bytes that can be stored in one address, no processing is performed. FIG. 5 is a diagram showing processing of a join instruction. (a) is an assembler mnemonic of an instruction to be executed, and STR is a label indicating an address. (b) is j
Before executing the oin instruction, (Q) shows the state of data on the storage device after executing the join instruction.

First, the data to be concatenated is stored (STR)
The data size at addresses ~(STR+n-1) is checked to see if it exceeds 4 bytes, which is the maximum size that can be stored at the first address. If it exceeds 4 bytes, processing is aborted. If the data after concatenation fits into 4 bytes, it is stored as shown in FIG. 5(b), and the data size after concatenation is stored in the size field of the STR address.

Next, a 5-plit instruction that divides variable-length data stored at a certain address into parts and expands them into a storage device will be explained. The assembler mnemonic for the 5plit instruction is.

For example, 5plit a dr,n is an instruction that divides the variable length data stored at the address specified by adr into n bytes and stores them sequentially starting from address adr.

The instruction to expand (Q) to (b) in Figure 5 is 5plit
STR becomes 1.

By providing such an instruction, data transfer can be performed using the maximum size that can be stored in one address (in this example, 4
When performing operations on data, the data storage format is changed according to the processing, such as dividing the data with the 5-plit instruction and performing it one byte at a time. It will be effective if it becomes possible.

Next, the operation of the present processor from reading an instruction to executing it will be explained. FIG. 4 shows the instruction execution control unit 101 in the processor in FIG.
This is the internal configuration of The instruction execution control unit includes a PC 420 that points to an address where a program instruction is stored, and an I R 40 where the currently executed instruction is read from the storage device and stored.
3. Offset register 4101 that indicates the offset to the branch destination when branching; selector 4 that selects the next instruction address;
One instruction cycle of the 60-bit processor consists of three phases: fetch, decode, and execute.

First, in the fetish cycle, the instruction at the address pointed to by the PC 420 is read into the lR 403. Since a storage device that can store variable length data at one address is used, one instruction is placed at the first address regardless of the instruction length. is stored. Therefore, in a fetch cycle, one instruction including not only an opcode but also an operand can be read into the IR 403 at a time. In other words, regardless of the instruction format shown in FIG. When the fetch is completed, the value of PC is immediately incremented by the plus 1 circuit 430 through the next instruction address register 440, and PC4 is set as the next instruction address.
20 and start fetching the next instruction. Then, in the execute cycle, the instruction is executed. However, if the instruction is a branch instruction, the branch destination address cannot be specified until the operand is read, so after reading the operand, the operand is offset. In the 1 selector 460, the value is stored in the register 410, and the adder 470 adds (the value of pc + 1) and the contents of the offset register 410 and sends it to the selector 460.
If the instruction being executed is a branch instruction, the contents of the branch destination address register are stored in the PC 420 and the next instruction fetch is started.

In this way, one instruction is stored at each location, so even if the instruction length is not constant, the instruction control unit can read the -instruction at once and interpret and execute the instruction word. Therefore, one instruction can be executed at high speed.

Furthermore, since instructions are stored sequentially starting from the first location, for instructions other than branch instructions, the next instruction can be fetched immediately after fetching the instruction.

61 One effect is that instruction fetching can be performed at high speed.

Next, as an example, a storage device will be described in which the size field of the storage device shown in FIG. 2 is used as a flag for checking whether data is unset. 6th
The figure shows the memory device 2 of FIG. 2 provided with a data size check circuit 610 and an unset data read signal line 601 that is output from the memory device to the outside.

In this storage device, as an initialization function, it is possible to set the data size of a certain address to O, and all data areas to be used are initialized to the data size O before program execution. During program execution, when the processor specifies an address to be read via the address bus 5, the storage device reads out the size field 211 and data field 210 of the corresponding address.

It is sent to the processor via data bus 3. The data in the size field is also sent to the processor through the data size bus 4, and at this time the size data is checked by the data size check circuit 610 to see if the value is O. If the value of the size data is 0, it means that the data has been read before writing the value to that address. Therefore, the data size check circuit 610 sends the unset data read signal through the unset data read signal line 601 to the processor. send to The processor detects this signal and performs one exception handling to prevent program malfunction.

As described above, according to this embodiment, it is possible to check whether a program refers to data at an address where no value is stored, which has the effect of preventing program malfunctions and facilitating debugging.

Next, as an example, a storage device that stores data of arbitrary length at one address by concatenating arbitrary pieces of data will be described.

FIG. 10 is a diagram showing the internal configuration of a storage device capable of storing data of arbitrary length. The storage device [2 is composed of a size block 1110 that stores the data size of data stored at each address, and a data block 1120 that stores the data stored at that address. Data block 1120 is divided into processing units called parts 1130 and addressed internally as part addresses.

Each part 1130 is composed of a data field 1131 for storing data and a use flag 1132 indicating whether the part is used.In this embodiment, the data field 1131 can store 2 bytes, Therefore, one part can store 2 bytes. The size block 1110 includes a size field 1111 that holds the data size of data stored at each address, and a link field 1112 that holds the part address within the data block where the data stored at the address is stored. In the 0-bit processor, data at one address is stored in consecutive part addresses within a data block.

As an example, the first example shows how data is stored in a storage device.
This will be explained using Figure 1.

In FIG. 11(a), character string data rMON is stored at address 38.
This is the state inside the storage device when YOJ is stored. FIG. 11(b) illustrates the data stored at addresses 37-39.

The size field 1201 at address 38 (exists in the size block) is 5 (bytes), which is the data size.
is stored, and the link field 1202 stores the first part address of the data block 1120 in which the data is stored. Therefore, 3 for the 3rd to 5th bars.
Data at address 8 is stored. rMONYOJ's "
0" is followed by meaningless data, but the data size is 5.
There is no problem because it is specified as bytes.

Next, the process of writing to the storage device will be explained. In Figure 11, 3-byte data r at address 38
When storing ABcJ, the processing performed on the storage device is as follows.
First, delete the data before it is stored. In other words, the use flags of the 3rd to 5th ports where the data at address 38 is stored are set to O.
and set the size field at address 38 to O. The state of the storage device at this time is shown in FIG. 12. Next, in FIG. Since the 2nd and 3rd parts are unused, the contents of the storage device are stored in the 2nd and 3rd parts by storing the data rABcJ in the 2nd and 3rd parts and storing the data size (3 bytes) in the size field. become that way.

As described above, this embodiment has the advantage that data of any data length can be stored within the range allowed by the memory capacity within the storage device.

Furthermore, since memory for storing data is not allocated to unused addresses, there is an effect that memory can be used effectively.

Next, a document processing system using a main memory device and a microprocessor to which the present invention is applied will be described.

This will be explained using FIG.

FIG. 7 is a block diagram of one document processing system.

This system includes a keyboard 701 for inputting documents, a processor 703 for processing the input documents, and a storage device that stores programs for document processing and the document being edited! 704 and a display 702 for displaying documents, half-width alphanumeric characters are represented using 1 byte, and full-width characters such as Kanji are represented using 2 bytes. In this system, where a mixture of half-width characters and full-width characters exist, the data stored at one address has a variable length, so the - character is stored at the first address regardless of whether it is full-width or half-width. That is, when a character string as shown in Figure 8 is input, starting from the address where one character string should be stored, "2" 1 byte, "Month" 2 bytes, "2" 1 byte, rIJ 1 byte, " 2 bytes are stored as shown in Figure 9. By storing documents in this manner, it becomes possible to efficiently search for character strings without being concerned about full-width and half-width characters. The case where the search string is "2" will be explained below as an example.

When searching for "2" from within a character string stored in a storage device as shown in Figure 9, the first address (a) of the character string is
A search can be performed by comparing the contents of the address and the search characters one by one starting from the first address. First, the first address (a) of the character string is stored in a register as a search address. This register is called the index register.The first step is to compare the contents pointed to by the index register with "2".

If they are equal, the search ends. If they are different, add 1 to the index register. In this state, the index register points to (b). In this way, the contents of the addresses and the search characters are successively compared until the index register exceeds the search end address (c).

In this way, in the document processing system using the present invention, the storage device identifies full-width sentences and half-width characters, and the processing device performs data calculations according to the data size, which simplifies the processing of two-document data. It has the effect of being

〔Effect of the invention〕

According to the present invention, it is possible to access data at high speed without being conscious of the data length of data to be processed.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an overview of the relationship between a storage device and a processor according to an embodiment of the present invention, FIG. 2 is a diagram showing details of the internal configuration of the storage device and processor shown in FIG. 1, and FIG. The figure shows the instruction format of the processor, Figure 4 shows the internal configuration of the instruction execution control section of the processor, and Figure 5 shows the JOI
FIG. 6 is a diagram showing the processing of the n instruction, FIG. 6 is a diagram showing a storage device equipped with a data size check mechanism and an unset data read signal line, which is an embodiment of the present invention, and FIG. 7 is an embodiment of the present invention. A diagram showing the configuration of a certain document processing system. FIG. 8 shows character strings input to the document processing system, FIG. 9 shows character strings stored in a storage device, and FIG. 10 shows character strings input to the document processing system. FIG. A storage device capable of storing data, Figure 11 is a diagram showing a method of storing arbitrary length data, and Figures 12 to 13 are diagrams showing the state inside the storage device when writing arbitrary length data. be. DESCRIPTION OF SYMBOLS 1... Processor, 2... Storage device, 3... Data bus, 4... Data size bus, 120... Internal data bus, 121... Internal data size bus, 10
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Claims (1)

[Scope of Claims] 1. In a computer system having a storage device having a storage address space, storage means capable of storing variable length data at one address in the storage device, and access for reading and writing the variable length data. A computer system characterized by providing means. 2. In a computer system having a storage device having a storage address space and a processing device that reads and processes the contents stored in the storage device, variable length data is stored in the processing device and at one address in the storage device. What is claimed is: 1. A computer system comprising: storage means capable of storing the variable-length data; and access means for reading and writing the variable-length data. 3. The computer according to claim 2, wherein the processing device is provided with an instruction execution control means for interpreting and executing variable length data stored in the storage device as one instruction word. system. 4. As the storage means, variable length data can be stored in one address by configuring one address in the storage device with a data field that holds data and a size field that holds the data length of the data. A computer system according to any one of claims 1, 2, and 3, characterized in that: 5. The storage means is characterized in that the variable length data can be stored by setting a maximum size of the variable length data and allocating the maximum size memory to all addresses of the storage device. A computer system according to any one of claims 1, 2, 3, and 4. 6. As the storage means, a link field is provided in addition to the data field and the size field,
5. The computer system according to claim 4, wherein variable length data can be stored by connecting arbitrary pieces of data using the link field. 7. The computer system according to claim 6, characterized in that the processing device is provided with an arithmetic device that reads the contents stored in the storage device as data and performs calculations according to size data. . 8. The computer system according to claim 6, wherein the access means is capable of setting or changing the data length of the variable length data by writing the data length of the variable length data in the size field. 9. The computer system according to claim 8, wherein a dedicated instruction for setting the data size is provided as a command word interpreted and executed by the processing device. 10. As the access means, a function is provided to initialize the size field at one address in the storage device to a value indicating that the variable length data is not stored, so that the variable length data is not written. 10. The computer system according to claim 9, further comprising an unset data read detection circuit capable of detecting readout. 11. As the access means, when writing the variable length data to one address in the storage device, if data is already stored at that address, a size that detects that variable length data of a different size is written. 10. The computer system according to claim 9, further comprising a mismatch detection circuit. 12. Claims characterized in that the instruction word interpreted and executed by the processing device is provided with an instruction specifying an address of the storage device where the unset data reading detection circuit and the size mismatch detection circuit operate. The computer system according to item 11. 13. In the storage device, a recognition means is provided to recognize the data length of the variable length data stored at one address, and the processing device interprets and executes the data length as the data at the address. 8. The computer system according to claim 7, further comprising a read instruction. 14. In the storage device, a compression means is provided for concatenating the variable length data of the consecutive addresses and storing it in one address, and a command word that is interpreted and executed by the processing device is a compression means dedicated to executing the compression means. 8. The computer system according to claim 7, further comprising an instruction. 15. In the storage device, a restoring means is provided for dividing and storing the variable length data at the address into consecutive addresses;
8. The computer system according to claim 7, wherein a dedicated instruction for executing the restoring means is provided as the instruction word interpreted and executed by the processing device.