JP5369449B2 - Active matrix liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix type liquid crystal display that reduces power consumption without degrading display quality. <P>SOLUTION: The device includes: a control unit 17 that controls a frame frequency so as to make it correspond to a voltage applied to a liquid crystal; a light adjusting means 13 for controlling luminance of light emitted by a back light 12 on the basis of image data. The control unit 17 controls the frame frequency on the basis of the evaluation result of the image data evaluated by the light adjusting means 13. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

  The present invention relates to an active matrix liquid crystal display device.

  In recent years, active matrix liquid crystal display devices using thin film transistors (TFTs) as switching elements have been developed.

  The active matrix liquid crystal display device supplies a plurality of pixels arranged in a matrix, a plurality of gate lines for sequentially scanning each pixel row by row, and data to be written to each pixel. A plurality of data lines are formed. Each pixel has a pixel TFT connected as a switching element having a gate electrode connected to the gate line and a drain electrode connected to the data line, a pixel electrode connected to the source electrode of the pixel TFT, and a common potential in each pixel. And a storage capacitor for accumulating charges for keeping the potential difference between the pixel electrode and the common electrode at a predetermined potential difference. Here, between the pixel electrode and the common electrode, for example, a liquid crystal whose alignment state changes according to a potential difference between the pixel electrode and the common electrode is disposed.

  In such an active matrix liquid crystal display device, for each frame, for example, gate lines are scanned sequentially from the gate line at the top of the screen toward the gate line at the bottom of the screen. By supplying a display signal voltage corresponding to the gate line selected therein to each data line, a voltage corresponding to each pixel is applied to the liquid crystal of the pixel, and a desired image as one screen is displayed in the display area. Is displayed. For example, the frame frequency is controlled so that the display screen is updated at a frequency of 60 Hz.

  By the way, for example, in Patent Document 1, the luminance of the backlight and the correction of the image data are adjusted according to the brightness of the image to be displayed. Describes technology to reduce power

  Further, for example, Patent Document 2 discloses a white pixel counter that calculates the overall brightness of a display screen based on the number of pixels of a display screen that displays an image and a display screen that is displayed in white in the displayed image. And a display device that responds to the white pixel counter and can maintain and adjust the brightness displayed on the display screen by providing the dimming circuit 6 that maintains and adjusts the brightness displayed on the display screen. Has been.

JP 60-125891 A JP-A-7-129113

However, in the past, the display screen is constantly updated at a constant frame frequency, so there are cases where it is driven at a higher frequency than necessary, and in such a case, an unnecessarily large amount of power is consumed. There was Tsu Oh.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an active matrix liquid crystal display device capable of reducing power consumption without impairing display quality.

In order to solve the above problems, an aspect of an active matrix liquid crystal display device according to the present invention includes a storage unit that stores image data, and a display pixel that displays an image based on the image data stored in the storage unit. A normally white mode liquid crystal display panel, a backlight for irradiating the liquid crystal display panel with light, and a light control means for controlling the light emission luminance of the backlight based on the image data stored in the storage means; Frequency control means for controlling a frame frequency based on the image data stored in the storage means, and the dimming means for the display pixels of the liquid crystal display panel for the image data for one screen Based on the ratio of the image data that causes white display, the emission luminance of the backlight decreases as the ratio decreases So as to reduce the controlling the emission luminance of the backlight, wherein the frequency control means so as to reduce the frame frequency in accordance with the ratio increases, and controls the frame frequency, characterized in that .
In order to solve the above problems, an aspect of the active matrix liquid crystal display device of the present invention includes a storage unit that stores image data, and a display that displays an image based on the image data stored in the storage unit. A normally black mode liquid crystal display panel having pixels, a backlight for irradiating the liquid crystal display panel with light, and light control for controlling the light emission luminance of the backlight based on the image data stored in the storage means And a frequency control means for controlling a frame frequency based on the image data stored in the storage means, and the dimming means for the image data for one screen, the liquid crystal display panel Based on the ratio of the image data that causes the display pixels to display white, the emission of the backlight decreases as the ratio decreases. As to reduce the brightness, and controls the emission luminance of the backlight, wherein the frequency control means so as to reduce the frame frequency in accordance with the ratio becomes smaller, characterized in that, to control the frame frequency to.

  According to the present invention, power consumption can be reduced without impairing display quality.

  Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. As shown in FIGS. 1 and 2, the active matrix liquid crystal display device 1 of the present invention includes, for example, a storage unit 10 that stores image data input from the outside, and an image based on the image data stored in the storage unit 10. , A backlight 12 that irradiates the display panel 11 with light, a light control means 13 that controls the light emission luminance of the backlight 12 based on image data stored in the storage means 10, and a display A scanning driver 14 for scanning the gate line of the panel 11, a signal driver 15 for supplying a display signal voltage to the data line of the display panel 11, and a predetermined voltage for applying a predetermined voltage to the common electrode of the display panel 11 The common voltage generation circuit 16, the scanning driver 14, the signal driver 15, and the common voltage generation circuit so that a desired image is displayed on the display panel 11. 16 a control unit 17 for controlling driving, and a power adjustment circuit 18 and the like are supplied to each section to adjust the power supplied to the voltage necessary for driving.

  The storage unit 10 has a storage capacity capable of storing image data for at least a plurality of screens. When image data for a new screen is input from the outside, for example, the storage unit 10 stores the image data in the first storage area 101 of the storage unit 10. The stored image data is updated (rewritten) to the newly input image data for one screen. In addition to the first storage area 101, the storage means 10 stores a second storage area in which image data stored in the first storage area 101 is corrected by the control unit 17 as will be described in detail later. 102.

The display panel 11 has a configuration in which a liquid crystal LC is sandwiched between two substrates 112 and 113 which are arranged opposite to each other and bonded by a sealant 111. A plurality of gate lines (for example, n gate lines) extended in the row direction and a plurality of data lines (for example, m data lines) extended in the column direction on one substrate 112. The display pixel P (i, j) shown in FIG. 3 is provided in the vicinity of each intersection of the gate line G (j) and the data line S (i). Here, FIG. 3 is a diagram showing an equivalent circuit corresponding to one display pixel among the plurality of display pixels P (i, j) provided in the display panel 11.

The gate electrode of the thin film transistor TFT (i, j) is connected to the gate line G (j) shown in FIG. 3, and the source electrode of the thin film transistor TFT (i, j) is connected to the data line S (i). Further, the pixel electrode D (i, j) is connected to the drain electrode of the thin film transistor TFT (i, j). A common electrode 115 is disposed on the other substrate 113 so as to face the pixel electrode D (i, j), and a liquid crystal LC is filled between the pixel electrode D (i, j) and the common electrode 115. Yes. Further, a storage capacitor Ccs is connected in parallel with the liquid crystal capacitor Clcd configured as described above. In such a configuration, when a voltage is applied between the pixel electrode D (i, j) and the common electrode 115, the pixel electrode D (i, j) and the common electrode 115 are connected according to the voltage. The alignment state of the filled liquid crystal changes and the light transmittance in the liquid crystal layer changes. As a result, the light transmission state from the backlight 12 arranged on the back surface of the display panel 11 changes, and image display is performed. Here, i = 1, 2, 3,..., M. j = 1, 2, 3,..., n.

  In the present embodiment, each display pixel P (i, j) of the display panel 11 displays black when a voltage is applied to the liquid crystal, and normally displays white when no voltage is applied to the liquid crystal. The white mode is mainly described, but the present invention is not limited to this. Even in the normally black mode in which white is displayed when a voltage is applied to the liquid crystal and black is displayed when no voltage is applied to the liquid crystal. Good.

  The dimming unit 13 includes an evaluation unit 131 that evaluates the stored image data for one screen each time image data for one new screen is stored in the first storage area 101 of the storage unit 10. The light emission luminance of the backlight 12 is controlled so that the luminance corresponds to the evaluation result of the image data by the evaluation means 131.

  For example, the evaluation unit 131 derives the ratio Re of the image data that causes the display pixels of the display panel 11 to display white with respect to the image data for one screen stored in the first storage area 101. The means 13 controls the light emission luminance Bl of the backlight 12 so that the luminance is in accordance with the ratio Re derived by the evaluation means 131. At this time, as shown in FIG. 4A, the light control means 13 reduces the light emission luminance B1 when the ratio Re of the image data causing the display pixel to display white is small, and displays the display pixel in white. The light emission luminance Bl of the backlight 12 is controlled so that the light emission luminance Bl increases when the ratio Re of the image data to be generated is large. Here, in the above-described normally white mode, the image data that causes the display pixel to display white is image data that minimizes the voltage applied to the liquid crystal of the display pixel. A configuration may be adopted in which image data to which a voltage equal to or lower than the threshold voltage is applied to the liquid crystal is regarded as image data that causes the display pixels to display white, and the ratio thereof is derived. In the normally black mode, the image data that causes the display pixel to display white is image data that maximizes the voltage applied to the liquid crystal of the display pixel. In this case, a predetermined threshold voltage is used. The image data to be applied with the above voltage to the liquid crystal may be regarded as image data that causes the display pixels to display white, and the ratio may be derived.

  As another example, for example, the evaluation unit 131 derives an average value of gradation levels (brightness components) as image data for one screen stored in the first storage area 101. The light unit 13 controls the light emission luminance Bl of the backlight 12 so that the luminance corresponds to the average value Ae derived by the evaluation unit 131. At this time, as shown in FIG. 4B, the light control means 13 reduces the light emission luminance Bl when the average value Ae is small (in the case of dark image data) and when the average value Ae is large ( The light emission brightness B1 of the backlight 12 is controlled so that the light emission brightness B1 is increased (for bright image data). FIG. 4B shows a case where the gradation level is 0 to 255.

  That is, the light control means 13 evaluates the brightness of the image to be displayed on the display panel 11 using the predetermined evaluation value by the evaluation means 131 built in the light control means 13, and the brightness according to the evaluation result. The light emission luminance of the backlight 12 is controlled so that

  Here, the light emission luminance Bl of the backlight 12 can be controlled by changing the power supply voltage or the driving duty supplied to the backlight 12, for example.

  The scan driver 14 is for outputting a high level or low level voltage as a scan signal to each gate line G (j) provided in the display panel 11. 3 gate lines G (j) are connected, and on the basis of a gate start pulse signal GSP as a vertical control signal Vs output from the control unit 17, as shown in FIG. And the gate lines G (j) are individually selected based on the horizontal control signal Hs output from the control unit 17. Note that the horizontal control signal Hs includes, for example, a first gate clock signal GCK1 and a second gate clock signal GCK2, and the first gate clock signal GCK1 and the second gate clock signal GCK2 are rectangular signals having opposite phases to each other.

  Hereinafter, the scan driver 14 will be described in detail. As shown in FIG. 6, the schematic configuration of the main part of the scan driver 14 is configured by, for example, holding circuits 141, 142, 143, 144,... Corresponding to the number of gate lines (n stages) arranged in series. . Each holding circuit has an input terminal IN, an output terminal OUT, a reset terminal RST, a clock signal input terminal CK, a high potential power input terminal Th, and a low potential power input terminal Tl. . The gate start pulse signal GSP is supplied to the input terminal IN of the first stage holding circuit 141 as the first stage input signal. Further, the output signal of the previous holding circuit is supplied to the input terminal IN of the second and subsequent holding circuits. Further, the output signal of the holding circuit at the next stage is supplied to the reset terminal RST of each holding circuit. Note that a reset signal END may be separately supplied to the reset terminal RST of the holding circuit (not shown) in the final stage (for example, the n-th stage), or the output signal of the holding circuit 141 in the first stage may be supplied. It is good also as a structure supplied.

  Further, the first gate clock signal GCK1 is supplied to the clock signal input terminal CK of the odd-numbered holding circuit, and the clock signal input terminal CK of the even-numbered holding circuit is supplied to the first gate clock signal GCK1. The second gate clock signal GCK2 having the opposite phase is supplied. In addition, a predetermined high voltage Vgh is supplied to the high potential power input terminal Th of each holding circuit, and a predetermined low voltage Vgl is supplied to the low potential power input terminal Tl of each holding circuit.

  As shown in FIG. 7, each holding circuit 141, 142, 143, 144,... Has six MOS field effect transistors (hereinafter referred to as MOS transistors) T11 to T16, and a capacitor C. Have.

  As shown in FIG. 5, the scan driver 14 starts scanning in the frame in response to the gate start pulse signal GSP, and in response to the first gate clock signal GCK1 and the second gate clock signal GCK2. Voltage output such as switching from the low level voltage Vgl to the high level voltage Vgh only for a predetermined period is performed for each gate line from the first gate line G (1) to the last gate line G (n) in order.

  That is, the scan driver 12 sequentially turns on the TFTs (i, j) corresponding to the gate lines G (j) for each gate line G (j), and is supplied to the data line S (i) at this time. The display signal voltage being written is written to the corresponding pixel electrode D (i, j).

  In each gate line, by adjusting the clock interval Pw in the first gate clock signal GCK1 and the second gate clock signal GCK2, the on period Ton as the period maintained at the high level voltage Vgh can be varied. It is configured. As will be described in detail later, the output frequency of the gate start pulse signal GSP is also adjusted so as to correspond to the adjustment of the clock interval Pw.

  The signal driver 15 applies to each data line S (i) provided on the display panel 11 based on the horizontal synchronization signal HS, the vertical synchronization signal VS, the image data DATA, and the clock signal CLK input from the control unit 17. The display signal voltage corresponding to each data line S (i) is output at a predetermined timing.

  As shown in FIG. 8, the functional block configuration of the signal driver 15 includes a sampling memory 151, a hold memory 152, a level shifter 153, a DA conversion circuit (DAC) 154, and an output circuit 155.

  The sampling memory 151 is for capturing image data corresponding to a pixel for one gate line in synchronization with the clock signal CLK, and has the same number of data storage areas as the number of data lines S (i). Yes. That is, the sampling memory 151 captures image data corresponding to the gate line for each gate line, and stores the captured image data in the data storage area of the corresponding data line S (i).

  The image data for one horizontal period captured by the sampling memory 151 is transferred from the sampling memory 151 to the hold memory 152 in accordance with a request from the hold memory 152 at the subsequent stage. When the image data is transferred to the hold memory 152, the sampling memory 151 shifts to an image data capturing state corresponding to the gate line of the next row as image data for the next one horizontal period. This is performed in synchronization with the horizontal synchronization signal HS.

  The hold memory 152 sequentially acquires image data for one horizontal period from the sampling memory 151 based on the horizontal synchronization signal HS. Then, the hold memory 152 outputs the acquired image data to the subsequent level shifter 153.

  The level shifter 153 converts the level of the input signal by boosting or the like so as to be adapted to the DA conversion circuit 154 in the next stage. The DA conversion circuit 154 converts the digital image data level-converted by the level shifter 153 into a display signal voltage as an analog voltage, and outputs it to the output circuit 155 at the subsequent stage.

  The output circuit 155 supplies the display signal voltage output from the DA conversion circuit 154 to the data line S (i) of the display panel 11 and functions as a buffer circuit. For example, it is configured as a voltage follower circuit using a differential amplifier circuit.

  The control unit 17 corrects the image data stored in the first storage area 101 based on the ratio Re and the average value Ae as evaluation values derived by the evaluation unit 131 incorporated in the light control unit 13. In addition, it generates and outputs various control signals as described above for controlling the operations of the scanning driver 14 and the signal driver 15, and has a configuration including an image data correction unit 171 and a control signal generation unit 172. It has become.

  The image data correction unit 171 stores the image data for one new screen in the first storage area 101 of the storage unit 10, and when the evaluation unit 131 derives the ratio Re and the average value Ae as evaluation values, this evaluation is performed. The image data for one screen stored in the first storage area 101 is corrected according to the value, and the image data stored in the second storage area 102 of the storage means 10 is updated to the corrected image data (rewrite). ).

  For example, when the ratio Re is used as the evaluation value, as shown in FIGS. 9A and 9B, when the ratio Re of the image data for causing the display pixel to display white is small, the display pixel is displayed. The image data is corrected so that the amount of increase in the gradation level is larger than when the ratio Re of the image data that causes white display to be large, and the gradation level is lower at the lower gradation level than at the higher gradation level. The image data is corrected so that the raising amount is increased. Note that the inclination shown in FIG. 9B indicates the inclination of the conversion characteristics of the image data in FIG. 9A.

  When the average value Ae is used as the evaluation value, as shown in FIGS. 10A and 10B, the floor when the average value Ae is smaller than when the average value Ae is large. The image data is corrected so that the tone level raising amount is increased, and the image data is corrected so that the tone level raising amount is larger at the low tone level than at the high tone level. Note that the inclination shown in FIG. 10B indicates the inclination of the conversion characteristics of the image data in FIG.

  Then, the image data correction unit 171 stores the image data corrected as described above in the second storage area 102 of the storage unit 10. The image data stored in the second storage area 102 is read by the control unit 17 so as to correspond to a frame frequency set as described later, and is output to the signal driver 15, and is based on this image data. An image is displayed on the display panel.

  In other words, in the present embodiment, the backlight emission luminance is adjusted based on the image data stored in the first storage area 101, and the image data is corrected to correspond to the adjustment of the backlight emission luminance. Thus, the power consumption of the display device 1 is reduced without changing the visual brightness.

  The control signal generation unit 172 generates and outputs various control signals as described above based on the ratio Re and the average value Ae derived as evaluation values by the evaluation unit 131, and synchronizes with the various control signals. The image data stored in the second storage area 102 is output to the signal driver 15.

  Specifically, since each display pixel has a higher ability to hold the applied voltage as the applied voltage to the liquid crystal is smaller, as shown in FIG. 11, the control signal generating unit 172 has a ratio Re as an evaluation value. When the average value Ae is equal to or greater than the predetermined thresholds Th1 and Th2, that is, when the image to be displayed is equal to or greater than the predetermined brightness, the drive frequency of the scanning driver 14 and the signal driver 15 is decreased. Various control signals are generated. That is, various control signals are generated so that the frame frequency decreases.

  For example, when the ratio Re and the average value Ae as evaluation values are equal to or greater than predetermined threshold values Th1 and Th2, the clock intervals Pw in the first gate clock signal GCK1 and the second gate clock signal GCK2 are used as evaluation values. The ratio Re and the average value Ae are twice as long as when the threshold values Th1 and Th2 are less than the predetermined threshold values Th1 and Th2, and the output frequency of the gate start pulse GSP and the clock signal CLK (not shown) is halved correspondingly To do. At this time, in each gate line, the ON period Ton does not overlap between the gate lines, and the ON period of each gate line is doubled.

  That is, the control unit 17 scans when the image data stored in the first storage area 101 is image data for displaying a bright image and the voltage applied to the liquid crystal in the display pixel is a small voltage. The scanning driver 14 and the signal driver 15 are driven and controlled so that the driving frequency (frame frequency) of the driver 14 and the signal driver 15 is reduced to ½. As a result, the power consumption can be further reduced without degrading the display quality. It should be noted that the adjustment rate of the frame frequency is not limited to ½, and is preferably adjusted as appropriate according to various loads of the display panel 11.

  In the present embodiment, the evaluation value derived by the evaluation unit 131 is commonly used for adjustment of backlight emission luminance, image data correction, and frame frequency control. Compared with the case where the evaluation unit 131 is provided individually, the manufacturing cost can be greatly reduced, and the relationship between the adjustment amount of the backlight emission luminance, the correction amount of the image data, and the control amount of the frame frequency is obtained. It becomes possible to control the display state so that there is no sense of incongruity.

  Note that the control signal generation means 172 displays white when a voltage is applied to the liquid crystal, and displays black when no voltage is applied to the liquid crystal. When the average value Ae is less than the predetermined thresholds Th3 and Th4, the clock interval Pw in the first gate clock signal GCK1 and the second gate clock signal GCK2 is set to the ratio Re or the average value Ae as the evaluation value. The output length of the gate start pulse GSP and the clock signal CLK (not shown) is halved in correspondence with this length, which is twice as long as the threshold values Th3 and Th4. In this way, even in the normally black mode, the control unit 17 determines that the driving frequency of the scanning driver 14 and the signal driver 15 is low when the voltage applied to the liquid crystal in the display pixel is a small voltage. The scan driver 14 and the signal driver 15 can be driven and controlled so as to decrease, and further power consumption can be reduced without impairing display quality.

In the above-described embodiment, the case where the length of the on period Ton changes when the drive frequency of the scanning driver 14 or the signal driver 15 is switched has been described. However, as illustrated in FIG. The start timing of the on period Ton may be changed without changing the length. If the length of the ON period Ton when switching the driving frequency of the scan driver 14 and signal driver 15 changes, while preferably it is possible to minimize short-off period of each gate line, the length of the ON period Ton When the start timing of the on period Ton is changed without changing the display period, it is preferable that the display signal voltage writing time can be made constant regardless of the display contents. What is necessary is just to select suitably according to the electronic device to which the active matrix liquid crystal display device 1 is applied.

  In the above-described embodiment, the case where two types of frame frequencies are prepared has been described. However, the frame frequency may be changed in a plurality of stages. At this time, the frame frequency only needs to be configured to decrease as the voltage applied to the liquid crystal in the display pixel becomes smaller.

  In the above-described embodiment, the light control unit 13, the image data correction unit 171, and the control signal generation unit 172 control the backlight emission luminance based on the evaluation values derived by the evaluation unit 131, respectively. Although the case where image data correction or frame frequency control is performed has been described, the image data correction unit 171 and the control signal generation unit 172 are based on the adjustment amount of the light emission luminance controlled by the light control unit 13. It is good also as a structure which performs correction | amendment or control of a frame frequency.

  The above-described embodiment is merely an example of the present invention, and it goes without saying that the specific configuration of each functional block can be changed and designed as appropriate within the scope of the effects of the present invention.

Configuration diagram of active matrix liquid crystal display device according to the present invention Cross section of display panel Equivalent circuit diagram for display pixels It is explanatory drawing of the relationship between an evaluation value and the light emission brightness | luminance of a backlight, (a) is a ratio of the image data which makes a display pixel display white, (b) is an image for evaluation value for 1 screen. For the average value of data (gradation level) Timing chart showing relationship between gate start pulse, first gate clock signal, second gate clock signal, and scanning signal Illustration of scan driver Explanation of holding circuit Illustration of signal driver Explanatory drawing of the relationship between the evaluation value and the correction amount of the image data when the evaluation value is the ratio of the image data that causes the display pixel to display white. Explanatory drawing of the relationship between the evaluation value and the correction amount of the image data when the evaluation value is the average value of the image data (tone level) for one screen. Explanatory diagram of relationship between evaluation value and frame frequency Explanatory drawing of the relationship between the evaluation value and scanning signal in another embodiment

Explanation of symbols

1: active matrix liquid crystal display device 10: storage means 11: display panel 12: backlight 13: dimming means 14: scanning driver 15: signal driver 16: common voltage generation circuit 17: control unit 131: evaluation means 171: image Data correction means 172: Control signal generation means

Claims (3)

Storage means for storing image data;
A normally white mode liquid crystal display panel having display pixels on which an image based on the image data stored in the storage means is displayed;
A backlight for irradiating the liquid crystal display panel with light;
Dimming means for controlling the luminance of the backlight based on the image data stored in the storage means;
Frequency control means for controlling a frame frequency based on the image data stored in the storage means;
With
The dimming means is configured to emit light from the backlight as the ratio decreases based on a ratio of the image data that causes the display pixels of the liquid crystal display panel to display white with respect to the image data for one screen. Controlling the emission luminance of the backlight so as to reduce the luminance;
The frequency control means controls the frame frequency so as to decrease the frame frequency as the ratio increases.
An active matrix type liquid crystal display device. Storage means for storing image data;
A normally black mode liquid crystal display panel having display pixels on which an image based on the image data stored in the storage means is displayed;
A backlight for irradiating the liquid crystal display panel with light;
Dimming means for controlling the luminance of the backlight based on the image data stored in the storage means;
Frequency control means for controlling a frame frequency based on the image data stored in the storage means;
With
The dimming means is configured to emit light from the backlight as the ratio decreases based on a ratio of the image data that causes the display pixels of the liquid crystal display panel to display white with respect to the image data for one screen. Controlling the emission luminance of the backlight so as to reduce the luminance;
The frequency control means controls the frame frequency so as to decrease the frame frequency as the ratio decreases;
An active matrix type liquid crystal display device. In the display of the image data for the one screen , the frequency control unit is configured to reduce the spatial average value of the voltage applied to the liquid crystal of the display pixel, or the image data for the one screen. in view of, to the total number of display pixels, the voltage applied to the liquid crystal of the display pixel based on the ratio have number table示画element smaller than a predetermined threshold voltage, in accordance with the ratio increases, the frame 3. The active matrix liquid crystal display device according to claim 1, wherein the frequency is reduced.

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