JP5363237B2 - Photoelectric conversion circuit and photoelectric conversion element used therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photoelectric conversion circuit and a photoelectric conversion element which can exclude a bias dependence property of a photoelectric conversion element (photo diode). <P>SOLUTION: A photoelectric conversion element PD and a diode element D are connected between a first control line L1 and a second control line L2 mutually in an inverse direction and in series. By biasing the diode element D in a forward direction, a predetermined voltage is provided between a cathode and an anode of the photoelectric conversion element PD. Thus, a predetermined voltage is provided to a plurality of photoelectric conversion elements PDs, so that a bias dependence property of the photoelectric conversion elements is excluded. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

The present invention relates to a photoelectric conversion circuit and a photoelectric conversion element used for the photoelectric conversion circuit, and more particularly to a circuit that can eliminate bias dependency of the photoelectric conversion element.

FIG. 6 shows a conventional photoelectric conversion circuit 600 shown in FIG. 2 of Patent Document 1 with some reference numerals changed. The photoelectric conversion circuit 600 is configured to clamp a voltage applied to both terminals of the photoelectric conversion element PD to a predetermined voltage by a bias voltage VDDPD and a cascode current mirror circuit. That is, the voltage between the cathode and the anode of the photoelectric conversion element (photodiode) PD is clamped to a predetermined voltage by the bias voltage VDDPD and the anode voltage Va generated on the cascode current mirror circuit side.

Next, a circuit operation of the photoelectric conversion circuit 600 will be briefly described. First, at initialization (reset), when the reset signal RST rises from a low level to a high level, the transistor N6 is turned on. At this time, the read signal RD is maintained at the low level, and the transistor N8 is turned off. One end (gate) of the MOS capacitor N5 is connected to the application terminal of the power supply voltage VDD via the transistor N6, and the terminal voltage Vb is raised to a predetermined initial voltage level that is substantially the power supply voltage. As a result, the transistor N7 is reset to the initial state of the full on state.

After the initialization of the photoelectric conversion circuit 600, when the photoelectric conversion element PD is exposed, the reset signal RST falls again to the low level, and the transistor N6 is turned off. At this time, the read signal RD is continuously maintained at the low level, and the transistor N8 is also turned off. Therefore, the MOS capacitor N5 is discharged by the mirror current Im drawn into the current mirror circuit, and the terminal voltage Vb is lowered from the initial voltage level. As a result, the transistor N7 depends on the amount of light received by the photoelectric conversion element PD, and the on state is lower than the initial state.

After the exposure, when the light reception signal is read, the transistor N8 is turned on when the read signal RD rises to a high level. At this time, the reset signal RST is continuously maintained at the low level, and the transistor N6 is turned off. Note that the source of the transistor N7 is connected to the column selection line Yn via the transistor N8. As a result, the output current Io corresponding to the conductivity of the transistor N7, that is, the amount of light received by the photoelectric conversion element PD is drawn from the column selection line Yn, and the output voltage Vo corresponding to this is obtained. This makes it possible to obtain the amount of light received by the photoelectric conversion element PD. The greater the amount of light received by the photoelectric conversion element PD, the lower the output current Io, and the lower the output voltage Vo.

However, since the photocurrent Id converted by the photoelectric conversion element PD is very small, the currents necessary for the MOS transistors N1, N2, N3, and N4 constituting the cascode type current mirror circuit to operate in the saturation region are respectively present. There is a problem that it does not flow sufficiently, and therefore it is difficult to clamp the anode voltage Va to a predetermined voltage.

FIG. 3 of Patent Document 1 shows a CIGS (Cupper Indium Gallium Selenium) photoelectric conversion element. That is, a thin film made of a compound of copper (Cupper), indium (Gallium), and selenium (Selenium), which is a non-silicon-based material different from a silicon-based photoelectric conversion element, is used as a photoelectric conversion element. The one used in is shown. Even in such a CIGS photoelectric conversion element, the bias voltage VDDPD is supplied to the cathode, and the anode voltage Va generated by the cascode current mirror circuit is supplied to the anode.

FIG. 7 shows the photoelectric sensor shown in FIG. 5 of Patent Document 2 with a part of reference numerals changed and a part of reference numerals added. Patent Document 2 suggests a technical idea suitable for so-called global shutter exposure control. In the photoelectric conversion circuit 700, the anode of the photoelectric conversion element 1 is connected to the ground potential 2, and the cathode thereof is connected to the diode node N1, that is, the cathode of the reset diode D1. Therefore, the cathodes of the photoelectric conversion element 1 and the reset diode D1 are connected in common, and the common connection point is connected to the diode node N1. The reset signal Vreset1 of the diode D1 is supplied to the anode of the reset diode D1. That is, in terms of circuit configuration, the photoelectric conversion element 1 and the reset diode D1 are connected in the opposite direction and in series between the control line Lr1 to which the reset signal Vreset1 is supplied and the ground potential 2.

The first main electrode of the shutter transistor T2 and the first terminal of the photodiode capacitor C10 are commonly connected to the diode node N1, and the second main electrode of the shutter transistor T2 and the first terminal of the conversion node capacitor C20 are connected to the node N3. Commonly connected. Further, the second terminal of the photodiode capacitor C10 and the second terminal of the conversion node capacitor C20 are both commonly connected to the ground potential 2. Further, the gate of the read transistor T3 and the first main electrode of the reset transistor T5 are commonly connected to the node N3, that is, the common connection point of the shutter transistor T2 and the conversion node capacitor C20. The second main electrode of the reset transistor T5 and the first main electrode of the read transistor T3 are both connected to a control line Lr2 to which a reset signal Vreset2 is supplied. The first main electrode of the row selection transistor T4 is connected to the second main electrode of the read transistor T3, and the second main electrode of the row selection transistor T4 is connected to the column bus Yn1.

FIG. 8 shows the photodetector shown in FIG. In the photodetector 800, the photodiode (photoelectric conversion element) 1 generates charge carriers as a function of incident light 9. The anode 11 of the photodiode 1 is connected to the ground potential GND, and the cathode 12 thereof is connected to the sense node 4. The sense node 4 is connected to the cathode 22 of the shunt diode 2. The sense node 4 is also a common connection point between the cathode 12 of the photodiode 1 and the cathode 22 of the shunt diode 2. The anode 21 of the shunt diode 2 is connected to the control line 5 to which the control voltage Vc is supplied. The control voltage Vc is assumed to be either constant in time or modulated over time in synchronization with the reset clock. When the control voltage Vc is constant, the value is from 0 to the bias voltage VR. The bias voltage VR is a reverse bias voltage supplied to the photodiode 1. That is, the control voltage Vc is selected so as to reverse bias the shunt diode 2. The shunt diode 2 is shielded from the incident light 9 by the shielding means 90.

In the photodetector 800, the sense node 4 is connected in common to the first main electrode of the reset switch 61 and the gate of the source follower 62, and the bias voltage VR is supplied to the second main electrode of the reset switch 61. The first main electrode of the column selection switch 63 is connected to the first main electrode 62, and the column line 7 is connected to the second main electrode of the column selection switch 63.

JP 2009-60424 A JP-T-2006-505159 JP 2003-202264 A

It is recognized that the above-mentioned Patent Document 1, Patent Document 2, and Patent Document 3 disclose or suggest the technical idea of supplying a predetermined voltage to the cathode or anode of a photoelectric conversion element (photodiode). However, the technical idea of eliminating the bias dependency of the photoelectric conversion element, that is, the photodiode, is not disclosed or suggested. The photoelectric conversion circuit according to the present invention provides a photoelectric conversion circuit and a photoelectric conversion element that can eliminate the bias dependency of a photodiode.

The photoelectric conversion device according to claim 1 of the present invention includes a first control line to which a first control voltage which is a DC voltage is supplied, a first capacitor to which a first fixed potential is supplied to one end, and the first control line. And a photoelectric conversion element connected between the other end of the first capacitor, the photoelectric conversion element is supplied with a cathode connected to the first control line, a potential lower than the cathode, and An anode connected to the other end of the first capacitor; a first electrode connected to the other end of the first capacitor; a second electrode; and a control electrode to which a second control voltage that is a DC voltage is supplied Connected to the other end of the second capacitor, a second capacitor including one end to which the second fixed potential is supplied, a second end to which the second electrode of the first transistor is connected. To the first fixed electrode and the third fixed potential A second transistor including a second electrode to be connected; a control electrode to which a second control voltage is supplied; a control electrode connected to the other end of the second capacitor; and a first electrode to which a reference potential is supplied And a third transistor including a second electrode; a first electrode connected to the second electrode of the third transistor; a control electrode to which a third control voltage is supplied; and a fourth electrode including a second electrode. A transistor, and a signal output line connected to the second electrode of the fourth transistor, the voltage value a of the first control voltage, the voltage value b of the second control voltage, the threshold voltage of the first transistor The voltage value d of c and the third fixed potential satisfies d + c ≦ b ≦ a + c.

The photoelectric conversion device according to claim 2 of the present invention is characterized in that the first, third, and fourth transistors are PMOSFETs, and the second transistor is an NMOSFET. The photoelectric conversion device according to claim 3 of the present invention further includes a second control line to which a fourth control voltage which is a DC voltage is supplied, and a diode element, and the diode element is connected to an anode of the photoelectric conversion element. And an anode connected to the second control line.

According to a fourth aspect of the present invention, there is provided a photoelectric conversion device comprising: a first control line to which a first control voltage that is a DC voltage is supplied; a first capacitor to which a first fixed potential is supplied at one end; and the first control line. And a photoelectric conversion element connected between the other end of the first capacitor, the photoelectric conversion element is supplied with an anode connected to the first control line, a potential higher than the anode, and A cathode connected to the other end of the first capacitor; a first electrode connected to the other end of the first capacitor; a second electrode; and a control electrode to which a second control voltage that is a DC voltage is supplied Connected to the other end of the second capacitor, a second capacitor including one end to which the second fixed potential is supplied, a second end to which the second electrode of the first transistor is connected. First electrode and third fixed potential A second transistor including a second electrode to be connected; a control electrode to which a second control voltage is supplied; a control electrode connected to the other end of the second capacitor; and a first electrode to which a power supply voltage is supplied And a third transistor including a second electrode; a first electrode connected to the second electrode of the third transistor; a control electrode to which a third control voltage is supplied; and a fourth electrode including a second electrode. A transistor, and a signal output line connected to the second electrode of the fourth transistor, the voltage value a of the first control voltage, the voltage value b of the second control voltage, the threshold voltage of the first transistor c and the voltage value d of the third fixed potential satisfy dc ≦ b ≦ ac.

The photoelectric conversion device according to claim 5 of the present invention is characterized in that the first, second, third and fourth transistors are NMOSFETs. The photoelectric conversion device according to claim 6 of the present invention further includes a second control line to which a fourth control voltage that is a DC voltage is supplied, and a diode element, and the diode element is connected to a cathode of the photoelectric conversion element. And a cathode connected to the second control line.

The photoelectric conversion device according to claim 7 of the present invention is characterized in that the first control voltage supplied to the first control line is set larger than the fourth control voltage supplied to the second control line. . The photoelectric conversion device according to claim 8 of the present invention is characterized in that the first control voltage supplied to the first control line is set smaller than the fourth control voltage supplied to the second control line. .

The photoelectric conversion device according to claim 9 of the present invention is such that the potential applied to the cathode of the diode element is lower than the potential applied to the anode of the direct current voltage supplied to the first control line and the second control line. The size of is set.

The photoelectric conversion device according to claim 10 of the present invention is characterized in that the photoelectric conversion element is silicon-based. The photoelectric conversion device according to claim 11 of the present invention is characterized in that the photoelectric conversion element is non-silicon-based. According to a photoelectric conversion device of a twelfth aspect of the present invention, the photoelectric conversion element is a non-silicon system made of copper, indium, gallium, and selenium.

The photoelectric conversion device according to claim 13 of the present invention is characterized in that the diode element is formed on the same chip as the photoelectric conversion element. The photoelectric conversion device according to claim 14 of the present invention is characterized in that the diode element uses a transistor having the same conductivity type as the first transistor. The photoelectric conversion device according to claim 15 of the present invention is characterized in that the diode element has the same size as the first transistor.

The photoelectric conversion device according to claim 16 of the present invention is characterized in that at least one of the first capacitor and the second capacitor is formed by a diffusion capacitance of a first transistor.

In the photoelectric conversion device according to claim 17 of the present invention, the photoelectric conversion element includes an aluminum light-shielding film having an opening region in part, a common electrode layer having an N-type zinc oxide layer and an intrinsic zinc oxide layer, and a cadmium sulfide layer. A CIGS layer, a metal electrode layer, an insulating layer, and a via layer, wherein the metal electrode layer is connected to the second control line through the via layer, and the common electrode layer is the first electrode It is connected to a control line. In the photoelectric conversion device according to claim 18 of the present invention, the first capacitor is a parasitic capacitance of the photoelectric conversion element or the first transistor, and the second capacitor is the first transistor, the second transistor, and the first transistor. It is characterized by a parasitic capacitance of 3 transistors.

The photoelectric conversion circuit of the present invention can obtain an output signal corresponding to the exposure amount with a constant accuracy regardless of the bias dependency of the photoelectric conversion element. Further, by appropriately setting the bias voltage of the photoelectric conversion element, it is possible to perform stable amplification of exposure sensitivity using the avalanche multiplication effect.

1 shows a photoelectric conversion circuit according to a first embodiment of the present invention. 2 shows a timing chart according to the first embodiment of the present invention. The photoelectric conversion circuit concerning the 2nd Embodiment of this invention is shown. The timing chart concerning the 2nd Embodiment of this invention is shown. The photoelectric conversion circuit concerning the 3rd Embodiment of this invention and a photoelectric conversion element using the same are shown. An example of a conventional photoelectric conversion circuit is shown. Another example of a conventional photoelectric conversion circuit is shown. Another example of a conventional photoelectric conversion circuit will be described.

(First embodiment)
FIG. 1 shows a photoelectric conversion circuit 100 according to the present invention. FIG. 2 shows a timing chart according to the first embodiment. The photoelectric conversion circuit 100 shown in FIG. 1 is arranged in a matrix, for example, and is prepared for, for example, configuring a CMOS image sensor. The cathodes and anodes of the plurality of photoelectric conversion elements PD are individually connected to the first control line L1 and the node Nd1. The cathodes of a plurality of photoelectric conversion elements PD (not shown) are commonly connected to the first control line L1. That is, FIG. 1 shows a cathode common type photoelectric conversion circuit. As the photoelectric conversion element PD, a silicon photodiode or a non-silicon photodiode described later can be used.

The anode and cathode of the diode element D are connected to the node Nd1 and the second control line L2, respectively. The node Nd1 corresponds to a common connection point between the anodes of the photoelectric conversion element PD and the diode element D. The diode element D may have a diode structure, or may have a transistor structure but be configured to obtain diode characteristics. Such diodes and transistors may be of the MOS type or of the bipolar type. In the first embodiment of the present invention, the MOS transistor is configured to exhibit diode characteristics. For example, the diode element D has the same conductivity type and the same size as the transistor Tr1 described later, and a control electrode (gate) and a first main electrode (for example, drain) are connected in common, and the common connection point and the second main electrode (for example, for example) The diode characteristic (square characteristic) generated in the electric circuit between the source and the source is used. If the diode element D and the transistor Tr1 have the same conductivity type and the same size, both threshold voltages described later can be made substantially uniform.

The diode characteristics referred to in this document include not only the generally well-known diode characteristics but also the square characteristics well-known for MOS transistors.

The photoelectric conversion element PD and the diode element D are connected in the opposite direction and in series between the first control line L1 and the second control line L2. A predetermined control voltage is separately supplied to the first control line L1 and the second control line L2 so that a bias is supplied to the diode element D in the forward direction. The first control voltage Ve1 and the second control voltage Ve2 supplied to the first control line L1 and the second control line L2 are, for example, Ve1 = 3.3V, Ve2 = 2.6V, and the relationship of Ve1> Ve2. Each control voltage is set so that More specifically, when the diode element D is forward-biased, the threshold voltage is set to Vt so that the relationship Ve1 ≧ (Ve2 + Vt) is established. Thus, the photoelectric conversion element PD can be operated in a reverse bias state.

The first terminal of the first capacitor C1 is connected to the node Nd1 of the photoelectric conversion circuit 100, and the second terminal is connected to the ground potential GND. The node Nd1 is connected to the first main electrode of the transistor Tr1. The second main electrode of the transistor Tr1 is connected to the node Nd2, the first terminal of the second capacitor C2 is connected to the node Nd2, and the second terminal is connected to the ground potential GND. A predetermined bias (transfer) voltage is connected to the control electrode G1 of the transistor Tr1, and a first main electrode of the transistor Tr2 and a control electrode of the transistor Tr3 are further connected in common to the node Nd2. The second terminal of the second capacitor C2, the second main electrode of the transistor Tr2, and the first main electrode of the transistor Tr3 are commonly connected to the ground potential GND. The second main electrode of the transistor Tr3 is connected to the first main electrode of the transistor Tr4 to which the read signal V4 is supplied to the control electrode, and the second main electrode of the transistor Tr4 is connected to the signal output line Yn4.

  In the first embodiment, the transistors Tr1, Tr3, and Tr4 are P-channel type and the transistor Tr2 is N-channel type. However, the channel type of these transistors can be changed at any time. For example, the transistor Tr2 may be a P-channel type and all the transistors may be a P-channel type.

The transistor Tr1 functions as a so-called transfer transistor that plays a role of transferring signals to each other depending on the magnitude relationship between the potentials of the nodes Nd1 and Nd2. For example, when the potential of the node Nd1 is higher than that of the node Nd2, the charge accumulated in the node Nd1 is transferred to the node Nd2. Conversely, when the potential of the node Nd2 is higher than that of the node Nd1, charges are transferred toward the node Nd1. In other words, charges are exchanged between the two nodes, and finally the potentials at both nodes settle to approximately the same magnitude.

The transistor Tr2 serves as a so-called reset transistor that maintains the charge of the second capacitor C2 in the initial state and initializes (resets) the potential of the node Nd2 to the initial state. The transistor Tr3 functions as a buffer transistor having a function of reading the potential of the node Nd2. The transistor Tr4 has a function of outputting a read signal output to the signal output line Yn4.

Under the configuration in which the second control voltage Ve2 is supplied to the second control line L2, the maximum potential Vnd1m that can be taken by the node Nd1 is Vnd1m = (Ve2 + Vt). Here, the threshold voltage Vt is a forward rising voltage of the diode element D. For example, when the second control voltage Ve2 is 2.6V and the threshold voltage Vt is 0.6V, the maximum potential Vnd1m is 3.2V. That is, one feature of the present invention is to control the maximum potential of charges accumulated in the first capacitor C1 by the diode element D.

When the voltage applied between the cathode and the anode of the photoelectric conversion element PD is used as small as possible, the magnitude of the first control voltage Ve1 supplied to the cathode of the photoelectric conversion element PD is larger than the voltage supplied to the anode. Is set to be higher by a predetermined size. The cathode of the photoelectric conversion element PD is higher than the anode by a predetermined voltage, and the reverse bias state is maintained. When the photoelectric conversion element PD performs photocurrent amplification using the avalanche multiplication effect, the first control voltage Ve1 is set to about 10V, for example. Whether the photoelectric conversion element PD is used for the avalanche multiplication effect or not, the magnitude of the voltage supplied between the cathode and the anode of the photoelectric conversion element PD is the first control voltage Ve1. , And can be determined according to the magnitude of the second control voltage Ve2. That is, by setting the diode element D in the forward bias state, the voltage supplied between the cathodes and the anodes of all the photoelectric conversion elements PD can be suppressed within a predetermined range. Can be eliminated. Note that the bias dependency of the photoelectric conversion element PD referred to in this document indicates that a difference occurs in the sensitivity of photoelectric conversion depending on the magnitude of the voltage applied to each photoelectric conversion element. Eliminating the bias dependence of the photoelectric conversion element PD is nothing but to equalize the sensitivity and response speed of each photoelectric conversion element.

The transfer signal V1 is not a temporal transition, but is a DC voltage that is always constant. The transfer signal V1 is set to a value smaller than the second control voltage Ve2 supplied to the cathode of the diode element D. For example, when the second control voltage Ve2 = 2.6V, the transfer signal V1 is set to V1 = 2.5V. Note that the high level of the initialization signal V2 is 3.3 V, and the low level is the ground potential GND. Further, the high level of the read signal V4 is set to 3.3 V, which is the same as the power supply voltage, and the low level is set to the ground potential GND.

  The timing chart 200 shown in FIG. 2 is schematically shown for convenience of explanation and drawing. The circuit operation will be described below with reference to FIGS.

In FIG. 2, time t <b> 0 indicates when the photoelectric conversion circuit 100 is powered on. The initialization signal V2 shown in FIG. 2A is supplied to the control electrode (gate) G2 of the transistor Tr2, and is set to be at a low level L at time t0, that is, when the power is turned on. The initialization signal V2 transitions from the low level L to the high level H at times t1, t4, t7, and t12, the initialization signal is validated at the high level H, and invalidated at other times. That is, initialization is performed when the initialization signal V2 is at the high level H.

The read signal V4 shown in FIG. 2B is supplied to the control electrode G4 of the transistor Tr4, and is maintained at the high level H at time t0. The read signal V4 transitions from the high level H to the low level L at times t2, t3, t5, t6, t8, t11, and t13, the read signal V4 becomes valid at the low level L, and invalid at other times. . That is, the read operation is performed when the read signal V4 is at the low level L.

The read signal V4 shown in FIG. 2B includes V4a and V4b. The read signal V4a is prepared for performing an original read operation, and the read signal V4b is prepared for an auxiliary operation before performing the read operation. That is, the original read operation is performed at times t3, t6, and t11, and the read signal is output to the signal output line Yn4. This output includes a so-called noise component different from the original signal component. May be. Therefore, the noise component must be subtracted from the original signal component. Reading this noise component is a read signal V4b having an auxiliary role. The read signal V4b is prepared at times t2, t5, t8, and t13, for example, immediately after the initialization signal V2. The noise component read by the read signal V4b is temporarily stored in storage means (not shown) connected to the signal output line Yn4, and subtracted from the signal component output by the original read signal V4a. Only the true signal component is extracted.

FIG. 2C shows the first control voltage Ve1 supplied to the first control line L1. The first control voltage Ve1 maintains a predetermined DC voltage for a period from when the power is turned on at time t0 to when the power is turned off. The first control voltage Ve1 is Ve1 = 3.3V in the first embodiment, although it depends on the magnitude of the reverse bias voltage applied to the photoelectric conversion element PD. Note that the magnitude of Ve1 = 3.3V is equal to the power supply voltage of the photoelectric conversion circuit 100.

FIG. 2D shows the second control voltage Ve2 supplied to the second control line L2. Similar to the first control voltage Ve1, the second control voltage Ve2 maintains a predetermined DC voltage during a period from when the power is turned on at time t0 to when the power is turned off. The second control voltage Ve2 is set to a predetermined magnitude in order to control the maximum potential applied to the anode of the photoelectric conversion element PD, but considering the magnitude of the first control voltage Ve1, the second control voltage Ve2 is more than the first control voltage Ve1. Small Ve2 = 2.6V.

FIG. 2E shows the transfer signal V1 supplied to the control electrode G1 of the transistor Tr1. The transfer signal V1 maintains a predetermined DC voltage for a period from when the power is turned on at time t0 to when the power is turned off. The transfer signal V1 is determined by the threshold voltage Vt1, the first control voltage Ve1, and the second control voltage Ve2 of the transistor Tr1, but in the first embodiment, V1 = 2.5V, which is slightly lower than the second control voltage Ve2. It is set.

FIG. 2F shows the node potential Vnd1 generated at the node Nd1. The node charge Vnd1 reflects the signal charge accumulated in the first capacitor C1. At the time t0, the power is turned on and exposure to the photoelectric conversion element PD is started at the same time. With the exposure, charges are accumulated in the first capacitor C1, and the node potential Vnd1 rises with time. When the node potential Vnd1 reaches the potential (V1 + Vt1), it is maintained at this potential level thereafter. Here, reference symbol V1 is a transfer signal supplied to the control electrode G1 of the transistor Tr1, and reference symbol Vt1 is a threshold voltage of the transistor Tr1. The magnitude of the threshold voltage Vt1 is, for example, 0.6V.

As shown in FIG. 2F, the node potential Vnd1 is substantially maintained at the potential (V1 + Vt1) until the time t9 after the time t1 elapses. That is, the node potential Vnd1 in the exposure period including the exposure period 1, the exposure period 2, and the exposure period 3 is controlled by the transfer signal V1 and the threshold voltage Vt1 supplied to the transistor Tr1. Although the exposure period is divided into three periods, it does not mean that the exposure is performed in three stages. For convenience of explanation, the exposure period is divided over time. The exposure period 1 is an exposure state immediately after the power is turned on, and the exposure period 2 is a time after the power is turned on and after a node potential Vnd1 = (V1 + Vt1), at least one initialization operation is performed. An exposure period 3 after exposure is shown as an exposure period 3 immediately before exposure is sufficiently performed and exposure is saturated.

The node potential Vnd1 shown in FIG. 2 (f) slightly rises after time t9. That is, when the exposure saturation period t7 to t12 is entered and the exposure is sufficiently performed or when strong light is incident on the photoelectric conversion element PD, the node potential Vnd1 starts to rise further. That is, when the exposure saturation period starts, the node potential Vnd1 starts to increase slightly, and the node potential Vnd1 is controlled to the potential (Ve2 + Vt) at time t10. Here, reference sign Ve2 is a second control voltage supplied to the second control line L2, and reference sign Vt is a threshold voltage of the diode element D, that is, a forward rising voltage. That is, when exposure enters a saturation state, the node potential Vnd1 is not restricted by the transistor Tr1, but is restricted by the second control voltage Ve2 supplied to the diode element D. As a result, the voltage between the anode and the cathode of the photoelectric conversion element PD is determined by the first control voltage Ve1 and the second control voltage Ve2, so that the bias dependency of the photoelectric conversion element PD itself can be eliminated.

FIG. 2G shows the node potential Vnd2 of the node Nd2. Unlike the potential change of the node potential Vnd1, the node potential Vnd2 responds to the operation of the node potential Vnd1 and the transistor Tr1. That is, the node potential Vnd2 is substantially zero until time t1 when the node potential Vnd1 reaches the potential (V1 + Vt1). When the node potential Vnd1 reaches the potential (V1 + Vt1), it gradually starts to rise and reaches the read level Vnd2a when the time t3 is reached. The node potential Vnd2 starts to rise until the initialization signal V2 is applied, and reset (initialization) is repeated in synchronization with the initialization signal V2. The node potential Vnd2 first rises to the potential (V1 + Vt1) due to the influence of the operating point of the transistor Tr1 at times t7 to t12, which is the exposure saturation period. After that, when the exposure saturation state continues, it is affected by the potential of the node Nd1, and rises to the same level as the node potential Vnd1. Therefore, in the exposure saturation period, electric charges are transferred between the node Nd1 and the node Nd2 from the higher potential to the lower potential, and finally the node potentials of both become substantially equal. The maximum potential Vnd2m of the node potential Vnd2 of the node Nd2 is Vnd2m = (Ve2 + Vt). That is, the anode of the photoelectric conversion element PD is controlled to a predetermined potential by the magnitude of the second control voltage Ve2 supplied to the cathode of the diode element D and the threshold voltage Vt of the diode element D.

FIG. 2H shows the voltage Vpd applied between the anode and cathode of the photoelectric conversion element PD. It can be seen that the voltage Vpd is determined by the first control voltage Ve1, the transfer signal V1 supplied to the transistor Tr1, the threshold voltage Vt1 of the transistor Tr1, the second control voltage Ve2, and the threshold voltage Vt of the diode element D. In particular, at times t7 to t12, which is an exposure saturation period, the voltage Vpd between the anode and the cathode of the photoelectric conversion element PD can be determined by the second control voltage Ve2 and the threshold voltage Vt of the diode element D. The bias dependence of PD can be eliminated.

(Second Embodiment)
FIG. 3 shows a photoelectric conversion circuit 300 according to the present invention. FIG. 4 shows a timing chart according to the second embodiment. The photoelectric conversion circuit 300 shown in FIG. 3 is arranged, for example, in a matrix, and is prepared, for example, to constitute a CMOS image sensor. The anodes and cathodes of the plurality of photoelectric conversion elements PD are connected to the first control line L10 and the node Nd10, respectively. Anodes of a plurality of photoelectric conversion elements PD (not shown) are commonly connected to the first control line L10. That is, FIG. 3 shows an anode common type photoelectric conversion circuit. A silicon-based photodiode is used as the photoelectric conversion element PD.

The cathode and anode of the diode element D are connected to the node Nd10 and the second control line L20, respectively. The node Nd10 corresponds to a common connection point between the cathodes of the photoelectric conversion element PD and the diode element D. The diode element D may have a diode structure, or may have a transistor structure but be configured to obtain diode characteristics. Such diodes and transistors may be of the MOS type or of the bipolar type. In the second embodiment of the present invention, the MOS transistor is configured to exhibit diode characteristics. For example, the diode element D has the same conductivity type and the same size as the transistor Tr10 described later, and the control electrode (gate) and the first main electrode (for example, drain) are connected in common, and the common connection point and the second main electrode (for example, for example) The diode characteristic (square characteristic) generated in the electric circuit between the source and the source is used. If the diode element D and the transistor Tr10 have the same conductivity type and the same size, both threshold voltages described later can be made substantially uniform.

The diode characteristics referred to in this document include not only the generally well-known diode characteristics but also the square characteristics well-known for MOS transistors.

The photoelectric conversion element PD and the diode element D are connected in the opposite direction and in series between the first control line L10 and the second control line L20. A predetermined control voltage is separately supplied to the first control line L10 and the second control line L20 so that a bias is supplied to the diode element D in the forward direction. The first control voltage Ve10 and the second control voltage Ve20 supplied to the first control line L10 and the second control line L20 have a relationship of Ve10 <Ve20, for example, Ve10 = 0V and Ve20 = 0.9V, respectively. Each control voltage is set so as to. More specifically, when the diode element D is biased in the forward direction, if the threshold voltage is Vt, the relationship Ve10 ≦ (Ve20−Vt) is set. Thus, the photoelectric conversion element PD can be operated in a reverse bias state.

The first terminal of the first capacitor C1 is connected to the node Nd10 of the photoelectric conversion circuit 300, and the second terminal is connected to the ground potential GND. Further, the first main electrode of the transistor Tr10 is connected to the node Nd10. The second main electrode of the transistor Tr10 is connected to the node Nd20, the first terminal of the second capacitor C2 is connected to the node Nd20, and the second terminal is connected to the ground potential GND. A predetermined bias (transfer) voltage is connected to the control electrode G10 of the transistor Tr10, and a first main electrode of the transistor Tr20 and a control electrode of the transistor Tr30 are further connected in common to the node Nd20. The second terminal of the second capacitor C2 is connected to the ground potential GND, and the second main electrode of the transistor Tr20 and the first main electrode of the transistor Tr30 are commonly connected to the power supply voltage. The second main electrode of the transistor Tr30 is connected to the first main electrode of the transistor Tr40 to which the read signal V40 is supplied to the control electrode, and the second main electrode of the transistor Tr40 is connected to the signal output line Yn40.

  In the second embodiment, the transistors Tr10, Tr20, Tr30, and Tr40 are N-channel type, but the channel type of these transistors can be changed at any time. For example, at least one of these transistors can be replaced with a P-channel type.

The transistor Tr10 functions as a so-called transfer transistor that plays a role of transferring charges from one node side to the other node side due to the magnitude relationship between the potentials of the nodes Nd10 and Nd20. For example, when the potential of the node Nd10 is higher than that of the node Nd20, the electric charge accumulated in the node Nd10 is transferred toward the photoelectric conversion element PD because it is extracted by the photoelectric conversion element PD in response to light reception. . On the other hand, when the potential of the node Nd20 is higher than that of the node Nd10, the charge stored in the node Nd20 is extracted by the photoelectric conversion element PD in response to light reception, and is transferred toward the photoelectric conversion element PD. That is, charge is exchanged between both nodes, and finally the potentials of both nodes settle to approximately the same magnitude.

The transistor Tr20 serves as a so-called reset transistor that maintains the charge of the second capacitor C2 in the initial state and initializes (resets) the potential of the node Nd20 to the initial state. The transistor Tr30 functions as a buffer transistor having a function of reading the potential of the node Nd20. The transistor Tr40 has a function of outputting a read signal output to the signal output line Yn40.

Under the configuration in which the second control voltage Ve20 is supplied to the second control line L20, the minimum potential Vnd10m that can be taken by the node Nd10 is Vnd10m = (Ve20−Vt). Here, the threshold voltage Vt is a forward rising voltage of the diode element D. For example, when the second control voltage Ve20 is 0.9V and the threshold voltage Vt is 0.6V, the minimum potential Vnd10m is 0.3V. That is, one feature of the present invention is to control the minimum potential of the electric charge accumulated in the first capacitor C1 by the diode element D.

When the voltage applied between the cathode and the anode of the photoelectric conversion element PD is used as small as possible, the magnitude of the first control voltage Ve10 supplied to the anode of the photoelectric conversion element PD is larger than the potential supplied to the cathode. Is set to be lower by a predetermined size. The cathode of the photoelectric conversion element PD is higher than the anode by a predetermined voltage, and the reverse bias state is maintained. When the photoelectric conversion element PD performs photocurrent amplification using the avalanche multiplication effect, the first control voltage Ve10 is set to, for example, about −10V. Whether the photoelectric conversion element PD is used for the avalanche multiplication effect or not, the magnitude of the voltage supplied between the cathode and the anode of the photoelectric conversion element PD is the first control voltage Ve10. It can be determined by the magnitude of the second control voltage Ve20. That is, by setting the diode element D in the forward bias state, the voltage supplied between the cathodes and the anodes of all the photoelectric conversion elements PD can be suppressed within a predetermined range. Can be eliminated. Note that the bias dependency of the photoelectric conversion element PD referred to in this document indicates that a difference occurs in the sensitivity of photoelectric conversion depending on the magnitude of the voltage applied to each photoelectric conversion element. Eliminating the bias dependence of the photoelectric conversion element PD is nothing but to equalize the sensitivity and response speed of each photoelectric conversion element.

The transfer signal V10 is not a temporal transition, but is a DC voltage that is always constant. Further, the transfer signal V10 is set to a value larger than the second control voltage Ve20 supplied to the anode of the diode element D. For example, if the second control voltage Ve20 = 0.9V, the transfer signal V10 is set to V10 = 1.0V. Note that the high level of the initialization signal V20 is 3.3 V, and the low level is the ground potential GND. Further, the high level of the read signal V40 is also set to 3.3 V which is the same as the power supply voltage, and the low level is set to the ground potential GND.

  A timing chart 400 shown in FIG. 4 is schematically shown for convenience of explanation and drawing. The circuit operation will be described below with reference to FIGS.

In FIG. 4, time t0 indicates when the photoelectric conversion circuit 300 is turned on. The initialization signal V20 shown in FIG. 4A is supplied to the control electrode (gate) G20 of the transistor Tr20, and is set to be at the low level L at time t0, that is, when the power is turned on. The initialization signal V20 transitions from the low level L to the high level H at times t1, t4, t7, and t12, the initialization signal is validated at the high level H, and invalidated at other times. That is, initialization is performed when the initialization signal V20 is at the high level H.

The read signal V40 shown in FIG. 4B is supplied to the control electrode G40 of the transistor Tr40, and is maintained at the low level L at time t0. The read signal V40 transitions from the low level L to the high level H at times t2, t3, t5, t6, t8, t11, and t13, the read signal V40 is validated at the high level H, and invalid at other times. . That is, the read operation is performed when the read signal V40 is at the high level H.

The read signal V40 shown in FIG. 4B is composed of V40a and V40b. The read signal V40a is prepared for performing an original read operation, and the read signal V40b is prepared for an auxiliary operation before performing the read operation. That is, the original read operation is performed at times t3, t6, and t11, and the read signal is output to the signal output line Yn40. This output includes a so-called noise component different from the original signal component. May be. Therefore, the noise component must be subtracted from the original signal component. Reading this noise component is a read signal V40b having an auxiliary role. The read signal V40b is prepared at times t2, t5, t8, and t13, for example, immediately after the initialization signal V20. The noise component read by the read signal V40b is temporarily stored in a storage means (not shown) connected to the signal output line Yn40, and subtracted from the signal component output by the original read signal V40a. Only the true signal component is extracted.

FIG. 4C shows the first control voltage Ve10 supplied to the first control line L10. The first control voltage Ve10 maintains a predetermined DC voltage for a period from when the power is turned on at time t0 to when the power is turned off. The first control voltage Ve10 is Ve10 = 0V in the second embodiment although it depends on the magnitude of the reverse bias voltage applied to the photoelectric conversion element PD. Note that the magnitude of Ve10 = 0V is equal to the ground potential GND of the photoelectric conversion circuit 300.

FIG. 4D shows the second control voltage Ve20 supplied to the second control line L20. Similar to the first control voltage Ve10, the second control voltage Ve20 maintains a predetermined DC voltage for a period from when the power is turned on at time t0 until the power is turned off. The second control voltage Ve20 is set to a predetermined magnitude in order to control the minimum potential applied to the cathode of the photoelectric conversion element PD, but considering the magnitude of the first control voltage Ve10, the second control voltage Ve20 is more than the first control voltage Ve10. Large Ve20 = 0.9V.

FIG. 4E shows the transfer signal V10 supplied to the control electrode G10 of the transistor Tr10. The transfer signal V10 maintains a predetermined DC voltage for a period from when the power is turned on at time t0 to when the power is turned off. The transfer signal V10 is determined by the threshold voltage Vt10 of the transistor Tr10, the first control voltage Ve10, and the second control voltage Ve20. In the second embodiment, V10 = 1.0 V, which is slightly higher than the second control voltage Ve20. It is set.

FIG. 4F shows the node potential Vnd10 generated at the node Nd10. The node charge Vnd10 reflects the signal charge accumulated in the first capacitor C1. At the time t0, the power is turned on and exposure to the photoelectric conversion element PD is started at the same time. With the exposure, charges are accumulated or transferred in the first capacitor C1, and the node potential Vnd10 rises or falls as time passes. When the node potential Vnd10 reaches the potential (V10-Vt10), it is maintained at this potential level thereafter. Here, V10 is a transfer signal supplied to the control electrode G10 of the transistor Tr10, and Vt10 is a threshold voltage of the transistor Tr10. The magnitude of the threshold voltage Vt10 is, for example, 0.6V.

As shown in FIG. 4F, the node potential Vnd10 is maintained substantially at the potential (V10−Vt10) until the time t9 after the time t1 elapses. That is, the node potential Vnd10 in the exposure period composed of the exposure period 1, the exposure period 2, and the exposure period 3 is controlled by the transfer signal V10 and the threshold voltage Vt10 supplied to the transistor Tr10. Although the exposure period is divided into three periods, it does not mean that the exposure is performed in three stages. For convenience of explanation, the exposure period is divided over time. The exposure period 1 is an exposure state immediately after the power is turned on, and the exposure period 2 is a time after the power is turned on and after a node potential Vnd10 = (V10−Vt10), at least one initialization operation is performed. The exposure state after the exposure is performed, and the exposure period 3 indicates the exposure state immediately before the exposure is sufficiently performed and the exposure is saturated.

The node potential Vnd10 shown in FIG. 4 (f) slightly decreases after time t9. That is, in the exposure saturation period t7 to t12, the node potential Vnd10 starts to further decrease when the exposure is sufficiently performed or when strong light is incident on the photoelectric conversion element PD. That is, when the exposure saturation period starts, the node potential Vnd10 starts to decrease little by little, and the node potential Vnd10 is controlled to the potential (Ve20−Vt) at time t10. Here, Ve20 is a second control voltage supplied to the second control line L20, and reference sign Vt is a threshold voltage of the diode element D, that is, a forward rising voltage. That is, when the exposure enters a saturation state, the node potential Vnd10 is not restricted by the transistor Tr10 but is restricted by the second control voltage Ve20 supplied to the diode element D. As a result, the voltage between the anode and the cathode of the photoelectric conversion element PD is determined by the first control voltage Ve10 and the second control voltage Ve20, so that the bias dependency of the photoelectric conversion element PD itself can be eliminated.

FIG. 4G shows the node potential Vnd20 of the node Nd20. Unlike the potential change of the node potential Vnd10, the node potential Vnd20 responds to the operation of the node potential Vnd10 and the transistor Tr10. The node potential Vnd20 is substantially 0 potential or an arbitrary potential until time t1 when the node potential Vnd10 reaches the potential (V10−Vt10). When the node potential Vnd10 reaches the potential (V10−Vt10), the initialization signal V20 is raised from the low level to the high level at time t1, whereby the potential Vnd20 of the node Nd20 is set to the power supply voltage Vdd that is the initial potential. The For example, the power supply voltage Vdd = 3.3V. Thereafter, it gradually begins to fall according to the exposure of the photoelectric conversion element PD, and reaches the read level Vnd20a when time t3 is reached. The node potential Vnd20 starts to decrease until the initialization signal V20 is applied, and reset (initialization) is repeated in synchronization with the initialization signal V20. The node potential Vnd20 first falls to the potential (V10−Vt10) due to the influence of the operating point of the transistor Tr10 from time t7 to t12, which is the exposure saturation period. After that, when the exposure saturation state continues, it is affected by the potential of the node Nd10 and falls to the same level as the node potential Vnd10. Therefore, in the exposure saturation period, electric charges are transferred from the higher potential to the lower potential between the node Nd10 and the node Nd20, and finally the node potentials of both become substantially equal. The minimum potential Vnd20m of the node potential Vnd20 of the node Nd20 is Vnd20m = (Ve20−Vt). That is, the cathode of the photoelectric conversion element PD is controlled to a predetermined potential by the magnitude of the second control voltage Ve20 supplied to the anode of the diode element D and the threshold voltage Vt of the diode element D.

FIG. 4H shows the voltage Vpd applied between the anode and cathode of the photoelectric conversion element PD. It can be seen that the voltage Vpd is determined by the first control voltage Ve10, the transfer signal V10 supplied to the transistor Tr10, the threshold voltage Vt10 of the transistor Tr10, the second control voltage Ve20, and the threshold voltage Vt of the diode element D. In particular, at times t7 to t12, which is the exposure saturation period, the voltage Vpd applied between the anode and cathode of the photoelectric conversion element PD can be determined by the second control voltage Ve20 and the threshold voltage Vt of the diode element D. The bias dependency of the photoelectric conversion element PD can be eliminated.

(Third embodiment)
FIG. 5 shows a photoelectric conversion circuit and a photoelectric conversion element according to the present invention. The photoelectric conversion circuit 500 employs a CIGS photoelectric conversion element as a photoelectric conversion element. The cathode common type photoelectric conversion circuit 100 shown in FIG. 1 uses a silicon-based photoelectric conversion element, but the photoelectric conversion circuit 500 shown in FIG. 5 uses a non-silicon-type photoelectric conversion element PDC. Is different.

The photoelectric conversion element PDC includes an aluminum light-shielding film 50 having an opening region 52 in part, a common electrode layer Ec, a cadmium sulfide layer 58, a CIGS layer 60, a metal electrode layer (molybdenum electrode) 65, an insulating film 66, and a circuit unit 68. Consists of. The common electrode layer Ec includes an N-type zinc oxide layer 54 and an intrinsic zinc oxide layer 56. The photoelectric conversion element PDC is connected to the circuit unit 68 through the via 64.

The circuit unit 68 of the photoelectric conversion circuit 500 includes a via 64 and a photoelectric conversion circuit 100a. The only difference between the photoelectric conversion circuit 100a and the photoelectric conversion circuit 100 shown in FIG. 1 is the presence or absence of the photoelectric conversion element PD, and the other circuit configurations are exactly the same. The node Nd1 of the photoelectric conversion circuit 100a is connected to the anode electrode of the photoelectric conversion element PDC, that is, the metal electrode layer 65 through the via 64. The circuit unit 68 and the CIGS photoelectric conversion element PDC are formed in one chip via the insulating film 66.

The common electrode layer Ec is connected to the first control line L1. The first control voltage Ve1 is supplied to the first control line L1. The metal electrode layer 65 has a function of an anode of the photoelectric conversion element PDC, and a second control voltage Ve2 is supplied to the metal electrode layer 65 via the diode element D. Therefore, the voltage applied between the common electrode layer Ec and the metal electrode layer 65 of the photoelectric conversion element PDC is always a predetermined constant voltage. Further, the photoelectric conversion element PDC is stacked on the upper part of the circuit portion 68 via an insulating film 68 such as a silicon dioxide film, and both are connected via a via 64.

With the above configuration, unlike the configuration using a silicon-based photoelectric conversion element, semiconductor elements such as transistors and capacitors can be freely arranged in the circuit unit 68 without considering the occupied area of the photoelectric conversion element PDC on the chip. it can.

The common electrode layer Ec is transmissive to light. When light is exposed through the opening region 52 between the aluminum light-shielding films 50, between the cadmium sulfide layer 58 that is an N-type semiconductor layer that forms the photoelectric conversion element PDC and the CIGS layer 60 that is a P-type semiconductor layer A photocurrent is generated.

Each of the metal electrode layers 65 is clamped to a predetermined potential (Ve2 + Vt) via the diode element D built in the photoelectric conversion circuit 500. This is nothing but that the photoelectric conversion elements PDC can be insulated with extremely high resistance. In such a configuration, the interval between the metal electrode layers 65 can be made as small as possible, so that the degree of integration of the photoelectric conversion elements PDC can be increased.

Further, the aluminum light-shielding film 50 allows exposure only on the metal electrode layer 65. Therefore, photons generated by exposure reach only the metal electrode layer 65 immediately below due to the vertical component of the electric field. For example, 3.3 V is supplied as the first control voltage Ve1 supplied to the common electrode layer Ec, and 2.6 V is supplied as the predetermined second control voltage Ve2 supplied via the diode element D. When the control voltage is supplied, the voltage applied between the common electrode layer Ec and the metal electrode layer 65 is clamped to a predetermined voltage of Ve1- (Ve2 + Vt), that is, 0.1V, assuming that the threshold voltage of the diode element D is 0.6V. Is done. When photocurrent multiplication is performed using the avalanche multiplication effect, the first control voltage Ve1 supplied to the common electrode layer Ec is set to about 10V, for example.

In the present invention, the magnitude of the voltage applied between the cathodes and anodes of a plurality of photoelectric conversion elements during initialization, readout, exposure, and exposure saturation can be suppressed within a predetermined range. Thereby, since the photoelectric conversion circuit and photoelectric conversion element which can exclude the bias dependence of a plurality of photoelectric conversion elements can be provided, industrial applicability is very high.

In the photoelectric conversion circuit according to the present invention, the diode element is always used in the forward bias configuration, so that the terminals of the plurality of photoelectric conversion elements connected between the first control line and the diode element are connected. It is clamped at a predetermined voltage, and can be operated at a predetermined voltage optimum for the operation of the photoelectric conversion element regardless of the bias dependency of the photoelectric conversion element. Therefore, since the stable operation of the photoelectric conversion element and the operation utilizing the avalanche multiplication effect can be realized, the industrial applicability of, for example, a high-sensitivity optical sensor used in a camera or the like is extremely high.

50 Aluminum light shielding film 52 Opening region 54 N-type zinc oxide layer 56 Intrinsic zinc oxide layer 58 Cadmium sulfide layer 60 CIGS layer 64 Via 65 Metal electrode layer (molybdenum electrode)
66 Insulating film 68 Circuit unit 100, 100a, 300, 500 Photoelectric conversion circuit C1 First capacitor C2 Second capacitor D Diode element EC Common electrode layer GND Ground potential G1, G2, G3, G4, G10, G20, G30, G40 Control Electrode (gate)
L1, L10 First control line L2, L20 Second control line L0 Power supply voltage supply line Nd1, Nd2, Nd10, Nd20 Node PD, PDC Photoelectric conversion element (photodiode)
Tr1, Tr2, Tr3, Tr4, Tr10, Tr20, Tr30, Tr40 Transistor Yn4, Yn40 Signal output line

Claims (18)

A first control line to which a first control voltage that is a DC voltage is supplied;
A first capacitor having one end supplied with a first fixed potential;
A photoelectric conversion element connected between the first control line and the other end of the first capacitor;
The photoelectric conversion element is
A cathode connected to the first control line;
An anode connected to the other end of the first capacitor and supplied with a lower potential than the cathode;
A first transistor including a first electrode connected to the other end of the first capacitor, a second electrode, and a control electrode to which a second control voltage that is a DC voltage is supplied;
A second capacitor including one end to which a second fixed potential is supplied and the other end to which the second electrode of the first transistor is connected;
A second transistor including a first electrode connected to the other end of the second capacitor, a second electrode connected to a third fixed potential, and a control electrode supplied with a second control voltage;
A third electrode including a control electrode connected to the other end of the second capacitor, a first electrode supplied with a reference potential, and a second electrode;
A fourth transistor including a first electrode connected to the second electrode of the third transistor, a control electrode to which a third control voltage is supplied, and a second electrode;
A signal output line connected to the second electrode of the fourth transistor;
The voltage value a of the first control voltage, the voltage value b of the second control voltage, the threshold voltage c of the first transistor, and the voltage value d of the third fixed potential satisfy d + c ≦ b ≦ a + c. Filling photoelectric conversion device. The first, third, and fourth transistors are PMOSFETs;
The photoelectric conversion device according to claim 1, wherein the second transistor is an NMOSFET. A second control line to which a fourth control voltage that is a DC voltage is supplied;
A diode element;
The diode element is
An anode connected to the anode of the photoelectric conversion element;
The photoelectric conversion device according to claim 2, further comprising a cathode connected to the second control line. A first control line to which a first control voltage that is a DC voltage is supplied;
A first capacitor having one end supplied with a first fixed potential;
A photoelectric conversion element connected between the first control line and the other end of the first capacitor;
The photoelectric conversion element is
An anode connected to the first control line;
A cathode that is supplied with a higher potential than the anode and connected to the other end of the first capacitor;
A first transistor including a first electrode connected to the other end of the first capacitor, a second electrode, and a control electrode to which a second control voltage that is a DC voltage is supplied;
A second capacitor including one end to which a second fixed potential is supplied and the other end to which the second electrode of the first transistor is connected;
A second transistor including a first electrode connected to the other end of the second capacitor, a second electrode connected to a third fixed potential, and a control electrode supplied with a second control voltage;
A third electrode including a control electrode connected to the other end of the second capacitor, a first electrode supplied with a power supply voltage, and a second electrode;
A fourth transistor including a first electrode connected to the second electrode of the third transistor, a control electrode to which a third control voltage is supplied, and a second electrode;
A signal output line connected to the second electrode of the fourth transistor;
A photoelectric conversion device in which the voltage value a of the first control voltage, the voltage value b of the second control voltage, the threshold voltage c of the first transistor, and the voltage value d of the third fixed potential satisfy dc ≦ b ≦ ac . The photoelectric conversion device according to claim 4, wherein the first, second, third, and fourth transistors are NMOSFETs. A second control line to which a fourth control voltage that is a DC voltage is supplied;
A diode element;
The diode element is
A cathode connected to the cathode of the photoelectric conversion element;
The photoelectric conversion device according to claim 5, further comprising an anode connected to the second control line.   4. The photoelectric conversion device according to claim 3, wherein the first control voltage supplied to the first control line is set to be larger than the fourth control voltage supplied to the second control line.   The photoelectric conversion device according to claim 6, wherein the first control voltage supplied to the first control line is set smaller than the fourth control voltage supplied to the second control line.   The magnitude of the DC voltage supplied to the first control line and the second control line is set so that the potential applied to the cathode of the diode element is lower than the potential applied to the anode. Photoelectric conversion device. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion element is silicon-based. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion element is non-silicon-based. The photoelectric conversion device according to claim 11, wherein the photoelectric conversion element is a non-silicon system made of copper, indium, gallium, and selenium.   The photoelectric conversion device according to claim 3, wherein the diode element is formed on the same chip as the photoelectric conversion element.   The photoelectric conversion device according to claim 13, wherein the diode element uses a transistor having the same conductivity type as the first transistor.   The photoelectric conversion device according to claim 14, wherein the diode element has the same size as the first transistor.   The photoelectric conversion device according to claim 1, wherein at least one of the first capacitor and the second capacitor is formed by a diffusion capacitance of a first transistor.   The photoelectric conversion element is
An aluminum light-shielding film partially having an opening region;
A common electrode layer having an N-type zinc oxide layer and an intrinsic zinc oxide layer;
A cadmium sulfide layer;
A CIGS layer;
A metal electrode layer;
An insulating layer;
Including a via layer,
The photoelectric conversion device according to claim 16, wherein the metal electrode layer is connected to the second control line via the via layer, and the common electrode layer is connected to the first control line. 5. The first capacitor is a parasitic capacitance of the photoelectric conversion element or the first transistor, and the second capacitor is a parasitic capacitance of the first transistor, the second transistor, and the third transistor. The photoelectric conversion device described in 1.