JP2010040981A - Photoelectric conversion device and electronic apparatus including same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photoelectric conversion device improved in resolution of illuminance in a low-illuminance region. <P>SOLUTION: This photoelectric conversion device includes: a first photoelectric conversion element or a second photoelectric conversion element having a spectral sensitivity characteristic different from that of the first photoelectric conversion element; a first or a second AD conversion circuit outputting a first or second digital signal; and a subtraction circuit for calculating the difference between the first and second digital signals. Each of the first and second AD conversion circuits includes: a capacitative element supplied with first potential through a first switch and carrying out discharge through a second switch; a comparator comparing the potential of one-side electrode of the capacitative element with second potential; a clock generation circuit for outputting a clock signal; counting and outputting a clock signal; and a latch circuit latching a count value in response to the signal of the comparator. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a photoelectric conversion device. Further, the present invention relates to an electronic device including the photoelectric conversion device. In particular, the present invention relates to a photoelectric conversion device that outputs a digital signal and an electronic apparatus including the photoelectric conversion device.

  Many photoelectric conversion devices used for detecting light are known. For example, a visible light sensor or the like has been put into practical use. A large number of photoelectric conversion devices are used in devices that require illuminance adjustment, on / off control, and the like according to the living environment of a human being.

  Some display devices detect brightness around the display device and adjust the display brightness. This is because the photoelectric conversion device detects ambient brightness and obtains appropriate display luminance, thereby improving visibility and reducing wasteful power of the display device. For example, a display device including a light sensor for adjusting luminance includes a mobile phone and a computer with a display unit.

The photoelectric conversion device uses a photoelectric conversion element such as a photodiode as a light sensing portion, and can detect illuminance based on the amount of current flowing through the photoelectric conversion element. Patent Document 1 discloses a charge accumulation type photosensor that changes by discharging a charge accumulated in a capacitor (capacitance element) by a constant current circuit (constant current source) by a current flowing from a photodiode according to an incident light amount. A configuration is described in which a potential is detected by a comparator, and a time required to change the potential detected by the comparator is output as a digital signal by a counter circuit and a latch circuit. In Patent Document 2, a silicon substrate is used, and a difference in physical quantity corresponding to the spectral sensitivity characteristic between the first photodiode and the second photodiode on the silicon substrate is taken, thereby obtaining a spectral sensitivity characteristic close to visual sensitivity. Is described.
JP-A-6-313840 JP 2006-332226 A

In the photoelectric conversion device of Patent Document 1, when the current flowing from the photodiode is small in accordance with the amount of incident light, there is a problem in that it is difficult to detect the illuminance because the capacitor element cannot accumulate charges enough to detect the amount of incident light. is there. In the photoelectric conversion device of Patent Document 2, although spectral sensitivity characteristics close to visual sensitivity can be obtained, when the current flowing from the photodiode is small according to the amount of incident light, the first photodiode and the second photodiode are spectrally separated. There is a problem that it becomes difficult to detect the illuminance because a difference in physical quantity according to the sensitivity characteristic cannot be obtained.

Further, with the progress of display device technology, the luminance of a backlight is improved in a liquid crystal display device, and the luminance of an EL element is improved in a display device including an electroluminescence element (EL element). Although improvement in luminance is important for achieving high image quality, an increase in power consumption becomes a problem. For the problem of increased power consumption, it is effective to reduce the luminance of the display device in a dark place such as a room to such an extent that visibility is not reduced. For this reason, a photoelectric conversion device that detects the brightness around the display device is required to detect with increased resolution, particularly in a low illuminance region.

The resolution means the measurement resolution in the unit illuminance section.

An object of the present invention is to provide a photoelectric conversion device that can obtain spectral sensitivity characteristics close to visual sensitivity and improve the resolution of illuminance in a low illuminance region.

According to one aspect of the present invention, a first photoelectric conversion element, a first amplifier circuit for flowing a first current obtained by amplifying the photocurrent of the first photoelectric conversion element, and the first photoelectric conversion element A second photoelectric conversion element having different spectral sensitivity characteristics, a second amplification circuit for flowing a second current obtained by amplifying the photocurrent of the second photoelectric conversion element, and the first amplification circuit A first AD converter circuit that outputs a first digital signal when the first current flows, and a second digital signal that flows when the second current flows toward the second amplifier circuit. A second AD converter circuit for outputting, and a subtractor circuit for outputting a difference between the first digital signal and the second digital signal, wherein the first AD converter circuit and the second AD converter circuit The AD converter circuit is supplied with the first potential via the first switch, and the second switch. Generating a clock signal, a capacitor that discharges in accordance with the first current and the second current through the H, a comparator that compares the potential of one electrode of the capacitor with the second potential, and A clock generation circuit for outputting, a counter circuit for counting up a count value by the clock signal, and outputting the count value, and a latch for latching and outputting the count value in accordance with a signal output from the comparator A photoelectric conversion device having a circuit.

According to another aspect of the present invention, there is provided a first photoelectric conversion element, a first amplifier circuit for flowing a first current obtained by amplifying an output current of the first photoelectric conversion element, a first photoelectric conversion element, Includes a second photoelectric conversion element having different spectral sensitivity characteristics, a second amplification circuit for flowing a second current obtained by amplifying the output current of the second photoelectric conversion element, the first current, and the A subtraction circuit for outputting a difference from the second current as a voltage value; a voltage-current conversion circuit for flowing a third current corresponding to the voltage value; and the third circuit toward the voltage-current conversion circuit. An AD converter circuit that outputs a digital signal when the current flows through the AD converter circuit. The AD converter circuit is supplied with a first potential through a first switch, and the AD converter circuit through a second switch. A capacitive element that discharges according to the first current and the second current; A comparator that compares the potential of one electrode of the capacitive element with a second potential, a clock generation circuit that generates and outputs a clock signal, and a counter that counts up the count value by the clock signal and outputs the count value The photoelectric conversion device includes a circuit and a latch circuit that latches and outputs the count value in accordance with a signal output from the comparator.

According to another aspect of the present invention, there is provided a first photoelectric conversion element, a first amplifier circuit for flowing a first current obtained by amplifying an output current of the first photoelectric conversion element, and the first photoelectric conversion element. A second photoelectric conversion element having a spectral sensitivity characteristic different from the second photoelectric conversion element, a second amplification circuit for flowing a second current obtained by amplifying the output current of the second photoelectric conversion element, and the second current A current mirror circuit for obtaining a third current corresponding to a difference between the first current and the second current so that the first current flows toward the first amplifier circuit. And an AD converter circuit for outputting a digital signal when the third current flows toward the first amplifier circuit, and the AD converter circuit is connected via the first switch. A first potential is supplied, and the first current and the first potential are supplied via a second switch. A capacitor that discharges in accordance with the current of the capacitor, a comparator that compares the potential of one electrode of the capacitor with a second potential, a clock generation circuit that generates and outputs a clock signal, and the clock signal The photoelectric conversion device includes a counter circuit that counts up a count value and outputs the count value, and a latch circuit that latches and outputs the count value according to a signal output from the comparator.

With the photoelectric conversion device of the present invention, it is possible to provide a photoelectric conversion device that can obtain spectral sensitivity characteristics close to visual sensitivity and improve the resolution of illuminance in a low illuminance region.

Embodiments of the present invention will be described below with reference to the drawings. However, the present invention can be implemented in many different modes, and those skilled in the art can easily understand that the modes and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention is not construed as being limited to the description of this embodiment mode. Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

(Embodiment 1)
In this embodiment, a structure and operation of a photoelectric conversion device of the present invention will be described. Note that the photoelectric conversion device described in this embodiment is a circuit that converts an analog signal related to illuminance (hereinafter referred to as an analog signal) obtained by a photoelectric conversion element into a digital signal (hereinafter referred to as a digital signal) and outputs the digital signal. (Hereinafter referred to as analog-digital conversion circuit: AD conversion circuit).

First, a circuit diagram of the photoelectric conversion device of the present invention will be described. A photoelectric conversion device 100 illustrated in FIG. 1 includes a first photoelectric conversion element 101, a first amplifier circuit 102, a first AD conversion circuit 103, a second photoelectric conversion element 104, a second amplifier circuit 105, and a second amplifier circuit. AD conversion circuit 106 and subtraction circuit 107. In the first photoelectric conversion element 101, one terminal (cathode side) is supplied with a high power supply potential (Vdd), and the other terminal (anode side) is electrically connected to the first amplifier circuit 102. The first amplifying circuit 102 is a circuit for flowing toward the first current Ia obtained by amplifying the photocurrent I _L output from the first photoelectric conversion element 101 to the low power supply potential (Vss). The first amplifier circuit 102 is supplied with the low power supply potential Vss. The first AD conversion circuit 103 is a circuit that outputs the first digital signal Sout1 in accordance with the first current Ia flowing toward the first amplifier circuit 102. In the second photoelectric conversion element 104, a high power supply potential Vdd is supplied to one terminal, and the other terminal is electrically connected to the second amplifier circuit 105. The second amplifier circuit 105 is a circuit for flowing toward the second current Ib obtained by amplifying the photoelectric current I _P output from the second photoelectric conversion element 104 to the low power supply potential Vss. The second amplifier circuit 105 is supplied with the low power supply potential Vss. The second AD conversion circuit 106 is a circuit that outputs the second digital signal Sout2 in accordance with the second current Ib flowing toward the second amplifier circuit 105. The subtraction circuit 107 calculates a difference between the first digital signal Sout1 output from the first AD conversion circuit 103 and the second digital signal Sout2 output from the second AD conversion circuit 106, and performs digital processing. It is a circuit for outputting as a signal Sout. Further, an arrow 108 in FIG. 1 represents external light incident on the first photoelectric conversion element 101 and the second photoelectric conversion element 104.

Note that the terms “first”, “second”, “third” to “N” (N is a natural number) used in this specification are given to avoid confusion of components and are not limited numerically. I will add that.

  Note that in this specification, A and B are connected to each other, including A and B being directly connected, as well as those being electrically connected. Here, A and B are electrically connected when A and B have an object having some electrical action, and A and B are substantially identical through the object. It shall represent the case of becoming a node.

Specifically, A and B are connected via a switching element such as a transistor, and when A and B are approximately at the same potential due to conduction of the switching element, or A and B are connected via a resistance element. When B is connected and the circuit operation is considered, such as when the potential difference generated at both ends of the resistance element is such that it does not affect the operation of the circuit including A and B, A and B are the same. This represents a case where it can be regarded as a node.

The spectral sensitivity characteristic of the first photoelectric conversion element 101 is assumed to be wider than the wavelength region of the spectral sensitivity characteristic of the second photoelectric conversion element 104. As an example, the first photoelectric conversion element 101 is an element having a spectral sensitivity shifted from the wavelength region of visible light, such as a photoelectric conversion element manufactured using a single crystal silicon substrate or polycrystalline silicon. In this specification, description will be made assuming that the first photoelectric conversion element is formed using a single crystal silicon substrate. A photoelectric conversion element formed using a single crystal silicon substrate has a high quantum efficiency in the vicinity of 900 nm that is an infrared region, unlike a wavelength region of 360 to 830 nm that is a wavelength region of visible light. Therefore, the spectral sensitivity of the external light of the first photoelectric conversion element 101 can be obtained in a wide range from the visible light region to the infrared region. And so that the photocurrent I _L corresponding to the spectral sensitivity of the single crystal silicon flows.

Further, the second photoelectric conversion element 104 has spectral sensitivity characteristics different from those of the first photoelectric conversion element 101. As an example, the second photoelectric conversion element 104 is made monolithically with the first photoelectric conversion element 101, and here, it is assumed that the second photoelectric conversion element 104 is made using a single crystal silicon substrate. Then, by setting the external light incident on the second photoelectric conversion element as light in the infrared region excluding visible light, a spectral sensitivity characteristic different from that of the first photoelectric conversion element 101 is obtained. To do. Therefore, the spectral sensitivity of the second photoelectric conversion element 104 becomes the one corresponding to the intensity of light in the infrared region, in the second photoelectric conversion element 104, the photoelectric current I _P corresponding to the spectral sensitivity of the infrared light It will flow.

Note that in this embodiment, as an example, in order to obtain a spectral sensitivity characteristic different from that of the first photoelectric conversion element 101 in the second photoelectric conversion element 104, red light is incident on the light incident side as illustrated in FIG. A filter that transmits light in the outer region (hereinafter referred to as infrared light transmitting filter 109) is provided. This is because, by calculating the difference from the digital signals obtained from the first photoelectric conversion element 101 and the second photoelectric conversion element 104, as disclosed in Patent Document 2, the infrared light has the intensity of visible light. This is due to the selection of a filter that passes through. In the present embodiment, a desired value is obtained by calculating a difference between a physical quantity corresponding to the spectral sensitivity characteristic obtained from the first photoelectric conversion element 101 and a physical quantity obtained from the spectral sensitivity characteristic obtained from the second photoelectric conversion element 104. The description will be made on the assumption that a physical quantity corresponding to the spectral sensitivity is obtained. Note that the presence or absence of the optical filter is not limited as long as the digital signal Sout can obtain the illuminance that is the intensity of visible light by calculating the difference.

Note that a PIN photodiode may be applied to the first photoelectric conversion element 101 and the second photoelectric conversion element 104. Further, as the first photoelectric conversion element 101 and the second photoelectric conversion element 104, a PN photodiode may be used instead of the PIN photodiode. The first photoelectric conversion element 101 and the second photoelectric conversion element 104 are preferably configured to be irradiated with light having the same intensity from the outside through openings having the same size. Because the same intensity of light is received by both the first photoelectric conversion element 101 and the second photoelectric conversion element 104 and the difference between the electrical signals is calculated, the illuminance can be accurately calculated. is there. Note that when the first photoelectric conversion element 101 and the second photoelectric conversion element 104 are formed to have different sizes, the light receiving state can be made approximately the same by providing a light shielding portion, which is preferable. is there.

The first amplifying circuit 102 is a circuit for generating a first current Ia obtained by amplifying the photocurrent I _L output from the first photoelectric conversion element 101. The second amplifying circuit 105 is a circuit for generating a second current Ib obtained by amplifying the photoelectric current I _P which is output from the second photoelectric conversion element 104. FIG. 2A illustrates an example of an amplifier circuit 200 applied to the first amplifier circuit 102 and the second amplifier circuit 105. As shown in FIG. 2A, the amplifier circuit 200 is formed of a current mirror circuit, and includes a first n-channel transistor 201 and a second n-channel transistor 202. The first terminal of the first n-channel transistor 201 is electrically connected to the anode of the first photoelectric conversion element 101. The gate terminals of the first n-channel transistor 201 and the second n-channel transistor 202 are electrically connected to each other, and the first terminal of the first n-channel transistor 201 is the first n-channel transistor. 201 and the gate terminal of the second n-channel transistor 202 are electrically connected. A low power supply potential Vss is supplied to the second terminals of the first n-channel transistor 201 and the second n-channel transistor 202.

In addition, the current mirror circuit applied to the first amplifier circuit 102 and the second amplifier circuit 105 includes the second n-channel transistor 202 illustrated in FIG. 2A as illustrated in FIG. It is good also as a structure arrange | positioned in parallel electrically in parallel. As shown in FIG. 2B, a plurality of second n-channel transistors 202-1 to 202-N (N is a natural number of 2 or more) are provided as the amplifier circuit 250, whereby the first current Ia and the second current Current Ib can be increased N times to flow on the second n-channel transistors 202-1 to 202-N side. Therefore, a sufficient current can flow even when the amount of light incident on the first photoelectric conversion element 101 and the second photoelectric conversion element 104 is small. A sufficient current can also be passed by increasing the channel width of the second n-channel transistor 201 or decreasing the channel length.

In addition, the first amplifier circuit 102 and the second amplifier circuit 105 illustrated in FIG. 1 may be configured to switch the amplification factor with respect to the input current (the photocurrent _IL and the photocurrent _Ip ) in accordance with the illuminance. Figure 3 shows the configuration of switching the amplification factor of the photocurrent I _L and the photocurrent I _P in accordance with the illuminance. In Figure 3, as an example, a circuit for amplifying the photocurrent _{I P} from the light current _{I L} and the second photoelectric conversion element 104 from the first photoelectric conversion element 101, FIG. 2 (A), (B) and an amplifier circuit 200 and the amplifier circuit 250 shown in, a switching circuit 300A and 300B switch the circuit for amplifying the photocurrent _{I L} and the photocurrent _{I P} by the selection signal select. The switching circuit 300A includes first switches 301A and 301B, and the switching circuit 300B includes second switches 302A and 302B. The selection signal Select selects the first AD conversion circuit 103 and the second AD conversion circuit 106. Switch the electrically connected amplifier circuit. Incidentally, arranged amplifier circuit in which a plurality of different amplification factors to obtain a photocurrent corresponding to the illuminance by the gain for the input current configured to switch in accordance with the illuminance by switching circuits 300A and 300B I _L and the photocurrent I The amplification factor of _P can be optimized.

  Note that a transistor such as an n-channel transistor or a p-channel transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region. Current can flow through the drain region, the channel region, and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it may be difficult to limit which is the source or the drain. Therefore, in this embodiment, the regions functioning as the source and the drain are referred to as a first terminal and a second terminal, respectively. A terminal functioning as a gate is expressed as a gate terminal.

Note that various types of transistors can be used as a transistor such as an n-channel transistor or a p-channel transistor. For example, a transistor manufactured using single crystal silicon formed over the same substrate as the photoelectric conversion element can be used. Alternatively, a transistor including a non-single-crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also referred to as semi-amorphous) silicon, or the like which is formed separately can be used. Further, as a semiconductor used for the channel formation region, a compound semiconductor, more preferably an oxide semiconductor may be used. Examples of the oxide semiconductor include zinc oxide (ZnO), titanium oxide (TiO ₂ ), magnesium zinc oxide (Mg _(x) Zn _(1-x) O), and cadmium zinc oxide (Cd _x Zn _{(1-x) 2} O _). ), Cadmium oxide (CdO), In—Ga—Zn—O-based amorphous oxide semiconductor (a-IGZO), or the like may be used. Since the oxide semiconductor is transparent, the oxide semiconductor can be provided so as to overlap with the photoelectric conversion element, and the photoelectric conversion device can be downsized.

Next, an apparatus that embodies the photoelectric conversion apparatus 100 illustrated in FIG. 1 will be described with reference to FIG. A photoelectric conversion device 100 illustrated in FIG. 4 has a specific circuit configuration with respect to the first amplifier circuit 102, the second amplifier circuit 105, the first AD converter circuit 103, and the second AD converter circuit 106 illustrated in FIG. Shows about. The first amplifier circuit 102 and the second amplifier circuit 105 are formed of a current mirror circuit as shown in FIG. The first AD conversion circuit 103 includes a first switch 401A, a second switch 402A, a capacitor 403A, a comparator 404A, a latch circuit 405A, a counter circuit 406A, and a clock generation circuit 407A. The second AD conversion circuit 106 includes a first switch 401B, a second switch 402B, a capacitor 403B, a comparator 404B (also referred to as a comparison circuit), a latch circuit 405B, a counter circuit 406B, and a clock generation circuit 407B.

In the first AD converter circuit 103, one terminal of the first switch 401A is supplied with a first potential (also referred to as a charge potential or Vset), the second terminal is one electrode of the capacitor 403A, 2 is electrically connected to one terminal of the switch 402A and the non-inverting input terminal of the comparator 404A. A low power supply potential Vss is supplied to the other electrode of the capacitor 403A. The second terminal of the second switch 402A is electrically connected to the first terminal of the second n-channel transistor 202 of the first amplifier circuit 102. A second potential (also referred to as a reference potential or Vref) is supplied to the inverting input terminal of the comparator 404A. The clock generation circuit 407A supplies a clock signal to the counter circuit 406A. The counter circuit 406A counts the wave number of the clock signal and supplies the obtained count value to the latch circuit 405A. The latch circuit 405A latches (holds) the count value acquired from the counter circuit 406A in accordance with the signal from the comparator 404A, and outputs it as the digital signal Sout1 from the first AD conversion circuit 103.

In the second AD conversion circuit 106, the first potential is supplied to one terminal of the first switch 401B, the second terminal is one electrode of the capacitor 403B, and the one terminal of the second switch 402B. , And the non-inverting input terminal of the comparator 404B. The low power supply potential Vss is supplied to the other electrode of the capacitor 403B. The second terminal of the second switch 402B is electrically connected to the first terminal of the second n-channel transistor 202 of the first amplifier circuit 102. A second potential is supplied to the inverting input terminal of the comparator 404B. The clock generation circuit 407B supplies a clock signal to the counter circuit 406B. The counter circuit 406B counts the wave number of the clock signal and supplies the obtained count value to the latch circuit 405B. The latch circuit 405B latches the count value acquired from the counter circuit 406B according to the signal from the comparator 404B, and outputs it as the digital signal Sout2 from the second AD conversion circuit 106.

  Note that in this specification, the switch is not limited to a specific one as long as it can control conduction or non-conduction between one terminal and the other terminal. Examples of the switch include an electrical switch and a mechanical switch. For example, a field effect transistor may be used.

In FIG. 4, it is preferable to use a p-channel transistor as the first switch 401A and an analog switch as the second switch 402A. Since the first switch 401A is electrically connected to the first potential Vset, which is a fixed potential, a p-channel transistor is preferably used. The second switch 402A preferably uses an analog switch in order to surely control on or off because both terminal potentials fluctuate. Further, it is preferable that the first switch 401A and the second switch 402A be alternately turned on or off. As a result, the first switch 401A and the second switch 402A can be operated by a single signal from a control circuit outside the photoelectric conversion device 100, so that manufacturing costs can be reduced.

Note that the capacitor 403A is charged with the first potential Vset when the first switch 401A is turned on, and then the second switch 402A is turned on according to the current flowing through the first amplifier circuit 102. It is what discharges. Therefore, in consideration of the time when charge is discharged to the second n-channel transistor 202 of the first amplifier circuit 102, the capacitance of the capacitor 403A should include a capacitor that can charge the charge. desirable. The first potential Vset is preferably set to a value lower than the high power supply potential Vdd and greater than the low power supply potential Vss. Note that in the case where the first potential Vset is set to the same value as the high power supply potential Vdd, the high power supply potential Vdd is preferably a fixed potential.

The second potential Vref supplied to the inverting input terminal of the comparator 404A is charged by the first potential Vset when the first switch 401A is turned on, and then discharged by the first amplifier circuit 102. This is a potential for obtaining the output signal of the comparator from the output terminal by comparing with the potential of one electrode of the capacitive element 403A. The second potential Vref is preferably set to a value smaller than the first potential Vset and larger than the low potential power supply Vss. As an output signal of the comparator, an H level signal or an L level signal is output.

Note that the latch circuit 405A is a circuit for latching the count value acquired from the counter circuit 406A in accordance with the output signal of the comparator 404A. The count value held by the latch circuit 405A is output to the subtraction circuit 107 as the digital signal Sout1 from the first AD conversion circuit 103. The output digital signal Sout is output from the latch circuit 405A to the subtraction circuit 107 through a bus line corresponding to the number of bits.

The counter circuit 406A is a circuit for counting the wave number of the clock signal output from the clock generation circuit 407A. The count value obtained by the counter circuit 406A is supplied to the latch circuit 405A.

The clock generation circuit 407A is a circuit for outputting a clock signal for counting by the counter circuit 406A to the counter circuit 406A. As an example of the clock generation circuit, a solid oscillator oscillation circuit, a CR oscillation circuit, a ring oscillator, or the like may be used.

Note that for the first switch 401B, the second switch 402B, the capacitor 403B, the comparator 404B, the clock generation circuit 407B, the counter circuit 406B, and the latch circuit 405B in the second AD conversion circuit 106, the first AD conversion circuit The configuration is the same as that described in 103, and the description thereof is omitted.

Note that the first AD conversion circuit 103 and the second AD conversion circuit 106 have a plurality of high power supply potential Vdd, low power supply potential Vss, first potential Vset, second potential Vref, and the like separately from the above-described structure. A constant voltage circuit for generating a potential of In addition, the first AD converter circuit 103 and the second AD converter circuit 106 switch on or off the first switches 401A and 401B and the second switches 402A and 402B separately from the above-described configuration, and are latch circuits. A control circuit for resetting 405A and 405B and counter circuits 406A and 406B is provided.

The subtraction circuit 107 is a circuit for calculating a difference between the digital signal Sout1 and the digital signal Sout2. Specifically, a difference circuit may be calculated by providing a logic circuit for each bus line corresponding to each bit. The digital value signal obtained by taking the difference between the digital signal Sout1 and the digital signal Sout2 is a value obtained by subtracting the spectral sensitivity characteristic of the infrared light from the spectral sensitivity characteristic of the single crystal silicon, and this digital value signal is the visual sensitivity. Is output as a digital signal Sout corresponding to the spectral sensitivity in the visible light region close to, and an illuminance output can be obtained.

Next, specific operations of the first AD conversion circuit 103 and the second AD conversion circuit 106 in the photoelectric conversion device 100 illustrated in FIG. 4 will be described with reference to FIGS. 5, 6A, and 6B. Will be described. Note that FIG. 5, FIG. 6A, and FIG. 6B illustrate the operation of the first AD converter circuit 103 as an example. FIG. 5 shows the potential Vcap of one electrode of the capacitor 403A when the first switch 401A and the second switch 402A are turned on or off, the potential Vcomp of the output signal of the comparator 404A, the clock signal, and It is shown about the timing chart about a count value. For Vcap and Vcomp, the intensity of illuminance when the first photoelectric conversion element 101 is irradiated with light is divided into three levels: L _Illu (large), M _Illu (medium), and S _Illu (small). I will explain. Further, as shown in FIG. 5, the operation of the first AD conversion circuit 103 is different in the three periods A, B, and C.

First, an operation of the first AD converter circuit 103 in the period A in which the first switch 401A is in the off state and the second switch 402A is in the on state illustrated in FIG. 5 will be described. Potential Vcap of one electrode of the capacitor 403A in the period A will continue to vary depending on the magnitude of the first current Ia obtained by amplifying the photocurrent I _L, the indeterminate state of the potential. Further, in the period A, the potential Vcomp of the output signal of the comparator 404A continues to fluctuate according to the potential of Vcap, and the potential is not determined. Note that the clock signal is output from the clock generation circuit 407A to the counter circuit 406A in period A. Therefore, although the count value is counted up in the counter circuit 406A, the count value is not held in the latch circuit 405A in the period A.

Next, a period B in which the first switch 401A is on and the second switch 402A is off is described. In period B, the potential Vcap of one electrode of the capacitor 403A is to be a first potential Vset regardless of the magnitude of the first current Ia obtained by amplifying the photocurrent _{I L.} In the period B, the potential Vcomp of the output signal of the comparator 404A is an H level signal because the first potential Vset exceeds the second potential Vref regardless of the illuminance.

FIG. 6A schematically illustrates on / off of each switch and the flow of charge in the period B. The capacitor 403A is supplied with the first potential Vset when the first switch 401A is turned on. Further, since the second switch 402A is off, there is no charge transfer from the capacitor 403A to the first amplifier circuit 102.

Next, a period C in which the first switch 401A is in an off state and the second switch 402A is in an on state will be described. First, in period C, when the illuminance to the first photoelectric conversion element 101 is large (L _{Illu in} FIG. 5), the first current Ia flowing toward the first amplifier circuit 102 increases, and one of the capacitors 403A The potential Vcap of the electrode decreases. Therefore, the time _{t 0} (time _{t 0} <time _{t 1} <Time _{t 2} <time _{t 3)} potential Vref becomes at the time _{t 1} the potential Vcap of the capacitor 403A with was Vset, from then capacitive element 403A When the discharge is completed, the potential becomes Vss. At this time, the potential Vcomp of the output signal of the comparator 404A outputs an L level signal when the potential Vcap of the capacitor 403A changes from the first potential Vset to the second potential Vref. Then, the latch circuit 405A holds the input count value with the signal. Note the same time the time _{t 0} to be the period C, the counter circuit 406A and the latch circuit 405A is reset, the count-up is performed based on the clock signal in the counter circuit 406A. Then, the fact that the count value _{t1 count} based on the clock signal of the period between the time _{t 0} of time _{t 1} by the potential Vout of the output signal of the comparator 404A to time _{t 1} is input to the latch circuit 405A is obtained Become.

Further, in the period C in which the first switch 401A is off and the second switch 402A is on, the illuminance to the first photoelectric conversion element 101 is medium (M _{Illu in} FIG. 5). Since the first current Ia flowing toward the first amplifier circuit 102 is small as compared with the case where the first current Ia is large, the potential Vcap of one electrode of the capacitor 403A decreases although the rate of decrease is small. Therefore, the potential Vss by potential Vref becomes the time _{t 2} the potential Vcap was Vset of the capacitor 403A at time _{t 0,} the discharge from the subsequent capacitive element 403A completed. At this time, the potential Vcomp of the output signal of the comparator 404A outputs an L level signal when the potential Vcap of the capacitor 403A changes from the first potential Vset to the second potential Vref. Then, the latch circuit 405A holds the input count value with the signal. Note the same time the time _{t 0} to be the period C, the counter circuit 406A and the latch circuit 405A is reset, the count-up is performed based on the clock signal in the counter circuit 406A. Then, the fact that the count value _{t2 count} based on the clock signal of the period between the time _{t 0} of time _{t 2} by the potential Vcomp of the output signal of the comparator 404A to the time _{t 2} is input to the latch circuit 405A is obtained Become.

In the period C in which the first switch 401A is in the off state and the second switch 402A is in the on state, and the illuminance to the first photoelectric conversion element 101 is small (S _{Illu in} FIG. 5), Although the first current Ia flowing toward one amplifier circuit 102 is also small and the rate of decrease is small, the potential Vcap of one electrode of the capacitor 403A decreases. Therefore, the potential Vss by potential Vref becomes at the time _{t 3} the potential Vcap of the capacitor 403A at time _{t 0} was Vset, the discharge from the subsequent capacitive element 403A completed. At this time, the potential Vcomp of the output signal of the comparator 404A outputs an L level signal when the potential Vcap of the capacitor 403A changes from the first potential Vset to the second potential Vref. Then, the latch circuit 405A holds the input count value with the signal. Note the same time the time _{t 0} to be the period C, the counter circuit 406A and the latch circuit 405A is reset, the count-up is performed based on the clock signal in the counter circuit 406A. Then, the fact that the count value _{t3 count} based on the clock signal of the period between the time _{t 0} of time _{t 3} by the potential Vcomp of the output signal of the comparator 404A to time _{t 3} is input to the latch circuit 405A is obtained Become.

FIG. 6B schematically illustrates on / off of each switch and charge flow in the period C. The capacitor 403A is not supplied with the first potential Vset anew when the first switch 401A is turned off. On the other hand, since the second switch 402A is on, the first current Ia flows from the capacitor 403A to the first amplifier circuit 102, and the capacitor 403A is discharged. The first current Ia flowing through the first amplifier circuit 102, by forming a current mirror circuit such that the first amplifier circuit 102 has been described in FIG. 2 (A), the photocurrent I _L Proportional size.

The first switch 401A is off, the second switch 402A is a period C in the state of ON, if the first is not irradiated light to the photoelectric conversion element 101 photocurrent I _L does not flow The potential Vcap of one electrode of the capacitor 403A hardly decreases because the first current Ia flowing through the first amplifier circuit 102 does not occur. Therefore, the potential Vcap of the capacitor 403A at time _{t 0} is but a Vset, no change in the potential Vref over time. At this time, the potential Vcomp of the output signal of the comparator 404A continues to output an H level signal because the potential Vcap of the capacitor 403A does not change from the first potential Vset to the second potential Vref. The clock signal, from the time t ₀ became period C, the output to the counter circuit 406A is carried out. Therefore, the count value corresponding to the illuminance cannot be obtained as described above, and the count value reaches the maximum value of the counter circuit 406A. In this case, it is preferable to output the maximum count value to the latch circuit.

FIG. 7 is a flowchart illustrating specific operations of the first AD conversion circuit 103 and the second AD conversion circuit 106 in the photoelectric conversion device 100 described with reference to FIGS. 5, 6 </ b> A, and 6 </ b> B. Will be described.

First, the photoelectric conversion device 100 starts charging (resetting) the charge to the capacitor 403A (step 701). As described above, the capacitor 403A is charged by turning on the first switch 401A and turning off the second switch 402A, so that the wiring to which the first potential Vset is supplied and the capacitor 403A are connected. This is done by electrical connection. In step 701, the capacitor 403A is charged and the clock signal is output from the clock generation circuit 407A.

Next, the photoelectric conversion device 100 resets the count value of the counter circuit 406A after charging the capacitor 403A with charge (step 702). In step 702, the count value held in the latch circuit 405A is initialized together with resetting the count value of the counter circuit 406A.

Next, the photoelectric conversion device 100 discharges the electric charge charged in the capacitor 403A by the first amplifier circuit 102 (step 703). As described above, electric charge is discharged from the capacitor 403A by turning off the first switch 401A and turning on the second switch 402A, thereby electrically connecting the capacitor 403A and the first amplifier circuit 102. It is done by letting Note that the discharge of the charge charged in the capacitor 403A may be started together with the reset of the counter circuit 406A performed in Step 702.

In step 703, the counter circuit 406A counts up the count value in response to the output of the clock signal from the clock generation circuit 407A (step 704).

Next, in step 704, it is determined whether or not the count value to be counted up has reached the maximum value (step 705). At step 705, if the count value has not reached the maximum value, it is determined whether or not the output signal Vcomp from the comparator 404A output to the latch circuit 405A is at the L level (step 706). At step 706, if the count value has not reached the maximum value and the output of the comparator 404A is not at the L level, the count value is incremented again at step 704. In step 705, when the count value to be counted up reaches the maximum value, and when the count value has not reached the maximum value and the output of the comparator 404A is at the L level, the latch circuit 405A latches the count value ( Step 707). By the above operation, the photoelectric conversion device 100 can output the digital signal Sout1 corresponding to the magnitude of the photocurrent I _L on the basis of the count value latched by the latch circuit 405A. The first AD conversion circuit 103 described above is, as the count value is smaller, the photocurrent I _L is large, it comes to as the light current I _L count value is large is small. When the count value is the maximum, light is not detected, so the light intensity is also “0”.

Digital In the description in FIGS. 5 to 7, the first AD converter 103 as an example, has been described, in the same manner for the second AD conversion circuit 106, in accordance with the magnitude of the photocurrent I _P The signal Sout2 can be output.

The digital signal Sout2 obtained from the second AD converter circuit is transmitted through the infrared light transmission filter 109 as shown in FIG. 17 to obtain a spectral sensitivity characteristic different from that of the first photoelectric conversion element 101. is irradiated in the photoelectric conversion element 104 is a signal corresponding to the photocurrent I _P obtained. On the other hand, in this embodiment mode, the digital signal Sout1 obtained from the first AD conversion circuit 103 is applied to the first photoelectric conversion element 101 made using a single crystal silicon substrate, and the photocurrent I _L obtained by irradiating the first photoelectric conversion element 101 is used. It is a signal according to. Therefore, unlike the wavelength region of visible light, it has high quantum efficiency in the vicinity of 900 nm that is the infrared region. Therefore, the digital signal Sout corresponding to the spectral sensitivity in the visible light region can be obtained by subtracting the digital signal Sout2 from the digital signal Sout1 by the subtraction circuit 107.

In the configuration of the present embodiment as described above, the photocurrent I _L, by taking the difference between the photocurrent I _P, it is possible to obtain an output of the illuminance as a digital value.

In addition, since the relationship between the light intensity and the photocurrent I _L is relatively linear, the digital signal Sout that changes according to the photocurrent I _L and the photocurrent I _P is output if the photocurrent I _L is small. The change in the digital signal Sout is moderated. Therefore, the digital signals Sout, if the photocurrent I _L is small, it is possible to increase the interval of values corresponding to the illuminance of the light irradiated to the photoelectric conversion element. In particular, the resolution can be improved in detecting the magnitude of light in a low illuminance region (for example, 1 lux (lx) or more and 1000 lux or less). FIG. 8 shows the relationship when the illuminance is on the horizontal axis and the digital value of the digital signal Sout is on the vertical axis. As shown in FIG. 8, the graph is a downward-sloping graph in which the digital value decreases as the illuminance increases.

In FIG. 8, the digital value of the digital signal Sout is a 16-bit (0 to 65535) digital value, and the illuminance corresponding to the digital value is, for example, 1 lux to 10,000 lux. ing.

In contrast to the graph in which the illuminance and the digital value of the digital signal Sout are lowered to the right, the so-called right-up graph in which the digital value increases as the illuminance increases, the digital value is saturated if the illuminance is too high. . In addition, when trying to increase the resolution of the low illuminance area in the graph rising to the right, it is necessary to take a corresponding digital value interval in the low illuminance area, so that the dynamic range of illuminance cannot be widened. On the other hand, in the configuration shown in this embodiment having a right-downward graph relationship, the digital value is saturated at low illuminance, so that the dynamic range can be widened even if the resolution in the low illuminance region is increased. Therefore, in the structure shown in this embodiment mode, it is possible to output a digital signal with a digital value corresponding to high illuminance with high resolution, particularly in a low illuminance region, and to realize a wide dynamic range.

As described above, the configuration of the photoelectric conversion device of this embodiment provides a photoelectric conversion device that can obtain spectral sensitivity characteristics close to visual sensitivity and improve the resolution of illuminance in a low illuminance region. Can do.

Note that the contents described in each drawing in this embodiment can be freely combined with or replaced with the contents described in any of the other embodiments as appropriate.

(Embodiment 2)
In this embodiment, a structure different from the above embodiment will be described.

First, a circuit diagram of the photoelectric conversion device of the present invention will be described. A photoelectric conversion device 900 illustrated in FIG. 9 includes a first photoelectric conversion element 101, a first amplification circuit 102, a second photoelectric conversion element 104, a second amplification circuit 105, a subtraction circuit 901, a voltage-current conversion circuit 902, And an AD conversion circuit 903. In the first photoelectric conversion element 101, one terminal (cathode side) is supplied with a high power supply potential (Vdd), and the other terminal (anode side) is electrically connected to the first amplifier circuit 102. The first amplifying circuit 102 is a circuit for flowing toward the first current Ia obtained by amplifying the photocurrent I _L output from the first photoelectric conversion element 101 to the low power supply potential (Vss). The first amplifier circuit 102 is supplied with the low power supply potential Vss. In the second photoelectric conversion element 104, a high power supply potential Vdd is supplied to one terminal, and the other terminal is electrically connected to the second amplifier circuit 105. The second amplifier circuit 105 is a circuit for flowing toward the second current Ib obtained by amplifying the photoelectric current I _P output from the second photoelectric conversion element 104 to the low power supply potential Vss. The second amplifier circuit 105 is supplied with the low power supply potential Vss. The subtracting circuit 901 is a circuit for calculating the difference between the first current Ia and the second current Ib and outputting it as a voltage Vsub. The voltage-current conversion circuit 902 is a circuit for causing the third current Isub corresponding to the voltage Vsub to flow toward the voltage-current conversion circuit 902. The AD conversion circuit 903 is a circuit that outputs a digital signal Sout according to the third current Isub that flows through the voltage-current conversion circuit 902. Further, an arrow 108 in FIG. 9 represents external light incident on the first photoelectric conversion element 101 and the second photoelectric conversion element 104.

Note that in this embodiment, as an example, in order to obtain a spectral sensitivity characteristic different from that of the first photoelectric conversion element 101 in the second photoelectric conversion element 104 having the configuration illustrated in FIG. An infrared light transmission filter 109 is provided on the incident side. This is because, by calculating the difference from the digital signals obtained from the first photoelectric conversion element 101 and the second photoelectric conversion element 104, as disclosed in Patent Document 2, the infrared light has the intensity of visible light. This is due to the selection of a filter that passes through. In the present embodiment, a desired value is obtained by calculating a difference between a physical quantity corresponding to the spectral sensitivity characteristic obtained from the first photoelectric conversion element 101 and a physical quantity obtained from the spectral sensitivity characteristic obtained from the second photoelectric conversion element 104. The description will be made on the assumption that a physical quantity corresponding to the spectral sensitivity is obtained. Note that the presence or absence of the optical filter is not limited as long as the digital signal Sout can obtain the illuminance that is the intensity of visible light by calculating the difference.

Note that the subtraction circuit 901 is a circuit that takes a difference between the first current Ia and the second current Ib obtained by the first amplifier circuit 102 and the second amplifier circuit 105 and outputs the difference as a voltage value. In FIG. 9, the voltage Vsub is output, but any circuit that outputs the difference between the first current Ia and the second current Ib may be used. It may be by value. In order to calculate the difference by the operational amplifier when the difference is taken by the subtracting circuit, the first current Ia and the second current Ib are once converted into voltage values, then input to the operational amplifier, and the voltage Vsub is output. And it is sufficient. The difference between the first current Ia and the second current Ib is calculated by the subtraction circuit 901, so that the spectral sensitivity characteristic of infrared light is subtracted from the spectral sensitivity characteristic of single crystal silicon. The voltage Vsub corresponding to the spectral sensitivity in the visible light region close to is output. Therefore, the voltage Vsub is a signal corresponding to the illuminance of light irradiated on the photoelectric conversion device 900.

Note that the voltage-current conversion circuit 902 is a circuit for converting the voltage Vsub into the third current Isub and flowing the third current Isub from the AD conversion circuit 903 toward the voltage-current conversion circuit 902. As an example, a transistor may be used so that the voltage Vsub is applied to the gate of the transistor. Note that the third current Isub is also a signal corresponding to the illuminance of the photoelectric conversion device 900, similarly to the voltage Vsub.

Note that the AD conversion circuit 903 has the same structure as that of the first AD conversion circuit 103 and the second AD conversion circuit 106 described in Embodiment 1. The operation is also the same as that described for the first AD conversion circuit 103 and the second AD conversion circuit 106 described in Embodiment 1. Therefore, the photoelectric conversion device 900 can output the digital signal Sout corresponding to the illuminance.

As described above, the configuration of the photoelectric conversion device of this embodiment provides a photoelectric conversion device that can obtain spectral sensitivity characteristics close to visual sensitivity and improve the resolution of illuminance in a low illuminance region. Can do.

Note that the contents described in each drawing in this embodiment can be freely combined with or replaced with the contents described in any of the other embodiments as appropriate.

(Embodiment 3)
In this embodiment, a structure different from the above embodiment will be described.

First, a circuit diagram of the photoelectric conversion device of the present invention will be described. A photoelectric conversion device 1000 illustrated in FIG. 10 includes a first photoelectric conversion element 101, a first amplifier circuit 102, a second photoelectric conversion element 104, a second amplifier circuit 105, a current mirror circuit 1001, and an AD conversion circuit 903. Have In the first photoelectric conversion element 101, one terminal (cathode side) is supplied with a high power supply potential (Vdd), and the other terminal (anode side) is electrically connected to the first amplifier circuit 102. The first amplifying circuit 102 is a circuit for flowing toward the first current Ia by amplifying the photocurrent I _L output from the first photoelectric conversion element 101 to the low power supply potential (Vss). The first amplifier circuit 102 is supplied with the low power supply potential Vss. In the second photoelectric conversion element 104, a high power supply potential Vdd is supplied to one terminal, and the other terminal is electrically connected to the second amplifier circuit 105. The second amplifier circuit 105 is a circuit for flowing toward the second current Ib is amplified photocurrent I _P output from the second photoelectric conversion element 104 to the low power supply potential Vss. The second amplifier circuit 105 is supplied with the low power supply potential Vss. The current mirror circuit 1001 is a circuit for causing the second current Ib to flow through the wiring through which the first current Ia flows toward the first amplifier circuit 102. When the first current Ia and the second current Ib flow through a wiring electrically connected to the AD conversion circuit 903, the first amplifier circuit 102, and the current mirror circuit 1001, the first current Ia and The second current Ib is offset and a third current Isub is generated. The AD conversion circuit 903 is a circuit that outputs a digital signal Sout according to the third current Isub flowing from the AD conversion circuit 903. Further, an arrow 108 in FIG. 9 represents external light incident on the first photoelectric conversion element 101 and the second photoelectric conversion element 104.

Note that in this embodiment mode, as an example, in order to obtain a spectral sensitivity characteristic different from that of the first photoelectric conversion element 101 in the second photoelectric conversion element 104 having the configuration illustrated in FIG. An infrared light transmission filter 109 is provided on the incident side. This is because, by calculating the difference from the digital signals obtained from the first photoelectric conversion element 101 and the second photoelectric conversion element 104, as disclosed in Patent Document 2, the infrared light has the intensity of visible light. This is due to the selection of a filter that passes through. In the present embodiment, a desired value is obtained by calculating a difference between a physical quantity corresponding to the spectral sensitivity characteristic obtained from the first photoelectric conversion element 101 and a physical quantity obtained from the spectral sensitivity characteristic obtained from the second photoelectric conversion element 104. The description will be made on the assumption that a physical quantity corresponding to the spectral sensitivity is obtained. Note that the presence or absence of the optical filter is not limited as long as the digital signal Sout can obtain the illuminance that is the intensity of visible light by calculating the difference.

Note that the current mirror circuit 1001 is a circuit for flowing a current having the same magnitude as the second current Ib obtained by the second amplifier circuit 105. FIG. 11 shows a specific circuit configuration of the current mirror circuit. In FIG. 11, a current mirror circuit 1001 includes a first p-channel transistor 1101 and a second p-channel transistor 1102. The first terminal of the first p-channel transistor 1101 and the first terminal of the second p-channel transistor 1102 are electrically connected to the high power supply potential Vdd. The gate terminals of the first p-channel transistor 1101 and the second p-channel transistor 1101 are electrically connected to each other, and are electrically connected to the second terminal of the first p-channel transistor 1101. . The second terminal of the first p-channel transistor 1101 is electrically connected to the second amplifier circuit 105, and the second current Ib flows toward the second amplifier circuit 105. A second terminal of the second p-channel transistor 1102 is electrically connected to the first amplifier circuit 102 and the AD conversion circuit 903.

Magnitude of the second current Ib flowing from the first current Ia and the current mirror circuit that flows toward the first amplifying circuit depends on the magnitude of the photocurrent I _L and the photocurrent I _P. The photocurrent _IL is output in accordance with the light intensity based on the spectral sensitivity characteristic of the single crystal silicon. On the other hand, the photocurrent _IP is output according to the intensity of infrared light from which spectral sensitivity characteristics other than light below visible light are separated from the spectral sensitivity characteristics of single crystal silicon. Therefore, the first current Ia becomes larger than the second current Ib, and Isub having a magnitude of (Ia−Ib) flows from the AD conversion circuit 903. The Isub which is the difference between Ia and Ib flows from the AD conversion circuit 903, so that the spectral sensitivity characteristic of infrared light is subtracted from the spectral sensitivity characteristic of single crystal silicon, and in the visible light region close to the visual sensitivity. Illuminance can be obtained as the digital signal Sout corresponding to the spectral sensitivity.

Note that the AD conversion circuit 903 has the same configuration as that of the first AD conversion circuit 103 and the second AD conversion circuit 106 described in Embodiment 1, as shown in FIG. The operation is also the same as that described for the first AD conversion circuit 103 and the second AD conversion circuit 106 described in Embodiment 1. Therefore, the photoelectric conversion device 900 can output the digital signal Sout corresponding to the illuminance.

As described above, the configuration of the photoelectric conversion device of this embodiment provides a photoelectric conversion device that can obtain spectral sensitivity characteristics close to visual sensitivity and improve the resolution of illuminance in a low illuminance region. Can do.

Note that the contents described in each drawing in this embodiment can be freely combined with or replaced with the contents described in any of the other embodiments as appropriate.

(Embodiment 4)
In this embodiment, a structure of a block diagram in which an external circuit that outputs a digital signal is added to the photoelectric conversion device described in the above embodiment will be described with reference to FIGS.

A digital output photo IC 1300 illustrated in FIG. 13 includes the photoelectric conversion device 100, the address memory 1301, and an I2C (Inter Integrated circuit) interface circuit 1302 illustrated in FIG. The I2C interface circuit 1302 includes a serial data line (SDA) for data communication with other devices and a serial clock line (SCL) for controlling and synchronizing data communication with other devices. Are electrically connected to an external device through an I2C bus. The I2C bus composed of SDA and SCL is a bus standard for performing control from the microcomputer 1311 by a unique address assigned to an address memory provided in each device. In the case where the other device is a liquid crystal display device, for example, an address memory 1321, an I2C interface circuit 1322, a display driver 1312 having a logic unit 1323, an address memory 1331, an I2C interface circuit 1332, and an LED having a logic unit 1333 The driver 1313 is electrically connected to the I2C bus. In the case where the other device is a display device including an EL element, an LED driver for controlling the LED as a backlight is not necessarily required.

Note that a digital signal obtained from the photoelectric conversion device in the above embodiment is sent to another external device such as the LED driver 1313 via the I2C interface circuit 1302. The LED driver 1313 generates and outputs a signal for controlling the LED, which is a backlight of the display device, in accordance with the digital signal relating to the illuminance obtained by the photo IC 1300.

FIG. 14 shows another structure of the digital output photo IC 1300 shown in FIG. A photo IC 1300 shown in FIG. 14 includes an address memory 1301, an I2C interface circuit 1302, and an LED driver 1401 in addition to the photoelectric conversion device 100. The I2C interface circuit 1302 is electrically connected to the display driver 1312 via an I2C bus including SDA and SCL. The configuration shown in FIG. 14 is different from FIG. 13 in that an LED driver 1401 having a logic unit 1333 inside the photo IC 1300 is used. Since the LED driver 1401 is provided inside the photo IC 1300, a digital signal generated by the photoelectric conversion device 100 can be directly received by the LED driver 1401 and output from the I2C interface circuit 1302, so that the circuit is shared. Therefore, downsizing and high added value can be achieved.

In FIGS. 13 and 14, as an example, the interface of each circuit is configured to use an I2C interface that is one of digital serial interfaces. In addition to the I2C bus, bus standards such as a universal serial bus (Universal Serial Bus) and a serial peripheral interface (Serial Peripheral Interface) can be used.

Note that the contents described in each drawing in this embodiment can be freely combined with or replaced with the contents described in any of the other embodiments as appropriate.

(Embodiment 5)
The photoelectric conversion device of the present invention has characteristics that it can obtain a spectral sensitivity characteristic close to visual sensitivity and can improve the resolution of illuminance in a low illuminance region. Therefore, an electronic apparatus including the photoelectric conversion device of the present invention can obtain illuminance with a spectral sensitivity characteristic close to visual sensitivity as a result of adding the photoelectric conversion device to its constituent elements, and light in a dark place. Can be detected. The photoelectric conversion device of the present invention includes a display device, a notebook personal computer, and an image playback device including a recording medium (typically a display capable of playing back a recording medium such as a DVD: Digital Versatile Disc and displaying the image. Device). In addition, as an electronic device that can use the photoelectric conversion device of the present invention, a mobile phone, a portable game machine or an electronic book, a video camera, a digital still camera, a goggle-type display (head-mounted display), a navigation system, and sound reproduction Devices (car audio, audio components, etc.). Specific examples of these electronic devices are shown in FIGS.

FIG. 15A illustrates a display device, which includes a housing 1501, a display portion 1502, a sensor portion 1503, and the like. The photoelectric conversion device of the present invention can be used for the sensor portion 1503. The sensor unit 1503 detects the intensity of external light. The display device can control the luminance of the display portion 1502 in accordance with the detected intensity of external light. By controlling the luminance of the display portion 1502 in accordance with the intensity of external light, power consumption of the display device can be suppressed. The display device includes all information display devices for personal computers, TV broadcast reception, advertisement display, and the like.

FIG. 15B illustrates a digital photo frame including a housing 1511, a display portion 1512, a sensor portion 1513, and the like. The display portion 1512 can function in the same manner as a normal photo frame by displaying an image taken with a digital camera or the like. The photoelectric conversion device of the present invention can be used for the sensor portion 1513. The sensor unit 1513 detects the intensity of external light. The display device can control the luminance of the display portion 1512 in accordance with the detected intensity of external light. By controlling the luminance of the display portion 1512 in accordance with the intensity of external light, the visibility on the display portion can be improved.

16A to 16C are diagrams illustrating an example of a mobile phone with an imaging function (hereinafter also referred to as a digital camera function). FIG. 16A is a perspective view seen from the front direction when the digital camera function is performed. FIG. 16B is a perspective view seen from the back side when the digital camera function is performed. FIG. 16C is a perspective view when the mobile phone function is performed. In FIG. 16A, a cellular phone with a digital camera function includes a housing 1601, a shutter button 1602, a flash 1603, a lens 1604, and a sensor 1605. 16B includes a housing 1601, a shutter button 1602, a display portion 1611, an audio output portion 1612, a sensor 1613, and an operation button portion 1614. 16C includes a housing 1601, a shutter button 1602, a display portion 1611, an audio output portion 1612, a sensor 1613, an operation button portion 1614, an operation button 1621, and an audio input portion 1622.

When the shutter button 1602 shown in FIGS. 16A to 16C is pressed, the shutter is opened, and an image can be taken by the imaging element included in the lens 1604. Note that a CCD (Charge Coupled Device), a CMOS sensor, or the like may be used as the imaging element of the lens 1604.

A flash 1603 shown in FIG. 16A irradiates auxiliary light at the same time that the shutter button is pressed and the shutter is opened according to the illuminance value detected by the sensor 1605. With the auxiliary light of the flash 1603, an image can be taken even when the periphery of the subject is under low illumination. The photoelectric conversion device of the present invention can be used for the sensor 1605. By using a photoelectric conversion device that outputs a digital signal as the sensor 1605, digital signals can be input and output with the lens 1604 and the flash 1603. Note that as the flash 1603, an LED flash or a xenon flash can be used. By using the xenon flash, the emission spectrum of the auxiliary light can be brought close to sunlight, so that a more natural image can be taken.

A display portion 1611 shown in FIGS. 16B and 16C is for viewing an image shown on the imaging element of the lens 1604. The sensor 1605 and / or the sensor 1613 can control the luminance in accordance with the detected illuminance. By controlling the luminance of the display portion 1611 in accordance with the illuminance, power consumption of the mobile phone can be suppressed and visibility can be improved. The operation button portion 1614 is a button capable of operating a digital camera function, and a plurality of functions can be operated by each button. When the display portion 1611 is a touch sensor panel, operation of a plurality of functions and viewing of an image can be performed integrally, and the size of the display portion can be increased. Note that FIG. 16B illustrates an audio output portion 1612 used for a mobile phone function.

FIG. 16C shows a mode when a call is made with a mobile phone. As shown in FIG. 16C, the cellular phone function is used by extending the housing 1601 in the form shown in FIGS. 16A and 16B. The voice output unit 1612 and the voice input unit 1622 are for making a call function. The operation button portion 1614 and the operation button 1621 are buttons for inputting a telephone number and the like.

Note that the cellular phone with a digital camera function described in this embodiment has a structure in which the housing is extended when the cellular phone function is used. However, even a clamshell cellular phone that is used by being folded is used. Application can be made.

Note that the contents described in each drawing in this embodiment can be freely combined with or replaced with the contents described in any of the other embodiments as appropriate.

FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 6 is a diagram for illustrating Embodiment 2; FIG. 5 is a diagram for illustrating Embodiment 3; FIG. 5 is a diagram for illustrating Embodiment 3; FIG. 5 is a diagram for illustrating Embodiment 3; FIG. 5 is a diagram for illustrating Embodiment 4; FIG. 5 is a diagram for illustrating Embodiment 4; FIG. 6 is a diagram for illustrating Embodiment 5; FIG. 6 is a diagram for illustrating Embodiment 5; FIG. 4 is a diagram for illustrating Embodiment 1; FIG. 6 is a diagram for illustrating Embodiment 2; FIG. 5 is a diagram for illustrating Embodiment 3;

Explanation of symbols

100 photoelectric conversion device 101 first photoelectric conversion element 102 first amplification circuit 103 first AD conversion circuit 104 second photoelectric conversion element 105 second amplification circuit 106 second AD conversion circuit 107 subtraction circuit 108 arrow 109 Infrared light transmission filter 200 Amplifying circuit 201 N-channel transistor 202 N-channel transistor 250 Amplifying circuit 701 Step 702 Step 703 Step 704 Step 705 Step 706 Step 707 Step 900 Photoelectric conversion device 901 Subtracting circuit 902 Voltage-current converting circuit 903 AD conversion Circuit 1000 Photoelectric conversion device 1001 Current mirror circuit 1101 p-channel transistor 1102 p-channel transistor 1300 Photo IC
1301 Address memory 1302 I2C interface circuit 1311 Microcomputer 1312 Display driver 1313 LED driver 1321 Address memory 1322 I2C interface circuit 1323 Logic unit 1331 Address memory 1332 I2C interface circuit 1333 Logic unit 1401 LED driver 1501 Housing 1502 Display unit 1503 Sensor unit 1511 Housing Body 1512 Display unit 1513 Sensor unit 1601 Case 1602 Shutter button 1603 Flash 1604 Lens 1605 Sensor 1611 Display unit 1612 Audio output unit 1613 Sensor 1614 Operation button unit 1621 Operation button 1622 Audio input unit 300A Circuit 301A Switch 302A Switch 401A Switch 401 Switch 402A switch 402B switches 403A capacitive element 403B capacitive element 404A comparator 404B comparator 405A latch circuit 405B latch circuit 406A counter circuit 406B counter circuit 407A clock generating circuit 407B clock generation circuit

Claims (10)

A first photoelectric conversion element;
A first amplifier circuit for flowing a first current obtained by amplifying the photocurrent of the first photoelectric conversion element;
A second photoelectric conversion element having a spectral sensitivity characteristic different from that of the first photoelectric conversion element;
A second amplifier circuit for flowing a second current obtained by amplifying the photocurrent of the second photoelectric conversion element;
A first AD converter circuit that outputs a first digital signal by flowing the first current toward the first amplifier circuit;
A second AD converter circuit that outputs a second digital signal by flowing the second current toward the second amplifier circuit;
A subtracting circuit for outputting a difference between the first digital signal and the second digital signal;
The first AD conversion circuit and the second AD conversion circuit are:
A capacitive element that is supplied with a first potential via a first switch and that discharges according to the first current and the second current via a second switch;
A comparator that compares the potential of one electrode of the capacitive element with a second potential;
A clock generation circuit for generating and outputting a clock signal;
A counter circuit that counts up the count value by the clock signal and outputs the count value;
And a latch circuit that latches and outputs the count value in accordance with a signal output from the comparator. A first photoelectric conversion element;
A first amplifier circuit for flowing a first current obtained by amplifying the output current of the first photoelectric conversion element;
A second photoelectric conversion element having a spectral sensitivity characteristic different from that of the first photoelectric conversion element;
A second amplifier circuit for flowing a second current obtained by amplifying the output current of the second photoelectric conversion element;
A subtracting circuit for outputting a difference between the first current and the second current as a voltage value;
A voltage-current conversion circuit for flowing a third current corresponding to the voltage value;
An AD conversion circuit that outputs a digital signal by causing the third current to flow toward the voltage-current conversion circuit;
The AD conversion circuit includes:
A capacitive element that is supplied with a first potential via a first switch and that discharges according to the first current and the second current via a second switch;
A comparator that compares the potential of one electrode of the capacitive element with a second potential;
A clock generation circuit for generating and outputting a clock signal;
A counter circuit that counts up the count value by the clock signal and outputs the count value;
And a latch circuit that latches and outputs the count value in accordance with a signal output from the comparator. A first photoelectric conversion element;
A first amplifier circuit for flowing a first current obtained by amplifying the output current of the first photoelectric conversion element;
A second photoelectric conversion element having a spectral sensitivity characteristic different from that of the first photoelectric conversion element;
A second amplifier circuit for flowing a second current obtained by amplifying the output current of the second photoelectric conversion element;
The second current is caused to flow toward the first amplifier circuit through which the first current flows, and a third current corresponding to a difference between the first current and the second current is obtained. A current mirror circuit to obtain,
An AD conversion circuit for outputting a digital signal when the third current flows toward the first amplifier circuit;
The AD conversion circuit includes:
A capacitive element that is supplied with a first potential via a first switch and that discharges according to the first current and the second current via a second switch;
A comparator that compares the potential of one electrode of the capacitive element with a second potential;
A clock generation circuit for generating and outputting a clock signal;
A counter circuit that counts up the count value by the clock signal and outputs the count value;
And a latch circuit that latches and outputs the count value in accordance with a signal output from the comparator. 4. The photoelectric conversion device according to claim 1, wherein the first photoelectric conversion element and the second photoelectric conversion element are formed over a single crystal silicon substrate. 5. The photoelectric conversion device according to claim 1, wherein the first amplifier circuit and the second amplifier circuit are current mirror circuits. 6. 6. The photoelectric conversion device according to claim 1, wherein the first photoelectric conversion element and the second photoelectric conversion element are photodiodes. 7. The photoelectric conversion according to claim 1, wherein the first photoelectric conversion element and the second photoelectric conversion element have openings of the same size for entering light. apparatus. 8. The photoelectric conversion device according to claim 1, wherein the photoelectric conversion device is electrically connected to an I2C interface circuit for outputting a digital signal obtained by the photoelectric conversion device to an external device. A photoelectric conversion device. 9. The infrared light transmission filter according to claim 1, wherein an infrared light transmission filter for making a spectral sensitivity characteristic different from that of the first photoelectric conversion element is incident on the second photoelectric conversion element. The photoelectric conversion device is provided on the side of the light source. An electronic apparatus comprising the photoelectric conversion device according to claim 1.

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