KR20090117192A - Apparatus for analog to digital converting for removing noise flowed from outside, and image pick-up device having the same - Google Patents

Abstract

PURPOSE: An analog-digital converter and an image pickup device equipping the analog-digital converter are provided to remove the noise component and remove supply power noise and switching noise. CONSTITUTION: An analog-digital converter and an image pickup device equipping the analog-digital converter include an optical black standard signal generation unit(50), a lamp signal generator, and a correlated double sampling block. The optical black standard signal generation unit generates a first sampling signal by performing correlated double sampling about pixel signal outputted from a first pixel. The optical black standard signal generation unit generates the second reference signal based on the first sampling signal and the first standard signal. The lamp signal generator generates the lamp signal based on the second reference signal.

Description

Apparatus for analog to digital converting for removing noise flowed from outside, and image pick-up device having the same}

The present invention relates to an image pickup device, and more particularly, to an analog-to-digital converter capable of outputting an image signal corresponding to the pixel signal by removing noise components included in the pixel signal, and the analog-to-digital converter. It relates to an image pickup device comprising a.

An image pick-up device is a semiconductor device that converts an optical image into an electrical signal. An image pick-up device mainly using a charge coupled device (CCD) and a CMOS process are used. CMOS image sensors (CIS) are widely used.

CMOS image sensors are economical because they can be manufactured using a general CMOS process, compared to CCD image pickup devices, and are advantageous for integration because analog-to-digital converters can be integrated together on a single chip. In addition, the CMOS image sensor is widely used in portable devices such as mobile phones and digital cameras with low power consumption due to low power and low voltage design.

However, unlike the image pickup device using the CCD, the CMOS image sensor uses a high resolution analog-to-digital converter for converting an analog signal output from an active pixel sensor (APS) that reacts to light into a digital signal. It requires a lot more noise than CCD. This noise is one of the factors that degrade the performance of the CMOS image sensor.

As a method of converting an analog signal into a digital signal in a CMOS image sensor, there is a method of using an analog-to-digital converter (ADC) and a method of using a column ADC.

The method using one ADC converts the analog signal output from the APSs of all columns into a digital signal using a single ADC operating at high speed. In addition, the method using a column ADC is arranged for each column of the ADC having a simple structure to convert the analog signal output from the APS of each column into a digital signal. Primarily uses low-power column ADCs.

In general, the analog-to-digital converter uses a CDS scheme to reduce noise in the image pickup apparatus. The CDS method suppresses noise by using a difference between a reset signal maintaining a constant voltage level and an image signal. Fixed pattern noise is easily observed in a pixel signal output from a unit pixel such as a CMOS image sensor. FPN) is widely used to detect only the desired signal components. In other words, the CDS method is effective to reduce the noise due to the characteristic difference between the FPN and the unit pixels in which the unit pixels are fundamental.

However, the conventional CDS method has a good noise characteristic against power supply noise generated in the CDS block itself and coupling noise due to switching, but does not efficiently cope with pixel supply power noise generated from unit pixels outside the CDS block. There is this.

Therefore, there is an urgent need for an analog-to-digital converter that can remove noise generated outside the CDS block.

Accordingly, an object of the present invention is to provide an analog-to-digital conversion device capable of removing supply power supply noise and switching noise.

The analog-to-digital converter according to the embodiment of the present invention includes an optical black reference signal generator, a ramp signal generator, and a correlated double sampling block. The optical black reference signal generator generates a first sampling signal by performing correlated double sampling on the pixel signal output from the first pixel, and generates a second reference signal based on the first sampling signal and the first reference signal. . The ramp signal generator generates a ramp signal based on the second reference signal. The correlated double sampling block generates the second sampling signal by performing the correlated double sampling on the pixel signal output from the second pixel, and outputs a comparison signal by comparing the second sampling signal with the ramp signal.

The optical black reference signal generator is configured to buffer the first sampling signal and the correlated double sampling circuit for generating the first sampling signal by performing the correlated double sampling on the pixel signal output from the first pixel. And an amplifier for generating a reference signal.

The lamp signal generator includes a voltage-to-current converter, a comparator, and a switching element. The voltage-current converter is connected between an output node and a first terminal for receiving a first power source, divides the voltage of the output node to output the divided voltage as a feedback signal, and based on the voltage of the output node. Generate a ramp signal. The comparator compares the second reference signal with the feedback signal and outputs a comparison signal. The switching element is connected between a second terminal for receiving a second power source and the output node, and performs a switching operation in response to the comparison signal.

The first pixel is an optical black pixel, and the second pixel is a unit pixel.

The ramp signal generator further includes a Miller compensation capacitor connected between the output terminal of the comparator and the output node.

The first reference signal is a reference voltage maintaining a constant voltage level.

An image pickup apparatus according to an exemplary embodiment of the present invention includes an active region, an optical black region, an optical black reference voltage generator, a ramp signal generator, and a correlated double sampling block. The active region includes a first pixel, and the optical black region includes a second pixel. The optical black reference signal generator generates a first sampling signal by performing correlated double sampling on the pixel signal output from the first pixel, and generates a second reference signal based on the first sampling signal and the first reference signal. do. The ramp signal generator generates a ramp signal based on the second reference signal. The correlation double sampling block generates a second sampling signal by performing correlation double sampling on the pixel signal output from the second pixel, and outputs a comparison signal by comparing the second sampling signal with the ramp signal.

As described above, the analog-to-digital converter according to the embodiment of the present invention has an effect of removing supply power supply noise and switching noise.

In addition, the analog-to-digital converter according to the embodiment of the present invention has an effect of stably outputting a ramp signal using a Miller compensation capacitor and reducing a layout size.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

1 is a schematic block diagram of an image pickup apparatus including an analog-to-digital converter according to an embodiment of the present invention, and FIG. 2 is a schematic block diagram of an analog-to-digital converter according to an embodiment of the present invention. . The image capturing apparatus 10 illustrated in FIG. 2 may be implemented as an image capturing apparatus 10 including a single slope ADC.

1 and 2, the image capturing apparatus 10 may include an active region 20, such as a pixel array, an optical black region 25, such as an optical black (OB) pixel array, and a row. A row decoder 30, a column decoder 35, a timing generator 40, a reference signal generator 45, a ramp signal generator 60, and an analog-to-digital conversion block 90).

The analog-to-digital conversion block 90 includes a correlated double sampling (CDS) block 70 and an analog-digital converter (ADC) 80.

The active area 20 includes a plurality of unit pixels arranged in a two-dimensional matrix between a plurality of rows and a plurality of columns. The active area 20 is a pixel signal (Pixel <0>-Pixel <n>) output from any one column in response to control signals (eg, TX, RX, SEL) output from the row decoder 30. ) Are transmitted to the respective CDS circuits 71, 73, and 75.

In general, a unit pixel includes a photosensitive device performing photoelectric conversion and a plurality of transistors, and the photosensitive device may be implemented as a photodiode or a phototransistor. For example, when the unit pixel is implemented with a 4-TR structure including one light sensing element and four transistors, the pixel array 20 may output control signals TX, RX, and SEL output from the row decoder 30. In response, the pixel signal output from the unit pixel, that is, the reset signal and the image signal are amplified and transmitted to the CDS block 70.

Each of the unit pixels is connected to a terminal for receiving a power supply for driving the unit pixel, for example, a power supply voltage. Accordingly, the supply power noise generated from the supply power is introduced into the pixel signal, and the supplied supply power noise is amplified together with the pixel signal and transmitted to the CDS block 70. These unwanted noise components, such as supply power noise, are reflected in the analog-to-digital conversion operation in the CDS block 70 to affect the digital signal values.

The optical black area 25 includes a plurality of optical black pixels. Unlike the active area 20, the optical black area 25 completely covers the upper part with metal to completely block light incident from the outside. Since the optical black area 25 is not affected by light, the optical black pixel is not generated by the photoelectric conversion. The optical black signal is output based only on the electrons generated inside the L-n.

The supply power supplied to the optical black pixels of the optical black region 25 is the same as the supply power supplied to the unit pixels of the active region 20. Therefore, the noise of the power supply included in the optical black signal OB_Pixel output from the optical black region 25 is a pixel signal Pixel <0> -Pixel <n> output from the active region 20, where n is a natural number. This is the same as the noise of the power supply included in). That is, the optical black region 25 may effectively transmit the same noise as the power supply noise generated in the active region 20 through the optical black signal.

The row decoder 30 is connected to the pixel array 20 and selects a row of the pixel array 20 sequentially or in a predetermined order in response to control signals output from the timing generator 40. .

The column decoder 35 is connected to the pixel array 20 and selects columns of the pixel array 20 sequentially or in a predetermined order in response to control signals output from the timing generator 40. .

That is, the pixel array 20 of the image capturing apparatus 10 may include pixel signals generated from at least one pixel selected by the row decoder 30 and the column decoder 35, that is, analog signals (reset signal and image signal). Is output to the analog-to-digital conversion block 90.

The timing generator 40 includes a pixel array 20, a row decoder 30, a column decoder 35, a timing generator 40, a reference signal generator 45, a ramp signal generator 60, and an analog-to-digital converter. At least one control signal for controlling at least one operation from the 90 is generated.

The reference signal generator 45 generates a first reference signal Vref that maintains a constant level regardless of noise fluctuations. The first reference signal Vref is provided as a reference signal of the OB reference signal generator 50.

In addition, the reference signal generator 45 includes an OB reference signal generator 50. The OB reference signal generator 50 generates a first sampling signal by performing a correlated double sampling on the optical black signal OB_Pixel output from the optical black region 25, and generates the first sampling signal and the first reference. The second reference signal V _{OB _ in1} illustrated in FIG. 3 is generated based on the signal Vref.

Although the reference signal generator 45 is illustrated as including the OB reference signal generator 50 in FIG. 1, the OB reference signal generator 50 may be implemented anywhere outside the reference signal generator 45. .

The ramp signal generator 60 may supply power noise included in the optical black signal OB_Pixel and the CDS circuit 57 based on the second reference signal V _{OB _ in1} output from the OB reference signal generator 50. A ramp signal Vramp that replicates the switching noise is output.

The analog-to-digital conversion block 90 includes a CDS block 70 and an analog-to-digital converter 80, and performs correlated double sampling on the pixel signals Pixel <0> -Pixel <n> output from the unit pixels. A second sampling signal VIN1 shown in FIG. 3 is generated, and a digital signal is generated based on the second sampling signal VIN1 and a ramp signal Vramp.

 Referring to FIG. 2, the analog-to-digital converter includes a reference signal generator 45, an OB reference signal generator 50, a ramp signal generator 60, and a CDS block 70.

The optical black (OB) reference signal generator 50 performs a first sampling by performing a correlated double sampling on an optical black signal OB_Pixel output from an optical black pixel (hereinafter, referred to as a “first pixel”). A signal is generated and a second reference signal V _{OB _ in1} is generated based on the generated first sampling signal.

The ramp signal generator 60 generates a periodic ramp signal Vramp based on the second reference signal V _{OB _ in1} output from the OB reference signal generator 50.

The CDS block 70 includes a plurality of CDS circuits 71, 73, and 75 connected for each column. The CDS circuit 71, 73, or 75 performs a correlated double sampling on the pixel signals Pixel <0> -Pixel <n> output from the unit pixels connected to any one column to perform the second sampling signal VIN1. And a second sampling signal VIN1 and a ramp signal Vramp are compared to output a comparison signal for generating a digital signal according to the comparison result.

FIG. 3 is a timing diagram for describing an operation of the analog-digital converter of FIG. 2. Hereinafter, the operation of the analog-to-digital conversion device capable of removing supply power supply noise and switching noise will be described with reference to FIGS. 2 and 3.

The OB reference signal generator 50 includes a CDS circuit 57 and an amplifier (or buffer) 55 and generates a second reference signal V _{OB _ in1} based on the optical black signal OB_Pixel.

The CDS circuit 57 includes a plurality of switches SW1 and SW2, a capacitor C0, and a first comparator 51. The CDS circuit 57 performs a correlated double sampling on the optical black signal OB_Pixel output from the first pixel based on the switching signals S1 and S3 shown in FIG. 3 to perform the first sampling signal or the first sampling signal. Generate a signal associated with at least a portion of the signal.

The amplifier 55 buffers a signal associated with at least a portion of the first sampling signal or the first sampling signal to generate a second reference signal V _{OB _ in1} . In an embodiment of the present invention, the amplifier 55 is implemented as a voltage follower, but is not limited thereto.

When the CDS circuit 57 performs a sampling operation, that is, each of the plurality of switches SW1 and SW3 in the CDS circuit 57 is turned on or turned off in response to the switching signals S1 and S3. Switching noise is generated. In addition, supply power noise generated from the power supply of the first pixel is introduced into the CDS circuit 57 through the optical black signal OB_Pixel.

Accordingly, as shown in FIG. 3, the second reference signal V _{OB _ in1} is generated not only in the optical black signal of the first pixel but also in the CDS circuit 57 and supply power noise introduced from the supply power of the first pixel. Included switching noise together.

As described above, the OB reference signal generator 50 includes a CDS circuit 57 having the same configuration as the CDS circuits 71, 73, and 75 included in the CDS block 70, and is output from the unit pixel. A ramp signal Vramp is reproduced by replicating a noise component (for example, supply power noise introduced from a unit pixel and switching noise generated in the CDS circuit 57) generated when the pixel signal is sampled.

The ramp signal generator 60 includes a first pad 65 having a voltage-to-current converter (or VI converter) 63, a second comparator 61, a switching element P1, and an external capacitor CL. A periodic ramp signal Vramp is generated based on the second reference signal V _{OB _ in1} output from the OB reference signal generator 50.

The voltage-to-current converter 63 includes a divider and a current source Ib connected between the output node ND1 and the first terminal for receiving the first voltage VSS. The divider includes a first resistor R1 connected to the output node ND1 and the first node ND2, and a second resistor R2 connected between the first node ND2 and the first terminal. The divider divides the voltage of the output node ND1 and outputs the divided voltage as a feedback signal at the first node ND2. The divided voltage is adjusted based on the resistance values of the first resistor and the second resistor, and fed back to the second input terminal (+) of the second comparator 61.

In addition, the current source Ib is connected to the first terminal from the output node ND1 through the third resistor R3 and outputs a ramp signal Vramp based on the voltage of the output node ND1.

The second comparator 61 outputs a comparison result by comparing the second reference signal V _{OB _ in1} inputted through the first input terminal (−) with a feedback signal inputted through the second input terminal (+). .

The switching element P1 is connected between the second voltage VDD and the output node ND1 and is turned on according to a comparison result output from the second comparator 61 to receive the second voltage VDD. A current path is formed between the two terminals and the output node ND1.

The switching element P1 may be implemented as a PMOSFET or an NMOSFET. For example, when the switching element P1 is implemented as a PMOSFET, the switching element P1 is maintained in a turn-on state in response to a comparison signal having a first level (eg, a low level).

As described above, the analog-to-digital converter according to the exemplary embodiment of the present invention includes a ramp signal replicating supply power noise generated in the first pixel and switching noise generated during the sampling operation in the CDS circuit 57. Vramp) can be created. The ramp signal Vramp is supplied as a reference signal of the CDS block 70.

The CDS block 70 includes a plurality of CDS circuits 71, 73, and 75 connected to each column, and the CDS circuits 71, 73, and 75 include a plurality of switches SW1 and SW2, capacitors. , And a third comparator 50.

The pixel array 20 is a pixel of a unit pixel (hereinafter referred to as a "second pixel") connected to any one column in response to a control signal (eg, TX, RX, and SEL) output from the row decoder 30. A signal, that is, a reset signal Vres and an image signal Vsig, are sequentially output to the respective CDS circuits 71, 73, and 75, and the CDS circuits 71, 73, and 75 are switched signals S1 and S3. In response to the reset signal Vres, the video signal Vsig is sampled.

That is, the CDS circuits 71, 73, and 75 perform correlated double sampling on the pixel signals Pixel <0>-Pixel <n> output from the second pixel to generate the second sampling signal VIN1.

 Here, a section in which the CDS circuits 71, 73, and 75 perform a sampling operation on the reset signal Vres is called a 'reset signal sampling period' (①-③), and the sampling operation is performed on the image signal Vsig. The section to be performed is called a 'video signal sampling section' (④-⑤).

The third comparator 59 compares the second sampling signal VIN1 input through the first input terminal (−) and the ramp signal Vramp input through the second input terminal (+), and according to the comparison result. Output the comparison signal.

When downward ramping starts, i.e. while the ramp signal Vramp is reduced, the analog-to-digital converter 80 counts the number of clock signals, and the comparison signal is changed from the first level (e.g., low level) to the second level (e.g. For example, the signal counted at the transition to the high level) is output as a digital signal. That is, the count value at the time point T1 when the level of the ramp signal Vramp that is decreased reaches the level of the second sampling signal VIN1 means a digital signal. As a result, the digital signal is equal to the reset signal Vres. An output value corresponding to a change amount (ΔSignal, hereinafter referred to as an “image signal change amount”) or a change amount ΔVramp of the ramp signal Vramp corresponding to the difference Vres-Vsig of the image signal Vsig.

As a result, the reference potential may be changed by the noise component included in the second sampling signal VIN1 in the variation amount ΔVramp of the ramp signal. Accordingly, the ramp signal variation ΔVramp and the image signal variation ΔSignal Have different values. In this case, an error may occur in the digital signal output from the analog-digital converter. As a result, the conventional analog-to-digital converter cannot output an image signal corresponding to the video signal generated by the photoelectric conversion.

Reset signal sampling period (①-③) for a first input terminal of the comparator 59 (-), the second sampling signal that is input to (the VIN1, Equation 1 VIN1 _1, i.e., VIN1 = VIN1 ₁₎ and the ramp signal ( Vramp, Vramp _{1 in} Equation ₁ That is, Vramp = Vramp ₁ and the difference between the second sampling signal VIN1 = VIN1 ₁ and the ramp signal Vramp ₁ (V _Diff , V _{Diff1 in} Equation 1, ie V _Diff = V _Diff1 ) It is shown as Equation 1.

Here, Vref is a first reference signal (Vref) and, △ V _S3 is turned on of the switches (S1 and S3) - indicates the respective switching noise that is generated during the off-component, △ Vpower the noise component of the supply voltage.

Referring to Equation 1, the second sampling signal VIN1 = VIN1 ₁ input to the first input terminal (−) of the third comparator 59 and the ramp signal Vramp = input to the second input terminal (+). Since Vramp ₁ is identical to each other, the second sampling signal VIN = VIN1 ₁ and the ramp signal Vramp = Vramp ₁ input to the third comparator 59 cancel each other.

Also, the image signal sampling interval (④-⑤), while the third comparator 59, a second sampling signal that is input to (the VIN1, Equation 2 VIN1 _2, i.e., VIN1 = VIN1 ₂₎ the ramp signal (Vramp, equation Vramp _{2 in 2} In other words, Vramp = Vramp ₂ and the difference between the second sampling signal VIN1 = VIN1 ₂ and the ramp signal Vramp = Vramp ₂ (V _Diff , V _{Diff2 in} Equation 2, ie V _Diff = V _Diff2 ) Equation 2 is shown.

Here, ΔSignal represents the difference between the reset signal Vres and the image signal Vsig (Vres-Vsig) output from the second pixel after the reset operation, that is, the amount of video signal conversion.

Referring to Equation 2, the noise component and the second noise component of the second sampling signal VIN1 = VIN1 ₂ input to the first input terminal (-) of the third comparator 59 during the video signal sampling period ④-⑤. The noise components of the ramp signal (Vramp = Vramp ₂ ) input to the input terminal (+) cancel each other, leaving only the actual amount of change (ΔSignal) of the image signal, that is, the image signal.

After the image signal sampling period ④-⑤, that is, when the ramp signal Vramp starts the downward ramp, the third comparator 59 compares the second sampling signal VIN1 with the ramp signal Vramp. A comparison signal for generating a digital signal is output.

As the ramp signal Vramp performs downward ramping, the level of the ramp signal Vramp input to the second input terminal (+) of the third comparator 59 also decreases. The third comparator 59 outputs a comparison signal having a first level (eg, a low level) while the level of the ramp signal Vramp is higher than the level of the second sampling signal VIN1, and outputs a comparison signal having the ramp signal Vramp. When the level is equal to or lower than the level of the second sampling signal VIN1, a comparison signal having a second level (eg, a high level) is output.

 That is, as shown in Equation 2, the noise component included in the second sampling signal VIN1 and the noise component included in the ramp signal Vram cancel each other, so that only the change amount ΔSignal of the image signal remains. The change amount? Vramp of the ramp signal, which decreases from the time when the ramp signal Vramp starts the down ramp until the comparison signal transitions, is equal to the change amount? Signal of the video signal. That is, the change amount ΔSignal of the video signal and the change amount ΔVramp of the ramp signal may be expressed as in Equation 3 below.

That is, the analog-to-digital converter according to the embodiment of the present invention is a ramp signal (Vramp) is a replica of the power supply noise generated in the pixel array 20 and the switching noise generated in the CDS circuit (71, 73 and 75) The ramp signal Vramp, which is generated by replicating the noise component, is provided as a reference signal of the CDS circuits 71, 73, and 75.

Accordingly, according to the present invention, the noise component included in the output signal of the unit pixel and the noise component included in the ramp signal cancel each other, thereby eliminating even the noise component remaining in the output signal output from the conventional analog-to-digital converter. It works.

In addition, the analog-to-digital converter according to the present invention can output the change amount (ΔVramp) of the ramp signal equal to the change amount (ΔSignal) of the image signal, it is possible to output an accurate image signal corresponding to the photoelectric change amount.

The CDS circuits 71, 73, and 75 included in the CDS block 70 have the same configuration and operation as the CDS circuit 57 included in the OB reference signal generator 50, and the CDS circuits 71, 73. , 75, and 57 may further include a comparator 53 for comparing the comparison signal output from the first comparator 51 or the second comparator 57 with the reference signal REF.

4 is a schematic block diagram of an analog-digital converter according to another embodiment of the present invention.

Referring to FIG. 4, the analog-to-digital converter includes a reference signal generator 45, an OB reference signal generator 50, a ramp signal generator 69, and a CDS block 70.

Except for the ramp signal generator 69, the analog-to-digital converter includes the configuration and operation of the reference signal generator 45, the OB reference signal generator 50, and the CDS block 70 shown in FIG. Since the reference signal generator 45 including the OB reference signal generator 50 and the CDS block 70 are the same, the detailed description is omitted in order to avoid duplication of description.

The ramp signal generator 69 includes a voltage-to-current converter (or VI converter) 63, a second comparator 61, a switching element P1, a mirror compensation capacitor Cc, and a first pad 65. A periodic ramp signal Vramp is generated based on the second reference signal V _{OB _ in1} output from the OB reference signal generator 50.

The voltage-current converter 63 includes a divider and a current source Ib connected between the output node ND1 and the first terminal. The divider includes a first resistor R1 connected to the output node ND1 and the first node ND2, and a second resistor R2 connected between the first node ND2 and the first terminal. The divider divides the voltage of the output node ND1 and outputs the divided voltage as a feedback signal at the first node ND2. In addition, the current source Ib is connected to the first terminal from the output node ND1 through the third resistor R3 and generates a ramp signal Vramp based on the voltage of the output node ND1.

The second comparator 61 outputs a comparison result by comparing the second reference signal V _{OB _ in1} inputted through the first input terminal (−) with a feedback signal input through the second input terminal (+). .

The switching element P1 is connected between the second terminal and the output node ND1 and is turned on according to the comparison result output from the second comparator 61 to between the second voltage VDD and the output node ND1. To form a current path.

The Miller compensation capacitor Cc is connected between the output terminal of the second comparator 61 and the output node ND1.

The ramp signal generator 69 has an unstable voltage at the output node ND1 due to a load capacitance (not shown) connected to the first pad 65. In general, as shown in FIG. 2, the ramp signal generator 60 inserts an external capacitor C _L into the first pad 65 to stabilize the voltage of the output node ND1. That is, the external capacitor CL may stabilize the voltage level of the output node ND1 by minimizing the influence of noise caused by a load capacitance (not shown) connected to the first pad 65. However, as the load capacitance connected to the first pad 65 increases, the layout area of the analog-to-digital converter increases as the size of the external capacitor C _L increases.

However, the ramp signal generator 69 may stabilize the voltage level of the output node ND1 without the external capacitor C _L by using the Miller compensation capacitor Cc.

Therefore, the ramp signal generator 69 according to the embodiment of the present invention can reduce the layout size by removing the external capacitor C _L. In addition, the production cost can be reduced by eliminating the process of inserting the external capacitor C _L into the lamp signal generator 69.

As described above, the analog-to-digital converter according to the embodiment of the present invention includes a ramp signal that replicates the supply power noise generated in the first pixel and the switching noise generated in the sampling operation in the CDS circuit 57. Vramp) and the ramp signal Vramp can be supplied as a reference signal of the CDS block 70 to correct an error generated during the analog-to-digital conversion.

That is, the analog-to-digital converter 80 according to the embodiment of the present invention uses the ramp signal Vramp output from the OB reference signal generator 50 to generate noise generated when a pixel signal of a unit pixel is performed. By removing the component, there is an effect of outputting a high resolution image signal.

Therefore, the analog-to-digital converter according to the present invention has the effect of eliminating supply power noise generated from the outside.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The detailed description of each drawing is provided in order to provide a thorough understanding of the drawings cited in the detailed description of the invention.

1 is a conceptual block diagram of an image capturing apparatus including an analog-digital converter according to an exemplary embodiment of the present invention.

2 is a schematic block diagram of an analog-to-digital converter according to an embodiment of the present invention.

FIG. 3 is a timing diagram for describing an operation of the analog-digital converter of FIG. 2.

4 is a schematic block diagram of an analog-digital converter according to another embodiment of the present invention.

Claims (8)

An optical black reference signal generator configured to generate a first sampling signal by performing correlated double sampling on the pixel signal output from the first pixel, and generate a second reference signal based on the first sampling signal and the first reference signal; A ramp signal generator configured to generate a ramp signal based on the second reference signal; And An analog signal including a correlated double sampling block configured to generate a second sampling signal by performing the correlated double sampling on the pixel signal output from the second pixel, and to compare the second sampling signal with the ramp signal and output a comparison signal; Digital converter. The optical black reference signal generator of claim 1, A correlated double sampling circuit configured to generate the first sampling signal by performing the correlated double sampling on the pixel signal output from the first pixel; And And an amplifier for buffering the first sampling signal to generate the second reference signal. The method of claim 1, wherein the lamp signal generator, A voltage connected between an output node and a first terminal for receiving a first power source, for distributing the voltage of the output node to output the divided voltage as a feedback signal, and generating the ramp signal based on the voltage of the output node; A current converter; A comparator comparing the second reference signal with the feedback signal and outputting a comparison signal; And And a switching element connected between the second terminal for receiving a second power source and the output node, the switching element performing a switching operation in response to the comparison signal. The analog-to-digital converter of claim 1, wherein the switching element is implemented as a PMOSFET or an NMOSFET. The apparatus of claim 1, wherein the first pixel is an optical black pixel and the second pixel is a unit pixel. The method of claim 3, wherein the ramp signal generator, And a Miller compensation capacitor connected between the output terminal of the comparator and the output node. The analog-to-digital converter of claim 1, wherein the first reference signal is a reference voltage maintaining a constant voltage level. An active region comprising a first pixel; An optical black region including a second pixel; An optical black reference signal generator configured to generate a first sampling signal by performing correlated double sampling on the pixel signal output from the first pixel, and generate a second reference signal based on the first sampling signal and the first reference signal ; A ramp signal generator configured to generate a ramp signal based on the second reference signal; And An image pick-up including a correlated double sampling block configured to generate a second sampling signal by performing correlated double sampling on the pixel signal output from the second pixel, and to output a comparison signal by comparing the second sampling signal with the ramp signal Device.

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