JP5353542B2 - Semiconductor device and test method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of shortening time for development of the semiconductor device, and to provide a method of testing the semiconductor device. <P>SOLUTION: Based on a first start signal Ss1 and a first halt signal Sh1, a clock signal control circuit 11a outputs a clock signal CK from a testing device, as a first internal clock signal ICK1, to an internal circuit 12a, a BIST circuit 13a and a delay control circuit 14a. The test start control circuit 28a of the delay control circuit 14a outputs a second start signal Ss2 of an H level to a second chip C2 when the first count value Dc1 of a counter circuit 25a becomes equal to a test start value Ds. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a semiconductor device test method.

  Conventionally, when a process step of forming a plurality of semiconductor devices (chips) on a semiconductor device substrate (wafer) is completed, an electrical characteristic test is performed in the state of the wafer in order to confirm the operation of the formed semiconductor device. Chips determined to be defective as a result of this electrical characteristic test are excluded from the assembly targets in the next assembly process, thereby preventing unnecessary assembly. Furthermore, the determination result is analyzed, and if there is an abnormality, the process condition is improved by feeding back the process condition.

  In recent years, semiconductor devices have been required to reduce test time in order to reduce costs. For this reason, the test apparatus (tester) performs the test of the electrical characteristics of the chip formed on the wafer in a plurality of times. This is because the test apparatus may exceed the allowable current of the test apparatus when the electrical characteristics of the chips formed on the wafer are collectively tested. Therefore, the test apparatus has simultaneously performed an evaluation test on a number of chips that do not exceed the allowable current.

  In this case, an electric signal delay circuit for delaying an electric signal such as a clock signal input from the test apparatus is provided in an area of the wafer excluding the area where the chip is formed (see, for example, Patent Document 1). ). The electrical signal delay circuit is provided on the wafer for each group of chips for which electrical property tests are performed simultaneously, and has different delay amounts. As a result, the test apparatus tests the electrical characteristics at different timings for each group of chips that simultaneously perform electrical characteristics tests.

JP 2004-119456 A

  However, in the above test method, each electric signal delay circuit delays an electric signal such as a clock signal by a delay element. For this reason, if the delay elements greatly vary in the process steps of the semiconductor device, the delay amount of each electric signal delay circuit also varies greatly. Therefore, the timing set for each group of chips may overlap, and the total current consumption of the chips formed on the wafer may exceed the allowable current of the test apparatus.

In the above test method, when the test program is changed, it is sometimes necessary to change the delay amount of the electric signal delay circuit.
When delay elements greatly vary in the process steps of the semiconductor device described above, or when a test program is changed, the circuit change is made to adjust the delay amount of the electric signal delay circuit, and the semiconductor device development period Will be prolonged.

  An object of the semiconductor device and the semiconductor device testing method is to shorten the development time of the semiconductor device.

According to an aspect of the present invention, a plurality of semiconductor devices are serially connected to a semiconductor device substrate and tested by a test device, the first test device from the previous stage or the first semiconductor device. A clock signal control circuit for supplying a clock signal as a first internal clock signal to an internal circuit based on a start signal; and a counter circuit for counting the first internal clock signal, wherein the counter circuit is configured to output the first internal clock signal. A delay for delaying and outputting a second start signal for supplying the clock signal to the internal circuit of the subsequent semiconductor device as a second internal clock signal based on the count value obtained by counting the signal to the subsequent semiconductor device possess a control circuit, said clock signal control circuit includes a first start signal and the first from the preceding the test device or the semiconductor device Based on a stop signal, the clock signal is supplied to the internal circuit as the first internal clock signal, and the delay control circuit is based on the count value of the counter circuit and operates in the subsequent stage of the semiconductor circuit during its circuit operation. A second pause signal for stopping the supply of the second internal clock signal to the internal circuit of the device is output to the semiconductor device at the subsequent stage .

  According to one aspect of the present invention, a semiconductor device and a test method for a semiconductor device can shorten the development time of the semiconductor device.

It is a schematic explanatory drawing of a wafer test. It is a block diagram of the 1st and 2nd chip | tip of 1st Embodiment. It is operation | movement explanatory drawing of the 1st and 2nd chip | tip of 1st Embodiment. It is a block diagram of the 1st and 2nd chip | tip of 2nd Embodiment. It is explanatory drawing of the 1st-16th selection control value.

(First embodiment)
Hereinafter, the first embodiment will be described with reference to FIGS.
FIG. 1 is a schematic explanatory diagram for testing the first to sixteenth chips C1 to C16 having the same circuit configuration formed on the wafer W1.

  As shown in FIG. 1, the wafer W1 has first to seventh pads P1 to P7 formed in a region excluding the first to sixteenth chips C1 to C16. The test apparatus (tester) T1 mounts the wafer W1, and makes a test by bringing the probe into contact with the first to seventh pads P1 to P7 of the wafer W1 and inputting and outputting signals and voltages.

  In the present embodiment, the test apparatus T1 includes a power supply terminal Te1, a ground terminal Te2, a clock signal output terminal Te3, a start signal output terminal Te4, a pause signal output terminal Te5, a read signal output terminal Te6, and a test result signal input terminal Te7. doing.

  The power supply terminal Te1, the ground terminal Te2, and the clock signal output terminal Te3 are respectively connected to the first to third pads P1 to P3 via probes, and the test apparatus T1 receives the power supply VDD, the ground GND, and the clock signal CK as the first. ~ Supplied to the 16th chips C1 to C16, respectively. Accordingly, the first to sixteenth chips C1 to C16 are supplied with the same power supply VDD and ground GND and operate in synchronization with the clock signal CK.

  The start signal output terminal Te4 is connected to the fourth pad P4 via a probe, and the test apparatus T1 outputs a first start signal Ss1 for causing the first to sixteenth chips C1 to C16 to start a test. The data is output to the first chip C1 via Te4 and the fourth pad P4. When the test apparatus T1 causes the first to sixteenth chips C1 to C16 to start a test, the test apparatus T1 outputs the first start signal Ss1 of the H level (start mode), and conversely, the first to sixteenth chips C1 to C16 In order to enter the standby state, the first start signal Ss1 at the L level (standby mode) is output.

  The pause signal output terminal Te5 is connected to the fifth pad P5 via a probe, and the test apparatus T1 outputs the first pause signal Sh1 for causing the first to sixteenth chips C1 to C16 to pause the test. The data is output to the first chip C1 via Te5 and the fifth pad P5. When the test apparatus T1 does not cause the first to sixteenth chips C1 to C16 to suspend the test, the test apparatus T1 outputs the first pause signal Sh1 of H level (non-pause mode), and conversely, the first to sixteenth chips C1 to C16. When the test is paused, an L level (pause mode) first pause signal Sh1 is output.

  The read signal output terminal Te6 is connected to the sixth pad P6 via the probe, and the test apparatus T1 reads the read signal Se for reading the test results of the first to sixteenth chips C1 to C16, and the read signal output terminal Te6. The data is output to the first chip C1 through the sixth pad P6. When the test apparatus T1 reads the test results of the first to sixteenth chips C1 to C16, the test apparatus T1 outputs a read signal Se of H level (read mode), and conversely, the test results of the first to sixteenth chips C1 to C16. When the signal is not read, a read signal Se of L level (non-read mode) is output.

  The test result signal input terminal Te7 is connected to the seventh pad P7 via a probe, and the test apparatus T1 sends the test result signal Sr, which is the test result of the first to sixteenth chips C1 to C16, to the seventh pad P7 and the test. The result is input from the 16th chip C16 via the result signal input terminal Te7.

  In the test of the first to sixteenth chips C1 to C16, first, the test apparatus T1 in the standby state of the test of the first chip C1, the first start signal Ss1 of the L level (standby mode), the H level (non-level). The first pause signal Sh1 in the pause mode) and the read signal Se in the L level (non-read mode) are output to the first chip C1. From this state, the test apparatus T1 outputs a first start signal Ss1 of H level (start mode) to the first chip C1 in order to cause the first chip C1 to start a test. Thereafter, the test apparatus T1 maintains the output of the first start signal Ss1 at the H level.

Thus, the first to sixteenth chips C1 to C16 are tested in the order of the first chip C1, the second chip C2,..., And the sixteenth chip C16.
Next, when the test of the first to sixteenth chips C1 to C16 is completed, the test apparatus T1 reads the test result signal Sr that is the test result of the first to sixteenth chips C1 to C16, so ) Is output to the first chip C1. Thereafter, the test apparatus T1 maintains the output of the read signal Se at the H level (read mode).

  As a result, the test apparatus T1 sequentially inputs the test result signal Sr, which is the test result of the first to sixteenth chips C1 to C16, from the sixteenth chip C16 via the seventh pad P7.

  As shown in FIG. 2, the first chip C1 includes a clock signal control circuit 11a, an internal circuit 12a having a specific function, a BIST (built-in self-test) circuit 13a for testing the internal circuit 12a, and a subsequent stage (this In this case, it has a delay control circuit 14a for delaying the test start of the second chip C2).

The clock signal control circuit 11a includes an AND circuit 16a and a clock gating circuit (also referred to as a clock gating buffer cell) 17a.
The AND circuit 16a receives the first start signal Ss1 and the first pause signal Sh1 from the test apparatus T1 via the fourth and fifth pads P4 and P5. The AND circuit 16a outputs the first mode signal Sm1 to the clock gating circuit 17a based on the first start signal Ss1 and the first pause signal Sh1.

  That is, the AND circuit 16a uses the clock gating circuit to output the first mode signal Sm1 at the H level (test execution mode) when both the first start signal Ss1 and the first pause signal Sh1 are at the H level (start and non-pause mode). To 17a.

  The AND circuit 16a operates when the first start signal Ss1 is at the L level (standby mode) or when the first start signal Ss1 is at the H level (start mode) and the first pause signal Sh1 is at the L level (called pause mode). At this time, the first level signal Sm1 of L level (test stop mode) is output to the clock gating circuit 17a.

  The clock gating circuit 17a receives the clock signal CK from the test apparatus T1 through the third pad P3. Based on the first mode signal Sm1, the clock gating circuit 17a outputs the clock signal CK as the first internal clock signal ICK1 to the internal circuit 12a, the BIST circuit 13a, and the delay control circuit 14a.

  When the first mode signal Sm1 of H level (test execution mode) is input, the clock gating circuit 17a outputs the input clock signal CK as the first internal clock signal ICK1. On the contrary, when the first mode signal Sm1 of L level (standby or test stop mode) is input, the clock gating circuit 17a outputs no signal, that is, the clock signal CK is used as the first internal clock signal ICK1. Do not pass.

  The internal circuit 12a receives the first internal clock signal ICK1 from the clock gating circuit 17a and the test pattern Dt from the BIST circuit 13a. Here, the test pattern Dt refers to input pattern data for testing. In the present embodiment, the first to sixteenth chips C1 to C16 formed on the wafer W1 have the same circuit configuration. Therefore, the same test pattern Dt is input to the internal circuits 12a to 12h of the first to sixteenth chips C1 to C16. The internal circuit 12a processes the test pattern Dt in synchronization with the input first internal clock signal ICK1, and outputs the first processing data Dd1 obtained by processing the test pattern Dt to the BIST circuit 13a. .

  The internal circuit 12a may have a plurality of operation modes. In the present embodiment, the internal circuit 12a has two types of modes, a normal operation mode and a low power consumption mode. Therefore, the test pattern Dt includes test data for testing these two types of operation modes of the internal circuit 12a. As shown in FIG. 3, the internal circuit 12a includes a first test current consumption period K1 for processing test data for testing the normal mode and a second test for processing test data for testing the low power consumption mode. It has a current consumption period K2.

  Specifically, in this test pattern Dt, as shown in FIG. 3, when the second first internal clock signal ICK1 rises from the level to the H level, the internal circuit 12a starts the first test current consumption period K1, When the first internal clock signal ICK1 rises from the L level to the H level, the first test current consumption period K1 ends. The internal circuit 12a starts the second test current consumption period K2 when the 16th first internal clock signal ICK1 rises from the L level to the H level, and the 18th first internal clock signal ICK1 changes from the L level to the H level. As a result, the second test current consumption period K2 ends.

Hereinafter, the rise of the signal from the L level to the H level is simply referred to as the rise of the signal. Further, the fall of the signal from the H level to the L level is simply referred to as the fall of the signal.
In the internal circuits 12b to 12h of the second to sixteenth chips C2 to C16, the same test pattern Dt as that of the internal circuit 12a of the first chip C1 is input. Therefore, when the test pattern Dt is input, the first chip The circuit operates at the same timing as the internal circuit 12a of C1.

The BIST circuit 13a includes a test circuit 21a, a first selection circuit (also referred to as a selector or a multiplexer) 22a, and a D-flip flop (D-FF) circuit 23a.
The test circuit 21a receives the first internal clock signal ICK1 from the clock gating circuit 17a and the first processing data Dd1 from the internal circuit 12a. The test circuit 21a operates in synchronization with the first internal clock signal ICK1. First, the test circuit 21a outputs a test pattern Dt to the internal circuit 12a in synchronization with the first internal clock signal ICK1. Then, the test circuit 21a inputs the first processing data Dd1 obtained by processing the test pattern Dt by the internal circuit 12a from the internal circuit 12a in synchronization with the first internal clock signal ICK1. Next, the test circuit 21a determines whether or not the first processing data Dd1 input from the internal circuit 12a is equal to the expected value Dh for the test pattern Dt output to the internal circuit 12a.

  That is, when the first processing data Dd1 and the expected value Dh with respect to the test pattern Dt are equal, the test circuit 21a indicates that the internal circuit 12a has processed the test pattern Dt normally and shows a determination result of “good”. The 1-chip determination data ISr1 is output to the first selection circuit 22a. On the other hand, when the first processing data Dd1 and the expected value Dh for the test pattern Dt are not equal, the test circuit 21a indicates that the internal circuit 12a has not processed the test pattern Dt normally and shows a determination result of “bad”. The L-level first chip determination data ISr1 is output to the first selection circuit 22a.

  The first selection circuit 22a receives the first chip determination data ISr1 of H level or L level (“good” or “bad”) from the test circuit 21a. The first selection circuit 22a outputs the first chip determination data ISr1 as the first selection signal Sc1 to the D-FF circuit 23a based on the read signal Se from the test apparatus T1.

  The first selection circuit 22a outputs the first chip determination data ISr1 as the first selection signal Sc1 to the D-FF circuit 23a when the L level (non-read mode) read signal Se is output from the test apparatus T1. To do. In contrast, the first selection circuit 22a does not output the first selection signal Sc1 (first chip determination mode ISr1) when the H level (read mode) read signal Se is output from the test apparatus T1. ing.

  In the D-FF circuit 23a, the first selection signal Sc1 is input from the first selection circuit 22a to the data input terminal D, and the first internal clock signal ICK1 is input from the clock gating circuit 17a to the clock input terminal CK. . When the first internal clock signal ICK1 rises, the D-FF circuit 23a holds the first selection signal Sc1 (first chip determination data ISr1) as the first holding signal Sf1 and outputs it from the output terminal Q to the second chip C2. To do.

  The delay control circuit 14a controls the test start of the counter circuit 25a, the first and second storage devices 26a and 27a composed of a writable ROM or RAM, and the subsequent chip (in this case, the second chip C2). A start control circuit 28a and a test pause control circuit 29a for controlling the test pause of the subsequent-stage chip (in this case, the second chip C2) are provided.

  The counter circuit 25a receives the first internal clock signal ICK1 from the clock gating circuit 17a. The counter circuit 25a counts the first internal clock signal ICK1 and counts up the first count value Dc1. The counter circuit 25a outputs the first count value Dc1 to the test start control circuit 28a and the test suspension control circuit 29a.

  The test start control circuit 28a receives the first count value Dc1 from the counter circuit 25a and the test start value Ds from the first storage device 26a, compares the two values Dc1 and Ds, and compares the comparison result with the second start signal. The result is output to the second chip C2 as Ss2. Then, when the first count value Dc1 is smaller than the test start value Ds, the test start control circuit 28a outputs a second start signal Ss2 of L level (standby mode), and conversely, the first count value Dc1 starts the test. When the value is equal to or greater than the value Ds, an H level (start mode) second start signal Ss2 is output.

  In other words, the test start value Ds is a value indicating what number the first internal clock signal ICK1 rises to start the test of the subsequent stage (in this case, the second chip C2). In this embodiment, the test start value Ds The value Ds is “9”. That is, as shown in FIG. 3, the test start value Ds indicates that the test of the second chip C2 is started after the ninth first internal clock signal ICK1 rises and the first test current consumption period K1 ends. Show. That is, in order to shorten the test time, the test start control circuit 28a reduces the second chip C2 after the first test current consumption period K1 of the first chip C1 ends and before the second test current consumption period K2 starts. The second start signal Ss2 of H level (starting row mode) for starting the test is output to the second chip C2.

  The test pause control circuit 29a receives the first count value Dc1 from the counter circuit 25a, and the first test pause value Dh1 and the second test pause value Dh2 (> first test pause value Dh1) from the second storage device 27a. The test pause control circuit 29a compares the first count value Dc1 with the first test pause value Dh1 and the second test pause value Dh2. Then, the test suspension control circuit 29a outputs the comparison result to the second chip C2 as the second suspension signal Sh2.

  More specifically, when the first count value Dc1 is smaller than the first and second test pause values Dh1 and Dh2, the test pause control circuit 29a outputs a second pause signal Sh2 of H level (non-pause mode). The test pause control circuit 29a also sets the second L level (pause mode) when the first count value Dc1 is equal to or greater than the first test pause value Dh1 and the first count value Dc1 is smaller than the second test pause value Dh2. The pause signal Sh2 is output. Further, when the first count value Dc1 becomes equal to or higher than the first and second test pause values Dh1, Dh2, the test pause control circuit 29a sets the second pause signal Sh2 at the H level (non-pause mode). Is output.

  That is, the first test pause value Dh1 is a value indicating what number of the first internal clock signal ICK1 rises and the test of the subsequent chip (in this case, the second chip C2) is paused. The first test pause value Dh1 is “16”. That is, as shown in FIG. 3, the first test pause value Dh1 pauses the test of the second chip C2 when the 16th first internal clock signal ICK1 rises and the second test current consumption period K2 starts. Shows that

  The second test pause value Dh2 is a value indicating how many times the first internal clock signal ICK1 rises to restart the test of the subsequent chip (in this case, the second chip C2) from the pause. In the embodiment, the second test pause value Dh2 is “18”. That is, as shown in FIG. 3, the second test pause value Dh2 is used to test the second chip C2 when the 18th first internal clock signal ICK1 falls and the second test current consumption period K2 ends. Indicates to resume.

  Accordingly, the delay control circuit 14a is a signal for preventing the second chip C2 from performing a test during the first test current consumption period K1 and the second test current consumption period K2 of the test performed by the first chip C1. Is generated and output.

  The second chip C2 includes a clock signal control circuit 11b, an internal circuit 12b having a specific function, a BIST circuit 13b that performs a test of the internal circuit 12b, and a delay that delays a test start of a subsequent chip (in this case, the third chip C3). A control circuit 14b is included.

The clock signal control circuit 11b includes an AND circuit 16b and a clock gating circuit 17b.
The AND circuit 16b receives the second start signal Ss2 and the second pause signal Sh2 from the first chip C1. The AND circuit 16b outputs the second mode signal Sm2 to the clock gating circuit 17b based on the second start signal Ss2 and the second pause signal Sh2.

  In other words, the AND circuit 16b uses the clock gating circuit to generate the second mode signal Sm2 at the H level (test execution mode) when both the second start signal Ss2 and the second pause signal Sh2 are at the H level (start or non-pause mode). To 17b.

  When the second start signal Ss2 is at the L level (standby mode) or the input second start signal Ss2 is at the H level (start mode) and the second pause signal Sh2 is at the L level (clock gating circuit 17b In the pause mode), the second mode signal Sm2 of L level (test stop mode) is output to the clock gating circuit 17b.

  The clock gating circuit 17b receives the clock signal CK from the test apparatus T1 through the third pad P3. Based on the second mode signal Sm2, the clock gating circuit 17b outputs the clock signal CK to the internal circuit 12b, the BIST circuit 13b, and the delay control circuit 14b as the second internal clock signal ICK2.

  When the second mode signal Sm2 of H level (test execution mode) is input, the clock gating circuit 17b outputs the clock signal CK as the second internal clock signal ICK2. On the contrary, when the L-level (test stop mode) second mode signal Sm2 is input, the clock gating circuit 17b outputs no signal, that is, the input clock signal CK is used as the second internal clock signal ICK2. Do not pass.

  The internal circuit 12b receives the second internal clock signal ICK2 from the clock gating circuit 17b and the test pattern Dt from the BIST circuit 13b. The internal circuit 12b processes the test pattern Dt in synchronization with the second internal clock signal ICK2, and outputs the second processing data Dd2 obtained by processing the test pattern Dt to the BIST circuit 13b.

The BIST circuit 13b includes a test circuit 21b, a first selection circuit 22b, and a D-FF circuit 23b.
The test circuit 21b receives the second internal clock signal ICK2 from the clock gating circuit 17b and the second processing data Dd2 from the internal circuit 12b. The test circuit 21b operates in synchronization with the second internal clock signal ICK2. First, the test circuit 21b outputs a test pattern Dt to the internal circuit 12b in synchronization with the second internal clock signal ICK2. The test circuit 21b receives the second processing data Dd2 obtained by processing the test pattern Dt by the internal circuit 12b from the internal circuit 12b in synchronization with the second internal clock signal ICK2. Next, the test circuit 21b determines whether the second processing data Dd2 input from the internal circuit 12b is equal to the expected value Dh for the test pattern Dt output to the internal circuit 12b.

  That is, when the second processing data Dd2 is equal to the expected value Dh for the test pattern Dt, the test circuit 21b is at the H level indicating that the internal circuit 12b has processed the test pattern Dt normally. The second chip determination data ISr2 is output to the first selection circuit 22b. On the other hand, when the second processing data Dd2 and the expected value Dh for the test pattern Dt are not equal, the test circuit 21b indicates that the internal circuit 12b has not processed the test pattern Dt normally, and indicates a “bad” test result. The L-level second chip determination data ISr2 is output to the first selection circuit 22b.

  The first selection circuit 22b receives the second chip determination data ISr2 from the test circuit 21b and the first holding signal Sf1 (first chip determination data ISr1) from the D-FF circuit 23a of the first chip C1. The first selection circuit 22b outputs the D-FF circuit 23b using the second chip determination data ISr2 as the second selection signal Sc2 when the L level (non-read mode) read signal Se is output from the test apparatus T1. Output to. Conversely, the first selection circuit 22b receives the first holding signal Sf1 (from the D-FF circuit 23a of the first chip C1) when the H level (reading mode) read signal Se is output from the test apparatus T1. The first chip determination data ISr1) is output as the second selection signal Sc2.

  In the D-FF circuit 23b, the second selection signal Sc2 is input from the first selection circuit 22b to the data input terminal D, and the second internal clock signal ICK2 is input from the clock gating circuit 17b to the clock input terminal CK. . When the second internal clock signal ICK2 rises, the D-FF circuit 23b holds the second selection signal Sc2 as the second holding signal Sf2 and outputs it from the output terminal Q to the third chip C3.

  That is, in the test of the first to sixteenth chips C1 to C16, the D-FF circuit 23b holds the second selection signal Sc2 of the second chip determination data ISr2 as the second holding signal Sf2 and outputs it to the third chip C3. To do. When the test of the first to sixteenth chips C1 to C16 is completed and the test result is read (in the read mode), the D-FF circuit 23b receives the first holding signal Sf1 (first signal) of the first chip C1. The chip determination data ISr1) is held as the second holding signal Sf2 and output to the third chip C3.

  The delay control circuit 14b is a test that controls the test start of the counter circuit 25b, the first and second storage devices 26b and 27b configured by a writable ROM or RAM, and the subsequent chip (in this case, the third chip C3). The start control circuit 28b includes a test pause control circuit 29b that controls the test pause of the subsequent chip (in this case, the third chip C3).

  The counter circuit 25b receives the second internal clock signal ICK2 from the clock gating circuit 17b. The counter circuit 25b counts the second internal clock signal ICK2, and counts up the second count value Dc2. The counter circuit 25b outputs the second count value Dc2 to the test start control circuit 28b and the test suspension control circuit 29b.

  The test start control circuit 28b receives the second count value Dc2 from the counter circuit 25b and the test start value Ds from the first storage device 26b, compares the two values Dc1 and Ds, and compares the comparison result with the third start signal. It outputs to 3rd chip | tip C3 as Ss3. Then, when the second count value Dc2 is smaller than the test start value Ds, the test start control circuit 28b outputs a third start signal Ss3 of L level (standby mode), and conversely, the second count value Dc2 starts the test. When the value is equal to or greater than the value Ds, the third start signal Ss3 of H level (start mode) is output.

  The test pause control circuit 29b receives the second count value Dc2 from the counter circuit 25b, the first test pause value Dh1 and the second test pause value Dh2 (> first test pause value Dh1) from the second storage device 27b. To do. The test pause control circuit 29b compares the second count value Dc2 with the first test pause value Dh1 and the second test pause value Dh2. Then, the test suspension control circuit 29b outputs the comparison result to the third chip C3 as the third suspension signal Sh3.

  More specifically, when the second count value Dc2 is smaller than the first and second test pause values Dh1 and Dh2, the test pause control circuit 29b outputs a third pause signal Sh3 of H level (non-pause mode). The test pause control circuit 29b also sets the third L level (pause mode) when the second count value Dc2 is equal to or greater than the first test pause value Dh1 and the second count value Dc2 is smaller than the second test pause value Dh2. The pause signal Sh3 is output. Further, when the second count value Dc2 becomes equal to or higher than the first and second test pause values Dh1 and Dh2, the test pause control circuit 29b outputs a third pause signal Sh3 of H level (non-pause mode). Yes.

  Accordingly, the delay control circuit 14b is a signal for preventing the third chip C3 from performing the test during the first test current consumption period K1 and the second test current consumption period K2 of the test performed by the second chip C2. Is generated and output.

Next, operations of the first and second chips C1 and C2 configured as described above will be described with reference to FIG.
Now, as a standby state, the test apparatus T1 outputs a first start signal Ss1 of L level (standby mode), a first pause signal Sh1 of H level (non-pause mode), and a clock signal CK to the first chip C1. Yes.

  First, when the clock signal CK rises at time t1, the test apparatus T1 outputs a first start signal Ss1 of H level (start mode). When the H level (start mode) first start signal Ss1 is output, the clock gating circuit 17a of the first chip C1 uses the clock signal CK as the first internal clock signal ICK1, and the internal circuit 12a of the first chip C1, BIST It outputs to the circuit 13a and the delay control circuit 14a. The BIST circuit 13a of the first chip C1 starts a test of the internal circuit 12a of the first chip C1 in synchronization with the first internal clock signal ICK1 from the clock gating circuit 17a of the first chip C1.

  At time t2, that is, when the second first internal clock signal ICK1 rising from time t1 rises, the current consumption Ia of the first chip C1 increases and the first test current consumption period K1 is entered.

  That is, the internal circuit 12a receives the test pattern Dt from the BIST circuit 13a and the first internal clock signal ICK1 from the clock gating circuit 17a. Then, the internal circuit 12a starts processing the test pattern Dt in synchronization with the first internal clock signal ICK1, and increases the current consumption Ia.

  At time t3, that is, when the ninth first internal clock signal ICK1 rises from time t1, the current consumption Ia of the first chip C1 decreases and the first test current consumption period K1 ends. That is, at time t3, the internal circuit 12a of the first chip C1 completes the processing of the test pattern Dt, so that its current consumption Ia decreases.

  At the time t3, that is, when the ninth first internal clock signal ICK1 rises from the time t1, the counter circuit 25a of the first chip C1 counts the first internal clock signal ICK1, and the first count value Dc1 Becomes “9”. As a result, the first count value Dc1 and the test start value Ds become equal, and the test start control circuit 28a of the first chip C1 becomes H level (start mode) when the next first internal clock signal ICK1 rises (time t4). ) Second start signal Ss2 is output to the second chip C2.

  When the second start signal Ss2 of H level is input, the clock gating circuit 17b of the second chip C2 uses the clock signal CK as the second internal clock signal ICK2, and the internal circuit 12b, the BIST circuit 13b, and the delay control of the second chip C2. Output to the circuit 14b. The BIST circuit 13b of the second chip C2 starts a test of the internal circuit 12b of the second chip C2 in synchronization with the second internal clock signal ICK2 from the clock gating circuit 17b of the second chip C2.

  At time t5, that is, when the eleventh first internal clock signal ICK1 rises from time t1, the current consumption Ib of the second chip C2 increases, and the second chip C2 has a first test current consumption period K1. to go into. That is, the internal circuit 12b of the second chip C2 receives the test pattern Dt from the BIST circuit 13b of the second chip C2 and the second internal clock signal ICK2 from the clock gating circuit 17b of the second chip C2. . The internal circuit 12b of the second chip C2 starts processing the test pattern Dt in synchronization with the second internal clock signal ICK2, and increases the current consumption Ib.

  At time t6, that is, when the fifteenth first internal clock signal ICK1 rises from time t1, the counter circuit 25a of the first chip C1 counts the rise of the first internal clock signal ICK1, 1 count value Dc1 becomes “15”.

  As a result, when the first count value Dc1 and the first test pause value Dh1 become equal and then the first internal clock signal ICK1 falls (time t7), the test pause control circuit 29a of the first chip C1 is set to the L level. The second pause signal Sh2 in (pause mode) is output to the second chip C2.

  When the L-level second pause signal Sh2 is input, the clock gating circuit 17b of the second chip C2 outputs nothing, that is, the clock signal CK is not output as the second internal clock signal ICK2. Since the second internal clock signal ICK2 is not input to the BIST circuit 13b of the second chip C2, the test of the internal circuit 12b of the second chip C2 is paused and the current consumption Ib of the second chip C2 decreases.

  At time t8, that is, when the 18th first internal clock signal ICK1 rises from time t1, the counter circuit 25a of the first chip C1 counts the rise of the first internal clock signal ICK1, The one count value Dc1 is “18”.

  As a result, when the first count value Dc1 and the second test pause value Dh2 become equal and then the first internal clock signal ICK1 falls (time t9), the test pause control circuit 29a of the first chip C1 Assuming that the internal circuit 12a of the chip C1 finishes the processing of the test pattern Dt, the second pause signal Sh2 of H level (non-pause mode) is output to the second chip C2.

  When the internal circuit 12a of the first chip C1 finishes the processing of the test pattern Dt, the test circuit 21a determines the quality of the test of the first chip C1 based on the first processing data Dd1 and the expected value Dh. The first chip determination data ISr1, which is the determination result, is output to the first selection circuit 22a.

  On the other hand, when the second chip C2 receives the second pause signal Sh2 at the H level (non-pause mode), the clock gating circuit 17b of the second chip C2 uses the clock signal CK as the second internal clock signal ICK2 and the second signal again. The data is output to the internal circuit 12b, the BIST circuit 13b, and the delay control circuit 14b of the chip C2. The BIST circuit 13b of the second chip C2 restarts the test of the internal circuit 12b of the second chip C2 in synchronization with the second internal clock signal ICK2 from the clock gating circuit 17b of the second chip C2.

  At time t10, that is, when the 19th first internal clock signal ICK1 rises from time t1, the second chip C2 returns to the first test current consumption period K1 and increases its consumption current Ib. .

  At time t11, that is, when the ninth second internal clock signal ICK2 rises from time t4, the first test consumption period of the second chip C2 decreases, and the first test current consumption of the second chip C2 decreases. Period K1 ends.

  At time t11, the counter circuit 25b of the second chip C2 counts the second internal clock signal ICK2, and the second count value Dc2 becomes “9”. As a result, the second count value Dc2 and the test start value Ds become equal, and the test start control circuit 28b of the second chip C2 next rises to the H level (start mode) when the second internal clock signal ICK2 rises (time t12). ) Of the third start signal Ss3 is output to the third chip C3.

  The third to sixteenth chips C3 to C16 have the same configuration as the first and second chips C1 and C2. As a result, when the first chip C1 receives the first start signal Ss1 at the H level from the test apparatus T1, the first to sixteenth chips C1 to C16 receive the first chip C1, the second chip C2, the third chip C3, ··········· Test in order of 16th chip C16. Hereinafter, the members of the third to sixteenth chips C3 to C16, which are the same as the members constituting the first and second chips C1 and C2, are not shown, but are given the same reference numerals and suffixes c to h, respectively. I will explain.

  That is, the first to sixteenth chips C1 to C16 sequentially start up the first to sixteenth start signals Ss1 to Ss16 shown in FIG. 1 each time each count value is equal to the test start value Ds. Therefore, the first to sixteenth chips C1 to C16 can shift the start of the first test current consumption period K1.

  In the first to sixteenth chips C1 to C16, based on the first to sixteenth pause signals Sh1 to Sh16, the second test current consumption period K2 of the former stage chip and the first test current consumption period K1 of the latter stage chip overlap. I try not to be.

  In other words, in the first to sixteenth chips C1 to C16, the second test current consumption period K2 of the preceding chip starts, and when each count value becomes equal to the first test pause value Dh1, the first test current consumption period K1 of the subsequent chip. Pause the test. The first to sixteenth chips C1 to C16 end the first test current consumption of the subsequent chip when the second test current consumption period K2 of the previous chip ends and each count value provided becomes equal to the second test pause value Dh2. The test for period K1 is resumed.

  Finally, when the test of the sixteenth chip C16 is completed, the D-FF circuits 23a to 23h of the first to sixteenth chips C1 to C16 have the first to sixteenth test results of their own internal circuits 12a to 12h. Chip determination data ISr1 to ISr16 are held.

Next, a description will be given of after the first to sixteenth chips C1 to C16 have all been tested.
When all the tests of the first to sixteenth chips C1 to C16 are completed, the test apparatus T1 outputs the H level (read mode) read signal Se to the first selection circuit 22a of the first to sixteenth chips C1 to C16. .

When the first selection circuit 22a of the first chip C1 receives the H level read signal Se, the first chip C1 does not select anything because there is no preceding chip.
When the first selection circuit 22b of the second chip C2 receives the read signal Se at the H level, the first holding signal Sf1 from the first chip C1 is selected as the second selection signal Sc2 and is output to the D-FF circuit 23b. .

  When the first selection circuit 22c of the third chip C3 receives the H level read signal Se, the first selection signal Sc3 from the second chip C2 is selected as the third selection signal Sc3 and is output to the D-FF circuit 23c. .

  Similarly to the above, in the first selection circuits 22d to 22h of the fourth to sixteenth chips C4 to C16, the first selection circuits 22d to 22h are based on the read signal Se of the H level (read mode). The third to fifteenth holding signals Sf3 to 15 are selected and output to the D-FF circuits 23d to 23h as the fourth to sixteenth selection signals Sc4 to Sc16.

  That is, when the H level (read mode) read signal Se is output from the test apparatus T1, the D-FF circuits 23a to 23h of the first to sixteenth chips C1 to C16 have a shift register configuration. Each time the clock signal CK is input, the first to sixteenth holding signals Sf1 to Sf16 (first to sixteenth chip determination data ISr1 to ISr16) held by the preceding chip in each D-FF circuit are as follows. The sixteenth holding signal Sf16, the fifteenth holding signal Sf15, the fourteenth holding signal Sf14,..., The first holding signal Sf1 in this order from the sixteenth chip C16 as the test result signal Sr via the seventh pad P7. It is output to the test apparatus T1.

As described above, according to the present embodiment, the following effects can be obtained.
(1) Based on the first start signal Ss1 and the first pause signal Sh1, the clock signal control circuit 11a uses the clock signal CK from the test apparatus T1 as the first internal clock signal ICK1, the internal circuit 12a, the BIST circuit 13a, the delay Output to the control circuit 14a. The BIST circuit 13a starts a test of the internal circuit 12a in synchronization with the first internal clock signal ICK1. The counter circuit 25a of the delay control circuit 14a counts the rising edge of the first internal clock signal ICK1, and counts up the first count value Dc1. Then, the test start control circuit 28a of the delay control circuit 14a outputs the second start signal Ss2 at the H level to the second chip C2 when the first count value Dc1 and the test start value Ds become equal.

  Therefore, in the first to sixteenth chips C1 to C16, the test of the subsequent chip can be started after the first test current consumption period K1 of the previous chip ends based on the test start value Ds. As a result, when the element variation in the process step becomes large or when the test program is changed, the delay amount of the subsequent chip with respect to the previous chip is adjusted without changing the circuit only by changing the test start value Ds. be able to.

  (2) Further, when the first count value Dc1 and the first test pause value Dh1 are equal, the test pause control circuit 29a of the delay control circuit 14a outputs the L-level second pause signal Sh2 to the second chip C2. The test of the second chip C2 is suspended. Then, when the first count value Dc1 and the second test pause value Dh2 are equal, the test pause control circuit 29a of the delay control circuit 14a outputs a second pause signal Sh2 of H level to the second chip C2 to perform the test. It was made to resume.

Therefore, in the first to sixteenth chips C1 to C16, the test of the first test current consumption period K1 of the subsequent stage chip can be suspended in the test of the second test current consumption period K2 of the previous stage chip. As a result, while maintaining the total current consumption of the first to sixteenth chips C1 to C16 below the allowable current of the test apparatus T1, the test apparatus T1 can start the test of the subsequent chip before the end of the test of the previous chip. Test time can be shortened.
(Second Embodiment)
In the first embodiment, the first to sixteenth chips C1 to C16 are tested one by one. In the second embodiment, a plurality of tests of the first to sixteenth chips C1 to C16 can be performed simultaneously. Hereinafter, a case where two tests of the first to sixteenth chips C1 to C16 are performed will be described according to FIGS. 4 and 5 with a focus on differences from the first embodiment. The same members as those shown in FIGS. 1 and 2 are denoted by the same reference numerals, and description of these elements is omitted for convenience of description.

  As shown in FIG. 4, in order to perform two tests on the first to sixteenth chips C1 to C16 simultaneously, each of the chips C1 to C16 includes the second and third selection circuits 32 and 33 and the third storage device 34. Each has. The third storage device 34 of the first to sixteenth chips C1 to C16 stores first to sixteenth selection control values Da1 to Da16 corresponding to the chips C1 to C16.

  The second selection circuit 32 of each of the chips C1 to C16 performs first to sixteenth selection control on the first to sixteenth start signals Ss1 to Ss16 from the preceding chip and the first to sixteenth start signals Ss1 to Ss16 generated by itself. Either one of them is passed according to the values Da1 to Da16. When the second selection circuit 32 receives the first to sixteenth selection control values Da1 to Da16 of “0”, the second selection circuit 32 passes the first to sixteenth start signals Ss1 to Ss16 from the preceding chip. On the contrary, when the 1st to 16th selection control values Da1 to Da16 of “1” are input, the second selection circuit 32 passes the 1st to 16th start signals Ss1 to Ss16 generated by itself.

  The third selection circuit 33 responds to the first to sixteenth selection control values Da1 to Da16 with the first to sixteenth suspension signals Sh1 to Sh16 from the previous chip and the first to sixteenth suspension signals Sh1 to Sh16 generated by itself. Pass one of them. The third selection circuit 33, when receiving the first to sixteenth selection control values Da1 to Da16 of “0”, passes the first to sixteenth pause signals Sh1 to Sh16 from the preceding chip. On the other hand, when the first to sixteenth selection control values Da1 to Da16 of “1” are input, the third selection circuit 33 passes the first to sixteenth pause signals Sh1 to Sh16 generated by itself.

  The first and second chips C1 and C2 perform a test simultaneously based on the first start signal Ss1 and the first pause signal Sh1 from the test apparatus T1. For this reason, the second and third selection circuits 32 and 33 of the first chip C1 pass the first start signal Ss1 and the first pause signal Sh1 from the test apparatus T1, and the second start signal Ss2 generated by itself and The second pause signal Sh2 is not allowed to pass. Accordingly, the first selection control value Da1 of “0” is stored in the third storage device 34 of the first chip C1.

  The third and fourth chips C3 and C4 simultaneously test based on the third start signal Ss3 and the third pause signal Sh3 from the second chip C2. Therefore, the second and third selection circuits 32 and 33 of the second chip C2 pass the third start signal Ss3 and the third pause signal Sh3 generated by themselves, and the second start signal Ss2 from the first chip C1. The second pause signal Sh2 is not allowed to pass. Accordingly, the second selection control value Da2 of “1” is stored in the third storage device 34 of the second chip C2.

  The second and third selection circuits 32 and 33 of the third chip C3 pass the third start signal Ss3 and the third pause signal Sh3 from the second chip C2, and generate the fourth start signal Ss4 and the fourth generated by the second chip C3. The pause signal Sh4 is not allowed to pass. Accordingly, the third storage device 34 of the third chip C3 stores the third selection control value Da3 of “0”.

  Similarly to the above, the fifth to sixteenth chips C5 to C16 have the fifth and sixth chips C5 and C6 based on the fifth start signal Ss5 and the fifth pause signal Sh5 from the fourth chip C4. Based on the seventh start signal Ss7 and the seventh pause signal Sh7 from the sixth chip C6, the ninth and tenth chips C9, C10 receive the ninth start signal Ss9 from the eighth chip C8 and the eighth chip C7, C8. Based on the ninth pause signal Sh9, the eleventh and twelfth chips C11, C12 are based on the eleventh start signal Ss11 and the eleventh pause signal Sh11 from the tenth chip C10, and the thirteenth and fourteenth chips C13, C14 are Based on the thirteenth start signal Ss13 and the thirteenth pause signal Sh13 from the twelfth chip C12, the fifteenth and sixteenth chips C15 and C16 receive the thirteenth from the fourteenth chip C14. For 5 start signal Ss15 and tested according to the 15 rest signal Sh15 respectively.

Accordingly, the fourth to sixteenth delay control values Da4 to Da16 of the fourth to sixteenth chips C4 to C16 are as shown in Table 60 of FIG.
Specifically, the fourth selection control value Da4 of the fourth chip C4 is “1”, the fifth selection control value Da5 of the fifth chip C5 is “0”, and the sixth selection control value Da6 of the sixth chip C6 is “ 1 ”,..., The fifteenth selection control value Da15 of the fifteenth chip C15 is“ 0 ”, and the sixteenth selection control value Da16 of the sixteenth chip C16 is“ 1 ”.

As described above, according to the present embodiment, the following effects can be obtained.
(1) Based on the first to sixteenth selection control values Da1 to Da16, the second selection circuit 32 of the first to sixteenth chips C1 to C16 starts from its second to sixteenth start signals Ss2 to Ss16 or from the previous stage. Any one of the first to fifteenth start signals Ss1 to Ss15 is allowed to pass.

  Further, the third selection circuits 33 of the first to sixteenth chips C1 to C16 are based on the first to sixteenth selection control values Da1 to Da16, and the second to the sixteenth pause signals Sh2 to Sh16, or from the previous stage. Any one of the first to fifteenth pause signals Sh1 to Sh15 is allowed to pass.

Therefore, since the two chips can be tested simultaneously in the test of the first to sixteenth chips C1 to C16, the test time can be shortened.
In addition, you may implement the said embodiment in the following aspects.

  In the present embodiment, the first to sixteenth chips C1 to C16 having two first and second test current consumption periods K1 and K2 in the test are embodied. However, the first to sixteenth test current consumption periods have three or more test current consumption periods. The first to sixteenth chips C1 to C16 may be embodied.

  Along with this change, the delay control circuits 14a to 14p of the first to sixteenth chips C1 to C16 have the test pause circuits for the number of test current consumption periods and the first and second test pause values Dh1 for each test current consumption period. , Dh2 is stored. The front chip needs to stop the test of the rear chip every test current consumption period.

Therefore, the same effects as in the present embodiment can be obtained even in the first to sixteenth chips C1 to C16 having three or more test current consumption periods in the test.
In the present embodiment, the wafer W1 has the first to sixteenth chips C1 to C16. However, the number of chips included in the wafer W1 is not particularly limited.

  In the second embodiment, two chips are tested simultaneously in the tests of the first to sixteenth chips C1 to C16. However, the present invention is not limited to this, and three or more chips may be tested simultaneously.

  For example, in the test of the first to sixteenth chips C1 to C16, when four chips are tested simultaneously, the first to fourth chips C1 to C4 are changed from the test apparatus T1 to the first start signal Ss1 and the first pause signal Sh1. The fifth to eighth chips C5 to C8 are based on the fifth start signal Ss5 and the fifth pause signal Sh5 from the fourth chip C4, and the ninth to twelfth chips C9 to C12 are based on the eighth chip C8. Based on the ninth start signal Ss9 and the ninth pause signal Sh9, the thirteenth to sixteenth chips C13 to C16 perform tests based on the thirteenth start signal Ss13 and the thirteenth pause signal Sh13 from the twelfth chip C12, respectively. become.

  Therefore, in the test of the first to sixteenth chips C1 to C16, when three or more chips are tested at the same time, the test time can be shortened compared to testing two chips simultaneously.

11a to 11p Clock signal control circuit 12a to 12p Internal circuit 13a to 13p BIST circuit 14a to 14p Delay control circuit 26a to 26p, 27a to 27p Storage devices (first and second storage devices)
32 First delay selection circuit (second selection circuit)
33 Second delay selection circuit (third selection circuit)
C1-C16 semiconductor device (chip)
CK clock signal Dc1 to Dc16 count value (first to sixteenth count value)
ICK1 to ICK16 first and second internal clock signals (first to sixteenth internal clock signals)
Sh1 to Sh16 first and second pause signals (first to sixteenth pause signals)
Ss1 to Ss16 first and second start signals (first to sixteenth start signals)
T1 test equipment W1 semiconductor device substrate

Claims (5)

A plurality of semiconductor devices formed by serial connection to a semiconductor device substrate and tested by a test device,
A clock signal control circuit for supplying a clock signal to the internal circuit as a first internal clock signal based on the first start signal from the test apparatus or the semiconductor device in the previous stage;
Has a counter circuit for counting said first internal clock signal, said counter circuit based on a count value obtained by counting the first internal clock signal, the second internal the clock signal to the internal circuit in the subsequent stage of the semiconductor device have a delay control circuit for delaying and outputting the second start signal to a subsequent stage of the semiconductor device for supplying a clock signal,
The clock signal control circuit includes:
Based on the first start signal and the first pause signal from the previous test apparatus or the semiconductor device, the clock signal is supplied to the internal circuit as the first internal clock signal,
The delay control circuit includes:
Based on the count value of the counter circuit, a second pause signal for halting the supply of the second internal clock signal to the internal circuit of the subsequent semiconductor device during the circuit operation of the counter circuit is provided to the subsequent semiconductor device. semiconductor device and outputs. The semiconductor device according to claim 1 ,
The delay control circuit includes:
A first delay selection circuit that outputs the first start signal or a signal obtained by delaying the first start signal as the second start signal to the subsequent semiconductor device;
A semiconductor device comprising: a second delay selection circuit that outputs the first pause signal or a signal obtained by delaying the first pause signal as the second pause signal to the subsequent semiconductor device. The semiconductor device according to claim 2 ,
The delay control circuit includes:
A storage device in which the start and end of a period during which a large amount of current flows in the semiconductor device in the test is stored as the count value;
The count value stored in the storage device is compared with the count value obtained by counting the first internal clock signal, and the second start signal and the second pause signal are output according to the comparison result. A semiconductor device. The semiconductor device according to claim 3 ,
A semiconductor device comprising: a BIST circuit that receives the first internal clock signal from the clock signal control circuit and tests the internal circuit in synchronization with the first internal clock signal. A semiconductor device test method in which a plurality of semiconductor devices are serially connected to a semiconductor device substrate and tested by a test device,
Supplying a clock signal as a first internal clock signal to an internal circuit based on a first start signal from the test apparatus or the semiconductor device in the previous stage;
Has a counter circuit for counting said first internal clock signal, said counter circuit based on a count value obtained by counting the first internal clock signal, the second internal the clock signal to the internal circuit in the subsequent stage of the semiconductor device a second start signal for supplying a clock signal by delaying a subsequent stage of the semiconductor device have a and outputting,
In the step of supplying the clock signal to the internal circuit as a first internal clock signal,
Based on the first start signal and the first pause signal from the previous test apparatus or the semiconductor device, the clock signal is supplied to the internal circuit as the first internal clock signal,
In the step of delaying and outputting the second start signal to the subsequent semiconductor device,
Based on the count value of the counter circuit, a second pause signal for halting the supply of the second internal clock signal to the internal circuit of the subsequent semiconductor device during the circuit operation of the counter circuit is provided to the subsequent semiconductor device. A method for testing a semiconductor device, comprising: outputting .

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