JP5344371B2 - Circuit verification apparatus, method and program - Google Patents

Description

  The present invention relates to a circuit verification apparatus, method, and program, and more particularly, to a circuit verification apparatus, method, and program such as a debug control apparatus for a circuit including a plurality of processors.

  With the progress of semiconductor technology, the degree of integration of semiconductor devices (logical LSI (Large Scale Integrated circuit)) has been improved year by year, and it has become possible to integrate a large-scale system on a single chip. For this reason, it has become possible to integrate a complicated system, which has conventionally been composed of a plurality of semiconductor devices, on a single chip. In addition, since semiconductor devices are difficult to modify and costly, semiconductor devices that use a CPU (Central Processing Unit), DSP (Digital Signal Processor), or the like whose functional operation can be changed by software even after being chipped. Devices have increased in recent years. Further, since a processor adapted to the processing content is used, it is general that there is not one kind of processor built in one chip.

  Debugging the processor sets breakpoints in a program that runs mainly on the processor, refers to the state of the processor (program counter and register values) at the time of the break, and stores the values of variables in the program (stored at a certain address) Or the value of the specified memory).

  There are mainly two methods for realizing breakpoints. One is that the event detection circuit (DCU, debug control circuit) added to the processor detects a break condition, temporarily interrupts the processor and moves the processing to the interrupt routine to temporarily control the program operation. A hardware break to stop. The other is by rewriting the corresponding instruction into a trap instruction (instruction that generates a software interrupt), and when the corresponding instruction is executed, the processor itself generates an interrupt and moves the process to the interrupt routine. A software break that temporarily stops program operation.

  Since hardware breaks are interrupted using a circuit, there are limitations such as the number of breakpoints set in advance in the processor can be set at the same time. On the other hand, the software break is not limited in this way, but is executed by rewriting the instruction. Therefore, it is essential to provide the processor with a function for rewriting the instruction. Therefore, when the instruction is stored in a ROM (Read Only Memory), there is a restriction that a software break cannot be used (see Patent Document 1).

  A general configuration of a circuit including a processor of related technology will be described with reference to FIG.

  The circuit shown in FIG. 1 includes a processor 100, a bus 101, a debug memory 102, an instruction memory 103, a data memory 104, a peripheral circuit A 105, a peripheral circuit B 106, and a debug control unit 107.

  The processor 100 acquires a program (instruction sequence) from the instruction memory 103 and the debug memory 102 through the bus 101 and performs an operation.

  The debug memory 102 is a part of the memory space of the processor 100, and is configured to return the value from the debug memory 102 instead of the instruction memory 103 when the processor 100 accesses the corresponding memory space. Yes. Further, the debug memory 102 is connected to the debug control unit 107 and can be read / written from outside the semiconductor device without going through the processor 100, thereby enabling debugging of the processor 100.

  Further, it is assumed that the peripheral circuit A 104 and the peripheral circuit B 105 are also connected to the bus 101.

  Here, when the processor 100 is in the debug mode (the state in which the processor 100 refers to the debug memory area), an instruction that saves the instruction at the address where the breakpoint is set is written in the debug memory 102. The processor 100 executes it to save the corresponding instruction (implementation of software breakpoint).

  More specifically, 1) an instruction for setting a breakpoint is stored in a register (can be realized by a load instruction), 2) a trap instruction is stored in a register (can be realized by a load instruction), and 3) an operation code of the trap instruction is stored. The stored register value is stored at the address of the breakpoint (which can be realized by a store instruction). An instruction string is written into the debug memory 102 and executed by the processor 100 itself, thereby realizing a software breakpoint.

  When observing the register value, the processor 100 executes an instruction (store instruction) for the processor 100 to write the register value to the debug memory 102, and the debug control unit 107 reads the value written to the debug memory 102. This is realized. In register writing, a load instruction describing a value to be set in the register is written in the debug memory 102 through the debug control unit 107, and the processor 100 executes the instruction to write the register. As another method, the debug control unit 107 may directly read / write a register in the processor 100. The reading and writing of the data memory 104 is the same, and the value of the program variable is realized by analyzing the instruction code string to grasp the position in the stack and reading the data memory 104 together with the value of the stack pointer. Variable overwriting is exactly the same.

  The debug memory 102 may be composed of, for example, 1) a code for stopping the processor 100, 2) a code to be processed (for example, a store instruction for register observation, etc.), and 3) a jump instruction to 1) above. Therefore, it is possible to cope with a very small memory area, and there are cases in which a register file or a plurality of registers are used instead of the memory.

  The debugging technique shows a general concept, and other different realization methods can be considered. The debugging function (reading and rewriting of registers and memories) is realized using the original functions of the processor (functions for storing register values in memory and loading memory values into registers). Even during debugging, the clock supply to the processor cannot be stopped. If the clock supply to the processor is stopped, communication with the processor becomes impossible, and the state cannot be grasped at all.

  The above description is a debugging form using ICE (In-Circuit Emulator), but recently, with the development of emulation technology using a dedicated processor or FPGA (Field Programmable Gate Array), the processor is an emulator. There is also an increasing number of programs that are implemented on the PC and debug programs on it.

  In the verification using the emulation technology, the same verification is performed by connecting the actual ICE to the processor that is being emulated externally in the same way as an actual semiconductor device, and the clock signal of the circuit being emulated is controlled and debugged. There is a method (see Patent Document 2).

  The former has only the semiconductor chip as an emulator, and the details are the same as described above. The latter method is realized by constantly observing an interrupt signal to the processor (for example, 108 in FIG. 1) and stopping the clock signal supplied to the entire circuit when the interrupt signal is generated. . Since the entire circuit mounted on the emulator stops operating, the circuit operation can be resumed by starting the clock supply again.

  In addition, since a general emulator can check all internal states with dedicated hardware, there is an advantage that problems such as inability to observe like ICE do not occur even when the clock to the processor is stopped. .

JP 2007-004516 A JP 2001-209556 A

  In debugging using hardware breaks or software breaks, the clock signal is always supplied, so the program execution of the corresponding processor is temporarily stopped, but other processors and peripheral circuits (peripheral circuit in FIG. 1). Since A and the peripheral circuit B) are supplied with the clock, the operation continues. For this reason, the operation timing of the processor and the peripheral circuit becomes inconsistent with the actual operation, and there is a problem that it does not operate normally due to a break. In addition, when a processor is entered into debug mode due to a break due to a break, other processors are operating normally, and there is a problem that the status of the processor other than the processor that has entered debug mode cannot be known. . This is the biggest problem in debugging when a plurality of processors operate in cooperation.

  On the other hand, although the clock control method of the hardware emulator solves this problem, the clock to the processor is stopped when a break occurs, so the program counter does not write back due to the processor pipeline. Problems such as the location and register values do not match. Furthermore, since recent processors have become complex, a processor described in a hardware description language typified by Verilog and VHDL (Very high speed IC Hardware Description Language) is required to obtain an accurate program counter value. There are also problems that need to be corrected.

  As described above, when debugging a circuit having a plurality of processors, the operation of the broken processor temporarily stops, but other processors and peripheral circuits continue to operate. This is the cause of the time being lost. On the other hand, when the break is realized for the peripheral circuit, the program on the processor continues to operate, and the same problem occurs.

  It is an object of the present invention to make it possible to observe the state of all the processors when a certain processor shifts to the debug mode, so that other processors also shift to the debug mode at the same time. The present invention also provides a circuit verification apparatus, method, and system that can resume the operation in the same manner as when the entire clock is stopped, and solve the program counter and register mismatch problem caused by the processor pipeline. is there.

  In order to achieve the above object, a circuit verification apparatus according to the present invention is an apparatus for verifying the operation of a circuit including a plurality of processors that perform operation verification by interrupt control and peripheral circuits other than the processor. A break detecting means for detecting whether a state of a signal from the circuit matches a preset break condition, and generating a break signal when the condition is met; a break signal from the processor; and a break detecting means from the break detecting means Interrupt control means for detecting a break signal and inputting an interrupt signal to all processors, clock control means for controlling a clock signal supplied to the processor and the peripheral circuit, and a break transmitted by the interrupt control means The generation is transmitted to the clock control means, and the break detection means and the debug control means of the processor Central control means for performing control, and the interrupt control means interrupts all processors included in the circuit when a break signal from the break detection means is detected and when a break signal from the processor is detected. When the interrupt control means detects a break signal, the clock control means supplies a clock signal to the processor and does not supply a clock signal to the peripheral circuit.

  The circuit verification method according to the present invention is a method for verifying the operation of a circuit including a plurality of processors that perform operation verification by interrupt control and a peripheral circuit other than the processor, wherein the break detection means includes Whether or not the state of the signal of the signal matches a preset break condition and generates a break signal if the condition is satisfied, and the interrupt control means receives the break signal from the processor and the break detection means The break signal is detected and an interrupt signal is input to all processors, the clock control means controls the clock signal supplied to the processor and the peripheral circuit, and the central control means is transmitted by the interrupt control means. Break occurrence is transmitted to the clock control means, and the break detection means and the debug control means of the processor are controlled. The interrupt control means inputs an interrupt signal to all processors included in the circuit when it detects a break signal from the break detection means and when it detects a break signal from the processor, The clock control means supplies a clock signal to the processor as soon as the interrupt control means detects a break signal, and does not supply a clock signal to the peripheral circuit.

  A circuit verification program according to the present invention is a program for verifying the operation of a circuit including a plurality of processors that perform operation verification by interrupt control and a peripheral circuit other than the processor. Detects whether or not the condition matches a preset break condition, and generates a break signal when the condition is met, and detects a break signal from the processor and a break signal from the break detection means Interrupt control means for inputting an interrupt signal to all the processors, clock control means for controlling a clock signal supplied to the processor and the peripheral circuit, and the occurrence of a break transmitted by the interrupt control means in the clock The break detection means and the processor debug control The interrupt control means is a program that functions as a central control means that performs control of the above-described control, and the interrupt control means includes all the circuits included in the circuit when a break signal is detected from the break detection means and when a break signal from the processor is detected. An interrupt signal is input to the processor, and the clock control means supplies a clock signal to the processor as soon as the interrupt control means detects a break signal, and does not supply a clock signal to the peripheral circuit. .

  According to the present invention, the following effects can be obtained.

  The first effect is that when a certain processor shifts to the debug mode, the other processors also shift to the debug mode, so that the states of all the processors in the system can be acquired through the central control means.

  The reason is that when one processor reaches a breakpoint, another processor is configured to interrupt similarly. Furthermore, even if the break condition is satisfied in the peripheral circuit, all processors are interrupted to enter debug mode, temporarily suspend program execution, stop supplying the clock signal to the peripheral circuit, and resume operation. This is because the number of clock signals to be input is adjusted according to the specification of the return instruction so that all processors and peripheral circuits can start operating simultaneously.

  For the same reason, the second effect is that the clock control means adjusts the number of input clock signals according to the specifications of each return instruction so that all processors and peripheral circuits can start operation simultaneously. A system including a processor also has an effect of enabling debugging while having all the above effects.

  As a third effect, since the clock continues to be supplied to the processor even in the debug mode, the program counter value and the register value do not coincide with each other when the processor is pipelined as in the emulator (Patent Document 2). There is also an effect that can be solved.

  As a fourth effect, when the circuit is mounted on the emulator described in Patent Document 2, it is necessary to correct the circuit description. However, the present invention is configured to make the most of the functions realized in the current processor. Therefore, the correction is minimized (with an interrupt), and there is an effect of greatly reducing the number of corrections.

It is a block diagram which shows the general structure of the circuit containing the processor of related technology. 1 is a block diagram showing an overall configuration of a debug control device which is a circuit verification device according to a first embodiment of the present invention. 3 is a timing chart showing an operation of the debug control device shown in FIG. 2. It is a specific example which shows the memory for debugging (operation | movement of the processor in debug mode). It is a flowchart which shows operation | movement of the debug control apparatus shown in FIG. It is a block diagram which shows the whole structure of the debug control apparatus which is a circuit verification apparatus which concerns on the 2nd Embodiment of this invention. It is a flowchart which shows operation | movement of the debug control apparatus shown in FIG.

  Next, embodiments of a circuit verification apparatus, method, and program according to the present invention will be described in detail with reference to the drawings.

(First embodiment)
First, a first embodiment of the present invention will be described with reference to FIGS.

  Referring to FIG. 2, the debug control device which is a circuit verification device according to the present embodiment is roughly divided into a processor block A 200.1, a processor block B 200.2, a peripheral circuit 201, a break detection unit (break detection unit). Means) 203, an interrupt control unit (interrupt control means) 205, a clock control unit (clock control means) 206, and a central control unit (central control means) 208.

  The break detection unit 203 detects whether or not a preset break condition is met based on the value of the signal 202 from the peripheral circuit 201, generates a break signal 204 if the condition is met, and generates an interrupt control unit 205. Output to.

  The interrupt control unit 205 is based on the break signal A212.1 output from the processor block A, the break signal B212.2 output from the processor block B, and the break signal 204 output from the break detection unit 203. Then, an interrupt signal AA211.1 and an interrupt signal BA211.2 are generated in the processor block A and the processor block B, and further, the clock control unit 206 is notified that a break has occurred.

  The clock control unit 206 controls the clock signal A 207.1 of the processor block A, the clock signal B 207.1 of the processor block B, and the clock signal C 207.3 of the peripheral circuit 201.

  The central control unit 208 includes debug control units 108.1 and 108.2 (described later), a break detection unit 203, an interrupt control unit 205, a clock, and the like in each of the processor blocks A200.1 and B200.2. The control unit 206 is controlled.

  Next, the processor blocks A200.1 and B200.2 will be described in detail. In the example of FIG. 2, since the processor blocks A200.1 and B200.2 have the same configuration, only the processor block A200.1 will be described below.

  The processor block A200.1 includes a processor A100.1, a bus 101.1, a debug memory 102.1, an instruction memory 103.1, a data memory 104.1, and a debug control unit 108.1. The This configuration is the same as the configuration described in the related art. Furthermore, the processor A is a processor that performs debugging by using an interrupt signal or a trap instruction as in the related art.

  Under the control of the central control unit 208, the debug control unit 108.1 reads and writes the debug memory 102.1 to realize a software break, and generates an interrupt signal AB210.1 based on a signal from the processor A100.1. This is a unit that generates a hardware break. This is the same as the related art. The difference from the related technology is that the debug control unit 108.1 outputs a break signal A212.1 that is activated when a break occurs to the outside, and further allows an interrupt signal AA211.1 to be input from the outside. It is.

  When a break occurs regardless of a software break or a hardware break in the processor A, the debug control unit 108.1 causes the interrupt control unit 205 to generate an interrupt signal BA211.2 to the other processor B, and the clock control unit In order to stop the clock signal C207.3 supplied by the 206 to the peripheral circuit 201, the break signal A212.1 is activated. On the other hand, when the interrupt signal AA211.1 becomes active (when the processor block B200.2 satisfies the break condition or when the break detection unit 203 satisfies the break condition), the debug control unit 108.1 By immediately activating the interrupt signal AB210.1, the processor A100.1 is shifted to the debug mode.

  In the present embodiment, the processor block A200.1 and the processor block B200.2 have the same configuration, but are not necessarily the same. That is, the processor A 100.1 and the processor B 100.2 may be processors having different architectures. Further, even in the case of the same processor, the capacity and configuration of the instruction memories 103.1 and 103.2 and the debug memories 102.1 and 102.2 do not need to be the same, and caches not shown in FIG. Etc., either one of the processor blocks may be included.

  In the debug mode, an actual operation can be simulated more faithfully by using a function capable of temporarily turning off the processor cache. The reason is that the problem of the processor operating at a timing different from the actual operation can be avoided by caching the debugging code. As another method for realizing the same, there is a method of setting a debugging memory area in an area where the cache is not activated.

  The peripheral circuit 201 is a circuit block other than the processors A100.1 and B100.2, and may be one as shown in FIG. 2, but generally there are a plurality (around several tens to several hundreds). A specific example of the peripheral circuit 201 is a circuit block that encodes an image or decodes an encoded image in the case of a semiconductor that handles images. In addition, there are various circuit blocks such as a circuit block for performing encryption, decryption, and memory control, and a circuit block connected to an external interface such as a USB (Universal Serial Bus) or a PCI (Peripheral Component Interconnect) bus. However, the present invention is not limited to this.

  The break detection unit 203 calculates whether a preset break condition is met based on the value of one or more signals 202 output from the peripheral circuit 201, and generates a break signal 204 if the break condition is met. Is a unit.

  The break condition of the break detection unit 203 is set by the central control unit 208. Break determination may be performed using dedicated hardware in the same manner as the processor, or break determination may be performed using a processor that operates at high speed. The former can cope with peripheral circuits that operate at high speed, but has a problem in that there is an upper limit to the number of breakpoints that can be set. On the other hand, in the latter case, the operating frequency of the peripheral circuit 201 must be slower than that of the processor. However, if it is sufficiently slow, there is an advantage that many breakpoints can be realized.

  The following can be considered as break conditions.

  1) The signal value matches or does not match a preset value.

  2) The signal value matches or does not match the preset range.

  3) The above 1) and 2) have reached a preset number.

  4) The above 1) and 2) occurred continuously for a preset number of clocks.

  5) For a plurality of signals, it was 1 when calculated using the logical product, logical sum, or inversion of 1) -4) above.

  In addition, it is preferable that a break condition can be set by an assertion description used in SystemVerilog or the like.

  The break signal 204 is input to the interrupt control unit 205, the purpose of which is the same as the break signal A212.1 described above. That is, when the break signal 204 becomes active, the interrupt control unit 205 immediately inputs the interrupt signals AA211.1 and BA211.2 to all the processor blocks A200.1 and B200.2, and the processor A200. 1, the operation of B200.2 is temporarily stopped and at the same time the fact that the break signal 204 becomes active is input to the clock control unit 206, and the operation of stopping the clock signal C207.3 supplied to the peripheral circuit 201 is performed. Do.

  When the interrupt signals A212.1, B212.2, and 204 of the processors A200.1 and B200.2 and the peripheral circuit 201 become active, the interrupt control unit 205 performs all the processor blocks A200.1 and B200.2. Simultaneously generate interrupt signals (interrupt signal AA211.1 and interrupt signal BA211.2). As a result, interrupt signals (interrupt signals AB210.1 and BB210.2) are input to the processors A200.1 and B200.2, and the processors A200.1 and B200.2 are in debug mode (positions with debug labels). ) Furthermore, the interrupt control unit 205 is a unit that notifies the clock control unit 206 that the break signals A212.1, B212.2, and 204 have become active.

  The clock control unit 206 is a unit that controls a clock signal supplied to each of the processor blocks A200.1 and B200.2 and the peripheral circuit 201. When receiving a notification that the break signal is active from the interrupt control unit 205, the clock control unit 206 supplies the clock signals A207.1 and B207.2 to all the processor blocks A200.1 and B200.2. The clock signal C207.3 to the circuit 201 operates to stop.

  When the clock signal is controlled by a PLL (Phase Locked Loop) or the like, it is difficult to stop the clock signal. Therefore, the clock signal output from the PLL may be masked in the same manner as the gated clock. good. Moreover, since recent semiconductors frequently use a gated clock in order to reduce power consumption, a part of the clock control unit 206 can be realized without adding a new circuit by making good use of the gated clock. However, in the case of a circuit that cannot stop the clock supply in the peripheral circuit, the clock must be continuously supplied. For example, an I / F (interface) circuit of a DRAM (Dynamic Random Access Memory) cannot normally perform a REFRESH (refresh) operation unless a clock is supplied, and destroys the data contents of the DRAM. Must continue to supply. On the other hand, a method for returning from the debug mode to the normal state will be described later.

  FIG. 3 shows an interrupt signal AA211.1, an interrupt signal BA211.2, a clock signal A207.1, and a clock signal B207 when the break signal A212.1, the break signal B212.2, or the break signal 204 is activated. .2 shows the operation of the clock signal C207.3.

  In FIG. 3, the clock signal is a signal for operating the processor block A, the processor block B, and the peripheral circuit 201, and the break signal indicates the logical sum of the break signal A212.1, break signal B212.2, and break signal 204. The interrupt signals indicate the interrupt signal AA211.1 and the interrupt signal BA211.2.

  Also, the lowermost part of FIG. 3 shows a pipeline operation of a general RISC (Reduced Instruction Set Computer) processor having a five-stage pipeline. In the figure, IF indicates instruction fetch, ID indicates instruction decode, EX indicates execution, MEM indicates memory access, and WB indicates write back. In the processor, assuming that the occurrence of a break due to detection by a hardware break and execution of a trap instruction are both in the EX stage, the above three instructions are executed and then jump to the interrupt routine. The lower two instructions are discarded. However, some processors execute the following two instructions.

  If the detection by the hardware break and the trap instruction are executed and the timing at which the break signals A212.1 and B212.2 become active are different, the break at the early timing is flip-flops to faithfully simulate the actual operation. By delaying and adjusting the time, a better debugging environment can be provided.

  FIG. 4 shows a specific example (pseudo assembler code) of processor interrupt processing.

  The debug label in FIG. 4 indicates a jump location due to the execution of a trap instruction of the processor or the occurrence of a hardware interrupt. An instruction or the like necessary for reading the register is stored between the debug label and the loop label. The loop from the loop label to the jmp instruction (jump instruction) is an infinite loop. The ret instruction is a return instruction and is an instruction for returning to the jump source position of the program (the position where the trap instruction was present). Here, when returning from the debug mode to the normal state, it is possible to return by rewriting the jmp loop instruction to a NOP instruction.

  Each of the above units is generally realized by hardware, but is not limited to this.

  Next, the overall operation of the present exemplary embodiment will be described in detail with reference to the flowchart of FIG.

  First, preparation for circuit operation is started (step S500). More specifically, various devices and devices necessary for the operation are connected to a circuit incorporating a processor block and peripheral circuits, the power is turned on, and circuit reset is activated. In a state where the debugger is connected from the outside, the processor implements a debugging routine immediately after the start in order to realize a breakpoint and the like, and thus the supply of the clock signal to the peripheral circuit is stopped.

  Next, the user performs break condition setting, break point setting, register read / write, and memory read / write through the central control unit (step S501).

  Next, it is selected whether to execute the program or end debugging (step S502). The program is executed when the user selects program execution (step execution or continue (continuous) execution). Here, when the end of debugging is selected, the execution of the debugging routine is ended (step S507).

  Next, the instruction rewritten to the trap instruction is returned to the original instruction (step S503). This step is realized by once loading the original instruction stored in the debug memory into the register, storing the instruction to be written to the corresponding address in the debug memory, and executing it by the processor. This step is done because the instruction that set the breakpoint must be executed. After executing the original instruction, it is necessary to replace it with the trap instruction again. If the processor has an instruction or function that interrupts again after the step, there is a method to use it instead of the original instruction. is there.

  Next, the original instruction replaced with the trap instruction is executed, and the process shifts to the debug mode again by interruption (step S504). Since a general processor has a mechanism for performing step execution (a mechanism that interrupts after execution of one instruction), the original instruction is executed using the mechanism. At this time, a clock for one instruction is supplied to the peripheral circuit.

  Next, the executed original instruction is rewritten again as a trap instruction in the same manner as when a breakpoint is set (step S505).

  Next, the return instruction returns the program to the next instruction at which a breakpoint is set (step S506), and the processor and peripheral circuits are in a normal state. Thereafter, the process returns to step S502, and the same processing as described above is repeatedly executed.

  As described above, in this embodiment, when a break occurs in a certain processor, all the processors in the circuit are forcibly interrupted to temporarily stop the program operation, and the peripheral circuit supplies the clock. The operation is stopped by stopping.

  Next, the effect of this embodiment will be described.

  In this embodiment, when a certain processor shifts to the debug mode, the other processors also shift to the debug mode. Therefore, there is an effect that the states of all the processors in the system can be acquired through the central control unit. Even in debug mode, the processor continues to supply the clock and executes write back, so it can solve the problem of observing the register before write back, and if the circuit is mounted on an emulator, it is necessary to correct the circuit description. Since the present embodiment is configured so as to make maximum use of the functions implemented in the current processor, the correction is minimized (interrupts are included), and there is also an effect of greatly reducing the number of corrections.

  In this embodiment, when an interrupt signal is input to the processor, the number of instructions executed by the i-th processor is different if the number of instructions executed before the transition from the interrupt occurrence to the interrupt vector is different. Assuming that A_i is A and the maximum value of A_i is B, the interrupt control unit delays BA_i cycles by a delay circuit such as a flip-flop (FF) after detecting the break signal (after the break occurs). An interrupt signal may be input to all the processors.

(Second Embodiment)
Next, the second embodiment of the present invention will be described with reference to FIGS.

  As shown in FIG. 6, the debug control device, which is a circuit verification device according to the present embodiment, includes return instruction detection units (return instruction detection means) 600.1 and 600.2 and a return to the first embodiment. In this configuration, information 602 is added.

  The return instruction detection units 600.1 and 600.2 detect that the processors A100.1 and B100.2 execute return instructions, and use them as return instruction detection signals 601.1 and 601.2. It is a unit that tells.

  The return information 602 is information in which the number of clocks consumed by the return instruction in each of the processors A100.1 and B100.2 is written. For example, this is a file in which processor A100.1 requires 7 cycles for a return instruction and processor B100.2 requires 5 cycles.

  The clock control unit 206 uses the return detection signal and the return information to return all the processors A100.1 and B100.2 and the peripheral circuit 201 at the same time. Controls the number of clocks given to.

  FIG. 7 is a flowchart showing the operation of the present embodiment. In this figure, steps S700, S701, S702, and S703 are added in addition to steps S500 to S507 in FIG. Steps S700 and S701 are inserted between steps S503 and S504, and steps S702 and S703 are inserted between steps S505 and S506. Steps S700 and S702 perform the same operation. Steps S701 and S703 perform the same operation.

  In the first embodiment, the return is performed by forcibly rewriting the “jmp loop” infinite loop to the NOP instruction when the debug ends and returns. However, the operation cycle does not match at the cycle level. For this reason, in this embodiment, it is possible to return in exactly the same cycle as the actual operation by including the control of step S700 and step S701.

  That is, in this embodiment, the clock is continuously supplied until it is detected that each processor has executed the return instruction (steps S700 and S702). More specifically, the operation will be described. When a processor executes a return instruction, the return instruction detection unit first detects it and notifies the clock control unit. Next, the clock signal supplied to the corresponding processor by the clock control unit is stopped. It then operates to wait until all clock signals have stopped (ie, all processors have executed a return instruction).

  In this embodiment, the return information 602 is used to supply the number of clocks necessary for each processor to execute the return instruction (steps S701 and S703). This is so that even if a plurality of processors have different architectures, all the processors can start operating simultaneously.

  Next, the effect of this embodiment will be described.

  In this embodiment, a return detection unit is added so that all the processors and peripheral circuits can start operation simultaneously, and input to each processor based on return information (information on the number of clocks required by the return instruction). Since the number of clock signals is adjusted, it is possible to restore all processors and peripheral circuits at the same time even with processors having different architectures.

  The circuit verification apparatus and method according to the present embodiment can be realized by hardware, software, or a combination thereof.

  For example, the circuit verification apparatus according to the present embodiment can be realized by hardware, but can also be executed by a computer reading a program for causing the computer to function as the apparatus from a computer-readable recording medium and executing the program. Can be realized.

  In addition, the circuit verification method according to the present embodiment can be realized by hardware, but it is also possible for the computer to read and execute a program for causing the computer to execute the method from a computer-readable recording medium. Can be realized.

  Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  INDUSTRIAL APPLICABILITY According to the present invention, the present invention can be used for a circuit verification device, a method, a program, and the like such as a debug control device for a circuit including a plurality of processors.

100.1, 100.2 Processor A, B
101.1, 101.2 Bus 102.1, 102.2 Debug memory 103.1, 103.2 Instruction memory 104.1, 104.2 Data memory 108.1, 108.2 Debug control unit 201 Peripheral circuit 203 Break detection unit 205 Interrupt control unit 206 Clock control unit 208 Central control unit 200.1, 200.2 Processor blocks A, B

Claims (9)

In an apparatus for verifying the operation of a circuit including a plurality of processors that perform operation verification by interrupt control and peripheral circuits other than the processor,
Break detecting means for detecting whether a state of a signal from the peripheral circuit matches a preset break condition, and generating a break signal when the break condition is met;
Interrupt control means for detecting a break signal from the processor and a break signal from the break detection means and inputting an interrupt signal to all processors;
Clock control means for controlling a clock signal supplied to the processor and the peripheral circuit;
Central control means for transmitting the break occurrence transmitted by the interrupt control means to the clock control means and controlling the break detection means and the debug control means of the processor,
The interrupt control means inputs an interrupt signal to all processors included in the circuit when a break signal from the break detection means is detected and when a break signal from the processor is detected,
The circuit verification device, wherein the clock control means supplies a clock signal to the processor immediately after the interrupt control means detects a break signal, and does not supply a clock signal to the peripheral circuit.   When an interrupt signal is input to the processor and the number of instructions executed before the transition from the interrupt generation to the interrupt vector is different, the number of instructions executed by the i-th processor is A_i, and the maximum value of A_i 2. The circuit verifying apparatus according to claim 1, wherein when B is B, the interrupt control means delays B-A_i cycles after detecting the break signal and inputs the interrupt signal to all processors. And a return instruction detecting means for detecting that the processor executes a return instruction.
The clock control means temporarily stops the supply of the clock signal when the return instruction is executed when returning from the debug state to the normal state, and executes the return instruction in each processor when the supply of the clock signal of all the processors is stopped. 2. The circuit verifying apparatus according to claim 1, wherein the number of clocks required for the processing is supplied to each processor, and the supply of clock signals to all the processors and peripheral circuits is resumed. In a method for verifying the operation of a circuit including a plurality of processors that perform operation verification by interrupt control and peripheral circuits other than the processor,
The break detection means detects whether the state of the signal from the peripheral circuit matches a preset break condition, and generates a break signal when the break condition matches,
The interrupt control means detects a break signal from the processor and a break signal from the break detection means, and inputs the interrupt signal to all processors,
A clock control means for controlling a clock signal supplied to the processor and the peripheral circuit;
The central control means transmits the break occurrence transmitted by the interrupt control means to the clock control means, and controls the break detection means and the debug control means of the processor.
A method,
When the interrupt control means detects a break signal from the break detection means and detects a break signal from the processor, it inputs an interrupt signal to all the processors included in the circuit,
A circuit verification method, wherein the clock control means supplies a clock signal to the processor as soon as the interrupt control means detects a break signal, and does not supply a clock signal to the peripheral circuit.   When an interrupt signal is input to the processor and the number of instructions executed before the transition from the interrupt generation to the interrupt vector is different, the number of instructions executed by the i-th processor is A_i, and the maximum value of A_i 5. The circuit verification method according to claim 4, wherein the interrupt control means delays BA_i cycles after detecting the break signal and inputs the interrupt signal to all the processors, where B is B. Further, a return instruction detection means detects that the processor executes a return instruction,
When the clock control means returns from the debug state to the normal state, the supply of the clock signal is temporarily stopped when the return instruction is executed, and the return instruction is executed by each processor when the supply of the clock signal of all the processors is stopped. 5. The circuit verification method according to claim 4, wherein the number of clocks required for the above is supplied to each processor, and the supply of clock signals to all processors and peripheral circuits is resumed. In a program for verifying the operation of a circuit including a plurality of processors that perform operation verification by interrupt control and peripheral circuits other than the processor,
Computer
Break detecting means for detecting whether a state of a signal from the peripheral circuit matches a preset break condition, and generating a break signal when the break condition is met;
Interrupt control means for detecting a break signal from the processor and a break signal from the break detection means and inputting an interrupt signal to all processors;
Clock control means for controlling a clock signal supplied to the processor and the peripheral circuit;
Central control means for transmitting the break occurrence transmitted by the interrupt control means to the clock control means and controlling the break detection means and the debug control means of the processor;
A program that allows
The interrupt control means inputs an interrupt signal to all processors included in the circuit when a break signal from the break detection means is detected and when a break signal from the processor is detected,
The circuit verification program characterized in that the clock control means supplies a clock signal to the processor as soon as the interrupt control means detects a break signal and does not supply a clock signal to the peripheral circuit.   When an interrupt signal is input to the processor and the number of instructions executed before the transition from the interrupt generation to the interrupt vector is different, the number of instructions executed by the i-th processor is A_i, and the maximum value of A_i 8. The circuit verification program according to claim 7, wherein the interrupt control means inputs the interrupt signal to all processors after delaying B-A_i cycles after detecting the break signal. Further, a program for causing a computer to function as return instruction detection means for detecting that the processor executes a return instruction,
The clock control means temporarily stops the supply of the clock signal when the return instruction is executed when returning from the debug state to the normal state, and executes the return instruction in each processor when the supply of the clock signal of all the processors is stopped. 8. The circuit verification program according to claim 7, wherein the number of clocks required for the processing is supplied to each processor, and the supply of clock signals to all the processors and peripheral circuits is resumed.

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