JP2007141200A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve debug efficiency when a data processor has a plurality of CPUs. <P>SOLUTION: When breaking conditions are established in any of a first CPU (10) and a second CPU (11), a simultaneous breaking mode capable of simultaneously breaking the first and second CPUs responding to establishment of the breaking conditions to minimize shift of instruction execution between the CPUs after establishment of the breaking conditions in any of the first CPU and the second CPU. In addition, a simultaneous execution mode in which execution starting timing of a user program by restoration from a breaking state is matched between the fist CPU and the second CPU is provided to minimize timing shift of user program execution by restoration from the breaking state between the CPUs. Thus, improvement of debug efficiency in system debug of a microcomputer system including the first CPU and the second CPU is attained. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

The present invention relates to a data processing apparatus equipped with a plurality of CPUs (central processing units), and further to a debugging technique therefor, for example, a technique effective when applied to a microcomputer.

  As a debugging technique for a microcomputer, which is an example of a data processing apparatus equipped with a plurality of CPUs, for example, the same number of debugging terminal groups as the number of installed processors are provided, and each terminal group has a corresponding debugging function. A technique for individually debugging each processor by connecting devices is known (see, for example, FIG. 4 of Patent Document 1). In such a configuration, as the number of CPUs to be mounted increases, it is necessary to add a debugging terminal and a debugging circuit accordingly, so that the cost is inevitably increased.

  On the other hand, a technique for sharing a debugging terminal by a plurality of mounted CPUs is known (for example, see FIG. 1 of Patent Document 1 and FIG. 1 of Patent Document 2). In order to share a debugging terminal with the debugging circuit of the first CPU and the debugging circuit of the second CPU, selective connection means is provided, and the debugging terminal is connected to the debugging circuit of the first CPU and the second CPU by the selective connection means. Is selectively coupled to the debug circuit. In this case, even if the number of CPUs increases, it is not necessary to add a debugging terminal or a debugging circuit. However, since the debugging circuit of the first CPU and the debugging circuit of the second CPU are configured to individually control the connected CPU, it is difficult to test the integrated system operation of the first CPU and the second CPU. Is done.

  On the other hand, a technique is known in which individual operation states of processors in a multiprocessor processing apparatus are held to hold the operation state of the entire integrated system (see, for example, Patent Document 3). According to this, when it is detected that the operation state of an arbitrary processor has changed from the normal running state to the test running state due to the establishment of a break condition or other factors, the system state is transitioned according to the operating state of the processor. At this time, if necessary, the operation state of the other processor whose operation state has not changed is changed from the normal running state to the test running state, and the operation test for the operation state in the test running state is controlled. Is done.

JP 2000-76199 A JP 2004-164367 A JP 2005-122375 A

  In system debugging of a microprocessor including a plurality of CPUs, in order to improve debugging efficiency, when a user program to be debugged (hereinafter referred to as a user program) is executed by the plurality of CPUs, a predetermined break condition is set. When established, it is desired to mount a function for simultaneously breaking the plurality of CPUs (simultaneous break function) and a function for simultaneously starting execution of the user program again by the plurality of CPUs after the break (simultaneous execution function).

  The simultaneous break function and the simultaneous execution function can be realized by software or hardware. The inventors of the present invention have examined the case where the simultaneous break function and the simultaneous execution function are realized by software on a personal computer coupled to an emulator. It has been found that there is a time difference in the order of. In addition, when the simultaneous break function and the simultaneous execution function are realized by hardware on an emulator, it is found that a time difference occurs in the order of several microseconds between the multiple CPUs in the simultaneous break and simultaneous execution. It was. Such a time difference causes a shift in the execution of a large number of instructions before the break function is started or the simultaneous execution is performed among a plurality of CPUs, and it is difficult to say that a debugging operation is performed synchronously among the plurality of CPUs. If the instruction deviation is less than several instructions, it can be said that the operation is synchronous.

  Patent Document 3 describes the necessity of synchronizing debugging operations among a plurality of CPUs such as simultaneously stopping processors under certain conditions when debugging operations performed by a plurality of CPUs in cooperation. However, the specific configuration for enabling simultaneous breaks and how much simultaneity is actually guaranteed are not clarified.

  Although it is necessary to break the plurality of CPUs selectively or simultaneously according to the establishment of the break condition, according to the technique described in Patent Document 3, the CPU that satisfies the break condition is always in a break when the condition is satisfied. Thus, there is no description about breaking other CPUs without breaking the CPUs that satisfy the break condition.

  According to the technique described in Patent Document 3, when a break condition is established in any CPU, the CPU is first broken, and after that is recognized by the debug circuit, another CPU is broken. However, there is no description of selectively breaking any number of CPUs including the CPUs to be observed that satisfy the condition or a plurality of CPUs simultaneously.

  According to the technology described in Patent Document 3, one of the CPUs breaks due to an external factor, and after that is recognized by the debug support circuit, another CPU breaks. There is no description about simultaneously breaking a plurality of CPUs.

  Further, according to the technique described in Patent Document 3, the execution control for an arbitrary number of CPUs when returning to the execution of the user program after any CPU is broken is not described.

  In system debugging of a microprocessor including a plurality of CPUs, it is important to smoothly trace the trace information about the operations of the plurality of CPUs in order to improve debugging efficiency. The inventors of the present invention have examined this, and it has been found that smooth tracing is difficult in the system debugging of the microprocessor for the following reason.

  In a microprocessor in which a plurality of clock signals having different frequencies are used, the frequency of the clock signal supplied to the CPU is the highest. Therefore, in the debug circuit, tracing is performed using the clock signal supplied to the CPU. Thus, the state of the CPU bus and the system bus can be traced without omission.

  However, in system debugging of a microprocessor including a plurality of CPUs, the operation speed between the plurality of CPUs is different, and the operation speed may be dynamically changed depending on the system. In such a case, since the frequency of the clock signal of the debug circuit at the time of tracing cannot be determined, smooth tracing is difficult.

  An object of the present invention is to provide a technique for improving the efficiency of system debugging in a data processing apparatus including a plurality of CPUs.

  Another object of the present invention is to provide a technique capable of selectively breaking an arbitrary CPU when a break condition is satisfied in a data processing apparatus including a plurality of CPUs.

  Another object of the present invention is to provide a technique for simultaneously executing a user program after a break in a data processing apparatus including a plurality of CPUs.

  Another object of the present invention is to provide a technique for enabling smooth tracing in a data processing apparatus including a plurality of CPUs.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] That is, a plurality of CPUs each having stop control means for stopping execution of a user program in response to a request for stopping execution of the user program, and restart control means for permitting or inhibiting execution of the user program; In a data processing apparatus including a debug circuit that enables debugging of a user program executed by a CPU of the CPU, the restart control unit for the plurality of CPUs is allowed to resume execution of the user program simultaneously in the debug circuit. An execution control circuit having a simultaneous execution mode is provided.

  According to the means described in [1] above, since the execution control circuit has the simultaneous execution mode, the timing shift of the user program execution due to the return from the break state is minimized among the plurality of CPUs. This achieves improved debugging efficiency in system debugging of a data processing apparatus including a plurality of CPUs.

  [2] In addition, a plurality of CPUs each having a stop control unit that stops execution of the user program in response to an execution stop request for the user program, a restart control unit that allows or suppresses execution restart of the user program, In a data processing apparatus including a debugging circuit that enables debugging of a user program executed by the CPU, when a break condition is established in any of the plurality of CPUs in the debugging circuit, in response, A break control circuit having a simultaneous break mode for simultaneously requesting stop of execution of the user program to the stop control means for the plurality of CPUs, and resuming execution of the user program simultaneously for the restart control means for the plurality of CPUs. And an execution control circuit having a concurrent execution mode to be permitted.

  According to the means described in [2] above, since the break control circuit has the simultaneous break mode, instruction execution between the plurality of CPUs after a break condition is established in any one of the plurality of CPUs. Deviation can be minimized. Further, since the execution control circuit and the simultaneous execution mode are provided, the timing shift of the user program execution due to the return from the broken state can be minimized among the plurality of CPUs. This achieves improved debugging efficiency in system debugging of a data processing apparatus including a plurality of CPUs.

  [3] At this time, in order to suppress an increase in the number of external terminals, the debug circuit provides a debug interface for externally outputting the debug results of the user program executed by the plurality of CPUs from a plurality of common debug terminals. It is good to provide.

  [4] Depending on the configuration of the user program, it may be desired to individually break one of the plurality of CPUs. In consideration of such a case, in the break control circuit, there is a break condition in one of the plurality of CPUs. When established, it is preferable to include an individual break mode in which any one of the plurality of CPUs can be individually broken or any arbitrary number can be individually broken.

  [5] Depending on the configuration of the user program, there is a case where it is desired to individually control the start of user program execution by returning from the break state for each CPU. In consideration of such a case, the execution control circuit includes a break state. It is preferable to include an individual execution mode capable of individually controlling the start of user program execution by returning from each CPU.

  [6] The break control circuit includes a break request circuit for forming a break request according to a predetermined break factor, and masking the break request according to a set break condition and a break factor. A break request mask circuit capable of requesting only the CPU targeted for a break from the CPUs to stop the execution of the user program can be configured.

  [7] The break request circuit may further include a plurality of break condition registers each capable of setting a break condition, and may be configured to perform break control for the corresponding CPU according to the setting conditions of the break condition setting register. .

  [8] The break condition register includes a first field capable of setting a CPU to be observed and a second field capable of setting a break condition for the CPU set in the first field. Can do.

  [9] The break control circuit further includes a sequential break condition register capable of setting a sequential break condition based on a combination of the plurality of break conditions, and determines a break condition based on setting information of the sequential break condition register. Thus, the CPU can be configured to request the corresponding CPU to stop executing the user program.

  [10] The debug interface may include a reset control circuit that receives inputs from the plurality of debug terminals and can individually make a reset request to a plurality of CPUs. According to this, since the debug interface has a function of individually controlling a reset request to a plurality of CPUs, it is possible to reset the state of an arbitrary number of CPUs from the plurality of CPUs.

  [11] The debug interface includes a reset control register for controlling a reset request by a plurality of CPUs, which can be set by receiving inputs from the plurality of debug terminals, and a set value of the reset signal control register Accordingly, it is possible to make it possible to individually make a reset request to each of the plurality of CPUs.

  [12] The execution control circuit includes a simultaneous execution control register that enables control of the simultaneous execution mode and the individual execution mode, and sets each CPU according to the setting of the simultaneous execution control register and the states of the plurality of CPUs. A control signal generation circuit for requesting resumption of execution of the user program can be configured.

  [13] The simultaneous execution control circuit can be configured by referring to whether or not the CPU is in a break state as the state of the plurality of CPUs.

  [14] The simultaneous execution control circuit can be configured by referring to whether or not a return instruction from a break is being executed as the state of the plurality of CPUs.

  [15] A plurality of CPUs that operate in synchronization with the supplied CPU clock signals, and a debug circuit that enables debugging of user programs executed by the plurality of CPUs based on the supplied debug clock signals, When the frequency of the debug clock signal supplied to the debug circuit is f1, and the highest frequency among the CPU clock signals supplied to the plurality of CPUs is f2, f1 ≧ A clock control circuit for forming the debug clock signal and the CPU clock signal is provided so that f2 is established.

  [16] A first CPU that operates in synchronization with a first CPU clock signal, a second CPU that operates in synchronization with a second CPU clock signal different from the first CPU clock signal, and the first CPU and the above based on a debugging clock signal A data processing apparatus is configured including a debug circuit that enables debugging of a user program executed by the second CPU. In this case, when the frequency of the debug clock signal is f1, and the higher one of the first CPU clock signal and the second CPU clock signal is f2, the above-mentioned is established so that f1 ≧ f2 is satisfied. A clock control circuit is provided for forming the debug clock signal and the CPU clock signal.

  According to the means described in [15] and [16], the clock control circuit forms the debug clock signal and the CPU clock signal so that f1 ≧ f2. This enables smooth tracing and achieves improved system debugging efficiency in a data processing apparatus including a plurality of CPUs.

  [17] At this time, the debug circuit synchronizes with the first CPU clock signal and takes in the trace information about the first CPU, and the debug circuit synchronizes with the second CPU clock signal. A second trace information input unit for capturing trace information about the second CPU, and a first synchronization unit for synchronizing the trace information captured via the first trace information input unit with the debug clock signal A second synchronization unit for synchronizing the trace information captured via the second trace information input unit with the debug clock signal, and the first synchronization based on the debug clock signal. Information for selectively fetching output information of the second section and output information of the second synchronization section in accordance with a preset condition It can be configured to include a management unit.

  [18] The debug circuit may include a trace memory capable of storing information selectively captured by the trace information processing unit in a predetermined storage area based on the debug clock signal. .

  [19] In order to enable external output of a large amount of trace information, a trace information output unit for externally outputting the processing result of the trace information processing unit to the debug circuit based on the debug clock signal is provided. It is good to provide.

  [20] In the above [19], in order to clarify whether the information output from the trace information output unit is the trace information for the first CPU or the trace information for the second CPU, The information output from the information output unit may include identification information that enables identification of the trace information about the first CPU and the trace information about the second CPU.

  [21] The clock control circuit includes a clock generator for generating an internal clock signal synchronized with a reference clock signal, a clock divider for dividing the internal clock signal generated by the clock generator, And a clock driver for driving a load based on the output signal of the clock divider. In this case, the clock driver can be configured to include the debug driver only during a period during which debugging is performed. A logic gate for externally outputting the clock signal can be included.

  [22] The clock control circuit includes a clock generator for generating an internal clock signal synchronized with the inputted reference clock signal, and a clock divider for dividing the internal clock signal generated by the clock generator. A frequency divider and a clock driver for driving a load based on the output signal of the clock frequency divider can be included. In this case, the clock frequency divider outputs a plurality of frequency-divided clock signals having different frequency-dividing ratios, and a frequency division corresponding to the frequency-divided clock signals according to the first frequency-dividing ratio information. A first multiplexer that selects a clock signal and outputs it as the first CPU clock signal, and selects a corresponding divided clock signal from the plurality of divided clock signals according to second division information and outputs it to the second CPU. The second multiplexer that outputs as a clock signal, the first division ratio information and the second division ratio information are compared and the smaller division ratio information is selected, and the plurality of division ratio information is selected according to the division ratio information. And a third multiplexer for selecting a corresponding divided clock signal from the divided clock signal and outputting it as the debug clock signal. Can.

  [23] The clock control circuit includes a clock generator for generating an internal clock signal synchronized with the inputted reference clock signal, and a clock divider for dividing the internal clock signal generated by the clock generator. A frequency divider and a clock driver for driving a load based on the output signal of the clock frequency divider can be included. In this case, the clock frequency divider outputs a plurality of frequency-divided clock signals having different frequency-dividing ratios, and a frequency division corresponding to the frequency-divided clock signals according to the first frequency-dividing ratio information. A first multiplexer that selects a clock signal and outputs it as the first CPU clock signal, and selects a corresponding divided clock signal from the plurality of divided clock signals according to second division information and outputs it to the second CPU. And a second multiplexer that outputs the clock signal. At this time, the clock signal supplied from the clock generator to the clock divider is used as the debug clock signal.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in a data processing apparatus including a plurality of CPUs, it is possible to improve the efficiency of system debugging by providing a simultaneous break mode and a simultaneous execution mode.

  In addition, in a data processing apparatus including a plurality of CPUs, it is possible to provide a technique that can selectively break any number of CPUs and break a plurality of selected CPUs simultaneously when a break condition is satisfied.

  Further, in a data processing apparatus including a plurality of CPUs, it is possible to provide a technique for simultaneously executing user programs in an arbitrary number of CPUs after a break.

  In a data processing apparatus including a plurality of CPUs, a technique for achieving an improvement in the efficiency of system debugging can be provided by enabling smooth tracing.

  As described above, according to the present invention, in a data processing apparatus including a plurality of CPUs, the simultaneous break mode and the simultaneous execution mode are provided, or smooth tracing is enabled, thereby improving the efficiency of system debugging. Can be achieved.

  FIG. 1 shows a microcomputer as an example of a data processing apparatus according to the present invention.

  The microcomputer 1 shown in FIG. 1 includes a first CPU (CPU 1) 10, a second CPU (CPU 2) 11, a debug circuit (DEBUG) 2, and various peripheral modules (MODL) 12-1 to 12-n, and is not particularly limited. Is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The first CPU 10, the second CPU 11, and the various peripheral modules 12-1 to 12-n are coupled to each other via a system bus 13 so that signals can be exchanged. The debug circuit 2 is coupled to the system bus 13, the first CPU 10, and the second CPU 11, and enables debugging of user programs executed by the first CPU 10 and the second CPU 11. Data of the system bus 13 (system bus data) SYSB-DATA is transmitted to the debug circuit 2 to the debug circuit 2. Between the debug circuit 2 and the first CPU 10, various signals required for debugging, that is, a stall control signal STL-CNT for permitting or suppressing the resumption of execution of the user program, a return instruction from a break, A return instruction execution signal RTB-CNT indicating whether or not the CPU is executing, a break acknowledge signal BRK-ACK indicating whether or not the CPU is in the break state, and a break request signal BRK for requesting execution stop of the user program -REQ, CPU bus data CPUB-DATA, and reset signal RST for reset request can be exchanged. Similarly, between the debug circuit 2 and the second CPU 11, various signals required for debugging, that is, a stall control signal STL-CNT, a return instruction execution signal RTB-CNT, and a break acknowledge signal BRK-ACK. The break request signal BRK-REQ, the CPU bus data CPUB-DATA, and the reset signal RST can be exchanged.

  When the break request signal BRK-REQ is asserted by the debug circuit 2, a break (user program execution stop) can be requested to the first CPU 10 or the second CPU 11. When the break acknowledge signal BRK-ACK is asserted by the first CPU 10 or the second CPU 11, the debug circuit 2 can grasp the break state of the first CPU 10 or the second CPU 11. Further, the debug circuit 2 is debugged by the first CPU 10 or the second CPU 11 asserting the return instruction execution signal RTB-CNT, and the debug circuit 2 is changed to the break state in the first CPU 10 or the second CPU 11. The execution of the user program can be started again after the debugging process is completed, that is, it is possible to grasp the state immediately before returning to the user program. By negating the stall control signal STL-CNT by the debug circuit 2, it is possible to instruct the first CPU 10 and the second CPU 11 to start executing the user program by returning from the break state. The debug circuit 2 can grasp various information output to the CPU bus (not shown) by the first CPU 10 and the second CPU 11 based on the CPU bus data CPUB-DATA. When the reset signal RST is asserted by the debug circuit 2, the first CPU 10 and the second CPU 11 can be reset. The debug result of the user program executed by the first CPU 10 and the debug result of the user program executed by the second CPU 11 are output to the outside of the microcomputer 1 via the common debug terminal 5 by the debug circuit 2.

  FIG. 2 shows a configuration example of the debug circuit 2.

  Although not particularly limited, the debug circuit 2 includes a debug interface (DEBUGI / F) 21, an execution control circuit (PRC-CNT) 22, and a break control circuit (BRK-CNT) 23 as shown in FIG. Become.

  The execution control circuit 22 has a function of controlling the user program execution in the first CPU 10 and the second CPU 11, and the user program execution start timing due to the return from the break state coincides between the first CPU 10 and the second CPU 11. It includes a simultaneous execution mode (simultaneous execution) and an individual execution mode (individual execution) capable of individually controlling the start of user program execution upon return from the break state for each CPU. The break acknowledge signal BRK-ACK transmitted from the first CPU 10 and the second CPU 11 is taken into the execution control circuit 22. The execution control circuit 22 detects the state of the corresponding CPU by referring to either the transmitted break acknowledge signal BRK-ACK or the return instruction execution signal RTB-CNT, and asserts a plurality of CPUs based on the detected state. It has a simultaneous execution mode for negating the stall control signal STL-CNT that has been made at the same timing. When the stall control signal STL-CNT that has been asserted is negated in the first CPU 10 and the second CPU 11, the return is executed by executing the return instruction RTB, and the execution of the user program is started. In the simultaneous execution mode, the stall control signal STL-CNT that has been asserted for a plurality of CPUs is negated at the same timing, so that the user program by the return from the break state is simultaneously executed by the first CPU 10 and the second CPU 11. Executed. Here, it should be understood that “simultaneous execution” includes a shift of several clocks as well as a case where the timing coincides perfectly. The simultaneous execution mode and the individual execution mode can be appropriately selected in consideration of debugging efficiency.

  The break control circuit 23 controls a break operation for the first CPU 10 and the second CPU 11 based on the CPU bus data CPUB-DATA and the break acknowledge signal BRK-ACK. In controlling the break operation, when a break condition is established in either the first CPU 10 or the second CPU 11, a break request signal BRK-REQ is simultaneously sent to the first CPU 10 and the second CPU 11 in response thereto. When the break condition is established in the simultaneous break mode to be asserted and in either the first CPU 10 or the second CPU 11, the break request signal BRK-REQ corresponding to either the first CPU 10 or the second CPU 11 is correspondingly generated. And an individual break mode to assert. The simultaneous break mode and the individual break mode can be appropriately selected in consideration of debugging efficiency. In order to make this selection possible, a break condition setting register may be provided in the break control circuit 23 and a break mode may be set in this register. Here, it should be understood that the simultaneous break includes not only the case where the break timings of the first CPU 10 and the second CPU 11 are completely aligned, but also the case where there is a shift of several clocks.

  FIG. 5 shows a configuration example of the execution control circuit (PRC-CNT) 22.

  The execution control circuit (PRC-CNT) 22 includes a stall control signal generation circuit 221 and a simultaneous execution control register 222, although not particularly limited.

  The stall control signal generation circuit 221 detects the state of the CPU corresponding to the break acknowledge signal BRK-ACK, and controls the execution of the return instruction in the first CPU 10 and the second CPU 11 based on the setting of the simultaneous execution control register 222. For execution control of the return instruction, the stall control signal STL-CNT corresponding to the first CPU 10 and the second CPU 11 is asserted, and the break acknowledge signal BRK-ACK corresponding to the first CPU 10 and the second CPU 11 is asserted. A simultaneous execution mode in which the stall control signal STL-CNT corresponding to the first CPU 10 and the second CPU 11 is simultaneously negated and the stall control signal STL-CNT corresponding to the first CPU 10 and the second CPU 11 is negated. And a separate execution mode for individually executing a return command from the first CPU 10 and the second CPU 11 that have reached the return command. The simultaneous execution mode and the individual execution mode can be appropriately selected in consideration of debugging efficiency. In order to make this selection possible, if a break mode is set in the break condition setting register, it is possible to execute in any mode.

  The stall control signal generation circuit 221 uses a break acknowledge signal BRK-ACK indicating that the execution of the return instruction is completed as an input signal for detecting the states of the plurality of CPUs. For example, in the simultaneous execution mode, when the first CPU 10 reaches the execution of the return instruction first and the second CPU 11 reaches the execution of the return instruction later after the debugging process under the control of the debug circuit 22, the first CPU 10 responds. The execution of the return instruction is stalled with reference to the asserted stall control signal STL-CNT. On the other hand, the second CPU 11 completes the execution of the return instruction without referring to the corresponding asserted stall control signal STL-CNT, and asserts the break acknowledge signal BRK-ACK. When the second CPU 11 asserts the corresponding break acknowledge signal BRK-ACK, the stall control signal generation circuit 221 simultaneously negates the stall control signal STL-CNT. The first CPU 10 detects negation by referring to the corresponding stall control signal STL-CNT, and executes a return instruction. The reference to the stall control signal STL-CNT is realized by, for example, an operation in which the first CPU 10 and the second CPU 11 read the simultaneous execution control register 222. Further, the first CPU 10 and the second CPU 11 can know the state by a stall control signal output from the debug circuit 22. When the stall control signal generation circuit 221 uses the break acknowledge signal BRK-ACK to realize the simultaneous execution mode, it is necessary to know in advance the execution order of the return instructions in the first CPU 10 and the second CPU 11.

  The stall control signal generation circuit 221 can use the return instruction execution signal RTB-CNT instead of the break acknowledge signal BRK-ACK as an input signal for detecting the states of the plurality of CPUs. For example, in the simultaneous execution mode, when the return instructions of the first CPU 10 and the second CPU 11 are executed simultaneously, stall control is performed by asserting all the return instruction execution signals RTB-CNT corresponding to the first CPU 10 and the second CPU 11. The signal generation circuit 221 negates the stall control signal STL-CNT at the same time. The first CPU 10 and the second CPU 11 detect negation by referring to the corresponding stall control signal STL-CNT, and execute a return instruction. When the stall control signal generation circuit 221 uses the return instruction execution signal RTB-CNT to realize the simultaneous execution mode, it is not necessary to know the execution order of the return instructions in the first CPU 10 and the second CPU 11 in advance. The return instruction execution signal RTB-CNT is asserted during execution of the return instruction in the corresponding CPU, and the return from the break state can be detected before execution of the return instruction is completed. For this reason, the simultaneous execution using the return instruction execution signal RTB-CNT can reduce the clock shift as compared with the simultaneous execution using the break acknowledge signal BRK-ACK.

  The concurrent execution control register 222 enables setting of the concurrent execution mode and the individual execution mode. Specifically, a plurality of bits corresponding to the first CPU 10 and the second CPU 11 are provided, and when the logical value is “0”, the execution of the return instruction in the first CPU 10 and the second CPU 11 is set to the individual execution mode. Is set. For example, when the logical value of the bit corresponding to the first CPU 10 is “0”, the return instruction in the first CPU 10 and the return instruction in the second CPU 11 are executed individually. On the other hand, when the logical value of the bit is “1”, the execution of the return instruction in the first CPU 10 and the second CPU 11 is set to the simultaneous execution mode. For example, when the logical value of the bit corresponding to the first CPU 10 is “1”, the execution of the return instruction in the second CPU 11 is controlled to be executed simultaneously with the return instruction in the first CPU 10.

  The simultaneous execution control register 222 may have a 1-bit configuration. Specifically, when the simultaneous execution control register has a logical value “0”, an individual execution mode is designated. In this case, the execution of the return instruction in the first CPU 10 and the second CPU 11 is executed individually in response to the corresponding break acknowledge signal BRK-ACK or return instruction execution signal RTB-CNT. On the other hand, when the simultaneous execution control register has a logical value “1”, the simultaneous execution mode is designated. By simultaneously negating the asserted stall control signal STL-CNT to the first CPU 10 and the second CPU 11, a return instruction is executed simultaneously by the first CPU 10 and the second CPU 11.

  FIG. 6 shows a configuration example of the break control circuit 23.

  The break control circuit 23 is not particularly limited, but as shown in FIG. 6, a program factor break request circuit (PRG-BRK-REQ) 230, an external factor break request circuit (EXT-BRK-REQ) 231, a condition satisfaction break A request circuit (CON-BRK-REQ) 232 and break request mask circuits 233 and 234 are included.

  The program factor break request circuit 230 fetches the break acknowledge signal BRK-ACK from the first CPU 10 or the second CPU 11 and asserts the break request signal 235 based on the break acknowledge signal BRK-ACK, for example, when a predetermined break instruction is executed in the execution of the user program. To do. In other words, the break status of the CPU is grasped by the break acknowledge signal BRK-ACK, and the break request signal 235 for causing the other CPU to break is asserted accordingly. This break request signal 235 is transmitted to the subsequent break request mask circuits 233 and 234.

  The external factor break request circuit 231 asserts a break request signal 236 based on a break factor given from the outside of the microcomputer 1 via an external terminal (not shown). The break request signal 236 is transmitted to the subsequent break request mask circuits 233 and 234. The condition satisfaction break request circuit (CON-BRK-REQ) 232 monitors the CPU bus data CPUB-DATA and system bus data SYSB-DATA of each CPU, and the CPU bus data CPUB-DATA is set to a preset break. When the condition is met, the break request signal 237 is asserted. This break request signal 237 is transmitted to the subsequent break request mask circuits 233 and 234.

  The break request mask circuits 233 and 234 are arranged corresponding to the CPUs 10 and 11, and mask the break request signals 235, 236 and 237 in accordance with the set break mode, so that the break target CPUs can be controlled. Only for that, the break request signal BRK-REQ is asserted.

  The break request mask circuit 233 asserts a break request signal BRK-REQ for the first CPU 10, and the break request mask circuit 234 asserts a break request signal BRK-REQ for the second CPU 11. Break request mask circuits 233 and 234 have the same configuration. For example, as shown in FIG. 7, the break request mask circuit 233 includes a program factor break request mask unit (PRG-BRK-REQ-MSK) 30-1, an external factor break request mask unit (EXT-BRK-REQ-MSK). 30-2, a condition satisfaction break request mask part (CON-BRK-REQ) 30-3, and an OR gate 32 for obtaining an OR logic of the outputs thereof. The program factor break request mask unit 30-1, the external factor break request mask unit 30-2, and the condition satisfaction break request mask unit 30-3 correspond to the break request mask circuits 233 and 234 shown in FIG. Then, the transmitted break request signals 235, 236, and 237 are masked. That is, the program factor break request mask unit 30-1 includes a mask register (MSK-PRG) 31-1, and performs a mask process of the break request signal 235 according to the setting information of the mask register 31-1. The external factor break request mask unit 30-2 includes a mask register (MSK-PRG) 31-2 and performs a mask process for the break request signal 236 in accordance with the setting information of the mask register 31-2. The condition satisfaction break request mask unit 30-2 includes a mask register (MSK-PRG) 31-3, and performs mask processing of the break request signal 237 according to the setting information of the mask register 31-3. For example, when the logical value “1” is set in the mask registers 31-1, 31-2, and 31-3, the corresponding break request signals 235, 236, and 237 are output as they are without being masked. At 32, the OR logic is obtained. On the other hand, when the logical value “0” is set in the mask registers 31-1, 31-2, 31-3, the corresponding break request signals 235, 236, 237 are masked. When masked, the corresponding output signal is fixed to a logical value “0”. By such mask processing, the break request signal BRK-REQ can be asserted to any CPU 10 or 11 regardless of whether the break factor is in the first CPU 10 or the second CPU 11. For example, when the break request signal 235, 236, 237 is masked by the break request mask circuit 233, the break request signal BRK-REQ for the first CPU 10 is not asserted. When the break request signals 235, 236 and 237 are masked by the break request mask circuit 234, the break request signal BRK-REQ for the second CPU 11 is not asserted. On the other hand, when the break request signals 235, 236, and 237 are not masked in any of the break request mask circuits 233 and 234, the first CPU 10 and the second CPU 11 are independent of whether the break factor is the first CPU 10 or the second CPU 11. When the break request signal BRK-REQ is asserted for both of them, a simultaneous break is enabled.

  FIG. 8 shows a configuration example of the condition satisfaction break request circuit (CON-BRK-REQ) 232 in FIG.

  Although the condition satisfaction break request circuit 232 is not particularly limited, as shown in FIG. 8, a plurality of condition match determination circuits (CND-JUD) 25-1, 25-2,..., 25-n (n is a natural number) And a sequential break determination circuit 27. The plurality of condition coincidence determination circuits 25-1, 25-2,..., 25-n include break condition registers (BRK-CND-REG) 26-2, 26-2,. When the CPU bus data CPUB-DATA from the second CPU 11 matches the setting information in the break condition registers 26-2, 26-2,..., 26-n, the corresponding condition match flag CNDM-FLG is asserted. Have The break condition registers 26-1, 26-2,..., 26-n include a CPU selection field 310 and a bus state selection field 320 as shown in FIG. In the CPU selection field 310, 2-bit CPU identification information to be subjected to break condition match determination is set. This CPU identification information is, for example, “01” when the break condition match determination target is only the first CPU 10, and “10” when the break condition match determination target is only the second CPU 11. When the target is both the first CPU 10 and the second CPU 11, “11” is set. In the bus state selection field 320, a compare condition (break condition) is set. The compare condition is not particularly limited, but includes bus designation, address, command, data, bus cycle, and the like. In addition, by having multiple break condition registers, it is possible to set multiple compare conditions (break conditions), and to set many compare conditions with one system debug setting, improving debugging efficiency. It becomes.

  The sequential break determination circuit 27 takes in the condition match flags CNDM-FLG from the plurality of condition match determination circuits 25-1, 26-2,..., 25-n, and determines whether the sequential break condition is satisfied. When the break condition is satisfied, the sequential break condition match flag SCNDM-FLG is asserted. The sequential break condition is a combination of a plurality of break conditions, and is considered to be matched when the break conditions are matched according to a certain order. The sequential break condition is set in the sequential break condition register 28 in the sequential break determination circuit 27, and the sequential break determination circuit 27 establishes a break condition that can occur sequentially based on the setting information in the sequential break condition register 28. It is determined whether or not. For example, when the break condition is established in the condition coincidence determination circuit 25-1 after the break condition is established in the condition coincidence determination circuit 25-2, when the sequential break condition is set in the sequential break condition register 28, When the condition is satisfied, the sequential break condition coincidence flag SCNDM-FLG is asserted. Such a sequential break enables more advanced break condition determination in addition to the break condition determination in the condition matching determination circuits 25-1 to 25-n.

  FIG. 3 shows a configuration example of the debug interface circuit 21.

  Although not particularly limited, the debug interface circuit 21 includes a JTAG (Joint Test Action Group) control unit (JTAG-CNT) 211 and a control circuit (CNTR) 212 as shown in FIG.

  The JTAG control unit 211 includes a bypass register (SDBPR) 51, a shift register (S-REG) 53, a multiplexer (MUX) 52, and a TAP (Test Access Port) control circuit (TAP-CNT) 54. A test input data signal TDI, a test output data signal TDO, a clock signal TCK, a test signal TMS, a test control signal TMS, which are JTAG predetermined signals, are connected to the outside of the microcomputer 1 via a plurality of common debug test terminals 5. The reset signal / TRST can be exchanged. Under the control of the TAP control circuit (TAP-CNT) 54, the value input from the TDI is interpreted as a control command or data using an IEEE-compliant internal control scan method (JTAG scan method), and debug information External output is possible.

  The control circuit 212 is coupled to the shift register 53 in the JTAG control unit 211 so that data can be exchanged with the JTAG control unit 211, and the control circuit 212 is connected to the execution control circuit 22 and the break control circuit 23. Various signals CNT such as control signals and data can be exchanged. The control circuit 212 includes a reset control register (RST-CNT-REG) 55 for reset control.

  The control circuit 212 generates a reset signal RST for resetting the first CPU 10 and the second CPU 11 according to the setting information in the reset control register 55. The reset register 55 includes bits corresponding to the first CPU 10 and the second CPU 11 on a one-to-one basis. The control circuit 212 asserts a reset signal RST for the first CPU 10 and the second CPU 11 by setting a logical value “1” in a bit corresponding to the first CPU 10 and the second CPU 11, and corresponds to the first CPU 10 and the second CPU 11. An individual reset mode in which a reset signal RST for the first CPU 10 and the second CPU 11 is negated by setting a logical value “0” in the bit is provided. The control circuit 212 has a simultaneous reset mode in which the reset signal RST corresponding to the first CPU 10 and the second CPU 11 is asserted simultaneously and then negated. The individual reset mode and the simultaneous reset mode can be appropriately selected in consideration of debugging efficiency.

  FIG. 4 shows another configuration example of the debug interface circuit 21.

  The configuration shown in FIG. 4 is greatly different from that shown in FIG. 3 in that a reset control circuit (RST-CNT) 213 is provided, and accordingly, the reset control register 55 in the control circuit 212 is omitted. Is a point.

  The control circuit 212 is coupled to the shift register 53 in the JTAG control unit 211 so that data can be exchanged with the JTAG control unit 211, and the control circuit 212 is connected to the execution control circuit 22 and the break control circuit 23. Various signals CNT such as control signals and data can be exchanged. The reset control circuit (RST-CNT) 213 interprets a reset command input from the TDI by being coupled to the shift register 53 and the TAP control circuit (TAP-CNT) 54 in the JTAG control unit 211. And an individual reset mode in which a reset signal RST for resetting the first CPU 10 and the second CPU 11 is individually asserted or negated. The reset control circuit 213 has a simultaneous reset mode in which the reset signal RST corresponding to the first CPU 10 and the second CPU 11 is asserted simultaneously and then negated. The individual reset mode and the simultaneous reset mode can be appropriately selected in consideration of debugging efficiency.

  According to the above example, the following effects can be obtained.

  (1) Since either of the first CPU 10 or the second CPU 11 has a simultaneous break mode in which the CPUs 10 and 11 can be simultaneously broken when a break condition is established in either of the first CPU 10 and the second CPU 11, Thus, it is possible to minimize the deviation in instruction execution between the plurality of CPUs 10 and 11 after the break condition is satisfied. In addition, since the user program execution start timing due to the return from the break state has a simultaneous execution mode in which the first CPU 10 and the second CPU 11 can coincide with each other, the timing shift of the user program execution due to the return from the break state is prevented It can be minimized between the CPUs 10 and 11. Thereby, it is possible to achieve improved debugging efficiency in system debugging of the microcomputer 1 including the first CPU 10 and the second CPU 11.

  (2) The break request mask circuits 233 and 234 are arranged corresponding to the CPUs 10 and 11, and are set as break targets by masking the break request signals 235, 236 and 237 according to the set break mode. The break request signal BRK-REQ is asserted only with respect to the CPU that performs the above processing. By such mask processing, the break request signal BRK-REQ can be asserted to any CPU 10 or 11 regardless of whether the break factor is in the first CPU 10 or the second CPU 11.

  (3) The sequential break determination circuit 27 fetches the condition match flags CNDM-FLG from the plurality of condition match determination circuits 25-1, 25-2,..., 25-n, and determines whether the sequential break condition is satisfied. If the break condition is satisfied, the sequential break condition coincidence flag SCNDM-FLG is asserted. When such a sequential break is performed, in addition to the break condition determination in the condition coincidence determination circuits 25-1 to 25-n, more advanced break condition determination can be performed.

  (4) The reset control circuit 213 included in the debug interface 21 has an individual reset mode in which the reset signal RST is individually asserted or negated. If such an individual reset is applied, it is possible to reset the other CPU executing another user program while operating one CPU executing a certain user program. More detailed control of the CPU becomes possible, and improvement in debugging efficiency can be achieved.

  FIG. 10 shows another configuration example of a microcomputer as an example of the data processing apparatus according to the present invention.

  The microcomputer 1 shown in FIG. 10 includes a first CPU 100, a second CPU 110, a debug circuit (DEBUG) 200, various peripheral modules (MODL) 120-1 to 120-n, a DMAC (direct memory access controller) 140, and The clock module (CLK-MODL) 300 is included and is not particularly limited, but is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. The first CPU 100, the second CPU 110, the DMAC 140, the debug circuit 200, and various peripheral modules 120-1 to 120-n are coupled via a system bus 130. The first CPU 100, the second CPU 110, and the DMAC 140 are bus masters for the system bus 130, respectively, and can acquire the bus right of the system bus 130 and perform transfer control of various data.

  The debug circuit 200 is coupled to the system bus 130, the first CPU 100, and the second CPU 110, and enables debugging of user programs executed by the first CPU 100 and the second CPU 110. The branch information BRA-INF # 0 and CPU bus information BUS-INF # 0 are transmitted from the CPU 100 to the debug circuit 200. The debug access information ACC-INF # 0 can be exchanged between the debug circuit 200 and the CPU 100. Branch information BRA-INF # 1 and CPU bus information BUS-INF # 1 are transmitted from the CPU 110 to the debug circuit 200. The debug access information ACC-INF # 1 can be exchanged between the debug circuit 200 and the CPU 100.

  The clock module CLK-MODL 300 forms a plurality of clock signals having different frequencies. The plurality of clock signals include a debug clock signal clkd, CPU clock signals clki0 and clki1, and a peripheral module clock signal clkb. The debug clock signal clkd is supplied to the debug circuit 200. The CPU clock signal clki0 is supplied to the CPU 100 and the debug circuit 200. The CPU clock signal clki1 is supplied to the CPU 110 and the debug circuit 200. The peripheral module clock signal clkb is supplied to the peripheral modules 120-1 to 120-n, the DMAC 140, the CPUs 100 and 110, and the debug circuit 200.

  The debug result of the user program executed by the first CPU 100 and the debug result of the user program executed by the second CPU 110 may be output from the debug circuit 200 to the outside of the microcomputer 1 via the common debug terminal 50. it can. Of the debug results, the trace information can be externally output via a dedicated trace terminal group 60.

  FIG. 11 shows a configuration example of the first CPU 100.

  The first CPU 100 includes, but is not limited to, a CPU core 101, an in-module memory 102, and a bus bridge 103, which are coupled to each other by a CPU bus 104 so as to exchange signals. CPU bus information BUS-INF # 0 is extracted from the CPU bus 104. The first CPU 100 executes a predetermined program for arithmetic processing. The in-module memory 102 includes a ROM (Read Only Memory) in which a program executed by the CPU core 101 is stored, and a RAM (Random / Random) used as a work area for arithmetic processing in the CPU core 101. Access memory). The branch information BRA-INF # 0 in the program execution is extracted from the CPU core 101. The CPU bus 104 and the system bus 130 are coupled by a bus bridge 103. The debug access information ACC-INF # 0 is extracted from the bus bridge 103.

  The second CPU 110 is configured in the same manner as the first CPU 100.

  FIG. 12 shows a configuration example of the debug circuit 200.

  Although not particularly limited, the debug circuit 200 includes a debug interface 201, an execution control circuit 202, a break control circuit 203, a debug access circuit 204, a first trace acquisition circuit 205, and a second trace acquisition circuit 207.

  The execution control circuit 202 controls execution of debugging. The break control circuit 203 controls a break operation based on a preset break condition. The debug access circuit 204 performs debug access via the system bus 130. The bus bridge 103 is also connected to a signal line for debug access information ACC-INF # 0. As a result, the debug circuit DEBUG 200 can access devices on the system bus.

  The debug interface 201 is coupled to the debug terminal 50, the execution control circuit 202, the break control circuit 203, and the debug access circuit 204, and can exchange predetermined signals with the JTAG (Joint Test Action Group) specification. And

  The first trace acquisition circuit 205 and the second trace acquisition circuit 207 have a function of monitoring the state of the bus in the system and acquiring a state that matches a predetermined condition. The first trace acquisition circuit 205 and the second trace acquisition circuit 207 include trace information such as branch information BRA-INF # 0, BRA-INF # 1, CPU bus information BUS-INF # 0, BUS-INF # 1. Is captured. The first trace acquisition circuit 205 and the second trace acquisition circuit 207 are respectively coupled to the system bus 130, and various control information related to traces can be exchanged via the system bus 130. The trace information acquired by the first trace acquisition circuit 205 can be output to the system bus 130 as necessary. The second trace acquisition circuit 207 is coupled to the trace terminal 60, and the trace information acquired by the second trace acquisition circuit 207 can be externally output via the trace terminal 60.

  FIG. 13 shows a configuration example of the first trace acquisition circuit 205.

  The first trace acquisition circuit 205 includes a trace processing unit 205A that performs trace processing, and a trace control unit 205B that controls the trace processing in the trace processing unit 205A. The trace processing unit 205A includes trace information input units 251 to 253, synchronization units 255 to 257, trace information processing unit 258, selection units 259 and 260, synchronization unit 261, and trace memory 262.

  The trace information input unit 251 takes in the branch information BRA-INF # 0 and the CPU bus information BUS-INF # 0 in synchronization with the CPU clock signal clki0. The fetched information is transmitted to the synchronization unit 255 at the subsequent stage, where it is synchronized with the debug clock signal clkd and then transmitted to the trace information processing unit 258 at the subsequent stage.

  The trace information input unit 252 takes in the branch information BRA-INF # 1 and the CPU bus information BUS-INF # 1 in synchronization with the CPU clock signal clki1. The fetched information is transmitted to the subsequent synchronization unit 256, where it is synchronized with the debug clock signal clkd and then transmitted to the subsequent trace information processing unit 258.

  The trace information input unit 253 takes in the system bus information SYS-INF in the system bus 130 in synchronization with the peripheral module clock signal clkb. The fetched information is transmitted to the subsequent synchronization unit 257, where it is synchronized with the debug clock signal clkd and then transmitted to the subsequent trace information processing unit 258.

  The trace information processing unit 258 has a function for selectively fetching information transmitted via the synchronization units 255, 256, and 257 in accordance with conditions preset in the trace control unit 205B. The operation of the trace information processing unit 258 is operated in synchronism with the debug clock signal clkd. Information selectively captured by the trace information processing unit 258 is transmitted to the selection units 259 and 260.

  The trace memory 262 is operated in synchronization with the debug clock signal clkd, and the first storage area 263 for storing information transmitted through the selection unit 259 and the information transmitted through the selection unit 260. And a second storage area 264 for storing. The information stored in the first storage area 263 can be transmitted to the system bus 130 via the selection unit 259, the synchronization unit 260, and the trace control unit 205B. The information stored in the second storage area 264 can be transmitted to the system bus 130 via the selection unit 260, the synchronization unit 261, and the trace control unit 205B. The synchronization unit 261 synchronizes the information transmitted from the trace control unit 205B with the debug clock signal clkd and the information transmitted via the selection units 259 and 260 with the peripheral module clock signal clkb. It has the function to do.

  The trace control unit 205B includes a control register 254, and the operation of the trace processing unit 205A is controlled in accordance with information set in the control register 254. The trace control unit 205B is operated in synchronization with the peripheral module clock signal clkb.

  FIG. 14 shows the format of the trace information data stored in the trace memory 262.

  The branch information packet BRA-PKT includes a branch type field, a time stamp field, a branch destination address field, and a branch source data field. The CPU bus information packet BUS-PKT includes a CPU bus command field, a time stamp field, a CPU bus address field, and a CPU bus data field. The system bus information packet SYS-PKT includes a system bus command field, a time stamp field, a system bus address field, and a system bus data field. The time stamp indicates the time when the packet is generated, and stores the count value of a counter (not shown). Based on the information given from the branch information BRA-INF # 0 and BRA-INF # 1 supplied to the debug circuit 200, the branch information packet BRA-PKT including the branch type, the branch destination address, and the branch source address is configured. The Based on information given from the CPU bus information BUS-INF # 0 and BUS-INF # 1, a CPU bus information packet BUS-PKT including a CPU bus command, a CPU bus address, and CPU bus data is constructed. Based on the information given from the system bus information SYS-INF, the system bus information packet SYS-PKT including the system bus command, system bus address, and system bus data is constructed.

  FIG. 15 shows a configuration example of the second trace acquisition circuit 207.

  The second trace acquisition circuit 207 includes a trace processing unit 207A that performs trace processing, and a trace control unit 207B that controls the trace processing in the trace processing unit 207A. The trace processing unit 207A includes trace information input units 271 to 273, synchronization units 275 to 277, a trace information processing unit 258, and a trace information output unit 279.

  The trace information input unit 271 takes in the branch information BRA-INF # 0 and the CPU bus information BUS-INF # 0 in synchronization with the CPU clock signal clki0. The fetched information is transmitted to the synchronization unit 275 at the subsequent stage, where it is synchronized with the debug clock signal clkd and then transmitted to the trace information processing unit 278 at the subsequent stage.

  The trace information input unit 272 takes in the branch information BRA-INF # 1 and the CPU bus information BUS-INF # 1 in synchronization with the CPU clock signal clki1. The fetched information is transmitted to the synchronization unit 276 at the subsequent stage, where it is synchronized with the debug clock signal clkd and then transmitted to the trace information processing unit 278 at the subsequent stage.

  The trace information input unit 273 takes in the system bus information SYS-INF in the system bus 130 in synchronization with the peripheral module clock signal clkb. The fetched information is transmitted to the subsequent synchronization unit 277, where it is synchronized with the debug clock signal clkd and then transmitted to the subsequent trace information processing unit 278.

  The trace information processing unit 278 has a function for selectively taking in the information transmitted via the synchronization units 275, 276, and 277 in accordance with conditions preset in the trace control unit 207B. The operation of the trace information processing unit 278 is synchronized with the debug clock signal clkd. Information selectively captured by the trace information processing unit 278 can be externally output via the trace information output unit 280. The trace information output unit 280 includes a FIFO (first-in first-out) buffer 280, and external output is possible in the order written in the FIFO buffer 280.

  The trace control unit 207B includes a control register 274, and the operation of the trace processing unit 207A is controlled in accordance with information set in the control register 274. The trace control unit 207B is operated in synchronization with the peripheral module clock signal clkb.

  FIG. 16 shows a format of a trace information packet output to the outside of the microcomputer 1 through the trace information output unit 279.

  The format of the trace information packet PKT output to the outside via the trace information output unit 279 includes command fields CMD1 and CMD2 and data fields DA0 to DA15 as shown in FIG. The presence or absence of the command field CMD2 is determined by the type of command indicated in the command field CMD1. The presence or absence of the data fields DA0 to DA15 is determined according to the type of the command field CMD2.

  For example, when there is no information to be output in the output of the trace information packet PKT, the STDBY command (0000) is output to CMD1. The STDBY command is completed only by CMD1.

  For example, when branch trace information is output according to the format of the trace information packet PKT, a BGC command (0100) is output to the command field CMD1. In the case of the BGC command, the command field CMD2 is output subsequently. The CMD2 command indicates the number of data fields to be output thereafter. In the data fields DA0 to DA15, a branch source address and a branch destination address are stored. This data field is compressed as necessary. For this reason, the number of data fields is not constant. Although details of the compression method are not particularly described, for example, a method of expressing the branch destination address by a difference from the branch source address is used.

  Here, in order to make it possible to identify whether the trace information packet PKT output from the trace information output unit 279 is related to the program execution in the first CPU 100 or the program execution in the second CPU 110. , MSID command (0010) is provided. The MSID command indicates whether the source data of the CPU packet to be output next from the trace information output unit 279 is related to the first CPU 100 or the second CPU 110. A command field CMD2 is output after the MSID command output as the command field CMD1. This CMD2 indicates “CPUID”, that is, the origin of data. For example, when CMD2 is “H′0”, the first CPU 100 is used, and when CMD2 is “H′1”, the second CPU 110 is used. Therefore, on the receiving side of the trace information output from the trace information output unit 279, the source data of the CPU packet output next from the trace information output unit 279 is related to the first CPU 100 by the “MSID”. Or the second CPU 110 can be identified.

  FIG. 17 shows the output conditions of the “MSID” packet.

  In order to output the “MSID” packet from the trace information output unit 279, it is necessary that a plurality of CPUs be traced (condition A). In this example, both the first CPU 100 and the second CPU 110 are required to be set in the control register 274 in the trace control unit 207B as the trace targets.

  Further, it is necessary to output the CPU packet next from the trace information output unit 279 (condition B).

  Then, the CPU packet to be output next from the trace information output unit 279 is the first CPU packet to be output after outputting N × 256 data packets (N is an integer greater than or equal to zero) (control packet is not included). Or the data source of the CPU packet to be output next is different from the data source of the CPU packet output last.

  When the above conditions are satisfied, an “MSID” packet is output from the trace information output unit 279.

  FIG. 18 shows the timing when the trace information packet PKT from the trace information output unit 279 is output.

  The trace information packet PKT is output in synchronization with the debug clock signal clkd during the period when the trace synchronization signal is set to the low level by the trace control unit 207B. This is an example in which the command field CMD2 and the data fields DA0 to DA5 are output after the BGC command is output to the command field CMD1. The first 4 data fields store 16-bit branch destination addresses (DA3-0, DA7-4, DA11-8 and DA15-12), and the next 2 data fields contain 8-bit branch sources. Addresses (SA3-0, SA7-4) are stored.

  FIG. 19 shows a configuration example of the clock module 300.

  Although not particularly limited, the clock module 300 includes a clock control unit 301, a high-speed clock generator 303, a clock frequency divider 304, and a clock driver 305.

  The high-speed clock generator 303 generates a high-speed clock signal (internal clock signal) PLL-CLK having a frequency higher than that of the reference clock signal 306 in synchronization with a reference clock signal 306 given from the outside. The high-speed clock generator 303 is formed by, for example, a PLL (Phase Locked Loop). The high-speed clock signal PLL-CLK formed by the high-speed clock generator 303 is divided by the clock divider 304 at the subsequent stage, so that a plurality of divided clock signals div_clkd, div_clki0, Div_clki1 and div_clkb are formed. For example, some of the divided clock signals may have the same division ratio. The plurality of divided clock signals are transmitted to the clock driver 305 at the subsequent stage. The clock driver 305 drives the load based on the input divided clock signals div_clkd, div_clki0, div_clki1, and div_clkb. The output clock signal from the clock driver 305 is used as a debug clock signal clkd, CPU clock signals clki0 and clki1, and a peripheral module clock signal clkb.

  The clock control unit 301 includes a clock control register 302 and controls operations of the high-speed clock generator 304, the clock divider 304, and the clock driver 305 according to information set in the clock control register 302. The clock control register 302 can be rewritten by the first CPU 100 or the second CPU 110 via the system bus 130.

  FIG. 20 shows a configuration example of the clock frequency divider 304.

  The clock divider 304 includes, but is not limited to, a divider circuit 341 for dividing the clock signal PLL-CLK output from the high-speed clock generator 303, selection circuits 342 to 345, and a minimum selection circuit 350. .

  The divided output of the frequency divider 341 includes a 1/1 divided output, 1/2 divided output, 1/4 divided output, 1/8 divided output, and 1/16 divided clock signal PLL-CLK. Round output and 1/32 frequency division output are included. The 1/1 divided output is equal to the frequency of the clock signal PLL-CLK, and the frequency decreases in the order of 1/2 divided output, 1/4 divided output, 1/8 divided output, and 1/16 divided output. .

  The selection circuits 342 to 345 include multiplexers (MUX) 346 to 349, respectively. The multiplexer 346 incorporated in the selection circuit 342 outputs the CPU clock signal clki0 by selecting the output signal of the frequency dividing circuit 341 in accordance with the clki0 frequency division ratio information corresponding to the CPU clock signal clki0. The multiplexer 347 incorporated in the selection circuit 343 outputs the CPU clock signal clki1 by selecting the output signal of the frequency dividing circuit 341 according to the clki1 frequency division ratio information corresponding to the CPU clock signal clki1. The multiplexer 348 built in the selection circuit 344 outputs the peripheral module clock signal clkb by selecting the output signal of the frequency dividing circuit 341 according to the clkb frequency division ratio information corresponding to the peripheral module clock signal clkb. The peripheral module clock signal clkb is the same as or lower in frequency than any one of the CPU clock signals clki0 and clki1.

  The minimum selection circuit 350 compares clki0 division ratio information and clki1 division ratio information, selects the smaller division ratio information, and supplies it to the multiplexer 349. Accordingly, the multiplexer 349 outputs the debug clock signal clkd by selecting the output signal of the frequency dividing circuit 341 according to the smaller frequency division ratio information of the clki0 frequency division ratio information and the clki1 frequency division ratio information. Thus, the debug clock signal clkd is always equal to the frequency of the clock signal having the higher frequency of the CPU clock signals clki0 and clki1, and debugging is performed based on the debug clock signal clkd.

  FIG. 22 shows a clock waveform of a main part in the clock frequency divider 304.

  In this example, the debug clock signal clkd is equal to the frequency of the CPU clock signal clki1.

  FIG. 23 shows a case where the frequency of the CPU clock signal is changed.

  In this example, the frequency of the CPU clock signal clki0 is changed at time T1. In order to prevent malfunction, the clock frequency is changed in synchronization with the rising edge of the clock signal having the lowest frequency (in this example, clkb). Since the frequency of the CPU clock signal clki1 is higher than that of the CPU clock signal clki0 from time T0 to time T1, the frequency of the debug clock signal clkd is made equal to the CPU clock signal clki1. However, since the frequency of the CPU clock signal clki0 is higher than that of the CPU clock signal clki1 after time T1, the frequency of the debug clock signal clkd is equal to the CPU clock signal clki0. Even when there is a frequency change, the CPU clock signal having a higher frequency is dynamically supplied as the debug clock signal clkd by the control of the minimum selection circuit 350 and other circuits, and the debug circuit is operated based on the CPU clock signal. The

  Thus, in the system debug of the microprocessor including a plurality of CPUs, even when the operation speeds between the plurality of CPUs are different, the debug clock signal clkd is the higher one of the clock signals clki0 and clki1 for the CPU. Since the frequency is always equal, the debug clock signal clkd supplied to the debug circuit 200 is set to an appropriate frequency. Thereby, smooth tracing can be performed.

  FIG. 21 shows a configuration example of the clock driver 305.

  Although not particularly limited, the clock driver 305 includes four AND gates (AND) 351 to 354 corresponding to the divided clock signals div_clkd, div_clki0, div_clki1, and div_clkb from the clock divider 304. CPU clock signals clki0 and clki1, peripheral module clock signal clkb, and debug clock signal clkd are output from AND gates 351 to 354, respectively. Corresponding frequency-divided clock signals div_clkd, div_clki0, div_clki1, div_clkb are transmitted to one input terminal of the four AND gates 351 to 354, and to the other input terminal of the AND gates 351 to 353. Driver control information clki0_en, clki1_en, clki0_en is transmitted from the clock control unit 301. A debug mode signal is transmitted from the clock control unit 301 to the other input terminal of the AND gate 354. This debug mode signal is asserted to a high level only while the microcomputer 1 is in the debug mode, and negated to a low level in the non-debug mode of the microcomputer 1. Therefore, the debug clock signal clkd is formed only during the period in which the microcomputer 1 is in the debug mode, and is not formed in the non-debug mode of the microcomputer 1. As a result, the debug circuit 200 operates only during the period in which the microcomputer 1 is in the debug mode and does not operate in the non-debug mode of the microcomputer 1. Reduction can be achieved.

  According to the above example, the following operational effects can be obtained.

  (1) In system debugging of a microprocessor including a plurality of CPUs, even when the operation speeds between the plurality of CPUs are different, the debug clock signal clkd is the higher of the clock signals clki0 and clki1 for the CPU. Since the frequency is always equal, the debug clock signal clkd supplied to the debug circuit 200 is set to an appropriate frequency. As a result, even when any of a plurality of CPUs operates at high speed, the debug circuit is supplied with a high-speed clock and can operate in synchronization with it to perform smooth tracing.

  (2) A debug mode signal is transmitted from the clock control unit 301 to the other input terminal of the AND gate 354, so that the debug clock signal clkd is a period during which the microcomputer 1 is in the debug mode. Only in the non-debug mode of the microcomputer 1. By not operating the debug circuit 200 in the non-debug mode of the microcomputer 1, current consumption in the non-debug mode of the microcomputer 1 can be reduced.

  Although the invention made by the present inventor has been specifically described above, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above example, a microcomputer having two CPUs has been described. However, when three or more CPUs are mounted, the number of break request mask circuits (233, 234) corresponding to the number of CPUs and the simultaneous execution control registers By increasing the number of bits of 222, the number of bits of the reset control register 55, etc., it is possible to cope easily. Further, the CPUs may be formed on the same semiconductor substrate, or may be a plurality of CPUs formed on a plurality of semiconductor substrates formed in the same package.

  For example, when three CPUs are mounted on one semiconductor substrate, if one break request mask circuit (233, 234) is set to mask a break request, two CPUs can be selectively broken simultaneously. . If the number of bits of the simultaneous execution control register 222 is set to 3 and 2 bits are set to the logical value “1”, two CPUs can be selectively executed simultaneously. Further, by setting the number of bits of the reset control register 55 to 3, and setting 2 bits thereof to the logical value “1” and then clearing them to the logical value “0”, the two CPUs can be selectively reset simultaneously.

  Since the frequency of the CPU clock signals clki0 and clki1 is never higher than the output clock signal PLL-CLK of the high-speed clock generator 303, the output clock signal PLL-CLK of the high-speed clock generator 303 is used as it is as a debugging clock signal. Even if it is used for clkd, it is possible to obtain the same operational effects as in the above example. In this case, the selection circuit 345 and the minimum selection circuit 350 in FIG. 20 are unnecessary.

  In the above example, the system bus has been described as a bus that obtains the bus right and performs various data transfer control.For example, there are a plurality of buses, and each bus can operate in parallel. The connected bus masters may be multi-layer buses that can operate in parallel as long as the devices to be accessed do not overlap, or may be composed of split transaction buses that separate the request bus and response bus Good. In the above description, the case where the invention made mainly by the present inventor is applied to the microcomputer which is a field of use as the background has been described. However, the invention can be widely applied to various data processing devices incorporating a plurality of CPUs. .

  The present invention can be applied on condition that at least a CPU is provided.

1 is a block diagram showing an example of the overall configuration of a microcomputer as an example of a data processing apparatus according to the present invention. It is a block diagram of a configuration example of a debug circuit included in the microcomputer. It is a block diagram of a configuration example of a debug interface included in the debug circuit. It is another example block diagram of a configuration of a debug interface circuit included in the debug circuit. It is a block diagram of a configuration example of an execution control circuit included in the debug circuit. It is an example block of a break control circuit included in the debug circuit. It is a block diagram of a configuration example of a break request mask circuit included in the break control circuit. It is a block diagram of a configuration example of a condition satisfaction break request circuit included in the break control circuit. It is a field configuration explanatory view of a break condition register included in the condition satisfaction break request circuit. It is another example block diagram of a configuration of a microcomputer as an example of a data processing apparatus according to the present invention. FIG. 11 is a block diagram illustrating a configuration example of a first CPU in FIG. 10. FIG. 11 is a block diagram illustrating a configuration example of a debug circuit in FIG. 10. FIG. 13 is a block diagram illustrating a configuration example of a first trace acquisition circuit in FIG. 12. It is format explanatory drawing of the data stored in the trace memory contained in the said 1st trace acquisition circuit. FIG. 13 is a block diagram illustrating a configuration example of a second trace acquisition circuit in FIG. 12. FIG. 16 is a format explanatory diagram of data output from a trace information output unit illustrated in FIG. 15. It is explanatory drawing of the MSID packet output condition in the structure shown by FIG. FIG. 16 is a timing diagram of data packet output in the configuration shown in FIG. 15. FIG. 11 is a block diagram illustrating a configuration example of a clock module illustrated in FIG. 10. It is a block diagram of a configuration example of a clock divider included in the clock module. It is a block diagram of a configuration example of a clock driver included in the clock module. It is a clock waveform diagram of the principal part in the clock frequency divider included in the clock module. It is another clock waveform diagram of the main part in the clock frequency divider included in the clock module.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Microcomputer 2 Debug circuit 5 Debug terminal 10 1st CPU
11 Second CPU
12-1 to 12-n Peripheral module 13 System bus 21 Debug interface 22 Execution control circuit 221 Stall control signal generation circuit 222 Concurrent execution control register 23 Break control circuit 30-1 Program factor break request mask unit 30-2 External factor break request Mask section 30-3 Condition satisfaction break request mask section 230 Program factor break request circuit 231 External factor break request circuit 232 Condition satisfaction break request circuit 233, 234 Break request mask circuit STL-CNT Stall control signal BRK-ACK Break acknowledge signal RTB- CNT return instruction execution signal SCNDM-FLG Sequential condition match flag 100 1st CPU
110 Second CPU
120-1 to 120-n Peripheral module 130 System bus 140 DMAC
DESCRIPTION OF SYMBOLS 200 Debug circuit 201 Debug interface 202 Execution control circuit 203 Break control circuit 204 Debug access circuit 205 Trace acquisition circuit 205A Trace processing part 205B Trace control part 207 Trace acquisition circuit 207A Trace processing circuit 207B Trace control part 251-253 Trace information input part 254 Control registers 255 to 257, 261 Synchronization unit 258 Trace information processing unit 259 to 261 Selection unit 262 Trace memory 271 to 273 Trace information input unit 274 Control register 275 to 277 Synchronization unit 278 Trace information processing unit 279 Trace information output unit 300 Clock module 301 Clock control unit 302 Clock control register 303 High-speed clock generator 304 Clock divider 305 Clock driver 341 Frequency divider 342 to 345 Select circuit 346 to 349 Multiplexer 350 Minimum select circuit 351 to 354 AND gate

Claims (23)

A plurality of CPUs each having stop control means for stopping execution of the user program in response to an execution stop request for the user program, and restart control means for permitting or suppressing execution restart of the user program;
A data processing device including a debug circuit that enables debugging of user programs executed by the plurality of CPUs,
The data processing apparatus according to claim 1, wherein the debug circuit includes an execution control circuit having a simultaneous execution mode for simultaneously permitting the restart control means for the plurality of CPUs to resume execution of a user program. A plurality of CPUs each having stop control means for stopping execution of the user program in response to a request to stop execution of the user program, and restart control means for permitting or suppressing execution restart of the user program;
A data processing device including a debug circuit that enables debugging of user programs executed by the plurality of CPUs,
The debug circuit is configured to simultaneously execute a user program execution stop request to the stop control means for the plurality of CPUs in response to a break condition established in any of the plurality of CPUs. A break control circuit comprising:
A data processing apparatus comprising: an execution control circuit having a simultaneous execution mode for simultaneously permitting the restart control means for the plurality of CPUs to resume execution of a user program.   3. The data processing apparatus according to claim 1, wherein the debug circuit includes a debug interface for externally outputting a debug result of the user program executed by the plurality of CPUs from a common debug terminal.   The break control circuit individually performs a user program execution stop request individually to the stop control means for the plurality of CPUs when a break condition is established in any of the plurality of CPUs. 4. A data processing apparatus according to claim 2, wherein the data processing apparatus has a break mode.   4. The data processing apparatus according to claim 2, wherein the execution control circuit has an individual execution mode for individually permitting the restart control means for the plurality of CPUs to resume execution of a user program. The break control circuit includes: a break request circuit for forming a break request according to a predetermined break factor;
A break request mask circuit capable of requesting a CPU to be a break target to stop execution of a user program by masking the break request in accordance with a set break mode. 2. A data processing apparatus according to 2 or 3.   7. The data processing apparatus according to claim 6, wherein the break request circuit further includes a plurality of break condition registers each capable of setting a break condition, and performs break control for a corresponding CPU according to the setting conditions of the break condition setting register.   8. The data according to claim 7, wherein the break condition register includes a first field capable of setting a CPU to be observed and a second field capable of setting a break condition for the CPU set in the first field. Processing equipment.   The break control circuit further includes a sequential break condition register that enables a sequential break condition to be set by a combination of the plurality of break conditions, and determines a break condition on the basis of setting information of the sequential break condition register and supports The data processing apparatus according to claim 6, wherein the CPU can request the CPU to stop execution of the user program.   4. The data processing apparatus according to claim 3, wherein the debug interface includes a reset control circuit that can individually make a reset request to the plurality of CPUs based on an input signal from the debug terminal.   The debug interface can be set based on an input signal from the debug terminal, and includes a reset control register for controlling a reset request to the plurality of CPUs, and according to a set value of the reset signal control register 4. The data processing apparatus according to claim 3, wherein a reset request can be individually made to each of a plurality of CPUs.   The execution control circuit includes a simultaneous execution control register that enables control of the simultaneous execution mode and the individual execution mode, and sets each CPU according to the setting of the simultaneous execution control register and the states of the plurality of CPUs. 4. A data processing apparatus according to claim 2, further comprising a control signal for requesting resumption of execution of the user program.   13. The data processing apparatus according to claim 12, wherein the simultaneous execution control circuit refers to whether or not the plurality of CPUs are in a break state.   13. The data processing apparatus according to claim 12, wherein the simultaneous execution control circuit refers to whether or not a return instruction from a break is being executed as a state of the plurality of CPUs. A plurality of CPUs that operate in synchronization with the supplied CPU clock signals;
A debugging circuit that enables debugging of a user program executed by the plurality of CPUs based on a supplied debugging clock signal, and a data processing device including:
The frequency of the debug clock signal supplied to the debug circuit is f1, and the highest frequency among the CPU clock signals supplied to the plurality of CPUs is f2, so that f1 ≧ f2 is satisfied. A data processing apparatus comprising a clock control circuit for forming a clock signal for debugging and the clock signal for CPU. A first CPU that operates in synchronization with a clock signal for the first CPU;
A second CPU that operates in synchronization with a second CPU clock signal different from the first CPU clock signal;
A debugging circuit that enables debugging of a user program executed by the first CPU and the second CPU based on a debugging clock signal;
When the frequency of the debug clock signal is f1, and the higher one of the first CPU clock signal and the second CPU clock signal is f2, the debug clock signal is set so that f1 ≧ f2 is satisfied. And a data processing apparatus comprising a clock control circuit for generating the CPU clock signal. The debug circuit includes a first trace information input unit for capturing trace information about the first CPU in synchronization with the first CPU clock signal;
A second trace information input unit for capturing trace information about the second CPU in synchronization with the second CPU clock signal;
A first synchronization unit for synchronizing the trace information captured via the first trace information input unit with the debug clock signal;
A second synchronization unit for synchronizing the trace information captured via the second trace information input unit with the debug clock signal;
A trace information processing unit for selectively capturing the output information of the first synchronization unit and the output information of the second synchronization unit according to a preset condition based on the debug clock signal; 17. The data processing apparatus according to claim 16, further comprising:   18. The data processing apparatus according to claim 17, wherein the debug circuit includes a trace memory capable of storing information selectively captured by the trace information processing unit in a predetermined storage area based on the debug clock signal.   18. The data processing apparatus according to claim 17, wherein the debug circuit includes a trace information output unit for outputting a processing result of the trace information processing unit to the outside based on the debug clock signal.   20. The data processing apparatus according to claim 19, wherein the information output from the trace information output unit includes identification information that enables identification of trace information about the first CPU and trace information about the second CPU. The clock control circuit includes a clock generator for generating an internal clock signal synchronized with an input reference clock signal,
A clock divider for dividing the internal clock signal generated by the clock generator;
A clock driver for driving a load based on the output signal of the clock divider,
21. The data processing apparatus according to claim 16, wherein the clock driver includes a logic gate for outputting the debug clock signal to the outside only during a period in which debugging is performed. The clock control circuit includes a clock generator for generating an internal clock signal synchronized with an input reference clock signal,
A clock divider for dividing the internal clock signal generated by the clock generator;
A clock driver for driving a load based on the output signal of the clock divider,
The clock divider outputs a plurality of divided clock signals each having a different division ratio, and
A first multiplexer for selecting a corresponding divided clock signal from the plurality of divided clock signals according to the first division ratio information and outputting it as the first CPU clock signal;
A second multiplexer for selecting a corresponding divided clock signal from the plurality of divided clock signals according to second division information and outputting it as the second CPU clock signal;
The first division ratio information and the second division ratio information are compared to select a smaller division ratio information, and a divided clock corresponding to the plurality of divided clock signals according to the division ratio information. 21. A data processing apparatus according to claim 16, further comprising: a third multiplexer that selects a signal and outputs the selected signal as the debug clock signal. The clock control circuit includes a clock generator for generating an internal clock signal synchronized with an input reference clock signal,
A clock divider for dividing the internal clock signal generated by the clock generator;
A clock driver for driving a load based on the output signal of the clock divider,
The clock divider outputs a plurality of divided clock signals each having a different division ratio, and
A first multiplexer for selecting a corresponding divided clock signal from the plurality of divided clock signals according to the first division ratio information and outputting it as the first CPU clock signal;
A second multiplexer for selecting a corresponding divided clock signal from the plurality of divided clock signals according to second division information and outputting it as the second CPU clock signal;
21. The data processing apparatus according to claim 16, wherein a clock signal supplied from the clock generator to the clock divider is used as the debug clock signal.

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