JP5337661B2 - Memory control device and control method of memory control device - Google Patents

Description

  The present invention relates to a memory control device having a self-diagnosis function and a memory control method thereof.

  In potentially dangerous process facilities such as nuclear power plants and chemical plants, passive measures such as bulkheads and emergency stop devices are used to reduce the impact on workers and the surrounding environment in the event of an emergency. Active measures are taken using the safety device. Of these, control of safety devices and the like has been conventionally realized by electromagnetic and mechanical means such as relays.

  However, in recent years, with the development of technology in programmable control equipment represented by programmable electronic devices (Programmable Logic Controller: PLC), there is an increasing need to use these as control means of a safety control system.

  For example, IEC61508 is an international standard issued in response to such a trend, and defines requirements for using an electrical / electronic / programmable electronic safety control device as part of a safety control system. (See Non-Patent Document 1).

  In IEC61508, Safety Integrity Level (SIL) is defined as a measure of the capability of a safety control system, and requirements for levels corresponding to each level from level 1 to level 4 are defined. The higher the SIL, the greater the degree to which the potential danger of the process equipment can be reduced. That is, SIL means how reliably certain safety control can be performed when an abnormality of a process facility is detected.

  Even if the safety control device is inactive in the normal operation state, it is required to be activated immediately when an abnormality occurs in the process equipment. Therefore, it is important to always perform self-diagnosis and check its own soundness. In addition, in a safety control system that requires a high SIL, the probability that the system will not operate due to an undetected failure is minimized, so it is necessary to perform a wide range and high-precision self-diagnosis on the safety control device used for this. There is.

  In IEC61508, self-diagnosis techniques to be applied are introduced for each type of component parts constituting the safety control device, and the effectiveness of each technique is shown in the form of a diagnostic rate. The diagnosis rate indicates the proportion of failures that can be detected when the diagnosis technique is adopted among all failures in each component. For example, "Abraham", which is a RAM diagnostic technique, can claim a diagnosis rate of up to 99% (see Patent Document 2).

  In addition, a method of monitoring the consistency of the output results of each other using a plurality of processors is effective as a failure detection means for a processor that is one of the components of the PLC. As a method for mutually diagnosing the outputs of a plurality of processors, it is effective to perform a similar control process at the same time and confirm that the outputs match each other. For example, there is a technique in which the outputs of a plurality of processors operating asynchronously are collated to detect immediately even if a processor fails (Patent Document 1).

  In addition to mutual diagnosis by a plurality of processors, it is effective for improving the diagnostic rate to check the soundness of the output for each input / output element such as a memory or a bus.

JP 2007-11639 A US Registration No. 6779128

IEC61508-1-7, “Functional safety of electrical / electronic / programmable electronic safety-related systems” part1-part7

  In a memory control circuit that controls access to a memory, the access operation is one-way due to the characteristics of the memory element, and there is no means for detecting a transient abnormality that occurs during the memory access control operation. Therefore, conventionally, there is a possibility that the operation may be continued in an unstable state where the abnormality of the memory control circuit can be detected, and it is necessary to improve its reliability.

  Also, if the abnormality is transient, it is desirable to continue operation after the abnormality is detected to improve availability.

  The present invention is a memory control device that is provided between a host device and a memory device and controls access to the memory device, wherein the memory control device has the same configuration as a main memory control circuit and a sub memory control circuit In the memory control device, the main memory control circuit and the sub memory control circuit each select a signal necessary for access to the memory device and generate a timing, and monitor an output signal of the sequence circuit An output signal monitoring circuit that performs synchronization adjustment of the main memory control circuit and the sub memory control circuit when at least one of the two output signal monitoring circuits detects a signal mismatch.

  Further, the synchronization adjustment circuit of the main memory control circuit and the sub memory control circuit report completion of the synchronization adjustment to complete the synchronization of the main memory control circuit and the sub memory control circuit.

  Further, the synchronization adjustment circuit is characterized in that the sequence circuit is returned to an initial state in response to a synchronization request to the main memory control circuit and the sub memory control circuit that are output in accordance with a signal mismatch.

  The main memory control circuit and the sub memory control circuit further include an access arbitration circuit that returns the sequence circuit to an initial state in response to a synchronization request from the synchronization adjustment circuit due to a signal mismatch.

  The synchronization adjustment circuit is characterized in that the synchronization adjustment of the main memory control circuit and the sub memory control circuit is completed to prepare for the next access.

  The synchronization adjustment circuit may complete the synchronization adjustment of the main memory control circuit and the sub memory control circuit according to the synchronization completion response output from the access arbitration circuit, and prepare for the next access.

  Further, in the electronic circuit having the memory control device, the host device, and the memory device, the memory device is connected to the main memory control circuit of the memory control device. In addition, a new memory device is connected to the secondary memory control circuit of the memory control device.

  Furthermore, in an electronic circuit having a memory control device, a host device, and a memory device, a plurality of the host devices are provided.

  Furthermore, a plurality of higher-level devices are formed from processors, and mutual matching is performed on the results of control processing by each processor.

  Further, in the control method of a memory control device provided between the host device and the memory device, wherein the memory control device for controlling access to the memory device has a main memory control circuit and a sub memory control circuit having the same configuration, the memory A signal necessary for accessing the memory device in the main memory control circuit and the sub memory control circuit of the control device is monitored, and an abnormal signal is output when a signal mismatch between the main memory control circuit and the sub memory control circuit is detected. In addition, the main memory control circuit and the sub memory control circuit are returned to their initial states.

  Furthermore, in the control method of the memory control device, when a signal mismatch between the main memory control circuit and the sub memory control circuit is detected, the main memory control circuit and the sub memory control circuit are adjusted for synchronization and prepared for the next access. It is characterized by.

  The present invention provides two memory control circuits having the same structure in a memory control device, compares signals necessary for each memory access, detects and outputs an abnormality in the memory control device by a self-diagnosis function, and controls memory control. Improve equipment safety. In addition, the memory control circuit is returned to the initial state after the abnormality is detected, and the availability is improved so that the synchronization adjustment is completed and the next memory access operation is immediately continued.

1 is a circuit diagram illustrating a memory control circuit according to a first embodiment of the present invention. It is a circuit diagram which shows the memory control circuit of Example 2 of this invention. It is a circuit diagram which shows the memory control circuit of Example 3 of this invention.

  Hereinafter, modes for carrying out the present invention will be described in the following order for each embodiment. Examples described below are preferred specific examples of the present invention, and various technically preferable limitations are given. However, the scope of the present invention is not limited to these examples unless otherwise specified in the following description. For example, the numerical conditions of each parameter given in the following examples are only suitable examples, and the arrangement relationship in each figure used for the description is also schematic.

FIG. 1 shows the configuration of a memory control circuit that is Embodiment 1 of the present invention. Here, a case will be described in which two host devices as masters accessing the memory device are provided, but there is no limit to the number of host devices in actual implementation. Here, the master includes all circuits and devices that access the memory device.
[Basic configuration]
A host device 1 and a host device 2 that operate as a memory access master are provided, and these request access to the memory device 17 via the memory control device 9.

  The memory control device 9 includes a memory control circuit 3 and a memory control circuit 4. In the first embodiment, the memory control circuit 3 operates as a main memory control circuit, and the memory control circuit 4 operates as a sub memory control circuit.

  The host device 1 is connected to the memory control circuit 3 and the memory control circuit 4 by a signal 18, and the host device 2 is connected to the memory control circuit 3 and the memory control circuit 4 by a signal 19. Memory access occurs asynchronously from the host device 1 and the host device 2, and the memory access output signal 18 of the host device 1 and the memory access output signal 19 of the host device 2 are sent to the memory control circuit 3 and the memory control circuit 4. The same signal is input in parallel. The signals 18 and 19 contain all information (address, data, read / write command, etc.) necessary for accessing the memory.

  The memory control circuit 3 includes an access arbitration circuit 7, a sequencer circuit 8, an output signal monitoring circuit 10, and a synchronization adjustment circuit 11. The memory control circuit 4 includes an access arbitration circuit 12, a sequencer circuit 13, an output signal monitoring circuit 15, and a synchronization adjustment circuit 16. The memory control circuit 3 and the memory control circuit 4 form circuits with exactly the same configuration.

The memory device 17 is connected only to the main memory control circuit 3 and is not connected to the memory control circuit 4. Here, the memory control circuit 4 is used for monitoring the memory control circuit 3. The memory device 17 includes all commonly used memory elements, memory circuits, and the like.
[Memory control circuit]
The memory control circuit will be described below. Signals 18 and 19 for memory access from the host devices 1 and 2 are connected to the access arbitration circuit 7 and the access arbitration circuit 12 that arbitrate access to the memory device 17. The access arbitration circuit 7 is used when there are a plurality of host devices, arbitrates access requests from the host devices 1 and 2, and outputs a selected result to the sequencer circuit 8 using a signal 20. As the access arbitration circuit, a commonly used method such as a memory round robin control method or a fixed priority method can be used, and these do not limit the present invention. The access arbitration circuit 12 has the same configuration as the access arbitration circuit 7.
[Sequencer circuit]
Based on the access selected by the access arbitration circuit 7, the sequencer circuit 8 operates the internal sequencer to select signals necessary for access to the memory device 17 and generate timing. Based on the result, the sequencer circuit 8 is connected to the memory device 17 by a signal 30 for memory access to exchange information.

  The signal 30 of the sequencer circuit 8 is connected to the output signal monitoring circuit 10 and the output signal monitoring circuit 15 for comparison. Further, the signal 30 is connected to the host device 1 and the host device 2, and reports the information stored in the memory device 17 to the host device 1 or the host device 2 when a read request is made.

  The signal 30 necessary for accessing the memory device 17 includes all signals such as address, write data, read data, control signal, and write / read.

  The sequencer circuit 8 outputs the sequencer operation state to the access arbitration circuit 7 by the signal 24. The access arbitration circuit 7 recognizes the state of the sequencer circuit 8 based on the signal 24 and generates a timing for issuing an operation instruction to the sequencer circuit 8.

  The sequencer circuit 8 reports the completion of memory access to the higher-level devices 1 and 2 by the response signal 26 and reports the completion of memory access to the higher-level device 2 by the response signal 27. From the signals 26 and 27, the higher-level devices 1 and 2 recognize that the memory access has been completed, and can perform the next memory access. The signals 26 and 27 are connected to the output signal monitoring circuit 10 and the output signal monitoring circuit 15.

The sequencer circuit 13 is the same circuit as the sequencer circuit 8, but its signal 31 is connected only to the output signal monitoring circuit 10 and the output signal monitoring circuit 15, and is not connected to the memory device 17. Further, the signals 28 and 29 of the sequencer circuit 13 are connected to the output signal monitoring circuit 10 and the output signal monitoring circuit 15, but are not connected to the host device 1 and the host device 2.
[Output signal monitoring circuit]
The output signal monitoring circuit 10 is intended to compare and monitor all signals such as control, address, and data signals output from the sequencer circuit 8 and the sequencer circuit 13.

  The output signal monitoring circuit 10 compares the output timing of each signal and the function for checking the coincidence of all signals such as control, address, and data output from the sequencer circuit 8 and the sequencer circuit 13 to the memory device 17. And a function of comparing and determining the memory access response signals output from the sequencer circuits 8 and 13 to the host device 1 and the host device 2 to confirm the consistency. As a result, the consistency of the signals output to the memory device and the soundness of the operation of the sequencer circuit can be confirmed, and the access order to the memory device can be confirmed by comparing and judging the memory access response signal. Sex can also be confirmed.

  The output of the output signal monitoring circuit 10 is connected to the host device 1 and the host device 2, and the synchronization adjustment circuit 11 and the synchronization adjustment circuit 16 by a signal 32. When the output signal monitoring circuit 10 compares and determines the signal, and detects a mismatch, it reports a mismatch detection report to the host device 1 and host device 2, and the synchronization adjustment circuit 11 and the synchronization adjustment circuit 16.

  Here, whether to report the signal mismatch to only one of the host device 1 and the host device 2 that is the access source or both is determined according to the request of the system and does not restrict the present invention. Absent. The output signal monitoring circuit 10 and the output signal monitoring circuit 15 do not output anything when no output mismatch is detected.

Even if a mismatch is reported by either the output signal monitoring circuit 10 or the output signal monitoring circuit 15, access to the memory device 17 from the memory control circuit 3 is not stopped. However, a mismatch error is immediately reported to the host device 1 and the host device 2. Here, when a mismatch is reported in either the output signal monitoring circuit 11 or the output signal monitoring circuit 15, whether or not to stop the memory access is determined according to the request of the system, and does not limit the present invention.
[Synchronization adjustment circuit]
The synchronization adjustment circuit 11 and the synchronization adjustment circuit 16 adjust the synchronization of the memory control circuit 3 and the memory control circuit 4 when a signal mismatch is reported from the output signal monitoring circuit 10 or the output signal monitoring circuit 15. If the signals match, the memory control circuit 3 and the memory control circuit 4 are operating normally, and therefore no synchronization adjustment is performed.

  When a signal mismatch is detected in at least one of the output signal monitoring circuit 10 and the output signal monitoring circuit 15, the synchronization adjustment circuit 11 and the synchronization adjustment circuit 15 detect that the memory control circuit 3 and the memory control circuit 4 Perform synchronization adjustment.

Hereinafter, the operation of the synchronization adjustment circuit 11 will be described in detail. The synchronization adjustment circuit 11 issues a synchronization request to the access arbitration circuit 7 by a signal 34 in order to adjust the synchronization of the memory control circuit based on the signal mismatch report from the output signal monitoring circuit 10 or the output signal monitoring circuit 15.
(Return to initial state)
The access arbitration circuit 7 stops access arbitration in response to the synchronization request from the synchronization adjustment circuit 11 and returns the sequencer circuit 8 to the initial state. The method for returning the sequencer circuit to the initial state may be either waiting until the sequencer circuit returns to the initial state or forcibly returning the sequencer circuit to the initial state. To return the sequencer circuit 8 to the initial state, an instruction is given from the output signal 20 of the access arbitration circuit 7. After confirming that the sequencer circuit 8 is in the idle state from the state signal 24 of the sequencer circuit 8, the access arbitration circuit 7 reports to the synchronization adjustment circuit 11 and the synchronization adjustment circuit 16 by a signal 35 that outputs a synchronization completion response. To do.
[Synchronization completed]
The synchronization adjustment circuit 11 determines that synchronization is completed by both the response of the signal 35 that outputs the synchronization completion response from the access arbitration circuit 7 and the signal 37 that outputs the synchronization completion response from the access arbitration circuit 12, and outputs the synchronization request. Stop and complete the mutual synchronization adjustment of the memory control circuit 3 and the memory control circuit 4 so that the next memory access can be processed to prepare for the next access from the host device. The configuration and operation of the synchronization adjustment circuit 16 are the same as those of the synchronization adjustment circuit 11.

  If the host device is a single memory control circuit that does not require an access arbitration circuit, the synchronization adjustment circuit outputs a synchronization request directly to the sequencer circuit to return to the initial state, and receives the result to determine the completion of synchronization.

  FIG. 2 shows the configuration of a memory control circuit that is Embodiment 2 of the present invention. In addition, description of the same part as Example 1 is abbreviate | omitted, and only description of the part used as the characteristic is given.

  FIG. 2 shows the operation of the memory control method according to the present invention, in which the processors 40 and 41 are connected in place of the host devices 1 and 2 of the first embodiment, and both the processors 40 and 41 are individually controlled. The memory control system by the multiprocessor to compare is shown. By performing mutual matching on the results of the control processing by each processor, it is possible to check the circuit operation more accurately and improve reliability. The configuration and operation of the memory control device 9 at this time are the same as in the embodiment.

  FIG. 3 shows the configuration of a memory control circuit that is Embodiment 3 of the present invention. In addition, description of the same part as Example 1 is abbreviate | omitted, and only description of the part used as the characteristic is given.

  FIG. 3 shows a memory control system in which two memory devices are connected and their operations are compared while performing control processing on each memory device individually. FIG. 3 is configured by adding a memory device 50 in addition to the host device 1, host device 2, memory control device 9, and memory device 17 of the first embodiment.

  In the first embodiment, the memory control circuit 4 is not connected to an actual memory device as a slave memory control circuit. On the other hand, in the third embodiment, the memory control circuit 4 is connected to the memory device 50 by a signal 31 necessary for memory access. Thereby, the data of both memory devices can be compared and checked, and the reliability of the entire memory control device can be further improved.

  The access requested by the host device 1 and the host device 2 is stored in the memory device 17 and the memory device 50 after the signals are compared in the memory control circuit 3 and the memory control circuit 4.

  The sequencer circuit 13 reports the completion of memory access to the higher order device 1 and the higher order device 2 by the response signals 28 and 29 in the same manner as the sequencer circuit 8. Whether the sequencer circuit 8 or the sequencer circuit 13 reports the completion of memory access to the host device 1 and the host device 2 does not limit the present invention depending on the operation of the system.

  When reporting information stored in the memory device in response to a request from the host device 1 and the host device 2, whether to report information stored in the memory device 17 or the memory device 50 depends on the operation of the system. It depends.

1, 2: Host device 9: Memory control device 3, 4: Memory control circuit 7, 12: Access arbitration circuit 8, 13: Sequencer circuit 10, 15: Output signal monitoring circuit 11, 16: Synchronization adjustment circuit 17, 50: Memory devices 40 and 41: processor

Claims (12)

A memory control device that is provided between a host device and a memory device and controls access to the memory device, and has a main memory control circuit and a sub memory control circuit having the same configuration.
The main memory control circuit and the sub memory control circuit respectively select a signal necessary for access to the memory device and generate a timing ; output signals of the sequence circuit of the main memory control circuit; An output signal monitoring circuit for comparing output signals of the sequence circuit of the memory control circuit, and an access from the memory control device to the memory device when the output signal monitoring circuit detects a mismatch of the output signals of the sequence circuit The sequence circuit is initialized based on the synchronization request from the output signal monitoring circuit that detects the signal mismatch while continuing the process, and the memory access is enabled by returning the main memory control circuit and the sub memory control circuit to the initial state. A memory control device comprising a synchronization adjustment circuit. 2. The memory control device according to claim 1, wherein the synchronization adjustment circuit of the main memory control circuit and the slave memory control circuit returns to the initial state and reports the completion of synchronization adjustment to enable memory access. A memory control device characterized by completing synchronization of a memory control circuit and a sub memory control circuit.   2. The memory control device according to claim 1, wherein the synchronization adjustment circuit returns the sequence circuit to an initial state in response to a synchronization request to the main memory control circuit and the sub memory control circuit that are output in accordance with a signal mismatch. Memory control device.   2. The memory control device according to claim 1, wherein the main memory control circuit and the sub memory control circuit further include an access arbitration circuit that returns the sequence circuit to an initial state in response to a synchronization request of the synchronization adjustment circuit due to a signal mismatch. A memory control device. 4. The memory control device according to claim 3, wherein the synchronization adjustment circuit prepares for the next access after completing the synchronization adjustment in which the main memory control circuit and the sub memory control circuit return to an initial state and memory access becomes possible. Memory control device. 5. The memory control device according to claim 4, wherein the synchronization adjustment circuit is configured so that the main memory control circuit and the sub memory control circuit can return to the initial state and access the memory in accordance with a synchronization completion response output from the access arbitration circuit. And a memory control device for preparing for the next access.   7. An electronic circuit having a memory control device according to claim 1, a host device, and a memory device, wherein the memory device is connected to a main memory control circuit of the memory control device. .   8. The electronic circuit according to claim 7, wherein a new memory device is connected to the slave memory control circuit of the memory control device.   7. An electronic circuit comprising: the memory control device according to claim 1; a host device; and an electronic circuit including the memory device, wherein a plurality of the host devices are provided.   The electronic circuit according to claim 9, wherein the plurality of higher-level devices are formed from processors, and the mutual matching is performed on the result of the control processing by each processor. A memory control device that is provided between the host device and the memory device and controls access to the memory device has the same configuration of the main memory control circuit, the sub memory control circuit , the main memory control circuit, and the sub memory control circuit. In a control method of a memory control device, comprising: a sequence circuit that is provided and selects a signal necessary for accessing the memory device and generates timing ;
The main memory control circuit compares an output signal including data and an address to be output to the memory device of the sequence circuit of the main memory control circuit with an output signal of the sequence circuit of the sub memory control circuit, and the sequence circuit When the output signal mismatch is detected, an abnormal signal is output, and the sequence circuit is initialized while continuing to access the memory device from the memory control circuit, so that the main memory control circuit and the sub memory control control method for a memory controller, characterized in that to enable memory accesses to return the circuit to the initial state to the main memory control circuit said slave memory control circuit. 12. The control method of a memory control device according to claim 11 , wherein the main memory control circuit compares an output signal of the sequence circuit of the main memory control circuit with an output signal of the sequence circuit of the sub memory control circuit, A control method for a memory control device , comprising: when a mismatch between the output signals of the sequence circuit is detected , returning the main memory control circuit and the sub memory control circuit to an initial state to prepare for the next access.

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