JP5326607B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of desired phase delay without requiring much time even if the frequency of a clock is low. <P>SOLUTION: The semiconductor device controls a delay amount in a first delay line in accordance with a result of phase comparison between a reference clock and a reference clock delayed in the first delay line, and causes a second delay line to delay a first clock based on a result of control to generate a control clock having a predetermined phase difference. In this semiconductor device, if the delay amount of the first delay line exceeds a predetermined threshold value delay amount not less than a delay amount corresponding to the settable maximum delay amount and less than the maximum delay amount, a clock outputted as the reference clock from a selector is switched from the first clock to the second clock having a constant multiple of frequency so that the control clock having a predetermined phase difference can be generated without requiring much time even if the frequency of the first clock is low. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, and is particularly suitable for use in a delay locked loop (DLL) circuit.

  A digital DLL (D-DLL) circuit is used, for example, as an interface (hereinafter also referred to as DDR-IF) of a DDR (Double Data Rate) memory. In the DDR-IF, when the period of the data strobe signal (clock) is T, it is necessary to give a delay of (T / 4) to the data strobe signal in order to accurately obtain data by the data signal. In order to obtain such a delay, a D-DLL circuit is used.

  For example, a D-DLL circuit for delaying the data strobe signal by (T / 4) includes a delay control unit (for example, Delay Line Control macro) and a delay unit (for example, Delay Line macro). The delay control unit compares the phase of the reference clock (data strobe signal, reference clock) with a period T and the delayed reference clock, and performs control so that the delay amount is a phase delay of 360 °. Further, the delay unit delays the data strobe signal by a phase corresponding to 90 ° (that is, a period of T / 4) based on the control result of the delay control unit.

  However, when the frequency of the reference clock is lowered, the delay time corresponding to a phase delay of 360 ° is increased, and it is impossible to delay the reference clock by 360 ° due to a shortage of delay elements in the delay control unit. It may be possible. In such a case, the inconvenience described above can be avoided by increasing the number of delay elements included in the D-DLL circuit or increasing the delay amount per delay element.

  In addition, when a clock supplied as a reference clock has a low frequency, a multiplied clock having a frequency that is a constant multiple of that clock is generated, and the generated multiplied clock is used as a reference clock so that normal operation can be performed. A DLL circuit has been proposed (see, for example, Patent Document 1).

JP 2000-49595 A

  However, as described above, there is a problem that increasing the number of delay elements included in the D-DLL circuit increases the circuit area, and increasing the delay amount per delay element increases the jitter. Further, since the DLL circuit described in Patent Document 1 performs switching so that the multiplied clock is used as the reference clock when the clock delay amount exceeds the maximum delay amount in the DLL circuit, it takes a long time for processing. Is required.

  An object of the present invention is to provide a semiconductor device that enables a desired phase delay without requiring much time even when the clock frequency is low.

According to one aspect of the present invention, a selection unit that outputs one of a first clock and a second clock (having a frequency that is a constant multiple of the first clock) as a reference clock, and a reference that is output from the selection unit a phase comparator for comparing the clock phase of the reference clock delayed by the first delay unit, according to the comparison result of the phase comparator, Gyosu control the delay amount of the reference clock in the first delay unit And a second delay unit that generates a control clock having a predetermined phase difference from the first clock based on a control result of the control unit. The control unit determines whether or not the delay amount of the reference clock in the first delay unit exceeds a threshold delay amount that is equal to or greater than (1/2) of the maximum delay amount that can be set in the first delay unit and less than the maximum delay amount. Determine whether. The selection unit outputs one of the first clock and the second clock according to the determination result of the control unit.

Processing can be performed by switching the clock before the amount of delay in the first delay unit reaches an overflow state, and even if the frequency of the first clock is low, the first clock is not required much time. A control clock having a predetermined phase difference can be generated based on the above.

It is a figure which shows the structural example of the DLL (delay locked loop) circuit in embodiment of this invention. It is a figure which shows the structural example of the delay information comparison circuit in this embodiment. It is a figure which shows the flow of a process in the DLL circuit in this embodiment. It is a figure which shows the operation example of the DLL circuit in this embodiment. It is a figure which shows the operation example of the DLL circuit in this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of a DLL (Delay Locked Loop) circuit to which a semiconductor device according to an embodiment of the present invention is applied. The DLL circuit in the present embodiment includes a plurality of delay circuits connected in series and delayed for unit time, and a digital DLL (D−) whose delay amount is controlled by a digital amount by adjusting the number of stages of delay circuits to be connected. DLL) circuit.

  In FIG. 1, 11 is a selector for clock switching, 12 is a first delay line, 13 is a phase comparison circuit, 14 is a first control circuit, 15 is a delay information comparison circuit, 16 is a second control circuit, 17 Is a second delay line, and 18 is an OR (logical sum operation) circuit. In the present embodiment, a DLL circuit applied to DDR-IF is shown as an example, and the data strobe signal DQS is delayed by 90 ° (delayed by T / 4 (quarter cycle)) and controlled. It shall be output as a clock.

The selector 11 receives the first clock RCK1 and the second clock RCK2, and selects either the first clock RCK1 or the second clock RCK2 according to the output of the OR circuit 18 to select the reference clock (reference clock). ). The first clock RCK1 is DDR-IF × 1CLK. The second clock RCK2 is a clock having a frequency that is a constant multiple of that of the first clock RCK1, and is set to x2CLK of DDR-IF here.
The present embodiment is not limited to DDR-IF × 2CLK, but may be DDR-IF × 4CLK, or DDR-IF × (N × CLK) (N is an integer of 1 or more).

  The OR circuit 18 receives the first clock switching signal CKC1 output from the delay information comparison circuit 15 and the second clock switching signal CKC2 output from the first control circuit 14, and outputs the calculation result. Output.

  The first delay line 12 has a plurality of delay circuits connected in series. Each of the delay circuits delays the input for a unit time and outputs it. The delay amount of the first delay line 12 is controlled by adjusting the number of delay circuits to be connected in accordance with the delay information (delay code) DLIA output from the first control circuit 14, and is output from the selector 11. The reference clock to be output is delayed by a desired delay amount and output. The delay information (delay code) DLIA corresponds to the number of delay circuits connected in series, for example.

  The phase comparison circuit 13 compares the phases of the reference clock output from the selector 11 and the reference clock delayed by the first delay line 12 and outputs the comparison result to the first control circuit 14. For example, the phase comparison circuit 13 compares whether the delay amount in the first delay line 12 is insufficient or excessive. Further, for example, a comparison is made as to whether or not the phase delay of the reference clock delayed by the first delay line 12 with respect to the reference clock output from the selector 11 exceeds 180 °.

  The first control circuit 14 receives the comparison result output from the phase comparison circuit 13 and the updated delay information (delay code) DLIN output from the delay information comparison circuit 15, and the delay information DLIA, The signal OVS and the second clock switching signal CKC2 are output. Here, the signal OVS is a signal indicating that the phase delay of the reference clock delayed by the first delay line 12 with respect to the reference clock output from the selector 11 exceeds 180 °. The second clock switching signal CKC2 is a signal that instructs the selector 11 to switch the clock output as the reference clock.

  For example, when receiving the updated delay information DLIN from the delay information comparison circuit 15, the first control circuit 14 outputs it to the first delay line 12 as delay information DLIA. Further, for example, when it is determined from the comparison result from the phase comparison circuit 13 that the reference clock has become a low frequency after locking, the second clock switching signal CKC2 is output. When the phase delay of the delayed reference clock exceeds 180 °, the signal OVS is output.

  The delay information comparison circuit 15 receives the delay information DLIA and the signal OVS output from the first control circuit 14, and outputs the delay information DLIN and DLIB and the first clock switching signal CKC1 according to them. Here, like the second clock switching signal CKC2, the first clock switching signal CKC1 is a signal that instructs the selector 11 to switch the clock output as the reference clock.

  The first control circuit 14 and the delay information comparison circuit 15 control the delay amount in the first delay line 12 according to the comparison result of the phase comparison circuit 13, and the delay amount (DLIA) is a predetermined threshold value. A control unit that determines whether or not the delay amount (hDLI) is exceeded is realized. For example, the delay in the first delay line 12 so that the phase delay of the delayed reference clock with respect to the undelayed reference clock finally becomes 360 ° by the first control circuit 14 and the delay information comparison circuit 15. The amount is controlled.

The delay information comparison circuit 15 is configured, for example, as shown in FIG. FIG. 2 is a block diagram illustrating a configuration example of the delay information comparison circuit 15.
The delay information comparison circuit 15 includes a comparison unit 21, a delay information update unit 22, and a delay information output unit 23.

  The comparison unit 21 receives the delay information DLIA output from the first control circuit 14 and the threshold value hDLI output from a setting unit (not shown) such as a register. As is clear from the above description, the delay information DLIA indicates the delay amount in the first delay line 12, and the threshold value hDLI indicates a predetermined threshold delay amount. For example, the delay information DLIA and the threshold value hDLI are 8-bit binary values (binary codes).

  The comparison unit 21 compares the delay information DLIA and the threshold value hDLI, and outputs the first clock switching signal CKC1 when the delay information DLIA exceeds the threshold value hDLI. That is, the comparison unit 21 instructs the selector 11 to switch the clock to be output as the reference clock when the delay amount in the first delay line 12 exceeds a predetermined threshold delay amount. Note that the comparison between the delay information DLIA and the threshold value hDLI indicates that at least the signal OVS is not output (not activated), that is, the phase delay of the reference clock delayed by the first delay line 12 is 180 °. It can be done when it does not exceed.

  Here, the predetermined threshold delay amount indicated by the threshold value hDLI is a delay amount that is equal to or greater than (1/2) of the maximum delay amount that can be set in the first delay line 12 and less than the maximum delay amount. For example, when the delay information DLIA and the threshold value hDLI are expressed by 8-bit binary values (“00000000” to “11111111”), and the delay amount is larger as the delay information DLIA value is larger, the threshold value hDLI is “10000000” to “ 11111110 ”. By doing so, it is possible to instruct switching of the clock output as the reference clock before the delay amount in the first delay line 12 reaches the overflow state. Further, the predetermined threshold delay amount indicated by the threshold value hDLI is desirably (1/2) of the maximum delay amount that can be set in the first delay line 12, and can be quickly transmitted without performing unnecessary processing. Can be instructed to switch the output clock.

  The delay information update unit 22 receives the delay information DLIA via the comparison unit 21. The delay information update unit 22 receives the signal OVS output from the first control circuit 14 and the first clock switching signal CKC1 output from the comparison unit 21.

  When the signal OVS and the first clock switching signal CKC1 are not output (not activated), the delay information update unit 22 increases the delay information DLIA by 1 and outputs the updated delay information DLIN. . In addition, when the signal OVS is output (activated), the delay information updating unit 22 sets the delay information DLIA to a double value and outputs the updated delay information DLIN. Further, when the first clock switching signal CKC1 is output (activated), the delay information update unit 22 sets the delay information DLIA to ½ and outputs it as updated delay information DLIN.

  The delay information output unit 23 receives the delay information DLIN output from the delay information update unit 22 and the first clock switching signal CKC1 output from the comparison unit 21. The delay information output unit 23 outputs the delay information DLIN as the delay information DLIB when the first clock switching signal CKC1 is not output (not activated). In addition, when the first clock switching signal CKC1 is output (activated), the delay information output unit 23 doubles the delay information DLIN and outputs it as the delay information DLIB.

  The second control circuit 16 receives the delay information DLIB output from the delay information comparison circuit 15 and controls the delay amount in the second delay line 17 accordingly.

  The second delay line 17 has a plurality of delay circuits connected in series. Each of the delay circuits delays the input for a unit time and outputs it. The delay amount of the second delay line 17 is controlled by adjusting the number of delay circuits to be connected in accordance with the delay information (delay code) output from the second control circuit 16. The second delay line 17 delays the data strobe signal DQS by a desired delay amount and outputs it as a control clock DLLO having a predetermined phase difference.

  For example, if the unit delay times of the delay circuits included in the delay lines 12 and 17 are the same, the second control circuit 16 causes the second delay line 17 to delay the data strobe signal DQS by 90 °. In addition, the delay information DLIB is set to (1/4) and output to the second delay line 17.

Next, the operation of the DLL circuit in this embodiment will be described.
FIG. 3 is a diagram showing an outline of the flow of processing in the DLL circuit in this embodiment.

  First, when the operation starts, the selector 11 outputs the first clock RCK1 (× 1CLK) as a reference clock, and the delay information DLI (DLIA) is initialized. In the following description, the delay information is an 8-bit binary value, and the initial value of the delay information DLI (DLIA) is “00000001”.

  The reference clock output from the selector 11 is output after being delayed by the delay amount corresponding to the delay information DLIA by the first delay line 12. The phase comparison circuit 13 compares the phases of the reference clock output from the selector 11 and the reference clock delayed by the first delay line 12 and outputs a comparison result. In accordance with the comparison result output from the phase comparison circuit 13, the delay information comparison circuit 15 performs the following processing relating to delay information (delay amount).

  First, the delay information comparison circuit 15 determines whether or not the phase delay of the reference clock delayed by the first delay line 12 with respect to the reference clock output from the selector 11 exceeds 180 ° (S1). This determination is made based on the signal OVS, for example.

  As a result of the determination in step S1, if the phase delay of the reference clock delayed by the first delay line 12 does not exceed 180 ° (NO in step S1), the process proceeds to step S2. In step S2, the delay information comparison circuit 15 compares the delay information DLIA with the threshold value hDLI, and determines whether or not the delay amount in the first delay line 12 exceeds a predetermined threshold delay amount.

  As a result of the determination in step S2, if the delay amount in the first delay line 12 does not exceed the predetermined threshold delay amount (NO in step S2), the delay information comparison circuit 15 uses the delay information DLI (DLIA). ) Is increased by 1 (S3), and the process returns to step S1. Until the phase delay of the reference clock delayed by the first delay line 12 exceeds 180 °, or the delay amount in the first delay line 12 exceeds a predetermined threshold delay amount, the above-described steps S1 to S1 are performed. The process of S3 is repeated.

  Here, as a result of the determination in step S1, if the phase delay of the reference clock delayed by the first delay line 12 exceeds 180 ° (YES in step S1), the process proceeds to step S4. In this case, the phase delay of the reference clock delayed by the first delay line 12 exceeds 180 ° before the delay amount in the first delay line 12 exceeds the predetermined threshold delay amount. Even when the phase delay reaches 360 °, the maximum delay amount that can be set in the first delay line 12 is not exceeded. Therefore, the delay information comparison circuit 15 shifts the delay information DLI to a double value (S4), and proceeds to a lock detection process (S6) in which the reference clock is delayed by 360 ° by the first delay line 12.

  If the result of determination in step S2 is that the delay amount in the first delay line 12 exceeds a predetermined threshold delay amount (YES in step S2), the process proceeds to step S5. In this case, the delay amount in the first delay line 12 exceeds the predetermined threshold delay amount before the phase delay of the reference clock delayed by the first delay line 12 exceeds 180 °. Become. Here, the predetermined threshold delay amount is a delay amount that is not less than (½) of the maximum delay amount that can be set in the first delay line 12 and less than the maximum delay amount.

  In other words, since the reference clock phase delay delayed by the first delay line 12 exceeds (1/2) of the maximum delay amount that can be set before it exceeds 180 °, the reference clock phase delay is reduced to 360. It is impossible to make it °. Therefore, the delay information comparison circuit 15 outputs the first clock switching signal CKC1, and instructs switching so that the second clock RCK2 is output as the reference clock (S5). Then, using the second clock RCK2 output as the reference clock, the process proceeds to a lock detection process (S6) in which the reference clock is phase-delayed by 360 ° by the first delay line 12.

  As described above, the phase delay of the first clock RCK1 delayed by the first delay line 12 exceeds 180 ° before the delay amount in the first delay line 12 exceeds the predetermined threshold delay amount. In this case, the first clock RCK1 is used as a reference clock. For example, as shown in FIG. 4, when the first delay line 12 delays the first clock RCK1 by a time corresponding to the times T11 to T13, a phase delay of 360 ° is obtained. The data strobe signal DQS can be delayed in phase by 90 ° by being delayed by the second delay line 17 by a time corresponding to 4 times T11 to T12. In FIG. 4, DLC and DL schematically show the delay circuits included in the first delay line 12 and the second delay line 17, and the hatched portions are used (connected). (The same applies to FIG. 5).

  Further, when the delay amount in the first delay line 12 exceeds a predetermined threshold delay amount before the phase delay of the first clock RCK1 delayed by the first delay line 12 exceeds 180 °, Clock switching is performed. For example, as shown in FIG. 5, even if the delay is performed by a predetermined threshold delay amount (here, (1/2) of the maximum delay amount that can be set indicated by HD), the phase of the first clock RCK1 If the delay does not reach 180 °, the second clock RCK2 is used as a reference clock. Then, when the second clock RCK2 is delayed by the time corresponding to the times T21 to T23 by the first delay line 12, if a phase delay of 360 ° is reached, 1/2 of that (with the second clock RCK2) The data strobe signal DQS can be phase-delayed by 90 ° by being delayed by the second delay line 17 by the time corresponding to the times T21 to T22 (180 ° phase delay).

  As described above, when the frequency of the first clock RCK1 (× 1CLK) is low, the second clock RCK2 that is the multiplied clock is used as the reference clock before the delay amount in the first delay line 12 reaches the overflow state. Switch to use. As a result, the lower limit frequency at which the DLL circuit can operate normally can be lowered, and even if the frequency of the first clock RCK1 (× 1CLK) is low, it does not take much time, and it is determined based on the data strobe signal DQS. A control clock having a phase difference of can be output. For example, the first clock RCK1 is normally used as the reference clock, and when the frequency of the first clock RCK1 is low, the second clock RCK2 having a double frequency is used, so that only the first clock RCK1 is used. It is possible to cope with up to ½ frequency as compared with the case of using.

  In addition, it is possible to cope with a low frequency without increasing the number of delay circuits included in the delay lines 12 and 17 or increasing the delay amount per delay circuit, increasing the circuit area, jitter. Inconveniences such as an increase in the number of occurrences do not occur.

  In the above-described embodiment, the case where the first clock RCK1 and the second clock RCK2 having twice the frequency of the first clock RCK1 are used as the reference clock has been described as an example. However, the present invention is not limited thereto. is not. For example, in addition to the first clock RCK1 and the second clock RCK2 having a frequency twice that of the first clock RCK1, a clock having a frequency four times that of the first clock RCK1 may be used. In this case, it is possible to cope with even lower frequencies (1/4 frequency).

In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Supplementary Note 1) A selection unit that receives a first clock and a second clock having a frequency that is a constant multiple of the first clock, and outputs either the first clock or the second clock as a reference clock. When,
A first delay unit that delays the reference clock output from the selection unit;
A phase comparison unit that compares the phase of the reference clock output from the selection unit and the reference clock delayed by the first delay unit;
According to the comparison result of the phase comparison unit, the delay amount of the reference clock in the first delay unit is controlled, and the delay amount corresponds to the maximum delay amount that can be set in the first delay unit. A controller that determines whether or not a predetermined threshold delay amount that is greater than or equal to an amount and less than the maximum delay amount;
A second delay unit that delays the first clock based on a control result of the control unit and generates a control clock having a predetermined phase difference from the first clock;
The semiconductor device according to claim 1, wherein the selection unit switches a clock output as a reference clock according to a determination result of the control unit.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the second clock is a clock having a frequency 2N (N is an integer equal to or greater than 1) times the first clock.
(Supplementary note 3) The semiconductor device according to Supplementary note 1 or 2, wherein the predetermined threshold delay amount is (1/2) of a maximum delay amount that can be set in the first delay unit.
(Supplementary Note 4) The selection unit outputs the first clock as a reference clock, and the determination result of the control unit indicates that the delay amount of the reference clock in the first delay unit exceeds the predetermined threshold delay amount. 4. The semiconductor device according to any one of appendices 1 to 3, wherein the selection unit switches to output the second clock as a reference clock.
(Additional remark 5) The said control part compares the delay amount of the said reference clock in the said 1st delay part, and the said predetermined | prescribed threshold delay amount, The signal which instruct | indicates clock switching to the said selection part according to a comparison result 5. The semiconductor device according to any one of appendices 1 to 4, further comprising a comparison unit that outputs a signal.
(Additional remark 6) The said 2nd delay part produces | generates the control clock which delayed the phase of the said 1st clock by 90 degrees based on the control result of the said control part. The semiconductor device according to any one of the above.
(Supplementary note 7) Each of the first delay unit and the second delay unit includes a plurality of delay circuits for delaying by unit time, and the plurality of delay circuits are connected in series. The semiconductor device according to any one of 1 to 6.

DESCRIPTION OF SYMBOLS 11 Selector 12 Delay line 13 Phase comparison circuit 14 1st control circuit 15 Delay information comparison circuit 16 2nd control circuit 17 Delay line 21 Comparison part 22 Delay information update part 23 Delay information output part RCK1, RCK2 Clock DLIA, DLIB, DLIN delay information CKC1, CKC2 Clock switching signal DQS Data strobe signal

Claims (4)

A selection unit that receives a first clock and a second clock having a frequency that is a constant multiple of the first clock, and outputs one of the first clock and the second clock as a reference clock;
A first delay unit that delays the reference clock output from the selection unit;
A phase comparison unit that compares the phase of the reference clock output from the selection unit and the reference clock delayed by the first delay unit;
And in response to said comparison result of the phase comparison unit, the first of said reference clock delay braking Gyosu that control unit in the delay unit,
A second delay unit that delays the first clock based on a control result of the control unit and generates a control clock having a predetermined phase difference from the first clock;
The control unit includes a threshold delay in which a delay amount of the reference clock in the first delay unit is equal to or greater than (1/2) of a maximum delay amount that can be set in the first delay unit and less than the maximum delay amount. Determine whether the amount exceeds,
The selection unit outputs one of the first clock and the second clock according to a determination result of the control unit.   2. The semiconductor device according to claim 1, wherein the second clock is a clock having a frequency 2N (N is an integer equal to or greater than 1) times the first clock. Comparing the control unit, which compares the delay amount and the previous Ki閾 value delay amount of the reference clock in the first delay section, it outputs a signal for instructing the clock switching the selector according to the comparison result the semiconductor device according to claim 1, wherein it has a part. The said 2nd delay part produces | generates the control clock which delayed the phase of said 1st clock by 90 degrees based on the control result of the said control part, The any one of Claims 1-3 characterized by the above-mentioned. The semiconductor device according to item.

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