JP5326406B2 - Transmitter - Google Patents

Description

The present invention relates to a transmitter including a latch circuit that latches differential data with a clock.

  In the high-speed optical transmission technology, a plurality of pairs of parallel differential signals are converted into a pair of high-speed serial differential signals and then converted into optical signals. Conversion to a pair of high-speed serial differential signals is performed by a semiconductor device called a serializer. In order to convert a parallel differential signal into a serial differential signal, the serializer receives parallel differential signals by a plurality of current mode logics (CML), adjusts the phase between the signals, and bundles the signals. Serialized. Therefore, since CML requires high-speed operation, it has a circuit configuration that switches current without using a transistor saturation region.

  In order to supply a high frequency clock to the CML latch circuit, the clock buffer is composed of a narrow band buffer. The narrow band buffer is a buffer that can obtain a high driving capability in a specific narrow band by utilizing circuit resonance. Circuit resonance occurs between a load capacitance such as a wiring capacitance seen from the buffer output and a parasitic capacitance of the MOS transistor and an inductance component inserted in the differential pair of the buffer output.

  On the other hand, the serializer is tested for operation before shipping. It is difficult to test the operation of a serializer operating at high speed at several tens of GHz at the wafer level. Therefore, it is necessary to perform an operation test after packaging the serializer to be tested. Since it cannot be determined whether it is a non-defective product until packaging, defective products are also packaged, which increases the test cost. In order to prevent such an increase in cost, it is necessary to perform an operation test at the wafer level at a low frequency of several tens of MHz.

In order to realize an operation test at a low frequency, a low-frequency clock buffer connected in parallel with a narrow-band buffer used for high-speed operation is required. To ensure sufficient driving capability for low frequency operation tests, the size of the low frequency clock buffer should be equal to or greater than that of the narrow band buffer. As the size of the low-frequency clock buffer increases, the load capacity to be driven increases during narrow-band buffer operation. An increase in load capacity adversely affects high-speed operation by the narrow band buffer. Therefore, if the driving capability of the low-frequency clock buffer is reduced in order to reduce the influence on the high-speed operation, the rise / fall time of the clock during the low-frequency operation test becomes longer. In the serializer, when the rising / falling time of the clock becomes long, a period in which both the clock and the inverted clock become the logical value 1 occurs. When both the clock and the inverted clock have a logic value 1, data cannot be latched by the differential clock, and an accurate low-frequency operation test cannot be performed. The following patent documents disclose a latch circuit in which an inverter is provided at the input stage of a clock signal having a relatively long rise and fall time, and the operation timing is controlled by the magnitude relationship between the potential of the clock signal and the threshold value of the inverter. .
Japanese Patent Laid-Open No. 04-352513

  It is an object of the present invention to provide a latch circuit that suppresses the influence on the characteristics of a narrow-band buffer and a test circuit that uses the latch circuit.

To solve the above problems, the transmitter, and the non-inverted clock having a first logic value and a second logic value, less than said first period within the first period non inverted clock is said first logic value A clock generation circuit that outputs an inverted clock that is the second logical value in a second period, sampling that inputs first differential data and the non-inverted clock, and samples the first differential data with the non-inverted clock A circuit, a first holding circuit that receives the second differential data output from the sampling circuit and the inverted clock, holds the second differential data according to the inverted clock, the non-inverted clock, and the Each of the inverted clocks has an enable signal generation unit that outputs an enable signal during the period of the first logical value, and a second holding circuit that holds the second differential data in accordance with the enable signal.

  According to the present invention, data omission can be prevented by shifting the phases of the non-inverted clock and the inverted clock by the clock transition time or more. In addition, it is possible to prevent the operation of the latch circuit from becoming unstable by holding the output of the sampling circuit while the non-inverted clock and the inverted clock are at the first logic value. As a result, an on-chip latch circuit low-speed test can be performed using a clock buffer with low driving capability.

Hereinafter, an embodiment of the present invention will be described in detail.
[Transmitter]
FIG. 1 is a block diagram of a transmitter 100 in the present embodiment. The transmitter 100 is a semiconductor device having a function of converting a plurality of differential signals into one differential signal. The transmitter 100 includes a serializer 102, a phase locked loop (Phase
Locked Loop (PLL) 104, switch 105, frequency divider 106, clock generation circuit 400, narrowband buffer 108, enable signal generation unit 500, and switches 110 and 112.

  The clock 116 is input to the PLL 104 and converted into a high-frequency differential clock. The narrow band buffer 108 is a buffer with high drive capability that outputs a differential clock having the same frequency as the differential clock input from the PLL 104. The frequency divider 106 divides the differential clock input from the PLL into a low frequency clock and outputs it. The clock generation circuit 400 receives the low frequency clock output from the frequency divider 106 as an input, and the clock 20 and an inverted clock having a period in which the clock 20 is at a logical value of 1 and shorter than this period. 21 is output. The enable signal generation unit 500 outputs an enable signal 348 that becomes a logical value 1 when both the clock 20 and the inverted clock 21 of the low-frequency differential clock output from the clock generation circuit 400 have a logical value 0. In this embodiment, a circuit capable of performing a low frequency test is referred to as a test circuit.

  The switching signal 118 turns on one of the switches 110 and 112. When the switch 110 is on, the clock 20 and the inverted clock 21 output from the clock generation circuit 400 are valid. In this case, the clock 20 and the inverted clock 21 are supplied to the serializer 102 as a non-inverted clock 334 and an inverted clock 346, respectively. When the switch 112 is on, the clock 22 and the inverted clock 23 output from the narrowband buffer 108 are valid. In this case, the clock 22 and the inverted clock 23 are supplied to the serializer 102 as a non-inverted clock 334 and an inverted clock 346, respectively.

The switching signal 118 outputs a signal for turning off the switch 105 when a signal for turning on the switch 112 is outputted. During the low frequency operation, the switch 105 is turned on in response to the switching signal 118 and outputs the clock input from the PLL 104. During high-frequency operation, the switch 105 is turned off in response to the switching signal 118, shuts off the output of the clock input from the PLL 104, and continues to output a signal having a logical value of 0. With such a configuration, the influence of the parasitic capacitance of the frequency divider 106, the clock generation circuit 400, and the enable signal generation unit 500 on the narrow band buffer 108 can be reduced during high frequency operation.

As will be described later, the enable signal 348 is used to stabilize the low-frequency operation of the serializer 102. With the above configuration, the logical value of the enable signal 348 during high-frequency operation is fixed. Thereby, the high frequency operation of the serializer 102 can be stabilized.
[Serializer]
The serializer 102 converts a plurality of pairs of parallel differential signals composed of input signals 1, 2, 3, 4, 5, 6, 7, and 8 into a pair of serial differential signals composed of signals 120 and 121. In this embodiment, the serializer 102 converts four pairs of parallel differential signals into a pair of serial differential signals. The serializer 102 includes multiplexers 10, 12, and 14. The multiplexer 10 receives a differential signal composed of signals 1 and 2 and a differential signal composed of signals 3 and 4 and outputs a differential signal composed of signals 330 and 332. The multiplexer 12 receives a differential signal composed of signals 5 and 6 and a differential signal composed of signals 7 and 8 and outputs a differential signal composed of signals 122 and 123. The multiplexer 14 receives a differential signal composed of signals 330 and 332 and a differential signal composed of signals 122 and 123 and outputs a differential signal composed of signals 120 and 121.

  Signals 1 to 8 are all input at the same frequency. Signals 330 and 332 are output from multiplexer 10 at twice the frequency of signals 1, 2, 3 and 4. The signals 122 and 123 are output from the multiplexer 12 at twice the frequency of the signals 5, 6, 7 and 8. Signals 120 and 121 are output from multiplexer 14 at a frequency twice that of signals 330, 332, 122, and 123. Therefore, the serial differential signal composed of the signals 120 and 121 is output at a frequency four times that of the parallel differential signals 1 to 8. The signals 120 and 121 are converted from an electric signal to an optical signal, and are transmitted at high speed to a receiving apparatus. Details regarding the operation of the multiplexer will be described later.

The enable signal 348, the non-inverted clock 334, and the inverted clock 346 are input to the respective multiplexers 10, 12, and 14. Details of the enable signal 348, the non-inverted clock 334, and the inverted clock 346 will be described later.
[Multiplexer]
FIG. 2 is a detailed block diagram of the multiplexer 14. The other multiplexers 10 and 12 have the same configuration. The multiplexer 14 converts the parallel differential signal composed of the signals 330, 332, 122, 123 into a serial differential signal composed of the signals 120, 121. The multiplexer 14 includes flip-flops 32 and 34, a test target circuit 300-3, a frequency divider 360, and a selector 30. The flip-flop 32 includes test target circuits 300-1 and 300-2. The flip-flop 34 includes test target circuits 300-4 and 300-5. The operation of each of the test target circuits 300-1 to 300-m during high-speed operation is the same as that of a normal latch circuit. Here, m is the total number of all test target circuits constituting the serializer 102. The enable signal 348 is input to each of the test target circuits 300-1 to 300-m. The enable signal 348 stably operates the test target circuits 300-1 to 300-m during the low speed operation. A detailed description of the test target circuit 300-m will be described later.

The frequency divider 360 divides the frequency of the input non-inverted clock 334 and inverted clock 346 so as to match the signals 330, 332, 122, and 123. For example, it is assumed that the signal 330 is 2 Gbps (bit per second). A 2 Gbps signal is 1 GHz in terms of frequency. In this case, the frequency divider 360 divides the frequencies of the non-inverted clock 334 and the inverted clock 346 to 2 GHz, which is twice the frequency of the signal 330. The clock frequency output from the frequency divider 360 is different for each multiplexer. Since the 1 GHz signals 330, 332, 122, and 123 are output from the multiplexers 10 and 12 in FIG. 1, the frequency dividers 360 mounted on the respective multiplexers are used to input the non-inverted clock 334 and the inverted clock 346. Divide the frequency to 1 GHz. The frequencies of the non-inverted clock 334 and the inverted clock 346 supplied to the serializer 102 are equal to or higher than the basic clock frequency of the signals 120 and 121 output from the final stage multiplexer 14.

  The flip-flop 32 receives the signals 330 and 332 and outputs the signals 50 and 51 in synchronization with the non-inverted clock 334. The flip-flop 34 receives the signals 122 and 123 and outputs signals 54 and 55 in synchronization with the non-inverted clock 334. That is, the signals 50 and 51 and the signals 54 and 55 are in phase. The test target circuit 300-3 receives the signals 50 and 51 and outputs the signals 52 and 53 in synchronization with the differential clock 346. Therefore, the signals 52 and 53 are input to the selector 30 with a delay of a half cycle of the non-inverted clock 334 from the signals 54 and 55.

  The selector 30 selects either the differential signal composed of the signals 52 and 53 or the differential signal composed of the signals 54 and 55 in accordance with the logical value of the non-inverted clock 334 and selects the differential signal composed of the signals 120 and 121 as the differential signal. Multiplex by division and output. The selector 30 selects a differential signal composed of signals 52 and 53 when the non-inverted clock 334 has a logical value of 0, and selects a differential signal composed of signals 54 and 55 when the non-inverted clock 334 has a logical value of 1.

  The selector 30 alternately outputs the logic values of the signals 52 and 53 and the signals 54 and 55 as the signals 120 and 121 according to the change in the logic value of the non-inverted clock 334. As described above, since the phases of the signals 52 and 53 are delayed by half a cycle of the non-inverted clock 334 relative to the signals 54 and 55, the selector 30 outputs two pieces of logical value data in one cycle of the non-inverted clock 334. I can do it.

As described above, the multiplexer 14 converts the two pairs of parallel differential signals composed of the signals 330, 332, 122, and 123 into a pair of serial differential signals composed of the signals 120 and 121, and has a frequency twice that of the input parallel differential signal. It can be converted into 4 Gbps, that is, 2 GHz signal and output.
[Test target circuit]
FIG. 3 is a circuit diagram of the circuit under test 300-1 in the present embodiment. The test target circuit 300-1 includes a latch circuit 200 and a holding circuit 354. The latch circuit 200 latches the signals 338 and 340 having the same logical value as that of the input signals 330 and 332 when the non-inverted clock 334 has the logical value 1 while the inverted clock 346 has the logical value 1.

  The normal operation of the latch circuit 200 at high frequency is as follows. Sampling circuit 350 samples signals 330, 332 when non-inverted clock 334 has a logical value of 1, and outputs a signal 338 having a logical value equal to signal 330 and a signal 340 having a logical value equal to signal 332. The sampling circuit 350 includes resistors 301 and 302 and MOS transistors 304, 305, and 306. One of the resistors 301 is connected to the positive power supply, and the other is connected to the drain of the MOS transistor 304. One of the resistors 302 is connected to the positive power supply, and the other is connected to the drain of the MOS transistor 305. The signal 338 is connected to the drain of the MOS transistor 304. The signal 340 is connected to the drain of the MOS transistor 305. The signal 330 is input to the gate of the MOS transistor 304. The signal 332 is input to the gate of the MOS transistor 305. When the signals 330 and 332 become the logical value 1, the MOS transistors 304 and 305 are turned on, and a current flows from the drain to the source.

  The sources of the MOS transistors 304 and 305 are connected to the drain of the MOS transistor 306, respectively. The gate of the MOS transistor 306 is connected to the non-inverted clock 334. The source of the MOS transistor 306 is connected to the drain of the MOS transistor 308. A bias voltage 336 is applied to the gate of the MOS transistor 308. The source of the MOS transistor 308 is connected to the ground. The MOS transistor 308 operates as a current source. The current value of the current source is determined by the voltage value of the bias voltage 336.

  When the non-inverted clock 334 becomes a logical value 1, the MOS transistor 306 is turned on. When the signal 330 becomes a logical value 1 and the MOS transistor 304 is turned on, the current value set by the MOS transistor 308 flows through the resistor 301. As a result, the logical value of the signal 340 becomes the inverted logical value 0 of the signal 330. At this time, since the signal 332 which is a differential pair of the signal 330 is a logical value 0, the MOS transistor 305 is off. Therefore, no current flows through the resistor 302, and the signal 338 has a logical value “1”. Therefore, when the non-inverted clock 334 has a logical value 1, the sampling circuit 350 receives the signals 330 and 332 and outputs signals 338 and 340 having logical values equal to the input signals.

  The holding circuit 352 continues to hold the logic values of the signals 338 and 340 while the inverted clock 346 is at the logic value 1. The holding circuit 352 includes MOS transistors 310, 312, and 314. The drain of the MOS transistor 310 is connected to the signal 338. The drain of the MOS transistor 312 is connected to the signal 340. The gate of the MOS transistor 310 is connected to the signal 340, and the gate of the MOS transistor 312 is connected to the signal 338. The sources of the MOS transistors 310 and 312 are connected to the drain of the MOS transistor 314, respectively. The gate of the MOS transistor 314 is connected to an inverted clock 346 obtained by logically inverting the non-inverted clock 334. The source of the MOS transistor 314 is connected to the drain of the transistor 308.

  Assuming that the signal 338 has a logical value 1, the differential signal 340 has a logical value 0. At this time, the MOS transistor 312 whose gate is connected to the signal 338 is turned on. When the inverted clock 346 has a logical value 1, the MOS transistor 314 is turned on. When the MOS transistor 314 is turned on, the current value set in the MOS transistor 308 flows through the resistor 301. As a result, the signal 340 is held at the logical value 0. Since the MOS transistor 310 whose gate is connected to the signal 340 is turned off, no current flows through the resistor 302. As a result, the signal 338 is held at the logical value 1. Therefore, when the inverted clock 346 has a logical value 1, the holding circuit 352 continues to hold the logical values of the signals 338 and 340.

  During a test operation at a low frequency, the rise and fall times of the non-inverted clock 334 and the inverted clock 346 become very long. When the rise and fall times of the non-inverted clock 334 and the inverted clock 346 are very long, both the non-inverted clock 334 and the inverted clock 346 may have a logical value “1”. At this time, since both the sampling circuit 350 and the holding circuit 352 operate, the latch circuit 200 cannot latch the logical value of the signal. Thus, the clock generation circuit 400 is used to shift the rising and falling phases so that the non-inverted clock 334 and the inverted clock 346 do not both have a logical value of 1. Thereby, it is possible to avoid the sampling circuit 350 and the holding circuit 352 from operating together. It is desirable that the time for shifting the phase is longer than the transition time of the non-inverted clock 334. As a result, it is possible to reliably prevent both the non-inverted clock 334 and the inverted clock 346 from having a logical value 1.

When both the non-inverted clock 334 and the inverted clock 346 are logic values 0, the sampling circuit 350 and the holding circuit 352 do not operate. If the sampling circuit 350 and the holding circuit 352 do not operate together, there is no one that determines the logical values of the signals 338 and 340, and the logical values of the signals 338 and 340 become unstable. Therefore, a holding circuit 354 is provided that latches the logical values of the signals 338 and 340 when the non-inverted clock 334 and the inverted clock 346 are both at the logical value 0.

  The holding circuit 354 operates only when the enable signal 348 has a logical value “1”. The enable signal 348 having the logical value 1 is input to the holding circuit 354 when both the non-inverted clock 334 and the inverted clock 346 have the logical value 0. The holding circuit 354 includes resistors 316 and 318 and MOS transistors 320, 322 and 324. One of the resistors 316 is connected to the signal 338 and the other is connected to the MOS transistor 320. One of the resistors 318 is connected to the signal 340 and the other is connected to the MOS transistor 322. The gate of the MOS transistor 320 is connected to the resistor 318, and the gate of the MOS transistor 322 is connected to the resistor 316. The sources of the transistors 320 and 322 are connected to the drain of the MOS transistor 324. The gate of the MOS transistor 324 is connected to the enable signal 348. The source of the MOS transistor 324 is connected to the ground.

  Assuming that the signal 338 has a logical value 1, the differential signal 340 has a logical value 0. At this time, the MOS transistor 322 whose gate is connected to the signal 338 via the resistor 316 is turned on. When the enable signal 348 becomes a logical value 1, the MOS transistor 324 is turned on. When MOS transistors 322 and 324 are turned on, current flows through resistor 301. As a result, the signal 340 is held at the logical value 0. Since the MOS transistor 320 whose gate is connected to the signal 340 via the resistor 318 is turned off, no current flows through the resistor 302. As a result, the signal 338 is held at the logical value 1. Therefore, while the enable signal 348 is a logical value 1, the holding circuit 354 continues to hold the logical values of the signals 338 and 340. As a result, the logical values of the signals 338 and 340 can continue to be latched even when the non-inverted clock 334 and the inverted clock 346 are both at the logical value 0. Therefore, the serializer 14 can operate normally during the test operation.

  A device having the holding circuit 354 and the enable signal generation unit 500 that outputs the enable signal 348 is referred to as a level holding unit. The level holding unit can hold the logical values of the signals 338 and 340 while the non-inverted clock 334 and the inverted clock 346 are both at the logical value 0 by the above-described operation.

  In the holding circuit 354, resistors 316 and 318 are inserted to reduce the influence of the signals 338 and 340 from the holding circuit 354. MOS transistors 320 and 322 have a drain capacitance. The capacitance component delays the rise and fall of the signal propagating through the signal line to which the capacitance component is connected. If the rise and fall of the signal are delayed, high-speed signal transmission becomes difficult. By connecting the resistors 316 and 318 between the signals 338 and 340 and the MOS transistors 320 and 322, the drain capacitance of the MOS transistors 320 and 322 can be made invisible. The resistance values of the resistors 316 and 318 are determined from the relationship with the resistance values of the resistors 301 and 302 so that when the MOS transistors 320 and 322 are turned on, the signals 338 and 340 can be determined to have a logical value of 0, respectively.

An inductor can be used instead of the resistors 316 and 318. An inductor has a very low impedance at a low frequency of several tens of MHz. For this reason, the logical values of the signals 338 and 340 can be held more accurately than when a resistor is inserted during low-frequency operation.
The impedance value of the inductor increases as the frequency becomes higher. By increasing the impedance value, the influence of the holding circuit 354 on the signals 338 and 340 during high-frequency operation is further reduced. The inductance value of the inductor is sufficiently large so that the parasitic capacitance of the holding circuit 354 does not affect the signals 338 and 340 during high-frequency operation.
[Clock generation circuit]
FIG. 4A is an example of a circuit diagram of a clock generation circuit 400 that adjusts the rising and falling timings of the clock and the inverted clock. FIG. 4B is a waveform diagram for explaining the operation of the clock generation circuit 400. The clock generation circuit 400 outputs the clock 20 and the inverted clock 21 having a period in which the clock 20 is a logical value 1 and shorter than this period during the logical value 0 period. The clock 20 and the inverted clock 21 are output from the switch 110 and become a non-inverted clock 334 and an inverted clock 346.

  4A, the clock generation circuit 400 includes NOT circuits 410, 414, 416, 420, 422, and NOR circuits 412, 418. The NOT circuit 410 receives the clock 401 and outputs a logic inversion signal of the clock. The NOR circuit 412 takes the output of the NOT circuit 410 as one input and the output of the NOT circuit 422 as the other input. The NOR circuit 412 outputs a signal having a logic value 0 when one input signal has a logic value 1. The NOT circuit 414 receives the output signal of the NOR circuit 412 and outputs its inverted signal. The NOT circuit 416 receives the output of the NOT circuit 414 and outputs the inverted signal as the clock 20.

  The NOR circuit 418 uses the output of the NOT circuit 416 as one input and the clock 401 as the other input. The NOR circuit 418 outputs a signal having a logic value 0 when one input signal has a logic value 1. The NOT circuit 420 receives the output signal of the NOR circuit 418 as an input and outputs its inverted signal. The NOT circuit 422 receives the output of the NOT circuit 420 and outputs its inverted signal as the inverted clock 21.

  4B is a waveform diagram of the clock 401, the clock 20, and the inverted clock 21 in the clock generation circuit 400. FIG. When the clock 20, which is the output of the NOT circuit 416, transitions from the logical value 1 to 0, the logical value 0 is input to one of the NOR circuits 418. The clock 401, which is the other input of the NOR circuit 418, also has a logical value of zero. Therefore, the NOR clock 418 and the NOT circuits 420 and 422 delay the T1 time from the transition of the clock 20, and the inverted clock 21 transitions from the logical value 0 to 1. Further, when the inverted clock 21, which is the output of the NOT circuit 422, transitions from the logical value 1 to 0, the logical value 0 is input to one of the NOR circuits 412. The output of the NOT circuit 410 which is the other input of the NOR circuit 412 is also a logical value 0. Therefore, the NOR circuit 412 and the NOT circuits 414 and 416 delay the clock 20 from the transition of the clock 21 by the time T2, and the clock 20 transits from the logical value 0 to 1. As a result, the clock generation circuit 400 receives the clock 401 and eliminates the period in which the clock 20 or the inverted clock 21 that is the phase inversion signal of the clock simultaneously has the logical value 1.

By using the clock generation circuit 400, even when a low-frequency clock whose signal rises and falls slowly is used, overlapping in which the clock and its inverted clock simultaneously have a logical value 1 can be avoided. By avoiding overlapping, either the sampling circuit 350 or the holding circuit 352 in FIG. 3 is operating, or neither is operating. That is, by eliminating the state in which the sampling circuit 350 and the holding circuit 352 operate simultaneously, it is possible to eliminate data omission in the latch circuit 200. Note that the times T1 and T2 in which the clock and its inverted clock are both at the logic value 0 can be adjusted by changing the number of NOT circuits 414, 416, 420, and 422. [Enable signal generator]
FIG. 5 is an example of a circuit diagram of the enable signal generation unit 500. The enable signal generator 500 outputs an enable signal 348 having a logic value 1 when both the clock 20 and the inverted clock 21 have a logic value 0. The enable signal generation unit 500 includes NOT circuits 502, 504, 506, and 508, AND circuits 510 and 512, and an OR circuit 514. The enable signal generation unit 500 has NOR logic, and the enable signal 348 has a logic value 1 when both the clock 20 and the inverted clock 21 have a logic value 0.

  When both the clock 20 and the inverted clock 21 have a logical value 1, the outputs of the NOT circuits 502, 504, 506, and 508 all have a logical value 0. Therefore, the outputs of the AND circuits 510 and 512 have a logical value 0, and the output of the OR circuit 514 also has a logical value 0.

  When either one of the clock 20 and the inverted clock 21 is a logical value 1, the outputs of the AND circuits 510 and 512 are a logical value 0, and the output of the OR circuit 514 is also a logical value 0.

  When both the clock 20 and the inverted clock 21 have a logical value 0, the outputs of the NOT circuits 502, 504, 506, and 508 all have a logical value 1. Therefore, the output of the AND circuit 510 has a logical value 1, and the output of the OR circuit 514 also has a logical value 1. Therefore, the enable signal generation unit 500 can set the enable signal 348 to the logical value 1 when both the clock 20 and the inverted clock 21 have the logical value 0.

When the clock 20 and the inverted clock 21 are both logical values 0, neither the sampling circuit 350 nor the holding circuit 352 in FIG. 3 operates. If neither of them operates, there is nothing that determines the logical values of the signals 338 and 340, so that the logical values of the signals 338 and 340 become unstable. When both the clock 20 and the inverted clock 21 have a logical value of 0, the holding circuit 354 holds the logical values of the signals 338 and 340 by inputting an enable signal 348 that becomes a logical value of 1 to the holding circuit 354. This prevents the logical values of the signals 338 and 340 from becoming unstable while the clock 20 and the inverted clock 21 are both at the logical value 0.
[Characteristics of NOT circuit]
FIG. 6A is a transistor configuration diagram of a NOT circuit used in the enable signal generation unit 500. 6B and 6C are input / output characteristic diagrams of transistors used in the NOT circuit. The NOT circuit used in the enable signal generation unit 500 has a threshold biased to either the low level or the high level of the signal.

  As described above, in order to reduce the influence on the resonance characteristics of the narrow band buffer during high frequency operation, the driving capability of the low frequency clock buffer is set low. When the driving capability of the clock buffer is low, the rise and fall times of the clock become long. As the clock rise and fall times become longer, the period during which the output logic value of the NOT circuit is not fixed becomes longer. If the output logic value of the NOT circuit is not determined, the logic value of the enable signal 348 is also not determined, so that the period during which the holding circuit 354 holds the logic values of the signals 338 and 340 is also uncertain. By adjusting the transistor characteristics of the NOT circuit, the holding circuit 354 can hold the logical values of the signals 338 and 340 more reliably.

  FIG. 6A is a transistor configuration diagram of NOT circuits 502, 504, 506, and 508 used in the enable signal generation unit 500. The NOT circuit 600 in FIG. 6A has a P-type MOS transistor 602 and an N-type MOS transistor 604. The NOT circuit 600 receives the signal 606 and outputs a signal 608. The logic value of the signal 608 is obtained by inverting the logic value of the signal 606.

  6B is an input / output characteristic diagram showing the relationship between the voltage of the input signal 606 and the voltage of the output signal 608 in FIG. 6A when the gate width of the P-type MOS transistor is smaller than the gate width of the N-type MOS transistor. The threshold voltage of the transistor can be changed by the gate width of the MOS transistor. For example, by making the gate lengths of the P-type and N-type MOS transistors the same and changing the ratio of the gate widths, the voltage X higher than VDD / 2 that is half the power supply voltage VDD can be set as the threshold value of the NOT circuit 600. .

FIG. 6C is an input / output characteristic diagram showing the relationship between the voltage of the input signal 606 and the voltage of the output signal 608 in FIG. 6A when the gate width of the P-type MOS transistor is larger than the gate width of the N-type MOS transistor. By making the gate lengths of the P-type and N-type MOS transistors the same and changing the ratio of the gate width, a voltage Y lower than VDD / 2 which is half of the power supply voltage VDD can be set as the threshold value of the NOT circuit 600.

  The NOT circuits 502 and 508 in FIG. 5 have the input / output characteristics shown in FIG. 6B. Further, NOT circuits 504 and 506 in FIG. 5 have the input / output characteristics shown in FIG. 6C. As a result, when the voltage values of the clock 20 and the inverted clock 21 are both equal to or lower than the voltage X, the enable signal 348 becomes a logical value 1. When the voltage value of one of the clock 20 and the inverted clock 21 becomes equal to or higher than the voltage Y, the enable signal 348 becomes a logical value 0. Thus, the period during which the holding circuit 354 holds the signals 338 and 340 can be clarified, and the logical values of the signals 338 and 340 can be held more reliably.

  FIG. 7 is a waveform diagram of the clock 20, the inverted clock 21, and the enable signal 348 when the enable signal generation unit 500 having the transistor characteristics of FIG. 6 is used.

When the voltage value of the clock 20 drops from VDD to X at time T3, the enable signal 348 transitions to a logical value 1. At time T4, when the voltage value of the inverted clock 21 increases from 0 to Y, the enable signal 348 transitions to the logical value 0. As a result, the transition timing of the logic value of the enable signal can be brought close to the transition timing of the clock 20 and the inverted clock 21. Thus, the period during which the holding circuit 354 holds the signals 338 and 340 can be clarified, and the logical values of the signals 338 and 340 can be held more reliably.
[Effectiveness of this embodiment]
This example is summarized as follows. In order to reduce the influence on the narrow band buffer for high frequency operation, the driving capability of the clock buffer for low frequency operation is reduced. The rise and fall times of the clock output from the clock buffer having a small driving capability and the inverted clock become very long. When the rise and fall times are long, a period in which the logical values of the clock and the inverted clock are 1 simultaneously occurs. When the logical value becomes 1 at the same time, the sampling circuit 350 and the holding circuit 352 constituting the latch circuit 200 operate simultaneously. If operated at the same time, the latch circuit 200 cannot latch data, and data omission occurs.

  In order to prevent data omission, the clock generation circuit 400 causes either the clock 20 or the inverted clock 21 to have a logical value 1 or both to have a logical value 0. In this case, either the sampling circuit 350 or the holding circuit 352 is operating, or both are not operating. That is, the sampling circuit 350 and the holding circuit 352 are not operated at the same time, so that data can be prevented from being missed.

  When the clock 20 and the inverted clock 21 simultaneously become the logical value 0, the sampling circuit 350 and the holding circuit 352 constituting the latch circuit 200 are stopped simultaneously. Since the sampling circuit 350 and the holding circuit 352 are simultaneously stopped, the logical value of the output signal of the latch circuit 200 becomes unstable.

  In order to stabilize the logic value of the output signal, a level holding unit that holds the logic value of the output signal of the latch circuit 200 while the clock 20 and the inverted clock 21 are simultaneously at the logic value 0 is provided. The level holding unit includes a holding circuit 354 and an enable signal generation unit 500. The enable signal generator 500 outputs an enable signal 348 having a logic value 1 while the clock 20 and the inverted clock 21 are simultaneously having a logic value 0. The holding circuit 354 holds the logical value of the output signal of the latch circuit 200 while the enable signal 348 is the logical value 1. With the above configuration, the output of the latch circuit 200 can be stabilized even at a low frequency, and a low-frequency operation test of the serializer can be performed.

It is a block diagram of a transmitter. It is a detailed block diagram of a multiplexer. 1 is a circuit diagram of a circuit under test that is an embodiment of the present invention. It is a circuit diagram and a waveform diagram of a clock generation circuit which is an embodiment of the present invention. It is a circuit diagram of the enable signal generation part which is one Example of this invention. It is the transistor block diagram of a NOT circuit, and the input-output characteristic figure of a transistor. It is a wave form diagram of a clock, an inversion clock, and an enable signal.

Explanation of symbols

10, 12, 14 Multiplexer 20, 22 Clock 21, 24 Inverted clock 32, 34 Flip-flop 30 Selector 100 Transmitter 102 Serializer 104 PLL
106 Divider 108 Buffer 110, 112 Switch 200 Latch circuit 300-m Test target circuit 334 Non-inverted clock 346 Inverted clock 348 Enable signal 350 Sampling circuit 352, 354 Holding circuit 400 Clock generating circuit 401 Clock 500 Enable signal generating unit 600 NOT circuit

Claims (5)

A non-inverted clock having a first logic value and a second logic value, and said second logic value in a short second period than the first period in the first period the non inverted clock is said first logic value A clock generation circuit that outputs an inverted clock of
A sampling circuit that inputs first differential data and the non-inverted clock, and samples the first differential data with the non-inverted clock;
A first holding circuit that inputs the second differential data output from the sampling circuit and the inverted clock, and holds the second differential data according to the inverted clock;
An enable signal generator that outputs an enable signal during the period of the first logic value for both the non-inverted clock and the inverted clock;
Transmitter characterized in that it comprises a second holding circuit holding said second differential data in response to said enable signal. The transmitter of claim 1 wherein the second holding circuit, characterized in that it comprises a latch portion for latching the differential data, and an inductor connected between the output of the latch portion and the target Honka circuit . The transmitter of claim 1 wherein the second holding circuit, characterized in that it comprises a latch portion for latching the differential data, and a resistor connected between the output of the latch portion and the target Honka circuit . A buffer that outputs a clock during testing,
And inputs the clock, a non-inverted clock having a first logic value and a second logic value, in the short second period than the first period in a first period in which the non-inverted clock is said first logic value A clock generation circuit that outputs an inverted clock that is the second logical value;
A switch for enabling output of the non-inverted clock and the inverted clock in response to a switching signal; a sampling circuit for inputting the first differential data and the non-inverted clock; and sampling the first differential data with the non-inverted clock; ,
A first holding circuit that inputs the second differential data output from the sampling circuit and the inverted clock, and holds the second differential data according to the inverted clock;
An enable signal generator that outputs an enable signal during the period of the first logic value for both the non-inverted clock and the inverted clock;
Transmitter characterized in that it comprises a second holding circuit holding said second differential data in response to said enable signal. 5. The transmitter according to claim 4, wherein the enable signal generation unit outputs the enable signal only when outputs of the non-inverted clock and the inverted clock are valid.