JP5325750B2 - Solid-state imaging device, imaging device - Google Patents

Description

  The present invention relates to a solid-state imaging device and an imaging device including the same.

  A photoelectric conversion element including a pair of electrodes and a photoelectric conversion layer sandwiched between them is provided above the silicon substrate, and charges generated in the photoelectric conversion layer are transferred from one of the pair of electrodes to the silicon substrate, and the charge is A photoelectric conversion layer stacked type solid-state imaging device that reads signals to the outside by a MOS circuit formed on a silicon substrate is known (see Patent Documents 1, 2, and 3).

  In such a solid-state imaging device, a bias voltage is applied to the photoelectric conversion layer during the exposure period in order to collect the charges generated in the photoelectric conversion layer with an electrode. Patent Document 1 discloses a method of performing white balance adjustment by changing the sensitivity of the photoelectric conversion element by changing the level of the bias voltage. Patent Document 2 discloses a method of correcting overexposure and underexposure by changing the amount of signal generated by the voltage applied to the photoelectric conversion layer so as not to saturate the signal output.

  The voltage applied to the photoelectric conversion layer generally requires a voltage (about 3.3V to 40V) equal to or higher than the power supply voltage (generally about 3.3V) used for the MOS circuit that reads signals from the photoelectric conversion layer. Therefore, depending on the voltage applied to the photoelectric conversion layer and the method of reading out a signal corresponding to the photoelectrically converted charge, the signal level read from the photoelectric conversion layer when excessive light is incident is the power supply voltage of the MOS circuit. Overvoltage is exceeded. As a result, not only image defects are caused, but there is a possibility that the solid-state image sensor is deteriorated or destroyed.

  Patent Document 3 discloses a method for preventing the destruction of the CMOS circuit by releasing the charge generated in the photoelectric conversion layer to the substrate of the CMOS circuit portion. However, in this method, it is necessary to add a special configuration for releasing charges to the substrate to the CMOS circuit, and a general-purpose CMOS process cannot be employed as it is.

JP 2006-94263 A JP 2009-49525 A JP 2002-271701 A

  The present invention has been made in view of the above circumstances, and provides a highly versatile photoelectric conversion layer stacked type solid-state imaging device capable of preventing destruction of a signal readout circuit due to excessive light and an imaging apparatus including the same. The purpose is to do.

The solid-state imaging device of the present invention is a solid-state imaging device having a plurality of pixels that receive light and output a signal corresponding to the light, and each of the plurality of pixels is a pair of substrates provided above the substrate. An electrode, a photoelectric conversion layer provided between the pair of electrodes, and a MOS circuit that is formed on the substrate and reads a signal corresponding to the electric charge generated in the photoelectric conversion layer by a MOS transistor, and the plurality of pixels include , an effective pixel which outputs a signal for image data generation, ineffective for outputting not used signal to generate the image data a signal which is utilized to control the bias voltage applied between the pair of electrodes A bias voltage application unit that applies a variable bias voltage according to an imaging condition between the pair of electrodes, and the bias voltage application unit is obtained from the ineffective pixel It is intended for variably controlling the bias voltage in accordance with the Patent.

  The imaging device of the present invention includes the solid-state imaging device.

  ADVANTAGE OF THE INVENTION According to this invention, the versatile photoelectric conversion layer laminated | stacked solid-state image sensor which can prevent the destruction of the signal read-out circuit by excessive light, and an imaging device provided with the same can be provided.

The figure which shows schematic structure of the imaging device for describing one Embodiment of this invention FIG. 1 is a schematic plan view showing the overall configuration of a solid-state imaging device in the imaging apparatus shown in FIG. Enlarged view of region A shown in FIG. The figure which shows schematic structure of the pixel arrange | positioned in the effective pixel area | region shown in FIG. The schematic diagram which showed the cross section of the pixel shown in FIG. 4, and the cross section of the low-pass filter connected to the counter electrode of the pixel The figure which shows schematic structure of the pixel arrange | positioned in the excessive light detection pixel area | region shown in FIG. The figure which shows the detailed structure of the peripheral circuit in the solid-state image sensor shown in FIG. The figure which showed the signal output characteristic of the photoelectric conversion element contained in the pixel arrange | positioned at the effective pixel area | region of the solid-state image sensor shown in FIG. Circuit diagram showing a configuration example of the booster circuit shown in FIG. The flowchart for demonstrating the imaging operation of the imaging device shown in FIG. The figure which showed the modification of the enlarged view of the area | region A shown in FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a diagram showing a schematic configuration of an imaging apparatus for explaining an embodiment of the present invention. Examples of the imaging device include an imaging device such as a digital camera and a digital video camera, an imaging module mounted on an electronic endoscope, a camera-equipped mobile phone, and the like. Here, a digital camera will be described as an example.

  The imaging apparatus shown in FIG. 1 includes a solid-state imaging device 30, a drive unit 20, a system control unit 21, a main memory 22, a digital signal processing unit 23, and a recording control unit 24.

  Although described in detail later, the solid-state image sensor 30 is a photoelectric conversion layer stacked type solid-state image sensor that reads a signal by a MOS circuit formed on a substrate such as a silicon substrate. That is, the solid-state imaging device 30 includes a plurality of pixels, and each pixel is formed on a pair of electrodes provided above the substrate, a photoelectric conversion layer provided between the pair of electrodes, and the substrate. A MOS circuit that reads out a signal corresponding to the electric charge generated in the photoelectric conversion layer by a MOS transistor is included.

  The drive unit 20 drives the solid-state imaging device 30 under the control of the system control unit 21.

  The main memory 22 temporarily stores the image signal output from the solid-state image sensor 30.

  The digital signal processing unit 23 performs digital signal processing (γ correction processing, RGB / YC conversion processing, etc.) on the imaging signal output from the solid-state imaging device 30 and stored in the main memory 22 to generate image data. .

  The recording control unit 24 controls the recording medium 25 that can be attached to and detached from the imaging apparatus, records image data on the recording medium 25, and reads image data from the recording medium 25.

  The system control unit 21 performs overall control of the entire imaging apparatus. The system control unit 21 determines imaging conditions such as imaging ISO sensitivity and exposure time, and controls the driving unit 20 to perform imaging according to the conditions.

  FIG. 2 is a schematic plan view showing the overall configuration of the solid-state imaging device in the imaging apparatus shown in FIG. FIG. 3 is an enlarged view of the region A shown in FIG. The solid-state imaging device 30 includes a sensor region in which a plurality of pixels that receive light and output a signal corresponding to the light are arranged, and other peripheral regions.

  The sensor area includes an effective pixel area 31 and an excessive light detection pixel area 32.

  In the effective pixel region 31, a plurality of pixels 31a are arranged in a two-dimensional shape (for example, a square lattice shape) in a horizontal direction and a vertical direction orthogonal thereto. The pixel 31a is a pixel for obtaining a signal for generating image data.

  The excessive light detection pixel region 32 is provided so as to surround the effective pixel region 31, and a plurality of pixels 32a are provided in this region. The pixel 32a is used to obtain a signal necessary for controlling the bias voltage applied between the pixel 31a and a pair of electrodes included in the pixel 32a, and the signal obtained from the pixel 32a is used for generating image data. Not. The size of the pixel 32a in plan view is larger than the size of the pixel 31a in plan view.

  The pixel 32a detects excessive light that increases the output signal of the MOS circuit in order to prevent the MOS circuit of each pixel 31a in the effective pixel region 31 from being destroyed or deteriorated. For this reason, it is preferable that the pixel 32a is disposed so as to completely surround the pixel 31a disposed on the outermost periphery of the effective pixel region 31 so that excessive light can be detected without omission.

  A peripheral circuit 33 is provided in the peripheral region of the solid-state image sensor 30. The peripheral circuit 33 includes a circuit that supplies a bias voltage to each pixel arranged in the sensor region, a circuit that drives a MOS circuit of each pixel, a circuit that performs signal processing on a signal read from each pixel, and the like.

  FIG. 4 is a diagram showing a schematic configuration of the pixel 31a arranged in the effective pixel region 31 shown in FIG. FIG. 5 is a schematic cross-sectional view of the pixel shown in FIG. 4 and a schematic cross-sectional view of a low-pass filter connected to the counter electrode of the pixel.

  As shown in FIG. 4, the pixel 31a includes a photoelectric conversion element P, a floating diffusion FD, an output transistor 5a, a selection transistor 5b, and a reset transistor 5c. The output transistor 5a, the selection transistor 5b, and the reset transistor 5c constitute the MOS circuit 5 shown in FIG. The output transistor 5a, the selection transistor 5b, and the reset transistor 5c are each composed of an n-channel MOS transistor.

  As shown in FIG. 5, the photoelectric conversion element P includes a pair of electrodes (a pixel electrode 14 and a counter electrode 16 opposed thereto) provided above the p-type silicon substrate 1 as a substrate, a pixel electrode 14 and a counter electrode. 16 and a photoelectric conversion layer 15 provided between the two.

  Subject light is incident on the counter electrode 16 from above. The counter electrode 16 is made of a conductive material such as ITO (indium tin oxide) that is transparent to the incident light because incident light needs to be incident on the photoelectric conversion layer 15. The counter electrode 16 has a common configuration for all pixels (pixels 31a and 32a). However, the counter electrode 16 may be divided for each pixel, and all the divided counter electrodes may be connected by wiring.

  The pixel electrode 14 is a thin film divided for each pixel 31a and is made of a transparent or opaque conductive material (ITO (indium tin oxide), aluminum, or the like).

  The photoelectric conversion layer 15 is a layer made of an organic or inorganic photoelectric conversion material that absorbs a specific wavelength region of incident light and generates a charge corresponding to the absorbed light amount. By constituting the photoelectric conversion layer 15 with a photoelectric conversion material (for example, quinacridone) that absorbs light in the green wavelength region and generates a charge corresponding thereto, visible light monochrome imaging is possible. By configuring the photoelectric conversion layer 15 with a photoelectric conversion material (for example, a phthalocyanine-based organic material or a naphthalocyanine-based organic material) that absorbs light in the infrared wavelength region and generates a charge corresponding to the light, infrared light is generated. Monochrome imaging is possible.

  The floating diffusion FD is electrically connected to the pixel electrode 14, and the potential thereof changes according to the potential of the pixel electrode 14. In the example of FIG. 4, a positive voltage VPX is applied to the counter electrode 16 during the exposure period, so that the potential of the floating diffusion FD increases with the start of exposure.

  The reset transistor 5c is for resetting the potential of the floating diffusion FD to a predetermined potential. The reset transistor 5c has a source terminal electrically connected to the floating diffusion FD, and a drain terminal supplied with a reset drain voltage VRD. When the reset pulse applied to the gate terminal of the reset transistor 5c becomes high level, the reset transistor 5c is turned on, and the potential of the floating diffusion FD is reset to the reset drain voltage VRD.

  The output transistor 5a converts the potential of the floating diffusion FD into a voltage signal and outputs it. In other words, the output transistor 5a outputs a signal corresponding to the amount of charge collected by the pixel electrode 14. The gate terminal of the output transistor 5a is electrically connected to the floating diffusion FD, and the power supply voltage VDD of the MOS circuit 5 is supplied to the drain terminal. The source terminal is connected to the drain terminal of the selection transistor 5b.

  The selection transistor 5b is for selectively outputting the output signal of the output transistor 5a to the signal line S. The source terminal of the selection transistor 5b is connected to the signal line S. When the selection pulse applied to the gate terminal of the selection transistor 5b becomes high level, the selection transistor 5b is turned on, and the voltage signal converted by the output transistor 5a is output to the signal line S.

  As shown in FIG. 5, a light shielding film 12 is provided above the silicon substrate 1 and below the pixel electrode 14, and the MOS circuit 5 is shielded from light by the light shielding film 12.

  The area of the pixel 31a shown in FIG. 3 is the same as the area of the pixel electrode 14 shown in FIGS. 4 and 5 in plan view. That is, the size of the pixel 31a in plan view is determined by the size of the pixel electrode 14 in plan view.

  As shown in FIG. 4, a low-pass filter (LPF) 40 is connected to the counter electrode 16 of each pixel 31a, and a booster circuit 50 is connected to the LPF 40. The LPF 40 and the booster circuit 50 are included in the peripheral circuit 33 shown in FIG.

  The booster circuit 50 is, for example, a charge pump booster circuit, and applies a variable bias voltage to the counter electrode 16 via the LPF 40. The LPF 40 is for suppressing power supply noise included in the power supply voltage of the booster circuit 50.

  As shown in FIG. 5, the LPF 40 includes parallel flat plates M1, M2, M3, a wiring part M4, and a connection part 41.

  The parallel plates M1, M2, and M3 are stacked in the vertical direction in the insulating layer 10 above the substrate 1 in the peripheral region and are provided in parallel to each other. The parallel plates M1 to M3 are electrically connected to each other through vias (not shown). Since the parallel plates M1 to M3 may be electrically connected to each other as necessary in the circuit configuration, it is not necessary to connect all of them, and they may be appropriately connected.

  The parallel plate M1 is formed on the gate insulating film 2 with a predetermined thickness. The parallel plate M2 is provided on the parallel plate M1 via a part of the insulating layer 10. The parallel plate M3 is provided on the parallel plate M2 via a part of the insulating layer 10.

  On the parallel plate M3 positioned at the top of the parallel plates M1 to M3, a wiring portion M4 is provided via a part of the insulating layer 10. The wiring part M4 is electrically connected to the parallel plate M3 via the connection part 41. A counter electrode 16 on the sensor region side is provided so as to partially extend to the peripheral region side, and the counter electrode 16 and the wiring portion M4 are electrically connected in the peripheral region. Further, the wiring portion M4 is electrically connected to the output of the booster circuit 50. Each of the parallel plates M1 to M3 functions as an electrode of the capacitor C of the RC circuit.

  In the peripheral region, the parallel plates M <b> 1 to M <b> 3 and the wiring part M <b> 4 are stacked above the substrate 1 at a distance from each other. In the photoelectric conversion layer stacked type solid-state imaging device 30, there is a sufficient space above the substrate 1 in the peripheral region. For this reason, by providing the parallel flat plates M1 to M3 and the wiring portion M4 in such a part, the design of the other constituent members of the solid-state imaging device 30 is not affected, and on the same substrate 1 on which the sensor region is formed. A low-pass filter 40 can be built.

  The parallel plates M1 to M3 and the wiring part M4 may be formed in the same process using the same conductive material as that of the photoelectric conversion element P and the wiring layer of the MOS circuit 5. For example, the wiring part M4 may be made of the same conductive material as the pixel electrode 14 of the photoelectric conversion element P. At this time, the position of the wiring part M4 and the pixel electrode 14 from the surface of the substrate 1 is the same.

The wiring part M4 functions as the resistance R of the RC circuit and can be configured using a predetermined metal material (top metal) located at the uppermost part of the peripheral region of the substrate 1. As the top metal, TiN (titanium nitride) is used instead of Au (gold), Al (aluminum), and Cu (copper) as a material that can be connected to ITO (indium tin oxide) constituting the counter electrode 16 without being oxidized. ). By using a material having a high resistivity such as TiN, the wiring portion M4 can be formed as a resistance and a wiring length can be realized. As a material constituting the wiring part M4, a resistivity of 1 × 10 ⁻⁷ Ωm or more is preferable.

  FIG. 6 is a diagram showing a schematic configuration of the pixel 32a arranged in the excessive light detection pixel region 32 shown in FIG. The pixel 32a has the same configuration as the pixel 31a except that the protection transistor 5d is added and the size of the pixel electrode 14 in plan view is increased.

  Also in the pixel 32a, the size of the pixel electrode 14 in plan view is the size of the pixel, and as shown in FIG. 3, the size of the pixel 32a is larger than that of the pixel 31a.

  In the protection transistor 5d, the level of the signal read to the signal line S by the MOS circuit 5 (synonymous with the signal output from the output transistor 5a) exceeds the power supply voltage VDD, and the MOS circuit 5 is destroyed or deteriorated. Functions as a protection circuit. The protection transistor 5d has a gate terminal and a drain terminal electrically connected to the pixel electrode 14 and the floating diffusion FD, and a power supply voltage VDD is supplied to the source terminal. The protection transistor 5d can prevent the signal level output from the output transistor 5a from exceeding the voltage VDD.

  The MOS circuit 5 of the pixel 31a and the MOS circuit 5 of the pixel 32a are formed with wirings so that signals can be read independently.

  The pixel 32a is larger in size than the pixel 31a and can take a wide area for forming the MOS circuit 5. For this reason, there is sufficient space for adding the protection transistor 5d, and the protection transistor 5d can have a high breakdown voltage. Therefore, the pixel 32a is configured to prevent the MOS circuit 5 from being destroyed even when a large amount of light is incident. On the other hand, since the pixel 31a is not provided with a protection circuit for protecting the MOS circuit 5, the MOS circuit 5 may be destroyed when a large amount of light is incident.

  Therefore, in this solid-state imaging device 30, when the level of the signal output from the pixel 31a becomes a level that may destroy the MOS circuit 5 of the pixel 31a, the booster circuit 50 is applied to the counter electrode 16. By controlling to lower the bias voltage VPX to be applied, destruction of the MOS circuit 5 of the pixel 31a is prevented. Hereinafter, a configuration for realizing such control will be described.

  FIG. 7 is a diagram showing a detailed configuration of the peripheral circuit 33 in the solid-state imaging device shown in FIG. The peripheral circuit 33 includes an LPF 40, a booster circuit 50, a comparison unit 70, a threshold storage unit 80, a read control unit 90, a CDS circuit 110, and an AD conversion circuit 120.

  The read control unit 90 controls the MOS circuit 5 of the pixel 31 a and the MOS circuit 5 of the pixel 32 a independently to read signals from each MOS circuit 5. The CDS circuit 110 performs correlated double sampling processing on the signal read from the MOS circuit 5. The AD conversion circuit 120 converts the signal output from the CDS circuit 110 into a digital signal and outputs it to the outside of the solid-state imaging device 30.

  The comparison unit 70 detects the level of the signal read by the MOS circuit 5 of the pixel 32a and subjected to correlated double sampling processing, compares the detected level with a threshold value, and compares the comparison result with the booster circuit 50. Notify

  The threshold storage unit 80 is a memory that stores a threshold used by the comparison unit 70 for comparison.

  The booster circuit 50 boosts the voltage supplied from the power supply 60 of the imaging device, and applies the boosted voltage to the counter electrode 16 via the LPF 40. As a result, a predetermined bias voltage VPX is applied between the pixel electrode 14 and the counter electrode 16 of each pixel 31a, 32a.

  The booster circuit 50 has a function of controlling the level of the bias voltage VPX, and supplies an optimum bias voltage VPX according to the imaging conditions. The booster circuit 50 also has a function of changing the level of the bias voltage VPX according to the comparison result notified from the comparison unit 70 in order to protect the MOS circuit 5 of the pixel 31a. Specifically, when the level of the signal read from the pixel 32a exceeds the first threshold, the booster circuit 50 sets the level of the bias voltage VPX so that the level falls below the first threshold. Control.

  As shown in FIG. 3, the pixel 31a and the pixel 32a have different sizes, and therefore the signal output characteristics thereof are different. For this reason, the first threshold value needs to be set in consideration of the difference in signal output characteristics between the pixel 31a and the pixel 32a.

  When imaging is performed under certain imaging conditions (bias voltage VPX, bias voltage VPX application time), the correspondence between the signal level output from the pixel 31a and the signal level output from the pixel 32a depends on the difference in pixel size. Become known. For this reason, when the signal level output from the pixel 31a becomes a level causing the destruction of the MOS circuit 5 (the power supply voltage VDD or a value slightly lower than that), the signal level output from the pixel 32a corresponding to this level is also I understand. Therefore, the signal level output from the pixel 32a corresponding to the level causing destruction is set as the first threshold value. In this way, when the signal level output from the pixel 32a exceeds the first threshold, it can be determined that the MOS circuit 5 of the pixel 31a may be destroyed.

  FIG. 8 is a diagram illustrating signal output characteristics of the photoelectric conversion element P included in the pixel 31a of the solid-state imaging element 30 illustrated in FIG. The horizontal axis shown in FIG. 8 indicates a period (exposure period) in which the bias voltage VPX is applied to the counter electrode 16, and the vertical axis indicates the output level of the signal read from the MOS circuit 5. “Counter voltage” shown in FIG. 8 indicates the bias voltage VPX applied to the counter electrode 16.

  As shown in FIG. 8, in the photoelectric conversion element P of the pixel 31a, the signal output level obtained in the same exposure period increases as the counter voltage increases. When the counter voltage is 1V, the signal level read from the MOS circuit 5 of the pixel 31a is almost zero.

  In the photoelectric conversion element P of the pixel 31a having such characteristics, assuming that the power supply voltage VDD of the MOS circuit 5 of the pixel 31a is 3.3V, the output signal variation (about 10%) with respect to the power supply voltage VDD3.3V. In addition, for the sake of safety, the output signal level of the pixel 32a corresponding to a voltage having a margin of about 10%, that is, 3.3 × 0.9 × 0.9 = 2.673V is first set. Is stored in the threshold value storage unit 80 as a threshold value.

  For example, first, the exposure period corresponding to the signal output of 2.673 V can be found from the graph shown in FIG. 8 when the bias voltage VPX = 15 V. Next, the signal output level corresponding to this exposure period is also found from the graph of the signal output characteristics when the bias voltage VPX = 15 V of the pixel 32a. For this reason, this signal output level may be set as the first threshold value. Similarly, the first threshold value can be obtained for each bias voltage VPX.

  The booster circuit 50 applies the level of the bias voltage VPX determined according to the imaging conditions and the level of the signal read from the pixel 32a when imaging is performed by applying the bias voltage VPX according to the application period. Is higher than the first threshold value (that is, when there is a high-luminance part in which the signal output of the pixel 31a exceeds 2.673 V in FIG. 8), the level is set to be lower than the first threshold value. Reduce the counter voltage. Thereby, the MOS circuit 5 of the pixel 31a can be protected.

  A plurality of first threshold values may be provided according to the level of the bias voltage VPX determined according to the imaging conditions.

  FIG. 9 is a circuit diagram showing a configuration example of the booster circuit 50 shown in FIG.

  The booster circuit 50 shown in FIG. 9 includes MOS diodes 51a to 51e having drain terminals and gate electrodes connected, capacitors 52a to 52e, a clock pulse supply unit 53, and an inverter 54.

  The MOS diodes 51a to 51e are switches for transferring charges to the output side, and are connected in multiple stages. On / off of the MOS diodes 51 a to 51 e is controlled by a clock pulse supplied from the clock pulse supply unit 53.

  A power supply 60 is connected to the drain terminal of the first-stage MOS diode 51a.

  The source terminal of the first-stage MOS diode 51a is connected to the drain terminal of the second-stage MOS diode 51b. One end of a capacitor 52a is connected to the gate electrode of the second-stage MOS diode 51b, and the output terminal of the inverter 54 is connected to the other end of the capacitor 52a. One of the two output terminals of the clock supply unit 53 is connected to the input terminal of the inverter 54.

  The source terminal of the second-stage MOS diode 51b is connected to the drain terminal of the third-stage MOS diode 51c. One end of the capacitor 52b is connected to the gate electrode of the third-stage MOS diode 51c, and the other of the two output terminals of the clock supply unit 53 is connected to the other end of the capacitor 52b.

  The source terminal of the third-stage MOS diode 51c is connected to the drain terminal of the fourth-stage MOS diode 51d. One end of a capacitor 52c is connected to the gate electrode of the fourth-stage MOS diode 51d, and the output terminal of the inverter 54 is connected to the other end of the capacitor 52c.

  The source terminal of the fourth-stage MOS diode 51d is connected to the drain terminal of the fifth-stage MOS diode 51e. One end of a capacitor 52d is connected to the gate electrode of the fifth-stage MOS diode 51e, and the other of the two output terminals of the clock supply unit 53 is connected to the other end of the capacitor 52d. A capacitor 52e is connected to the source terminal of the fifth-stage MOS diode 51e, and this capacitor 52e is connected to the LPF 40.

  In such a booster circuit 50, the voltage Vout output to the LPF 40 is Vout = 5 (VDD−Vth). Vth is a threshold voltage of each of the MOS diodes 51a to 51e.

  In the booster circuit 50, the clock pulse supply unit 53 changes the level of the voltage Vout by changing the frequency of the clock pulse output from the two output terminals. The clock pulse supply unit 53 changes the frequency of the clock pulse and changes the output voltage level of the booster circuit 50 in accordance with the comparison result notified from the comparison unit 70 or the instruction from the read control unit 90.

  Although the output voltage is changed according to the frequency of the clock pulse here, the present invention is not limited to this. For example, the number of diodes connected in multiple stages may be changed by a switch or the like, and the output voltage may be changed depending on the number of diodes connected. A booster circuit that changes the output voltage by changing the input voltage in an analog manner may be used. As in the circuit configuration shown in FIG. 9, the voltage can be easily changed greatly by changing the output voltage according to the frequency of the clock pulse.

  An imaging operation of the imaging apparatus configured as described above will be described.

  FIG. 10 is a flowchart for explaining the imaging operation of the imaging apparatus shown in FIG. When the shooting mode is started, the system control unit 21 sets the imaging conditions at the time of main imaging such as the level of the bias voltage VPX, the exposure period, and the aperture according to the set ISO sensitivity, shooting scene, and the like (step S1).

  After setting the imaging conditions, the system control unit 21 performs provisional imaging with the solid-state imaging device 30 under the imaging conditions set in step S1 (step S2).

  Here, “imaging” is generated in the photoelectric conversion layer 15 during the period of time after the floating diffusion FD is reset and a bias voltage according to the imaging condition is applied to the counter electrode 16 for a period of time according to the imaging condition. This is an operation of accumulating the processed signal in the floating diffusion FD.

  At the time of imaging, the readout control unit 90 controls the booster circuit 50 and sets the frequency of the clock pulse so that the bias voltage VPX is at a level according to the imaging conditions. Thereby, the bias voltage VPX at a level according to the imaging condition is applied to the counter electrode 16 and imaging is performed.

  After the provisional imaging, the system control unit 21 performs control to read out a signal generated by the provisional imaging (hereinafter referred to as a provisional imaging signal) from only the pixel 32a. The level of the provisional imaging signal output from the MOS circuit 5 of the pixel 32 a is detected by the comparison unit 70. Then, the comparison unit 70 compares the detected level with the first threshold value (step S3). At this time, the comparison unit 70 selects a first threshold value corresponding to the level of the bias voltage VPX included in the imaging condition set in step S1.

  In step S3, when the level of the temporary imaging signal exceeds the first threshold (determination: NO), the clock pulse supply unit 53 of the booster circuit 50 changes the frequency of the clock pulse to The bias voltage VPX is lowered so that the level falls below the first threshold (step S4).

  The system control unit 21 sets the bias voltage VPX finally changed in step S4 as an imaging condition for final main imaging, and shifts to an imaging standby state (step S5).

  If there is a shooting instruction, the main imaging is performed under the final imaging conditions. When the actual imaging is completed, the system control unit 21 performs control to read out the signal from only the pixel 31 a, digital signal processing is performed on the signal obtained from the pixel 31 a to generate image data, and this is recorded on the recording medium 25. Is done.

  As described above, according to this imaging apparatus, it is possible to change the bias voltage applied to the counter electrode 16 during the main imaging according to the level of the signal obtained from the pixel 32a by the temporary imaging. For this reason, it is possible to prevent the MOS circuit 5 of the pixel 31a from malfunctioning or being destroyed during the main imaging. As a result, a highly reliable solid-state imaging device can be provided.

  In addition, the solid-state imaging device 30 can be realized only by adding an excessive light detection pixel 32a to a general photoelectric conversion layer stacked type solid-state imaging device. For this reason, a general-purpose CMOS process can be used as it is, and an increase in cost can be prevented.

  In the above description, the size of the pixel 32a is assumed to be larger than the size of the pixel 31a. However, the present invention is not limited to this.

  For example, the pixel 31a and the pixel 32a may have the same size. In this case, since both signal output characteristics are the same, the level of the output signal that causes destruction of the MOS circuit 5 of the pixel 31a may be set as the first threshold value as it is.

  Further, as shown in FIG. 11, the size of the pixel 32a may be smaller than the size of the pixel 31a. By reducing the size of the pixel 32a, the signal level obtained from the pixel 32a can be relatively reduced even when the same amount of light is incident on the pixel 31a and the pixel 32a. That is, the pixel 32a can detect a larger amount of light, and is suitable for the excessive light detection pixel. When the size of the pixel 32a is made smaller than the size of the pixel 31a, the signal output of the pixel 32a is not easily increased. Therefore, it is not necessary to provide a protection circuit in the MOS circuit 5 of the pixel 32a.

  In the above description, the pixels 31a and 32a have one photoelectric conversion element P above the silicon substrate. However, the present invention is not limited to this. For example, color imaging can be performed by providing three photoelectric conversion elements P and three MOS circuits 5 corresponding thereto in one pixel. Alternatively, in one pixel, in the silicon substrate below the photoelectric conversion layer 15 of the photoelectric conversion element P, two photodiodes that detect different colors from the photoelectric conversion layer 15 and detect different colors, respectively, Color imaging can also be achieved by providing two MOS circuits 5 corresponding to this.

  When three photoelectric conversion elements P are provided in one pixel, it is preferable to change the level of the bias voltage VPX for each color detected by each photoelectric conversion element P, according to white balance which is one of the imaging conditions. Thus, it is preferable to determine the value of the bias voltage VPX of each of the three photoelectric conversion elements P. Even when one photoelectric conversion element P and two silicon photodiodes are provided in one pixel, the value of the bias voltage VPX of the photoelectric conversion element P is set according to the white balance of the color detected by one photoelectric conversion element P. Just decide.

  In the above description, the protection circuit is provided only for the pixel 32a. However, the protection circuit may be provided for the pixel 31a. In this case, since the MOS circuit 5 of the pixel 31a can be protected by controlling the bias voltage VPX by the booster circuit 50, the withstand voltage of the protection circuit provided in the pixel 31a does not need to be so high. For this reason, the protection circuit can be miniaturized, and the protection circuit can be added without disturbing the miniaturization of the solid-state imaging device 30 so much.

  As described above, the following items are disclosed in this specification.

  The disclosed solid-state imaging device is a solid-state imaging device having a plurality of pixels, and the pixels include a pair of electrodes provided above a substrate, a photoelectric conversion layer provided between the pair of electrodes, and the A MOS circuit that is formed on the substrate and reads out a signal corresponding to the electric charge generated in the photoelectric conversion layer by a MOS transistor, wherein the plurality of pixels include an effective pixel for obtaining a signal for generating image data; A non-effective pixel for obtaining a signal necessary for controlling a bias voltage applied between the electrodes, and a bias voltage applying unit that applies a variable bias voltage according to an imaging condition between the pair of electrodes. The bias voltage application unit variably controls the bias voltage in accordance with a signal obtained from the ineffective pixel.

  In the disclosed solid-state imaging device, the ineffective pixels are arranged outside a region where the effective pixels are arranged.

  In the disclosed solid-state imaging device, the size of the ineffective pixel is larger than the effective pixel.

  The disclosed solid-state imaging device includes a protection circuit that protects the MOS circuit so that the MOS circuit of the ineffective pixel does not output a signal having a level equal to or higher than the power supply voltage of the MOS circuit.

  In the disclosed solid-state imaging device, the size of the non-effective pixel is smaller than the effective pixel.

  In the disclosed solid-state imaging device, the non-effective pixels are arranged so as to surround the effective pixels.

  The disclosed solid-state imaging device includes a protection circuit that protects the MOS circuit so that the MOS circuit of the effective pixel does not output a signal having a level higher than the power supply voltage of the MOS circuit.

  The disclosed imaging device includes the solid-state imaging device.

DESCRIPTION OF SYMBOLS 1 Silicon substrate 5 MOS circuit 14 Pixel electrode 15 Photoelectric conversion layer 16 Counter electrode 31a Image data generation pixel 32a Bias control pixel 50 Booster circuit

Claims (8)

A solid-state imaging device having a plurality of pixels that receive light and output a signal corresponding to the light ,
Each of the plurality of pixels includes a pair of electrodes provided above the substrate, a photoelectric conversion layer provided between the pair of electrodes, and a charge formed in the photoelectric conversion layer formed on the substrate. Including a MOS circuit for reading a signal by a MOS transistor;
Signals that are used to control the bias voltage applied between the pair of electrodes , and that are not used to generate the image data, wherein the plurality of pixels output an image data generation signal. Ineffective pixels that output
A bias voltage application unit that applies a variable bias voltage according to imaging conditions between the pair of electrodes,
The bias voltage application unit is a solid-state imaging device that variably controls the bias voltage according to a signal obtained from the ineffective pixel. The solid-state imaging device according to claim 1,
A solid-state imaging device in which the non-effective pixels are arranged outside a region where the effective pixels are arranged. The solid-state imaging device according to claim 1 or 2,
A solid-state imaging device in which the size of the ineffective pixel is larger than that of the effective pixel. The solid-state imaging device according to claim 3,
A solid-state imaging device having a protection circuit that protects the MOS circuit so that the MOS circuit of the ineffective pixel does not output a signal having a level equal to or higher than a power supply voltage of the MOS circuit. The solid-state imaging device according to claim 1 or 2,
A solid-state imaging device in which the size of the non-effective pixel is smaller than the effective pixel. The solid-state imaging device according to any one of claims 1 to 5,
A solid-state imaging device in which the non-effective pixels are arranged so as to surround the effective pixels. It is a solid-state image sensing device according to any one of claims 1 to 6,
A solid-state imaging device having a protection circuit for protecting the MOS circuit so that the MOS circuit of the effective pixel does not output a signal having a level equal to or higher than a power supply voltage of the MOS circuit.   An imaging device provided with the solid-state image sensor of any one of Claims 1-7.

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