JP5323877B2 - LAMINATED CIRCUIT MATERIAL AND METHOD OF REDUCING ELECTRICAL RESISTANCE OF THIN FILM LAMINATE USING SAME - Google Patents
LAMINATED CIRCUIT MATERIAL AND METHOD OF REDUCING ELECTRICAL RESISTANCE OF THIN FILM LAMINATE USING SAME Download PDFInfo
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Description
5GHz以上の高周波数の電気信号を伝送する回路の形成材料である積層回路材料及びそれを用いた薄膜積層材の電気抵抗低下方法に関する。
The present invention relates to a laminated circuit material that is a material for forming a circuit that transmits an electric signal having a high frequency of 5 GHz or more, and a method for reducing the electrical resistance of a thin film laminated material using the same .
従来、高周波数電気信号を伝送する信号伝送線路において、放射や反射を少なくし、伝送損失を低減した信号伝送線路が特許文献1で提案されている。この信号伝送線路は、図5に示すようにSi基板1上に金属薄膜接地層4を設け、その上に窒化シリコン(SiN)や酸化シリコン(SiO2)などの絶縁膜2、金(Au)若しくはアルミニウム(Al)などの高導電性の金属薄膜線路3を設けた構造となっている。
Conventionally,
更に、より高導電性の銅(Cu)を金属薄膜線路に用いたCu配線構造体が特許文献2に提案されている。図6は、このCu配線構造体の断面構造を示したものであるが、Si基板1上にタングステン(W)や窒化チタン(TiN)などのベースメタル層5を設け、その上に窒化シリコン(SiN)のCu拡散防止絶縁膜7を間に介してCu配線層6と酸化シリコン(SiO2)の絶縁膜2を設けた構造となっている。
また、プリント配線基板上においては、表面粗度の小さい銅箔を張り付けた後にエッチングによってパタンニングしたり、リソグラフによってパタンを構成したのち、めっきによって回路が形成されたりしている。
Further,
On the printed wiring board, a copper foil having a small surface roughness is pasted and then patterned by etching, or a pattern is formed by lithograph and then a circuit is formed by plating.
基板上の信号伝送線路は図5、図6のように構成されている。
しかしながら、基板の材質が半導体である場合には、基板の抵抗値が低くリーク分が存在し、線路インピーダンスを設計値通りにできないために、数GHz以上の超高周波信号や数Gビット/秒以上の超高速信号を伝送しようとする場合、信号伝送線路よりの放射、反射などが多く、また伝送損失も極めて大きくなるなどの問題点が生じる。又、同一基板上に複数の信号伝送線路を形成した場合に、信号伝送線路の相互間のアイソレーションも悪化するという問題点もある。
The signal transmission line on the substrate is configured as shown in FIGS.
However, when the substrate is made of a semiconductor material, the resistance value of the substrate is low, there is a leak, and the line impedance cannot be as designed, so that an ultra-high frequency signal of several GHz or higher, or several Gbit / second or higher. However, there are many problems such as radiation and reflection from the signal transmission line, and extremely large transmission loss. In addition, when a plurality of signal transmission lines are formed on the same substrate, there is a problem that the isolation between the signal transmission lines also deteriorates.
更に、5GHz以上の高周波数の電気信号は、表皮効果により回路の表層しか流れないため、特性インピーダンスが大きくなり、信号遅延、電力ロス、及び発熱などの諸問題を引き起こす恐れがある。その防止には回路の表面積を大きくすることが有効であるが、小型化が要求されるモバイル機器等の伝送回路の設計において大きな問題を抱えることとなる。 Furthermore, since an electric signal having a high frequency of 5 GHz or more flows only on the surface layer of the circuit due to the skin effect, the characteristic impedance increases, which may cause various problems such as signal delay, power loss, and heat generation. In order to prevent this, it is effective to increase the surface area of the circuit, but there is a big problem in the design of a transmission circuit such as a mobile device that is required to be downsized.
そこで、本発明は前記問題点を解消するためになされたもので、特性インピーダンスを小さくできるために、超高周波又は超高速信号の伝送時においても反射や放射が少なく、かつ低損失である回路材料及びそれを用いた薄膜積層材の電気抵抗低下方法を提供することを目的とする。
Therefore, the present invention has been made to solve the above problems, and since the characteristic impedance can be reduced, the circuit material has low reflection and radiation and low loss even during transmission of an ultrahigh frequency or ultrahigh speed signal. Another object of the present invention is to provide a method for reducing the electrical resistance of a thin film laminate using the same.
請求項1記載の発明は、単一元素からなる原子層を単層若しくは10原子層未満の複数層で構成する導体層と、導体層を構成する元素同士間の原子間結合よりもより安定な結合を形成する単一又は複数の元素からなる原子層を単層若しくは10原子層未満の複数層で構成する拘束層と基板とからなり、基板上に拘束層を形成し、その上に導体層及び拘束層を形成した積層構造の、前記導体層と前記拘束層の原子同士を原子的整合状態で、前記導体層と前記拘束層の界面におけるミスフィットひずみが9.0%以下となるように、前記導体層と前記拘束層を基板上に積層した積層構造材料を用いることにより、前記基板上に前記導体層と前記拘束層を前記積層構造と同様の順に積層した積層構造の、前記導体層あるいは前記拘束層の少なくともいずれかの積層する層数を10原子層を超える層数積層した場合、あるいは拘束層がなく導体層を直接基板上に積層した構造の場合に比べて、直流電気抵抗値としての室温における導体断面積当りの比抵抗値あるいは室温における薄膜断面積あたりの比抵抗値を低下させることを特徴とする薄膜積層材の電気抵抗低下方法である。ここで示す積層回路材料の原子間結合の安定性は、原子間相互作用エネルギーや原子間のポテンシャルエネルギーの大きさに相当しており、安定状態に近いほど小さい値となる。
The invention according to
請求項2に記載の発明は、前記拘束層と導体層を拘束層が最外層となるように両者を交合に積層した構造からなる積層構造を基板上に積層した薄膜積層材の電気抵抗低下方法であって、拘束層と導体層とが原子的整合状態で積層されていることを特徴とする請求項1に記載の薄膜積層材の電気抵抗低下方法である。
According to a second aspect of the present invention, there is provided a method for reducing an electrical resistance of a thin film laminated material in which a laminated structure having a structure in which the constraining layer and a conductor layer are laminated so that the constraining layer is an outermost layer is laminated on a substrate. The constraining layer and the conductor layer are laminated in an atomically aligned state. 2. The method of lowering electrical resistance of a thin film laminate according to
請求項3に記載の発明は、前記導体層と拘束層からなる回路材料において、その構造が拘束層/導体層/拘束層の3層構造、若しくは更に拘束層の面上に導体層/拘束層の2層構造を複数回繰返し積層した構造からなる積層構造を基板上に積層した薄膜積層材の電気抵抗低下方法であって、拘束層と導体層並びに導体層と拘束層とが原子的整合状態で積層されていることを特徴とする請求項1並びに請求項2に記載の薄膜積層材の電気抵抗低下方法である。
According to a third aspect of the present invention, in the circuit material comprising the conductor layer and the constraining layer, the structure is a three-layer structure of constraining layer / conductor layer / constraining layer, or further a conductor layer / constraining layer on the surface of the constraining layer. a two-layer structure an electrical resistivity reduction method of a thin film laminate of the layered structure laminated on a substrate made of structures multiple times repeatedly laminated, constraining layer and is atomically aligned with constraining layer and the conductor layer and the conductor layer a
請求項4に記載の発明は、前記導体層がCu、Au、Ag、Alのいずれかの元素から構成され、前記拘束層が、前記導体層の格子定数に近い格子定数を有する単一乃至複数の元素からなる結晶構造を有する層であることを特徴とする請求項1乃至請求項3に記載の薄膜積層材の電気抵抗低下方法である。
According to a fourth aspect of the present invention, the conductor layer is composed of any element of Cu, Au, Ag, and Al, and the constraining layer has a single or plural lattice constants that are close to the lattice constant of the conductor layer. a
請求項5に記載の発明は、前記導体層が面心構造を基本構造とする結晶構造であることを特徴とする請求項1乃至請求項3に記載の薄膜積層材の電気抵抗低下方法である。
The invention according to
請求項6記載の発明は、前記拘束層が単原子層若しくは複数原子層からなるCu3Pd、CuPt、CuAu、PtV3、Ag3In、Al3Zr、AuV3から選択された少なくとも一つの化合物層を含むことを特徴とする請求項1乃至請求項5記載の薄膜積層材の電気抵抗低下方法であって、上記の化合物はいずれも導体層を構成する元素同士間の原子間結合よりもより安定な結合を形成する元素を含んでいる。なお、拘束層の構成元素の原子量は、電子の散乱効果を有効に抑えるためには、拘束層を構成する元素において平均して得られる原子番号ができるだけ大きいことがさらに望ましい。
The invention according to
請求項7記載の発明は、前記拘束層及び前記表面層の両者の表面方位が(100)方位又は(111)方位のどちらかの方位を有することを特徴とする請求項1乃至請求項6記載の薄膜積層材の電気抵抗低下方法である。
Invention according to
請求項8記載の発明は、単一元素からなる原子層を単層若しくは10原子層未満の複数層で構成する導体層と、導体層を構成する元素同士間の原子間結合よりもより安定な結合を形成する単一又は複数の元素からなる原子層を単層若しくは10原子層未満の複数層で構成する拘束層と基板とからなり、基板上に拘束層を形成し、その上に導体層及び拘束層を形成した積層構造で、さらに前記導体層と前記拘束層の原子同士を原子的整合状態で積層する積層構造の、前記導体層と前記拘束層の界面におけるミスフィットひずみが9.0%以下となるように、前記導体層と前記拘束層を基板上に積層した積層回路材料であって、
前記拘束層の最隣接原子間隔dmと前記導体層の最隣接原子間隔dcが以下の関係式(1)を満たすことを特徴とする積層回路材料である。
{(dm−αdc)2/(dm)2}1/2 ≦0.09 (1)
ここで、αは1、2、3のいずれかの値である。αが大きくなるほど界面転位が入りやすくなり、αが4を越えると平滑な界面が得られなくなる。
The invention according to claim 8 is more stable than a conductor layer in which an atomic layer made of a single element is composed of a single layer or a plurality of layers less than 10 atomic layers, and an interatomic bond between elements constituting the conductor layer. A constrained layer composed of a single layer or a plurality of elements of less than 10 atomic layers and a substrate comprising a single layer or a plurality of elements forming a bond, a constrained layer is formed on the substrate, and a conductor layer thereon In addition, a misfit strain at the interface between the conductor layer and the constraining layer in the layered structure in which the constraining layer is formed and the atoms of the conductor layer and the constraining layer are laminated in an atomically aligned state is 9.0. % Is a laminated circuit material in which the conductor layer and the constraining layer are laminated on a substrate,
Nearest neighbor atomic distance d c nearest neighbor atomic distance d m between the conductor layer is the product layer circuit material you satisfy the following relation (1) of the constraining layer.
{(D m -αd c) 2 / (d m) 2} 1/2 ≦ 0.09 (1)
Here, α is any one of 1, 2, and 3. As α increases, interfacial dislocations are more likely to occur, and when α exceeds 4, a smooth interface cannot be obtained.
本発明によれば、電気伝送回路を形成する導体層である金属層を薄くし、且つ金属層との結合力が強く金属層の格子振動を抑制する作用の大きな化合物層を金属層上下面に形成することにより、薄膜の厚み方向に伝達するフォノン強度を低下せしめ、薄膜の面方向に伝搬するフォノンの非弾性散乱を抑制する。このフォノンによる電子の非弾性散乱が抑制されることにより金属層の面方向への抵抗値が小さくなり、そのシート抵抗を小さくでき、信号遅延や電力損失による誤作動を効率よく防止できる。
According to the present invention, the metal layer, which is a conductor layer forming the electric transmission circuit, is thinned, and the compound layer having a strong binding force with the metal layer and a large effect of suppressing the lattice vibration of the metal layer is formed on the upper and lower surfaces of the metal layer. By forming, the phonon intensity transmitted in the thickness direction of the thin film is reduced, and inelastic scattering of phonons propagating in the plane direction of the thin film is suppressed. By suppressing the inelastic scattering of electrons by the phonons, the resistance value in the surface direction of the metal layer is reduced, the sheet resistance can be reduced, and malfunction due to signal delay and power loss can be efficiently prevented.
本発明において、導体層である金属層とその格子振動を抑制する拘束層である化合物層を規則的に積層することは、金属層の厚み方向に伝達するフォノンによる導電電子の非弾性散乱を抑制し、面方向に高い電子移動性を示すようになる。従って、より高い電気伝導性が得られ、そのシート抵抗を低減することができる。
In the present invention, regularly laminating a metal layer as a conductor layer and a compound layer as a constraining layer that suppresses lattice vibration suppresses inelastic scattering of conductive electrons due to phonons transmitted in the thickness direction of the metal layer. However, high electron mobility is exhibited in the surface direction. Therefore, higher electrical conductivity can be obtained and the sheet resistance can be reduced.
なお、高い電気導電性、つまり低い導体の直流抵抗が得られるとシート抵抗が低減されるのは、周波数ω、導体の透磁率μ、導体の直流抵抗ρとした場合、交流回路におけるシート抵抗Rsは、Rs=(ωμρ/2)1/2とした関係をもつためである。又、Rsは交流回路における電力損失に関係する導体損失係数や信号遅延に関わる遅延時間に比例する関係をもつため、導体の直流抵抗ρを小さくすると電力損失や信号遅延が起こりにくくなる。又、交流回路におけるシート抵抗Rsは直流抵抗ρの1/2乗に、周波数ω、導体の透磁率μ等から得られる定数を掛けた値になることから、直流抵抗ρ測定することにより、交流回路におけるシート抵抗Rsを評価できる。 Note that when high electrical conductivity, that is, low DC resistance of the conductor is obtained, the sheet resistance is reduced when the frequency ω, the permeability of the conductor μ, and the DC resistance of the conductor ρ are the sheet resistance Rs in the AC circuit. Is because Rs = (ωμρ / 2) 1/2 . Since Rs has a relationship proportional to a conductor loss coefficient related to power loss in an AC circuit and a delay time related to signal delay, if the DC resistance ρ of the conductor is reduced, power loss and signal delay are less likely to occur. In addition, since the sheet resistance Rs in the AC circuit is a value obtained by multiplying the DC resistance ρ to the 1/2 power by a constant obtained from the frequency ω, the magnetic permeability μ of the conductor, etc., the AC resistance can be measured by measuring the DC resistance ρ. The sheet resistance Rs in the circuit can be evaluated.
化合物層を拘束層に用いるのは、導体層のフォノン散乱を抑制するためであるが、化合物層中の電子の移動度が低く、導電性の高い金属層を電気が中心的に流れるため、拘束層の電気抵抗への影響は比較的小さいことになる。通常は、化合物層を拘束層に用いるが金属層も拘束層として用いることができる。拘束層に金属層を用いる場合には、拘束層に化合物層を用いる場合より拘束層中の電子移動度は大きいが、フォノン散乱の抑制効果は逆に小さい場合が多い。
拘束層の総数は、導体層の比抵抗値自体には影響を及ぼさないが、金属層に対する拘束層の割合が大きくなると、薄膜あたりの比抵抗値の値は増加するので、拘束層に対する導体層の原子層比率は大きくすることが望ましいが、導体層の比率が高くなりすぎると、逆に拘束層のフォノン散乱抑制効果が不十分となり比抵抗値が増加するため、拘束層と導体層の比率は、適宜設計する必要がある。拘束層を設けない場合は、導体層内の電子はフォノン散乱を受け、高い抵抗値となる。
The compound layer is used as the constraining layer in order to suppress phonon scattering in the conductor layer. However, since the electron mobility in the compound layer is low and electricity flows centrally in the highly conductive metal layer, the constraining layer is used. The effect on the electrical resistance of the layer will be relatively small. Usually, a compound layer is used as a constraining layer, but a metal layer can also be used as a constraining layer. When a metal layer is used as the constraining layer, the electron mobility in the constraining layer is higher than when a compound layer is used as the constraining layer, but the effect of suppressing phonon scattering is often small.
The total number of constraining layers does not affect the specific resistance value of the conductor layer itself. However, as the ratio of the constraining layer to the metal layer increases, the specific resistance value per thin film increases. It is desirable to increase the atomic layer ratio, but if the conductor layer ratio becomes too high, the constraining layer phonon scattering suppression effect is insufficient and the specific resistance value increases. It is necessary to design appropriately. When the constraining layer is not provided, electrons in the conductor layer are subjected to phonon scattering and have a high resistance value.
拘束層としては、導体層を構成する元素よりも、安定な結合を形成することが必要である。そのため、導体層を構成する元素の種類によって、拘束層を構成する元素の組合せは異なる。例えば、導体層をCuとした場合、拘束層化合物としては、Cu3Pd,CuPt,CuAu,PtV3等が考えられ、拘束層に用いる単一元素としては、Au、Pt,Ru,W,Zrなどが考えられる。どちらも拘束層に用いることができ、さらに拘束層を構成する元素の原子番号は大きいほど、電子の散乱効果を抑える作用が大きいため、より好ましい。
拘束層として用いる単一原子層又は化合物層の原子間隔はそれぞれ積層する導体層の原子間隔に近い方が望ましく、導体層の種類に応じて、規定する必要がある。導体層と拘束層の最隣接原子間距離の差が広がると、拘束層に整合に導体層の金属層が生成しなくなったり、導体層の金属層に転位が生じ、フォノンの非弾性散乱が起こりやすくなるためのである。つまり、拘束層は、拘束層が導体層より安定な結合を有することと、導体層と拘束層の原子間隔が小さく両者のミスフィットひずみが小さいことの2つの要件を満足することが必要である。
As the constraining layer, it is necessary to form a more stable bond than the elements constituting the conductor layer. Therefore, the combination of elements constituting the constraining layer differs depending on the type of element constituting the conductor layer. For example, when the conductor layer is Cu, the constraining layer compound may be Cu3Pd, CuPt, CuAu, PtV3, etc., and the single element used in the constraining layer may be Au, Pt, Ru, W, Zr, or the like. It is done. Both can be used for the constraining layer, and the larger the atomic number of the elements constituting the constraining layer, the more the action of suppressing the electron scattering effect is greater, and thus the more preferable.
It is desirable near the interatomic distance of a single atomic layer or compound layer conductive layer in interatomic spacing of laminating each used as a constraint layer, depending on the type of the conductor layer, necessary Ru Oh prescribed. When the difference between the distances between the adjacent atoms of the conductor layer and the constraining layer widens, the metal layer of the conductor layer does not form in alignment with the constraining layer, or dislocation occurs in the metal layer of the conductor layer, causing inelastic scattering of phonons. This is to make it easier. In other words, the constraining layer needs to satisfy the two requirements that the constraining layer has a more stable bond than the conductor layer and that the atomic spacing between the conductor layer and the constraining layer is small and the misfit strain between the two is small. .
拘束層としては、導体層を構成する元素よりも、安定な結合を形成することが必要である。そのため、導体層を構成する元素の種類によって、拘束層を構成する元素の組合せは異なる。例えば、導体層をCuとした場合、拘束層化合物としては、Cu3Pd,CuPt,CuAu,PtV3等が考えられ、拘束層に用いる単一元素としては、Au、Pt,Ru,W,Zrなどが考えられる。どちらも拘束層に用いることができ、さらに拘束層を構成する元素の原子番号は大きいほど、電子の散乱効果を抑える作用が大きいため、より好ましい。
拘束層として用いる単一原子層又は化合物層の原子間隔をそれぞれ積層する導体層の原子間隔に近い方が望ましく、導体層の種類に応じて、規定する必要がる。導体層と拘束層の最隣接原子間距離の差が広がると、拘束層に整合に導体層の金属層が生成しなくなったり、導体層の金属層に転位が生じ、フォノンの非弾性散乱が起こりやすくなるためのである。
つまり、拘束層は、拘束層が導体層より安定な結合を有することと、導体層と拘束層の原子間隔が小さく両者のミスフィットひずみが小さいことの2つの要件を満足することが必要である。
As the constraining layer, it is necessary to form a more stable bond than the elements constituting the conductor layer. Therefore, the combination of elements constituting the constraining layer differs depending on the type of element constituting the conductor layer. For example, when the conductor layer is Cu, the constraining layer compound may be Cu3Pd, CuPt, CuAu, PtV3, etc., and the single element used in the constraining layer may be Au, Pt, Ru, W, Zr, or the like. It is done. Both can be used for the constraining layer, and the larger the atomic number of the elements constituting the constraining layer, the more the action of suppressing the electron scattering effect is greater, and thus the more preferable.
It is desirable that the atomic spacing of the single atomic layer or the compound layer used as the constraining layer is closer to the atomic spacing of the conductive layers to be laminated, and it is necessary to define the atomic spacing according to the type of the conductive layer. When the difference between the distances between the adjacent atoms of the conductor layer and the constraining layer widens, the metal layer of the conductor layer does not form in alignment with the constraining layer, or dislocation occurs in the metal layer of the conductor layer, causing inelastic scattering of phonons. This is to make it easier.
In other words, the constraining layer needs to satisfy the two requirements that the constraining layer has a more stable bond than the conductor layer and that the atomic spacing between the conductor layer and the constraining layer is small and the misfit strain between the two is small. .
導体層としての金属薄膜の生成方位は(111)面や(100)面が望ましいが、生成方位を(111)面や(100)面として規定している理由を以下に示す。金属薄膜の表面方位が(111)面の場合には、膜の垂直方向が最も原子間距離の離れた方向となるため、膜に平行な方向がイオン核からのシールド効果が大きく、散乱を起こしがたく、電気をもっとも伝達しやすいためである。一方、(100)面の場合には、膜厚方向における原子振動モードが、膜厚に垂直となる成分が大きいため、化合物薄膜によるフォノンの抑制効果が大きくなり、導電方向となる膜厚方向に対する散乱の影響を小さくすることができるためである。更に、本発明においては、導体層を拘束層上に、所定方位の単結晶として積層するので、結晶粒界によるフォノン散乱の影響を受けにくく、さらに自由電子の粒界による直接的な散乱も受けないので、この点でも有利である。 The generation direction of the metal thin film as the conductor layer is preferably the (111) plane or the (100) plane. The reason why the generation direction is defined as the (111) plane or the (100) plane is described below. When the surface orientation of the metal thin film is the (111) plane, the vertical direction of the film is the direction with the most interatomic distance, so the direction parallel to the film has a great shielding effect from ion nuclei and causes scattering. This is because it is easy to transmit electricity most easily. On the other hand, in the case of the (100) plane, the atomic vibration mode in the film thickness direction has a large component that is perpendicular to the film thickness. This is because the influence of scattering can be reduced. Furthermore, in the present invention, the conductor layer is laminated on the constraining layer as a single crystal of a predetermined orientation, so that it is not easily affected by phonon scattering due to crystal grain boundaries, and is also subject to direct scattering due to free electron grain boundaries. This is also advantageous in this respect.
拘束層としての化合物層は導体層としての金属層と同じ元素を必ずしも含まなくても良いが、導体層としての金属層と同じ元素を含む場合の方が、化合物層上に均一的に金属層が生成しやすくなるため好ましい。化合物層と導体層としての金属層が同じ元素を含む場合には、その原子位置を核として金属層が生成するため、薄膜がアイランド状にならずに形成されにくいため、欠陥の少ない、フォノン非弾性散乱の少ない回路を形成することができる。 The compound layer as the constraining layer does not necessarily include the same element as the metal layer as the conductor layer. However, when the compound layer includes the same element as the metal layer as the conductor layer, the metal layer is uniformly formed on the compound layer. Is preferable because it is easy to generate. When the compound layer and the metal layer as the conductor layer contain the same element, the metal layer is generated with the atomic position as the nucleus, so the thin film is not formed in an island shape and is difficult to form. A circuit with less elastic scattering can be formed.
図1は、面心構造を有する化合物層の結晶構造の原子配列を示す具体例である。拘束層としての化合物層の結晶構造としては、面心構造を有する結晶構造であるものが望ましく、面心構造の代表例としては、L12、L11、L10などの構造があり、これらを順に、図1(a)、図1(b)、図1(c)に示す。
図1(a)は、L12構造を有するCu3Pd化合物、CuAu化合物等の場合である。例えば、導体層がCuの場合は、Cu3Pd化合物が望ましく、導体層がAlの場合はAl3Zr化合物が望ましい。この場合、Cu3Pd化合物の格子定数は0.3676nmで、これと積層するCu導体層の格子定数は0.3615nmである。又、Al3Zr化合物の格子定数は0.4093nmで、Al導体層の格子定数は0.405nmである。L10構造の代表例としては、CuAu、CuPtがあり、その格子定数は、0.3972nm、0.3777nmであり、Cu導体層に近い値を示す。さらに、面心構造を有するL11構造の化合物も適宜用いることができるが、この場合にも、導体層と化合物層の格子定数との関係から、ミスフィットひずみの大きさと導体層と拘束層の結合状態の安定性を考慮して候補を選定することになる。
FIG. 1 is a specific example showing an atomic arrangement of a crystal structure of a compound layer having a face-centered structure. The crystal structure of the compound layer as the constraining layer is preferably a crystal structure having a face-centered structure. Typical examples of the face-centered structure include structures such as L1 2 , L1 1 , L1 0, and the like. In order, FIG. 1 (a), FIG. 1 (b), and FIG. 1 (c) show.
1 (a) is, Cu 3 Pd compound having an L1 2 structure, a case of a CuAu compound. For example, when the conductor layer is Cu, a Cu 3 Pd compound is desirable, and when the conductor layer is Al, an Al 3 Zr compound is desirable. In this case, the lattice constant of the Cu 3 Pd compound is 0.3676 nm, and the lattice constant of the Cu conductor layer laminated thereon is 0.3615 nm. The lattice constant of the Al 3 Zr compound is 0.4093 nm, and the lattice constant of the Al conductor layer is 0.405 nm. Representative examples of L1 0 structure, CuAu, there is CuPt, its lattice constant, 0.3972nm, a 0.3777Nm, shows a value close to Cu conductor layer. Furthermore, it can be used suitably also compounds of L1 1 structure having a face-centered structure, also in this case, from the relationship between the lattice constant of the conductive layer and the compound layer, misfit strain measurement and the conductor layer and the constraining layer The candidate is selected in consideration of the stability of the combined state.
表1には、前記化合物層の他、その他の例も含めた拘束層の結晶構造とそれと組合せる導体層のミスフィットひずみの関係を示す。表1に示したミスフィットひずみの組合せは拘束層としての役割を果たす候補となることが期待される。これらの拘束層を導体層と組合せて薄膜積層体に適用するためには、拘束層の結合状態が導体層の結合状態より安定である必要がある。例えば、Cuを導体層として、CuAuを拘束層とした場合に、格子定数0.38nmにおいて原子間ポテンシャルを求めると、Cu同士を0.0mRyとして、CuとAuとの間の原子間ポテンシャルは−32.5mRyと低い値を示すことから、CuとAuとの間の原子間の結合状態は、Cu同士の場合より安定な状態にある。
導体層をCuとした場合、その他のCu3Pd,CuPt,PtV3等の化合物やAu、Pt,Ru,W,Zrの単一元素化合物の結合状態はCu同士の場合より安定であることも簡便な計算により確認できる。
Table 1 shows the relationship between the crystal structure of the constraining layer including other examples in addition to the compound layer and the misfit strain of the conductor layer combined therewith. The combination of misfit strains shown in Table 1 is expected to be a candidate for serving as a constraining layer. In order to apply these constraining layers to a thin film laminate in combination with a conductor layer, the constrained layer needs to be more stable than the conductor layer. For example, when Cu is used as a conductor layer and CuAu is used as a constrained layer, when the interatomic potential is obtained at a lattice constant of 0.38 nm, the interatomic potential between Cu and Au is −m with 0.0mRy between Cu. Since it shows a low value of 32.5 mRy, the bonding state between atoms between Cu and Au is in a more stable state than that between Cu.
When the conductor layer is made of Cu, the bonding state of other compounds such as Cu 3 Pd, CuPt, PtV 3 and single element compounds of Au, Pt, Ru, W, Zr may be more stable than the case of Cu. It can be confirmed by simple calculation.
本発明は、基板上に拘束層と導体層を積層した積層回路材料及びそれを用いた薄膜積層材の電気抵抗低下方法に関する発明で後述する実施例はSi基板を用いて構成したが、発明に使用する基板としては、積層回路材料の用途に応じて、Si基板の他、酸化物基板や樹脂基板や化合物半導体などを基板とすることができる。
The present invention relates to a laminated circuit material obtained by laminating a constraining layer and a conductor layer on a substrate, and an invention relating to a method for reducing the electrical resistance of a thin film laminated material using the same. As a substrate to be used, an oxide substrate, a resin substrate, a compound semiconductor, or the like can be used as the substrate in addition to the Si substrate, depending on the use of the laminated circuit material.
(実施例1)
分子線エピタキシ法により、表2に示す導体層と拘束層の組合せで表面方位(100)のSi単結晶基板上に拘束層としてCu3Pt化合物を3原子層生成し、その上に導体層としてCuを2原子層、3原子層、4原子層及び10原子層分生成した。これらのCu層の表面方位は(100)である。これらのCu層の上に、更にCu3Pd化合物を3原子層分生成させて幅0.1mm、長さ3mmの薄膜積層材である本発明例のNo.1〜3、比較例のNo.20を作製した。図2は、本実施例において作成した本発明例のNo.1、No.2の薄膜積層材の内、導体層としてCuを2原子層、3原子層積層した場合を示す。
Example 1
By molecular beam epitaxy, a Cu 3 Pt compound as a constrained layer is formed on a Si single crystal substrate having a surface orientation (100) with a combination of the conductor layer and constrained layer shown in Table 2, and a conductor layer is formed thereon. Cu was produced for two atomic layers, three atomic layers, four atomic layers, and ten atomic layers. The surface orientation of these Cu layers is (100). On these Cu layers, a Cu 3 Pd compound corresponding to three atomic layers was further formed to form a thin film laminate having a width of 0.1 mm and a length of 3 mm. 1-3, No. of the comparative example. 20 was produced. FIG. 2 shows the No. of the present invention example created in this example. 1, no. Of the two thin film laminates, the case where Cu is laminated in two atomic layers and three atomic layers as a conductor layer is shown.
又、同様の原子層形成条件により、拘束層―導体層―拘束層の積層構造で、導体層としてのCu原子層の層数を3層とし、拘束層のCu3Pt化合物層を10原子層形成した比較例No.21の薄膜積層材を作製した。他の比較例として、Si単結晶基板に拘束層を介さず直接Cu原子層を1原子層(比較例No.22)、3原子層(比較例No.23)及び10原子層(比較例No.24)形成した薄膜積層材を作製した。なお、原子層の層数は、その原子層状態をSPM(走査触針型顕微鏡)並びに透過型電子顕微鏡で観察して求めた。
これらの薄膜積層材を用い、室温並びに77Kで、直流電気抵抗値を直流4端子法により測定した。直流電気抵抗値は室温、77Kでの導体層断面積当りの比抵抗値ρc(μΩcm)、薄膜断面積当りの比抵抗値ρtf(μΩcm)として求めた。その結果を表2に記す。
Also, under the same atomic layer formation conditions, the layered structure of constrained layer-conductor layer-constraint layer, the number of Cu atomic layers as a conductor layer is three, and the Cu 3 Pt compound layer of constrained layer is 10 atomic layers The formed Comparative Example No. 21 thin film laminates were produced. As another comparative example, a Cu atomic layer is directly formed on a Si single crystal substrate without a constraining layer as a 1 atomic layer (Comparative Example No. 22), 3 atomic layer (Comparative Example No. 23), and 10 atomic layer (Comparative Example No.). .24) A thin film laminate was formed. The number of atomic layers was determined by observing the atomic layer state with an SPM (scanning stylus microscope) and a transmission electron microscope.
Using these thin film laminated materials, the DC electric resistance value was measured by the DC four-terminal method at room temperature and 77K. The DC electric resistance value was determined as a specific resistance value ρ c (μΩcm) per conductor layer cross-sectional area at 77 K at room temperature and a specific resistance value ρ tf (μΩcm) per thin film cross-sectional area. The results are shown in Table 2.
表2から、本発明例のNo.1〜No.3示す薄膜積層材では、室温の比抵抗値は4原子層までは導体層の原子層数が増加するにつれて、薄膜積層材内の導体層の断面積が増大するために、その比抵抗値は減少する。しかし、連続する導体層の層数が10原子層になると、拘束層によるフォノン振動抑制効果が働かなくなり、逆に非常に高い比抵抗値となることが判る。また、比較例No.21の薄膜積層材を用いた拘束層の厚さが10原子層と厚い場合も、拘束層のフォノン振動抑制効果が働くために導体層の比抵抗値は他の場合と同様に低い値を示すものの、拘束層の厚さが厚いために、比抵抗の高い拘束層も含めた薄膜全体の比抵抗値としては高い値となる。また、拘束層がなく、導体層をSi基板上に直接積層した比較例No,22〜No.24の場合は、フォノン振動を抑制することができないために、室温における比抵抗は、導体層及び薄膜全体ともに高くなった。これに対し、77Kの低温では、表2に示す発明例、比較例のいずれの材料も、低い値を示す。 From Table 2, No. of the present invention example. 1-No. In the thin film laminate shown in FIG. 3, the specific resistance value at room temperature is up to 4 atomic layers, and as the number of conductor layers increases, the cross-sectional area of the conductor layer in the thin film laminate increases. Decrease. However, it can be seen that when the number of continuous conductor layers is 10 atomic layers, the phonon vibration suppressing effect by the constraining layer does not work, and on the contrary, the resistivity value is very high. Comparative Example No. Even when the thickness of the constraining layer using the thin film laminated material of 21 is as thick as 10 atomic layers, the specific resistance value of the conductor layer shows a low value as in the other cases because of the effect of suppressing the phonon vibration of the constraining layer. However, since the thickness of the constraining layer is large, the specific resistance value of the entire thin film including the constraining layer having a high specific resistance is a high value. Further, Comparative Examples No. 22 to No. 22 in which no constraining layer was provided and the conductor layer was directly laminated on the Si substrate. In the case of 24, since the phonon vibration could not be suppressed, the specific resistance at room temperature was high for both the conductor layer and the entire thin film. On the other hand, at the low temperature of 77K, the materials of the invention examples and comparative examples shown in Table 2 show low values.
(実施例2)
次に、拘束層に用いる化合物層の相違による比抵抗値の違いを求めた。実施例1と同様の方法で、表面方位(100)の別々のSi単結晶基板上にCuPt、CuAu、Cu3Pdの3種類の化合物層を3原子層形成し、さらに各々のSi基板上に形成した化合物層の上にCu層を3原子層生成した、その上にSi基板上に形成した化合物層と同じ化合物層を3原子層分生成し、寸法幅0.1mm×長さ3mmの本発明例No.4〜No.6の薄膜積層材を作製した。図3は、実施例2で作製した化合物層にCuPt層を使用した本発明例No.5の薄膜積層材を示す。
作製した薄膜積層材の直流抵抗値を実施例1と同様の方法で測定し、薄膜積層材断面積当り及び導体層断面積当りの比抵抗値に換算して求めた。その結果を表3に示す。なお、表3の本発明例No.4のCu3Pdを拘束層とした試料、並びに比較例No.25の拘束層がない試料は、それぞれ先の実施例1で求めた表2の本発明例No.2、比較例No.23のデータを引用した。
(Example 2)
Next, the difference of specific resistance value by the difference of the compound layer used for a constrained layer was calculated | required. In the same manner as in Example 1, three atomic layers of three types of CuPt, CuAu, and Cu 3 Pd were formed on separate Si single crystal substrates having a surface orientation (100), and further each Si substrate was formed on each Si substrate. Three atomic layers of Cu layer were formed on the formed compound layer, and three atomic layers of the same compound layer as the compound layer formed on the Si substrate were formed thereon, and a book having a dimension width of 0.1 mm × length of 3 mm. Invention Example No. 4-No. 6 thin film laminates were produced. 3 shows an example No. 1 of the present invention in which a CuPt layer was used for the compound layer produced in Example 2. 5 shows a thin film laminated material.
The direct-current resistance value of the produced thin film laminate was measured by the same method as in Example 1 and obtained by converting into specific resistance values per cross-sectional area of the thin-film laminate and conductor cross-sectional area. The results are shown in Table 3. It should be noted that Example No. No. 4 Cu 3 Pd as a constrained layer, and Comparative Example No. Samples having no constraining layer of 25 are the inventive example Nos. In Table 2 obtained in Example 1 above. 2, Comparative Example No. 23 data were cited.
導体層と拘束層のミスフィットひずみが小さい本発明例No.4のCu3Pd化合物(ミスフィットひずみ 1.66%)及び本発明例のNo.5のCuPt化合物(ミスフィットひずみ 4.29%)は、室温での導体層断面積当たりの比抵抗値、室温における薄膜断面積当りの比抵抗ともに、拘束層をCuAuで構成した本発明例No.6のミスフィットひずみが9.0%の場合より、小さい値を示す。
この理由は、本発明例No.6に示す導体層と拘束層のミスフィットひずみが9.0%と大きい拘束層をCuAu層で構成した場合、界面に転位が導入されるために拘束層をCu3Pdで構成した本発明例No.4や拘束層をCuPtで構成した本発明例No.5のミスフィットひずみが小さく界面転位が存在しない場合に比べて、界面転位による自由電子の散乱が誘発された結果少し高めの比抵抗値を示す。比較例のNo.25は拘束層が存在しないため、自由電子によるフォノン散乱の抑制効果が存在しないために、比抵抗値は最も悪い結果となった。
Example No. of the present invention having a small misfit strain between the conductor layer and the constraining layer. No. 4 Cu 3 Pd compound (misfit strain 1.66%) No. 5 CuPt compound (misfit strain 4.29%) is the invention example No. in which the constraining layer is made of CuAu in both the specific resistance value per conductor cross-sectional area at room temperature and the specific resistance per thin film cross-sectional area at room temperature. . 6 shows a smaller value than the case where the misfit strain of 6 is 9.0%.
The reason for this is that Example No. of the present invention. When the constrained layer having a large misfit strain of 9.0% of the conductor layer and the constrained layer shown in Fig. 6 is composed of a CuAu layer, the constrained layer is composed of Cu 3 Pd because dislocation is introduced into the interface. No. 4 and Inventive Example No. 1 in which the constraining layer is made of CuPt. Compared with the case where the misfit strain of 5 is small and no interfacial dislocation exists, the result of the scattering of free electrons by interfacial dislocation shows a slightly higher specific resistance value. Comparative Example No. Since no constraining layer is present in No. 25, the effect of suppressing phonon scattering by free electrons does not exist, and thus the specific resistance value is the worst.
又、ミスフィットひずみは、導体層の原子間距離が広がる方向のプラス側が、マイナス側に比べて、電子の平均自由行程が大きくなり、フォノン散乱が減少するためにどちらかといえばプラス側が望ましい。
Further, the misfit strain is preferably positive on the plus side in the direction in which the interatomic distance of the conductor layer increases, because the mean free path of electrons is larger than that on the minus side, and phonon scattering is reduced.
又、ミスフィット歪は、導体層の原子間距離が広がる方向のプラス側が、マイナス側に比べて、電子の平均自由行程が大きくなり、フォノン散乱が減少するためにどちらかといえばプラス側が望ましい。 The misfit strain is preferably positive because the mean free path of electrons is larger on the plus side in the direction in which the interatomic distance of the conductor layer increases than on the minus side, and phonon scattering is reduced.
(実施例3)
実施例1、実施例2では、表面方位が(100)面の結果を示したが、ここでは表面方位が(111)面である導体層をSi基板上に形成した薄膜の電気抵抗の測定結果を示す。導体層の表面方位が(111)面となるように、Si単結晶基板の方位が(111)面のものを用意し、その上に拘束層―導電層―拘束層の順に膜形成を行った。
具体的には、実施例1と同様な方法で、表面方位(111)のSi単結晶基板上に3原子層からなるPtV3化合物層を3原子層生成し、その上にCuを3原子層分生成させたところ、Cu層の表面方位は(111)となった。その上に更にPtV3化合物を3原子層生成させ、幅0.1mm、長さ3mmの本発明例No.7の薄膜積層材を作製した。
図4には、このPtV3化合物層によりCu層を挟んで積層した場合の薄膜積層材を示す。
作製した薄膜積層材の直流抵抗値を実施例1と同様の方法で測定し、薄膜積層材断面積当り及び導体層断面積当りの比抵抗値を求めた。その結果を表4に記す。
(Example 3)
In Example 1 and Example 2, the result of the surface orientation of the (100) plane was shown. Here, the measurement result of the electric resistance of the thin film in which the conductor layer having the surface orientation of the (111) plane is formed on the Si substrate. Indicates. A Si single crystal substrate with a (111) plane orientation was prepared so that the surface orientation of the conductor layer was the (111) plane, and a film was formed in the order of constraining layer-conductive layer-constraining layer thereon. .
Specifically, in the same manner as in Example 1, three atomic layers of a PtV 3 compound layer composed of three atomic layers are formed on a Si single crystal substrate having a surface orientation (111), and Cu is formed on the three atomic layers. As a result, the surface orientation of the Cu layer was (111). Further, three atomic layers of a PtV 3 compound were formed thereon, and the present invention No. 1 having a width of 0.1 mm and a length of 3 mm was used. 7 thin film laminates were produced.
FIG. 4 shows a thin film laminated material in the case where the PtV 3 compound layer is laminated with a Cu layer interposed therebetween.
The direct current resistance value of the produced thin film laminate was measured in the same manner as in Example 1, and the specific resistance value per thin film laminate cross section and conductor layer cross section was determined. The results are shown in Table 4.
表4の本発明例No.7に示す表面方位(111)のPtV3化合物層を拘束層として用いた場合の比抵抗値は、表2の本発明例No.1に示す拘束層に表面方位(100)方位のCu3Pd層を化合物層として用いた場合や表2の本発明例No.2に示す表面方位(100)方位のCuPt層を化合物層として用いた場合を表3のNo.5の薄膜積層材を用いた場合に比較すると、室温、77Kの場合ともにこれらと同様の低い比抵抗値が得られる。このことから、表4の本発明例No.7に示す拘束層として、表面方位(111)のPtV3化合物層を拘束層に用いた場合も、拘束層によるフォノン抑制効果が認められる。表4の本発明例No.7の拘束層と導体層のミスフィットひずみは、約7.0%である。
Inventive Example No. The specific resistance value when the PtV3 compound layer having the surface orientation (111) shown in FIG. When a Cu3Pd layer having a surface orientation (100) orientation is used as the compound layer for the constraining layer shown in FIG. No. 2 in Table 3 shows a case where a CuPt layer having a surface orientation (100) orientation shown in FIG. As compared with the case of using the thin film laminate material No. 5, the same specific resistance values as those at room temperature and 77K can be obtained. From this, the present invention example No. When a PtV3 compound layer having a surface orientation (111) is used for the constraining layer as the constraining layer shown in FIG. Inventive Example No. The misfit strain of the constraining
このNo.7の結果と表3に記載した本発明例No.4、No.5、No.6の結果を総合すると、ミスフィットひずみの大きさは、実用レベルとしてはぎりぎり9.0%程度までは許容されるものと考えられる。また、より望ましい範囲としては、7.0%、さらに望ましい範囲としては4.3%と考えられる。 This No. 7 and the invention example No. described in Table 3 . 4, no. 5, no. When the results of 6 are combined, it is considered that the magnitude of misfit strain is allowed up to about 9.0% as a practical level. A more desirable range is 7.0%, and a further desirable range is 4.3%.
に記載した本発明例No.4、No.5、No.6の結果を総合すると、ミスフィット歪みの大きさは、実用レベルとしてはぎりぎり9.0%程度までは許容されるものと考えられる。また、より望ましい範囲としては、7.0%、さらに望ましい範囲としては4.3%と考えられる。 Invention Example No. described in 4, no. 5, no. When the results of 6 are combined, it is considered that the magnitude of misfit distortion is allowed up to about 9.0% as a practical level. A more desirable range is 7.0%, and a further desirable range is 4.3%.
(実施例4)
Si基板上に形成する拘束層と導体層の組合せにおいて、導体層にCu以外の元素を用いた場合の結果を示す。尚、ここでは、拘束層と導体層はともに構成元素に共通する元素(同一元素)を含むが、必ずしも両層の構成元素に共通する元素を含む必要はない。ただし、拘束層と導体層が共通元素を含む場合は、導体層の電子軌道が安定するメリットがあるため、ここでは、拘束層と導体層に共通する元素を含む場合を示す。
実施例1と同様の方法で表面方位(100)のSi単結晶基板上に、拘束層としてAg3In、Al3Zr、AuV3の3種類の化合物層を3原子層生成し、その上にそれぞれAg、Al、Auからなる導体層を3原子層分生成し、その上に更に、先の拘束層と同じ化合物層を拘束層として3原子層分生成して幅0.1mm、長さ3mmの本発明例No.8〜No.10の薄膜積層材を作製した。比較例として拘束層を設けず導体層のみを3原子層設けた薄膜積層材を比較例No.26〜No.28として作製した。
作製した薄膜積層材の直流抵抗値を実施例1と同様の方法で測定し、薄膜積層材断面積当り及び導体層断面積当りの比抵抗値を求めた。その結果を表5に示す。
Example 4
The result in the case of using elements other than Cu for a conductor layer in the combination of the constrained layer formed on a Si substrate and a conductor layer is shown. Here, both the constraining layer and the conductor layer contain an element common to the constituent elements (the same element), but it is not always necessary to contain an element common to the constituent elements of both layers. However, when the constraining layer and the conductor layer contain a common element, there is a merit that the electron trajectory of the conductor layer is stabilized. Therefore, here, a case where an element common to the constraining layer and the conductor layer is included is shown.
Three atomic layers of three types of compound layers of Ag 3 In, Al 3 Zr, and AuV 3 are formed as a constraining layer on a Si single crystal substrate having a surface orientation (100) in the same manner as in Example 1, and on that, A conductor layer made of Ag, Al, and Au is generated for three atomic layers, and further, the same compound layer as the previous constraining layer is used as a constraining layer to generate three atomic layers, and the width is 0.1 mm and the length is 3 mm. Inventive Example No. 8-No. Ten thin film laminates were produced. As a comparative example, a thin film laminate in which only three conductor layers are provided without a constraining layer is used as a comparative example. 26-No. 28 was produced.
The direct current resistance value of the produced thin film laminate was measured in the same manner as in Example 1, and the specific resistance value per thin film laminate cross section and conductor layer cross section was determined. The results are shown in Table 5.
表5の本発明例No.8〜No.10に示すように導体層がCu以外の元素の場合、拘束層Ag3Inと導体層Ag、拘束層Al3Zrと導体層Al、拘束層AuV3と導体層Auのいずれにおいても、拘束層と導体層を拘束層―導体層―拘束層の積層構造とした場合、室温での比抵抗値は、導体層断面積当たりの比抵抗値ρc、薄膜断面積当たり比抵抗値ρtfともに低い値を示す。これに対し、拘束層を設けず導体層のみの拘束層と導体層の積層構造としない比較例No.26〜No,28では、フォノン散乱の抑制効果が認められないために、比抵抗値が高くなっている。このことから、フォノン散乱の抑制効果は、導体層の種類によらず、導体層のフォノン散乱を拘束層で抑制することができれば良いことが判る。 Inventive Example No. 8-No. As shown in FIG. 10, when the conductor layer is an element other than Cu, the constraining layer Ag 3 In and the conductor layer Ag, the constraining layer Al 3 Zr and the conductor layer Al, and the constraining layer AuV 3 and the conductor layer Au And the conductor layer have a laminated structure of constrained layer-conductor layer-constraint layer, the specific resistance value at room temperature is low for both the specific resistance value ρ c per conductor layer cross-sectional area and the specific resistance value ρ tf per thin film cross-sectional area. Indicates the value. On the other hand, Comparative Example No. in which no constraining layer is provided and a constraining layer consisting only of a conductor layer and a laminated structure of conductor layers is not used. In No. 26 to No. 28, since the effect of suppressing phonon scattering is not recognized, the specific resistance value is high. From this, it can be seen that the effect of suppressing phonon scattering is not limited to the type of the conductor layer, and it is sufficient that the phonon scattering of the conductor layer can be suppressed by the constraining layer.
(実施例5)
実施例5は、Si基板上に、拘束層と導体層の積層構造を複数回積層した場合の例を示す。表面方位(100)のSi単結晶基板上にPt層を拘束層として単原子層成長させた後に、導体層であるCu層を単原子積層して、更に拘束層のPt層と導体層のCu層を交互に各5層形成した後に、その上に拘束層のPt層を1原子層分形成して、Pt層6層、Cu層5層からなる幅0.1mm、長さ3mmの本発明例No.11の薄膜積層材を作製した。
作製した薄膜積層材の直流抵抗値を実施例1と同様の方法で測定し、薄膜積層材断面積当り及び導体層断面積当りの比抵抗値を求めた。その結果を表6に示す。
(Example 5)
Example 5 shows an example in which a laminated structure of a constraining layer and a conductor layer is laminated a plurality of times on a Si substrate. After growing a monoatomic layer using a Pt layer as a constrained layer on a Si single crystal substrate with a surface orientation (100), a Cu layer as a conductor layer is monoatomically stacked, and a Pt layer as a constrained layer and a Cu layer as a conductor layer are further stacked. After five layers are alternately formed, a Pt layer as a constraining layer is formed on one atomic layer thereon, and the present invention has a width of 0.1 mm and a length of 3 mm comprising six Pt layers and five Cu layers. Example No. 11 thin film laminates were produced.
The direct current resistance value of the produced thin film laminate was measured in the same manner as in Example 1, and the specific resistance value per thin film laminate cross section and conductor layer cross section was determined. The results are shown in Table 6.
表6の本発明例No.11の場合、拘束層が化合物層の場合より、拘束層自身のフォノン散乱抑制効果は少ないが、導体層の層数が5層と多いことと、拘束層であるPt層も導電性があるために比抵抗値が非常に小さい値を示す。このように、拘束層と導体層を複数回繰り返して積層した構成とすることによっても、良好な積層回路材料が得られる。 Inventive Example No. In the case of 11, the phonon scattering suppression effect of the constraining layer itself is less than that of the constraining layer as a compound layer, but the conductor layer has a large number of five layers and the Pt layer as the constraining layer is also conductive. Shows a very small specific resistance value. Thus, a favorable laminated circuit material can also be obtained by adopting a configuration in which the constraining layer and the conductor layer are repeatedly laminated a plurality of times.
本発明では、本発明の拘束層と導体層を積層する基板としては、Si単結晶を用いたが、基板として、拘束層と導体層が格子整合性を保って積層できれば良く、それを阻害しない限り、任意の基板を用いることができる。また、基板として、拘束層と導体層が格子整合性を保って積層するための手段として、Si単結晶等を数原子層分子線エキタピシー法等により基板上に設ければ、積層回路材料の用途に応じて、Si基板の他、酸化物基板や樹脂基板や化合物半導体などを基板として使用することができる。半導体基板などに応用した高周波高速応答性に優れたデバイス等が得られる。 In the present invention, a Si single crystal is used as the substrate on which the constraining layer and the conductor layer of the present invention are laminated. However, as the substrate, it is sufficient if the constraining layer and the conductor layer can be laminated while maintaining lattice matching. As long as an arbitrary substrate can be used. In addition, as a means for laminating a constraining layer and a conductor layer while maintaining lattice matching as a substrate, if a Si single crystal or the like is provided on the substrate by a several atomic layer molecular beam epitaxy method or the like, the use of the laminated circuit material Accordingly, an oxide substrate, a resin substrate, a compound semiconductor, or the like can be used as the substrate in addition to the Si substrate. Devices with excellent high-frequency and high-speed response applied to semiconductor substrates and the like can be obtained.
1 Si基板
2 絶縁膜
3 金属薄膜線路
4 金属薄膜接地層
5 ベースメタル層
6 Cu配線層
7 Cu拡散防止絶縁層
DESCRIPTION OF
Claims (8)
前記拘束層の最隣接原子間隔dmと前記導体層の最隣接原子間隔dcが以下の関係式(1)を満たすことを特徴とする積層回路材料。
{(dm−αdc)2/(dm)2}1/2 ≦0.09 (1)
ここで、αは、1、2、3のいずれかの値である。
A single or multiple conductor layer comprising a single atomic layer composed of a single element or less than 10 atomic layers and a bond more stable than an interatomic bond between elements constituting the conductive layer A laminated structure comprising a constrained layer comprising a single layer or multiple layers of less than 10 atomic layers and a substrate, a constrained layer formed on the substrate, and a conductor layer and constrained layer formed thereon Further, in the laminated structure in which the atoms of the conductor layer and the constraining layer are laminated in an atomically aligned state, the misfit strain at the interface between the conductor layer and the constraining layer is 9.0% or less. A laminated circuit material in which a conductor layer and the constraining layer are laminated on a substrate ,
Product layer circuit materials you characterized in that nearest neighbor atomic distance d c nearest neighbor atomic distance d m between the conductor layer satisfies the relation (1) below the constraining layer.
{(D m -αd c) 2 / (d m) 2} 1/2 ≦ 0.09 (1)
Here, α is any one of 1, 2, and 3.
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