JP5317851B2 - Frequency sweep circuit - Google Patents

Description

The present invention is a frequency sweep circumventive path, is adopted, such as a radar and various sensors FM-CW method in which a particular distance measurement, to a frequency sweep circumventive path performing frequency sweep at a high speed.

  Conventionally, FM-CW (Frequency-Modulated Continuous Wave) radars and various sensors have been widely used in distance measurement, etc., and these radars and sensors are used to form transmission waves and detect received waves. A frequency sweep circuit for sweeping a predetermined range of frequencies is used.

  For example, in FM-CW radar, a certain degree of accuracy is required in FM modulation (frequency modulation) as an important parameter in distance measurement. The accuracy of FM modulation greatly affects distance measurement accuracy and In order to eliminate the transmission of a frequency deviating from the band specified by the law and maintain the high stability of the transmission wave, high accuracy is required.

  That is, the accuracy of the distance is determined by the size of the occupied frequency bandwidth, and when detecting a close distance or the like, a swing width close to a maximum of 76 MHz of the occupied frequency width defined in the Radio Law is required. The output frequency of the detected phase detection signal is determined by the sweep time. Furthermore, it is not allowed to output a signal that protrudes within the radio frequency band 200 MHz.

  Conventionally, as a frequency sweep method for achieving high frequency stability, there are a method using a phase-locked oscillation loop (hereinafter referred to as PLL), a method using a digital / analog converter to obtain a frequency amplitude setting signal, and the like. It is known.

  FIG. 7 shows a basic PLL sweep circuit, which includes a voltage controlled oscillator (VCO) 1, a divider 2, a frequency multiplier (x8) 3, an amplifier 4, and a frequency divider. A programmable counter 6 having (1 / N) 5, a CPU 7, a reference signal source (TCXO) 8, a phase frequency detector (PFD) 9 and a loop filter 10, and the output of the PFD 9 is sent to the VCO 1 through the loop filter 10. Configured to return.

In such a PLL sweep circuit, the output frequency F _VCO of the _{VCO 1 is set} to a frequency in the 3 GHz band that is most easily handled from the performance of the programmable counter 6, and a part of the output of the VCO 1 is supplied to the program counter 6. 6 gives the frequency F _{VCO / N} of the control signal to the PFD 9. In this PFD 9, when the reference frequency Fref is input from the reference signal source 8, frequency division to this frequency Fref is performed, and a feedback loop that returns the output of the PFD 9 via the loop filter 10 and the VCO1 operates. Stabilized at phase-synchronized frequency. When frequency sweeping is performed, a predetermined range of sweep frequencies can be obtained by continuously changing the setting of the output control signal (data) of the programmable counter 6.

JP-A-2005-150856

  However, in the conventional PLL sweep circuit, the frequency stability is extremely excellent, but the high-speed sweep cannot be performed due to the restriction of the response time of the PLL, and the frequency sweep waveform has a stepped shape, so that the repetition is not necessary originally. There was a problem that frequency (period) and measurement wave could not be separated.

  FIG. 8 shows frequency changes during sweeping, where Tfset is a counter change time, Δt is a PLL lock time, and Δf is a PLL frequency change width at one control point. As shown in FIG. 8, in the conventional PLL sweep, there is a lock time Δt longer than a certain time in the loop band until the phase is synchronized with the frequency set by the PLL, and the frequency changes stepwise. Therefore, there is a repetition frequency (repetition component) based on a periodic function of the counter change time Tfset (for example, 20 μs to 10 μs), and this repetition frequency appears in the output signal of the PFD 9. As a result, this repetitive frequency signal becomes a pseudo ranging signal and hinders ranging.

  For example, when the frequency point of the PLL in frequency sweep is switched at intervals of 10 μs (= Tfset), the repetition frequency becomes 100 kHz, which becomes spurious and is output from the PFD 9, and is based on this frequency sweep. When the signal is used for a phase detector such as a radar, spurious signals present in the carrier appear at the output of the PFD 9.

  In addition, oversampling (a technique for reducing noise components during analog-to-digital conversion and averaging signals obtained from multiple points by finely shifting sampling points), which is considered to be the most difficult in PLL sweep, is not possible. There is also.

On the other hand, there is a method using the above-mentioned digital / analog converter as a method for preventing the generation of a stepped waveform which is a problem in the PLL sweep.
FIG. 9 shows a frequency sweep circuit using this digital / analog converter. This circuit includes a VCO 1, a frequency multiplier 3 and an amplifier 4, and a digital / analog converter (DAC) based on the CPU 11. The electronic tuning voltage (control signal) output from 12 is applied to the VCO 1.

  According to such a frequency sweep circuit, a control signal having a voltage calibrated in advance equal to a predetermined frequency slope is output from the CPU 11, and a frequency sweep wave is generated by changing the electronic tuning voltage applied from the DAC 12 to the VCO 1. The In this case, unlike the PLL sweep, a loop is not used, so that the electronic tuning voltage applied to the VCO 1 can be changed at a high speed, so that a high-speed frequency change is possible and a digital switching period signal is easily obtained. There is an advantage that it can be removed by a filter.

  However, on the other hand, since frequency control depends on the electronic tuning voltage generated from the DAC 12, the frequency control is difficult, and the change in frequency with respect to the electronic tuning voltage of the VCO 1 may be different under environmental conditions such as temperature. There is an inconvenience. In addition, the circuit configuration is complicated and large, and there is a problem in terms of cost.

The present invention has been made in view of the above problems, and its purpose is to enable high-speed sweep without generating a repetitive frequency signal with a stepped waveform, and to be influenced by environmental conditions such as temperature. no is to provide a frequency sweep circumventive path can perform frequency control stably.

To achieve the above object, the invention of claim 1, the voltage controlled oscillator, a phase locked oscillation loop having a programmable counter and the phase detector with the frequency divider, the frequency sweep circuit that performs frequency sweeping, the sweep A frequency setting control signal is generated, and the frequency pull-in operation is performed by the current frequency point control signal within the frequency pull-in time, and the next frequency point control signal is transferred to the phase via the programmable counter. It is placed between the control circuit that outputs to the detector and performs continuous frequency sweep without passing through the phase-synchronized state, and the phase detector and the voltage-controlled oscillator, and controls the slope of the frequency change during the sweep. An inclination control filter is provided .

According to the configuration of the present invention, in the control signal of a plurality of continuous frequency points for performing frequency sweep, the frequency of the next point is within the frequency acquisition time during which the frequency acquisition operation is performed by the control signal of the current point. By controlling to output the control signal, the frequency pull-in operation at the next point is performed before the current frequency point becomes phase-synchronized, and continuous frequency sweep is performed without the phase-synchronized part. Is done.
Further, by adjusting the cut-off frequency of the control filter-out inclination, it is possible to vary the inclination characteristic of the sweep is the change in frequency per unit time.

  According to the present invention, since there is no phase synchronization portion, a high-speed sweep is possible without generating a repetitive frequency signal with a stepped waveform. In addition, since a feedback loop circuit including a phase detector is used, stable frequency control can be performed compared to a circuit using a digital / analog converter, and the sweep frequency may be influenced by environmental conditions such as temperature. There is no effect. Further, unlike a circuit using a digital / analog converter, the circuit configuration is not complicated and large-scale, and the cost is not increased.

It is a block diagram which shows the structure of the frequency sweep circuit which concerns on the Example of this invention. It is explanatory drawing which shows operation | movement of the phase frequency detector of an Example. It is a graph which shows the switching point and frequency transition of the frequency point control signal in the frequency sweep circuit of an Example. It is a graph which shows the transition point and frequency transition of the frequency point control signal in the conventional frequency sweep circuit. It is a graph which shows the response characteristic by the filter for inclination control of an Example. It is a figure which shows the swept example of the frequency sweep circuit of an Example, and the enlarged part of a frequency switching interval. It is a block diagram which shows the structure of the conventional PLL sweep circuit. It is a figure which shows the change of the frequency at the time of the sweep in the PLL sweep circuit of FIG. It is a block diagram which shows the structure of the frequency sweep circuit using the conventional digital / analog converter.

  FIG. 1 shows the configuration of a frequency sweep circuit according to an embodiment of the present invention. This frequency sweep circuit is a VCO (voltage controlled oscillator) 1 using a frequency of 3 GHz and a distributor 2 as in the conventional circuit. A frequency multiplier (× 8) 3 for obtaining a frequency of 24 GHz, an amplifier 4 and a reference signal source (TCXO) 8 are provided. In addition, a programmable counter 14 and a CPU 15 are provided for outputting a control signal (voltage) at a sweep frequency point, and a slope control filter comprising a phase frequency detector (PFD) 16, a stabilization filter 17 and a time constant filter. 18 is arranged.

Then, a loop (phase-locked oscillation loop-PLL: Phase Locked Loop) that feeds back the output from the VCO 1 through the programmable counter 14, the PFD 16, the stabilization filter 17, and the slope control filter 18 is formed. A signal obtained by comparing the phase and frequency of the control signal (frequency F _IN ) output from the programmable counter 14 and the output (frequency Fref) from the reference signal source 8 is output.

FIG. 2 shows the operation of the PFD 16 in the PLL. As shown in the figure, an input signal having a frequency f ₀ (a signal from the programmable counter 14) is a reference signal having a frequency Fref (a signal from the reference signal source 8). ) From the state that reached within 360 degrees with respect to the phase of), the phase synchronization state becomes a region, and as a function before and after that, by determining whether the frequency f ₀ is higher or lower than the frequency Fref, the frequency pulling operation is performed. Done. In other words, when the frequency is high, the frequency is changed in the direction of decreasing, and the loop is configured until the phase becomes the same. On the other hand, when the frequency is low, the frequency is increased and the phase becomes the same. Operates (retracts).

  Then, after such a pull-in operation, as described with reference to FIG. 8, there is a lock time (Δt) composed of a phase synchronization portion. In the embodiment, the sweep is executed without using this phase synchronization portion.

  FIG. 3 shows frequency transitions and control signal switching points at the time of sweeping in the embodiment, and FIG. 4 shows frequency transitions and control signal switching points in the conventional circuit. In the circuit, as shown in FIG. 4, for example, when the control signal of the frequency point F (1) is given to the PFD, the circuit enters the phase synchronization portion Db through the portion Da whose frequency is moved by the frequency pull-in. Then, at the switching point indicated by the phase synchronization portion (period) Db, the control signal (movement instruction data) of the next frequency point F (2) is given, and the drawing operation to the frequency F (2) is performed. In this way, a control signal for the next frequency is given to the switching point of the phase synchronization portion Db.

On the other hand, in the embodiment, as shown in FIG. 3, for example, when the control signal (F _IN ) of the frequency point F (1) is given from the programmable counter 14 to the PFD 16, the frequency pull-in operation is performed by the PLL. The control signal of the next frequency point F (2) is given within the time (period) ta of the frequency pull-in operation. As a result, the phase can be shifted to the next frequency point without passing through the synchronization state during the phase synchronization operation of the PLL, and the sweep is executed by continuing the frequency pull-in at each point. This is a frequency pull-in sweep method.

  In addition, in the embodiment, a slope control filter 18 that is a time constant filter is provided, whereby the slope characteristic of the frequency change obtained by the PFD 16 can be made variable. That is, in the case of a general PLL, a low-pass filter (LPF) is used as a function for determining temporal transient characteristics. In the embodiment, a secondary lag-lead filter is used as the inclination control filter 18.

  FIG. 5 shows a response characteristic (range of δF) when the cutoff frequency is changed in the inclination control filter 18. As shown in FIG. 5, when the cutoff frequency of the filter 18 is lowered. Moving to a gentle slope on the T4 side and increasing the cutoff frequency, it moves to a steep slope on the T1 side. This is a general operation of the transient response characteristic of the filter. By using such an action, it is possible to determine the amount of frequency change per unit time, that is, the slope.

  FIG. 6 shows a sweep example of the embodiment. For example, the frequency point switching interval is 8 μs, and the frequency of 70.3125 kHz can be moved to this interval. That is, the change width necessary for the linear change can be determined from the repetition time of the switching point of the frequency point and the entire sweep frequency width. In the embodiment, the output of the VCO 1 is multiplied by 8 to 24 GHz. When the fluctuation width is 72 MHz, the VCO 1 requires a vibration width of 72 MHz / 8 to 9 MHz, so that the frequency fluctuation width is 9 MHz with a sweep time of 1024 μs.

  When this 9 MHz is composed of 128-point data and this is output from the programmable counter 14 as a control signal, since 1024 μs / 128 = 8 μs, the frequency switching interval is 8 μs, and at that interval The frequency shift is 9 MHz / 128 = 70.3125 kHz. Therefore, when the frequency is changed in a straight line, it is sufficient to perform a frequency shift of 70.3125 kHz per 8 μs.

  In this way, by adjusting the switching interval and the moving frequency in the switching interval for switching to output the control signal of the next point within the frequency pull-in time to the current point, the entire line is linear with a desired slope. Moving frequency modulation, i.e. sweeping, is possible. Here, in practice, since the phase synchronization portion is not passed, there is no restriction such as the phase margin of the loop, and the frequency change is simply performed by the information from the PFD 16. Therefore, the overall frequency fluctuation width is determined by the frequency shift amount per unit time.

  Furthermore, in the embodiment, the stabilization filter 17 is provided on the output side of the PFD 16 so that the PLL loop does not become abnormal. That is, the stabilization filter 17 can be a lag lead type filter or the like, and operates so that the sweep becomes linear by smoothing. Here, the stabilization filter 17 and the slope control filter 18 and the PLL loop are related to each other, and the response time is faster in the direction in which the loop band is widened, and is delayed in the direction in which the loop band is narrowed. Considering this relationship, it is necessary to optimize the filters 17 and 18.

  In addition, since phase synchronization is not performed, it is possible to reduce the frequency switching points and shorten the sweep time.

  According to such an embodiment, since the setting of the frequency point is the same as the PLL operation, there is an advantage that the frequency setting can be performed individually, and the frequency is brought close to the frequency of the reference signal source every time the frequency point is switched. Since the operation is performed, stable frequency control without fluctuation due to temperature and environment is possible, and it is not necessary to obtain a calibration value unlike a circuit using a digital / analog converter.

  In addition, since the present invention is a system that does not perform PLL phase synchronization, it is possible to perform frequency change modulation at high speed and linearly, no spurious signal of an extra component is generated in the output signal, and it is not stepped. Since linear modulation is performed, oversampling which is difficult in the PLL sweep can be performed well. That is, there is an advantage that sampling at the time of analog-digital conversion can be performed at a desired point to reduce a noise component.

  The present invention can be applied to FM-CW radar (long range radar), ranging sensor, intrusion warning sensor, human body sensor, level meter and the like.

1 ... VCO (voltage controlled oscillator), 3 ... frequency multiplier,
6, 14 ... programmable counter,
7, 15 ... CPU, 8 ... reference signal source,
9, 16 ... PFD (phase frequency detector),
10 ... Loop filter, 17 ... Stabilization filter,
18... Inclination control filter (time constant filter)

Claims (1)

In a frequency sweep circuit that includes a voltage controlled oscillator, a programmable counter having a frequency divider, and a phase-locked oscillation loop having a phase detector, and performs a frequency sweep,
A control signal for frequency setting for sweep is generated, and the control signal for the next frequency point is passed through the programmable counter within the frequency acquisition time during which the frequency acquisition operation is performed by the control signal for the current frequency point. A control circuit that outputs to the phase detector and performs a continuous frequency sweep without going through a phase synchronization state ;
A frequency sweep circuit, comprising: a slope control filter that is disposed between the phase detector and the voltage controlled oscillator and controls a slope of a frequency change in sweep .

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