JP4983409B2 - Phase-locked oscillator and multi-radar system using the same - Google Patents

Description

  The present invention relates to a phase-locked oscillator and a multi-radar system using the same. The present invention is particularly suitable for use in a phase-locked oscillator suitable for use in an RF band oscillator such as an FM-CW radar and a multi-radar system using the same.

  FIG. 35 is a diagram for explaining the prior art, and FIG. 35 (A) shows a frequency modulation portion of a conventional FM-CW radar. The basic configuration of the FM-CW system is to generate a triangular wave modulation signal with a function generator (FG) or the like, and to apply frequency modulation to the voltage controlled oscillator (VCO) with this modulation signal. What is important in the FM-CW system is to apply accurate triangular wave frequency modulation. For this purpose, for example, the maximum and minimum frequency deviations do not change with respect to the center frequency, and the frequency is time-dependent. In addition, it is necessary to change linearly, that is, the inclination (frequency change speed) does not change. The output frequency of the FM-CW radar depends on the stability of the external conditions (temperature, power supply, etc.) of the VCO, and the frequency shift of the output frequency depends on the modulation sensitivity of the VCO and the output frequency. A new VCO is required. Also, in order for the frequency to increase linearly, good linearity of the VCO is required.

  FIG. 35B shows a typical configuration of a conventional FM-CW radar transmitter. For the temperature change of the oscillation frequency, the CPU refers to the data table based on the temperature detected by the temperature sensor and corrects the center voltage of the triangular wave. For the linearity of the oscillation frequency, the CPU similarly corrects the triangular wave voltage by referring to the data table.

  FIG. 35C is a diagram showing another configuration example of the conventional FM-CW radar transmitter, and shows a method of superimposing a triangular wave on a PLL (Phase Locked Loop) circuit. In this method, the center frequency is stabilized by synchronizing the phase of the PLL with the center frequency. On the other hand, for the linearity of the frequency shift applied to the center frequency, the CPU corrects the triangular wave voltage by referring to the data table.

Conventionally, the oscillation frequency is stabilized by using a triangular wave that is phase-synchronized with the crystal oscillator 6a as a modulation signal, and control is performed so as not to exceed the upper and lower limits of the frequency deviation by detecting the frequency of the output RF signal. An oscillation circuit that performs the above is known (Patent Document 1).
JP-A-6-120735

  However, if the above-mentioned data table is used to correct the temperature change and linearity of the oscillation frequency, it is not only necessary to have a separate large data table, but also individual data for each device depending on circuit element variations. It is necessary to create a table, which greatly increases the number of test steps. In the configuration shown in FIG. 35C, the feedback by the PLL is applied to the VCO output modulated by the triangular wave, so that the modulation characteristic of the VCO output is deteriorated. Further, it is assumed that the modulation characteristic of the VCO in Patent Document 1 is linear. If it is not linear, it is necessary to perform linearity correction using a data table or the like.

  In addition, the multi-radar system is configured by arranging a plurality of FM-CW radars, and by assigning a different detection area to each radar, a wider area can be detected with higher accuracy. The multi-radar system may be one device equipped with a plurality of radars, or may be a plurality of devices equipped with at least one radar. For example, when a radar is mounted on a vehicle such as an automobile, the radar mounted on each vehicle constitutes a multi-radar system.

  FIG. 36 is a diagram for explaining the frequency assignment of each of a plurality of radars in a conventional multi-radar system. FIG. 36A shows a case where radio waves transmitted from a radar interfere with each other. When transmission signals modulated by triangular waves are transmitted from a plurality of radars using the same frequency band, the frequencies of the transmission signals are the same. Timing occurs, it is impossible to distinguish which radar signal is transmitted from which radar, and correct measurement cannot be performed. Therefore, when a plurality of radars are arranged, it is necessary to prevent the frequencies of the transmission signals of the radars from interfering with each other. Therefore, as shown in FIG. 36 (B), at least the frequency is set so that the frequency bands do not overlap each other. It is necessary to allocate a frequency band corresponding to the fluctuation width of each radar to each radar.

  On the other hand, when the usable frequency band is limited, it is not possible to secure a wide band to be allocated to one radar. That is, a large frequency shift of the transmission signal cannot be taken. The greater the frequency shift of the transmission signal, the higher the sensitivity and resolution. Therefore, when the allocated band is not sufficiently wide, the sensitivity and resolution are lowered.

  In addition, it is necessary to provide a predetermined interval between adjacent transmission signals in consideration of fluctuations in the center frequency and frequency shift of transmission signals due to temperature changes and changes over time. If this fluctuation is large, a wide interval must be secured in order to prevent interference, and the frequency shift amount of the transmission signal or the number of radars (number of channels) is sacrificed.

  FIG. 37 is a diagram for explaining fluctuations in the center frequency and frequency shift of a transmission signal frequency-modulated with a triangular wave. FIG. 37A illustrates a case where the center frequency of the transmission signal varies, and FIG. 37B illustrates a case where the frequency shift of the transmission signal varies. FIG. 37C is a diagram illustrating an example of frequency allocation in consideration of frequency fluctuations. In FIG. 37C, if the frequency shift is 200 MHz and the variation is 50 MHz with respect to the 1 GHz band, only two radars can be arranged (only two channels can be secured), and the frequency band is efficient. Is not being used.

  The present invention has been made in view of the above-described problems of the prior art, and the object of the present invention is to always obtain a highly stable VCO output with a simple configuration and control irrespective of variations in characteristics of the VCO circuit and temperature fluctuations. It is to provide a phase-locked oscillator.

  It is another object of the present invention to provide a multi-radar system that can use a given frequency band more efficiently by using a phase-locked oscillator that always provides a highly stable VCO output.

  A phase-locked oscillator according to the first aspect of the present invention (VCO calibration) includes a phase comparator that compares the phases of a reference signal and a comparison signal, a low-pass filter that integrates a phase error signal of the phase comparator, and the low-pass filter. A control unit that performs the main control of this device interposed in the subsequent stage of the filter, a VCO circuit that generates a signal having a frequency corresponding to the control voltage of the control unit output, and divides the output signal of the VCO circuit to A phase-locked oscillator including a PLL loop including a variable frequency divider that forms a comparison signal, wherein the control unit locks the PLL loop at a plurality of frequencies and measures a control voltage at each lock. And linearity calibration means for obtaining a modulation sensitivity representing a frequency change in a section connecting the frequencies based on the measured control voltages.

  According to the present invention, the configuration in which the PLL loop is locked at a plurality of frequencies makes it possible to easily and accurately control the voltage for causing the VCO to oscillate at the required frequency even if the modulation sensitivity of the VCO varies or depends on temperature. can get.

  The phase-locked oscillator according to the second aspect of the present invention (VCO drive) locks the PLL loop at a predetermined frequency, and then opens the PLL loop in a state where the PLL circuit is opened based on the obtained modulation sensitivity. VCO driving means for generating and outputting a voltage signal for generating a linearity-corrected frequency change centered on a predetermined frequency is further provided.

  According to the present invention, the configuration in which the VCO circuit is driven by a voltage signal that has been linearly calibrated can always provide stable oscillation characteristics regardless of variations in the characteristics of the VCO circuit and temperature fluctuations.

  In the third aspect (intermittent PLL control) of the present invention, the VCO driving means samples the output of the low-pass filter in synchronization with the timing at which the VCO circuit outputs the center frequency, and the detected phase error signal is within a predetermined range. In the case of exceeding the control voltage, the control voltage is offset in the direction of decreasing the phase error signal. Therefore, the center frequency can be kept constant by intermittent PLL control.

  A phase-locked oscillator according to a fourth aspect (intermittent FLL control) of the present invention is a first frequency divider that divides a reference signal and a first output that divides the output of a VCO circuit to form the comparison signal. The VCO driving means periodically resets the counters of the first and second frequency dividers at a period that is an integral multiple of the signal period applied to the VCO circuit, and the VCO circuit When the phase error signal output from the low-pass filter sampled in synchronization with the output timing of the center frequency exceeds a predetermined range, the control voltage is offset in a direction to reduce the phase error signal.

  In the present invention, both frequency-divided signals are forcibly phase-matched by a configuration in which the counters of the first and second frequency dividers are periodically reset. However, if the frequency of the VCO output is shifted, the phase between both frequency-divided signals will spread quickly. Therefore, in the present invention, by periodically detecting the phase error signal of the low-pass filter output, the rate of change of the phase error signal is monitored to detect whether the frequency of the VCO output is deviated. In the present invention, since the counters of the first and second frequency dividers are not reset to a specific absolute phase by periodically resetting, the phase pull-in is fast. Note that the control that determines that the lock state is established if only the frequencies are aligned is referred to as FLL (Frequency Locked Loop) control in this specification.

  The phase-locked oscillator according to the fifth aspect of the present invention (PLL high-speed pull-in) is a first variable frequency divider that divides the reference signal, and the output of the VCO circuit is divided to form the comparison signal. 2, and the control unit sets a predetermined frequency dividing ratio in the first and second variable frequency dividers and then forms a PLL loop to form a phase between the reference signal and the comparison signal. When starting the pull-in, a control voltage corresponding to the predetermined frequency division ratio is applied to the VCO circuit, and counters of the first and second variable frequency dividers are reset.

  According to the present invention, a VCO output close to the required frequency can be obtained from the beginning by applying a control voltage corresponding to the set division ratio from the beginning to the VCO circuit. Further, by resetting the counters of the first and second variable frequency dividers, the initial phases of both frequency-divided signals are forcibly aligned. In this case, the frequency of both frequency-divided signals is already substantially the same, and the initial phase of both frequency-divided signals is matched, so the PLL loop quickly converges to the locked state.

  A phase-locked oscillator according to a sixth aspect of the present invention (comprising a VCO circuit whose modulation sensitivity does not change with temperature) includes a phase comparator that compares the phases of a reference signal and a comparison signal, and a phase error signal of the phase comparator. A low-pass filter that integrates, a control unit that intervenes in the subsequent stage of the low-pass filter, a VCO circuit that generates a signal having a frequency corresponding to the control voltage of the output of the control unit, and the VCO circuit A phase-locked oscillator including a PLL loop including a variable frequency divider that divides an output signal to form the comparison signal, wherein the control unit changes a PLL lock frequency at a predetermined interval, Control voltage measuring means for measuring the control voltage at the time of each lock for a range covering the range, and the modulation sensitivity representing the respective sections by dividing the fluctuation range of the measured control voltage into a plurality of sections A linearity calibration means to be obtained and a voltage signal for generating a linearity-corrected frequency change centered on the predetermined frequency in the VCO circuit in a state in which the PLL loop is opened after the PLL loop is locked at a predetermined frequency. And VCO driving means for generating and outputting the control voltage at the time of locking and the modulation sensitivity representing each of the obtained intervals.

  According to the present invention, once the modulation sensitivity in the required frequency range is obtained in advance, the modulation sensitivity does not change much with temperature. Therefore, when the VCO is driven at an arbitrary temperature, the VCO drive means locks the PLL loop at a predetermined frequency. Then, with the PLL loop open, a voltage signal for causing the VCO circuit to generate a linearity-corrected frequency change centered on a predetermined frequency is obtained as the control voltage (reference voltage) at the time of locking and the determination. By generating and outputting based on the modulation sensitivity representing each section, the VCO circuit can always be driven at the correct frequency regardless of the temperature.

  A multi-radar system according to a seventh aspect of the present invention is a multi-radar system including a plurality of FM-CW radars having the phase-locked oscillator according to any one of the first to sixth aspects of the present invention. The control unit of each FM-CW radar is a control voltage that periodically increases and decreases, and that is synchronized with a predetermined synchronization signal so that the increasing and decreasing directions and increasing and decreasing speeds of the control voltage coincide with each other. The VCO circuit of each FM-CW radar is a signal whose frequency is periodically increased or decreased by a predetermined frequency deviation amount with respect to the center frequency according to the increase or decrease of the control voltage. The center frequencies of the signals are different from each other, and the signals in which the frequency increase / decrease direction and speed of the signals coincide with each other are output.

  According to the present invention, it is possible to reduce the frequency interval of each signal without causing radio wave interference, and it is possible to set more channels.

  In the multi-radar system according to an eighth aspect of the present invention, in the seventh aspect, one of the control units of each FM-CW radar generates the synchronization signal and outputs it to the remaining control units.

  A multi-radar system according to a ninth aspect of the present invention is the multi-radar system according to the seventh aspect, wherein one of the control units of each FM-CW radar receives a synchronization signal supplied from the outside, and the remaining control units Output to.

  In the multi-radar system according to a tenth aspect of the present invention, in the seventh aspect, the control unit of each FM-CW radar receives a synchronization signal supplied from the outside.

A multi-radar system according to an eleventh aspect of the present invention includes a plurality of radars that generate and output a modulation signal that is frequency-modulated so that the frequency periodically increases or decreases using each of a plurality of synchronized triangular waves as a control signal. In a multi-radar system, the modulation signals output from each radar have different center frequencies, and the upper and lower limits of the frequency that periodically increases and decreases are different from each other for each modulation signal output by each radar, and the upper and lower limits. timing at which the value is output in synchronization with the predetermined synchronization signal to each other match so each modulated signal, further, with respect to the lower limit frequency of the modulation signal generated based on at least one of the triangular wave, at least It is characterized in that the upper limit frequency of another modulation signal generated based on another one triangular wave is set to be large .

  A multi-radar system according to a twelfth aspect of the present invention is the multi-radar system according to the eleventh aspect, wherein each radar is synchronized with a predetermined synchronizing signal so that the frequency increasing / decreasing direction and speed of the signal coincide with each other. Is generated.

  In a multi-radar system according to a thirteenth aspect of the present invention, in the eleventh aspect, one of the plurality of radars generates the synchronization signal and outputs it to the remaining radars.

  In the multi-radar system according to a fourteenth aspect of the present invention, in the eleventh aspect, one of the plurality of radars receives a synchronization signal supplied from the outside and outputs it to the remaining radars.

  According to a fifteenth aspect of the present invention, in the eleventh aspect, the plurality of radars receive a synchronization signal supplied from the outside.

  A multi-radar system according to a sixteenth aspect of the present invention is the radar according to the eleventh aspect, wherein the plurality of radars are mounted on a plurality of vehicles, and are mounted on the vehicle traveling in the first direction. Generates a signal having a frequency included in the first frequency band, and the radar mounted on the vehicle traveling in the second direction different from the first direction has a second frequency different from the first frequency band. A signal having a frequency included in the frequency band is generated.

  As described above, according to the phase-locked oscillator of the present invention, even if a VCO circuit having variations in characteristics and temperature changes is used, the output frequency is stabilized by PLL control, and the output frequency change by VCO driving with the PLL open. Therefore, it is extremely important to improve the reliability of the phase-locked oscillator, and further contribute to the spread of FM-CW radar and the like using the oscillator.

  Further, according to the multi-radar system of the present invention, even if the frequency shift amount of the channel allocated to the usable frequency band is about the same as the conventional one, the frequency interval of the channel is narrowed without causing radio wave interference. In comparison with the prior art, a large number of channels can be set in the frequency band, and the frequency utilization efficiency is remarkably improved.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described in detail with reference to the accompanying drawings. Note that the same reference numerals denote the same or corresponding parts throughout the drawings.

(Phase-locked oscillator)
FIG. 1 is a block diagram of a phase-locked oscillator according to the first embodiment. In the figure, 1 is a clock oscillator that generates a PLL reference clock signal CK, 2 is a phase comparator that constitutes a PLL loop, 11 is a variable frequency divider for the clock signal CK, 12 is a variable frequency divider for VCO output, 13 Is a phase comparator (PD) that compares the phases of both frequency divider outputs φR and φV, 3 is a low-pass filter (LPF) that integrates the phase error signal of the PD 13 output, and 4 is a processor unit corresponding to the controller of the present invention. (PU), 14 is an A / D converter that samples the phase error signal Vpd of the LPF3 output, 15 is a CPU that performs the main control and processing of this oscillator, and 16 is a control voltage output from the CPU 15 that is converted into an analog control voltage Vcont. The D / A converter 5 performs a voltage-controlled oscillator (VCO) that outputs an oscillation signal having a frequency corresponding to the control voltage Vcont, and 6 passes through or shuts off the output of the VCO 5. A switch (SW).

  The CPU 15 performs control to stabilize the oscillation frequency of the VCO 5 by configuring the PLL loop continuously or periodically regardless of the characteristic variation of the VCO 5 and temperature fluctuation, and the triangular wave with the PLL loop open during radar operation. Control is performed to generate a signal and to output a frequency modulation output subjected to linearity correction to the VCO 5. Specifically, various functions such as control voltage measurement means, linearity calibration means, and VCO drive means (radar transmission processing) according to the present invention are realized by executing various processes shown in FIGS. You can also

  The control voltage measuring means measures the control voltage Vcont at each lock by locking the PLL loop at a plurality of frequencies. At that time, setting data is output to the phase comparison unit 2 to set the frequency dividing ratios of the variable frequency dividers 11 and 12 as desired. Furthermore, the phase error signal Vpd output from the LPF 5 is periodically sampled, and the control voltage Vcont is updated in the direction of decreasing the phase error signal Vpd in accordance with a known PLL process, so that the PLL loop is sequentially locked at a plurality of frequencies. The control voltage Vcont acquired at the time of each lock is the control voltage Vcont necessary for causing the VCO 5 to oscillate at each predetermined frequency regardless of the characteristic variation of the VCO 5 and the temperature fluctuation.

An inset (a) in FIG. 1 shows a conceptual configuration diagram of an example PLL loop. Here, the function of the loop filter realized by the LPF 3 and the CPU 15 is represented by a digital filter having a transfer characteristic F (s). By configuring the digital filter with the CPU 15, the filter characteristics can be changed by the gain and the clock cycle. If the input of the digital filter is X (n) and the output is Y (n), the difference equation is
Y (n) = (A + B) .X (n) + Y (n-1) -A.X (n-1)
It is represented by If this is converted to Z,
Y (z) = (A + B) * X (z) + z-1 * Y (z) -A * z-1 * X (z)
And the transfer characteristic F (z) of the filter is
F (z) = Y (z) / X (z) = A + B / (1-Z-1)
It is represented by If this is represented by F (s),
F (s) = A + B / (1-e−j2πfT)
It becomes.

Further, assuming that the phase of the input in the case of the PLL is θi (s) and the phase of the output is θo (s), the transfer characteristic H (s) of the loop is
H (s) = θo (s) / θi (s)
= K · F (s) / {s + K · F (s)}
However, K = Kd · Kv / N
It is represented by

  Next, the linearity calibration means obtains a modulation sensitivity that represents (for example, linear approximation) a frequency change in a section connecting the frequencies based on the measured control voltages Vcont. The VCO driving (radar transmission) means locks the PLL loop at a predetermined frequency (for example, the center frequency of the transmission signal), and then opens the PLL loop and opens the VCO circuit based on the calculated modulation sensitivity. A voltage signal for generating a linearity-corrected frequency change centered on a predetermined frequency is generated and output. At the time of this radar transmission, since loop control is opened, loop feedback that suppresses the frequency change of the VCO 5 is not applied, so that high fidelity of the frequency change can be maintained. Further, the frequency of the radar transmission wave is also stabilized by intermittently performing loop control for stabilizing the center frequency of the radar transmission for every cycle of the radar transmission. Hereinafter, these controls and processes will be described in detail.

  FIG. 2 is a flowchart of the control voltage measurement process according to the embodiment. Each control voltage V0 for obtaining the center frequency f0, the lower limit modulation frequency f1, and the upper limit modulation frequency f2 in the VCO output by changing the frequency division ratio of the PLL. The case where V1 and V2 are measured is shown. In step S11, the output EN to the RF switch SW6 is disabled so as not to output an unnecessary wave when measuring the control voltage Vcont, and the output of the radio wave (RF) is cut off. In step S12, the contents of the register i holding the measurement sequence are initialized (for example, i = 1). In step S13, the frequency division ratios Nr and Nc of the frequency dividers 11 and 12 are set so that the PLL locks at the frequency fi (initially the lower limit frequency f1). As a result, the PD 13 outputs a phase error signal corresponding to the phase error of both the divided signals φR and φV, and integrates (filters) it with the LPF 3.

  In step S14, the CPU 15 periodically acquires the phase error output Vpd of the LPF3 output. In step S15, it is determined whether or not the signal Vpd is within a predetermined range centered on a required center value (for example, 2.5 V). To do. If it is not within the predetermined range, the PLL loop is not in the locked state, so the process proceeds to step S16, and the control voltage Vcont is updated in the direction in which Vpd approaches the center value according to the normal PLL mode.

  Thus, when the phase error output Vpd becomes the center value in the determination in step S15, the PLL loop is in a locked state, so the process proceeds to step S17, and the control voltage Vcont at that time is set to Vi (initially control for the lower limit frequency f1). The voltage V1) is stored in the memory. In step S18, the contents of the register i are updated, and the next measurement object is set to the center frequency f0, for example. In step S19, it is determined whether or not the content of the register i is the measurement end. If the measurement is not completed, the process returns to step S13. Thus, the subsequent center frequency f0 (V0) and upper limit frequency f2 (V2) are measured, and when the measurement is completed in the determination of step S19, this process is exited.

  FIG. 3 shows a timing chart of the control voltage measurement operation according to the first embodiment. The phase error output Vpd of an example changes in the range of 0 to 5V, and is determined to be in the locked state around the middle 2.5V. Initially, the PLL sets the frequency division ratios Nr and Nc so as to lock at the lower limit frequency f1, for example, and performs PLL loop control at predetermined time intervals. The CPU 15 periodically acquires Vpd and updates the control voltage Vcont in a direction in which the phase error output Vpd approaches 2.5 V according to normal PLL loop control. Thus, the loop control is continued, and when Vpd ≈ 2.5 V is reached, it is in a locked state. At this time, the oscillation frequency f of the VCO 5 is accurately the lower limit frequency f 1 regardless of the characteristic variation of the VCO 5 and the fluctuation due to temperature. It has become. The CPU 15 acquires the control voltage Vcont at this time and stores it in the memory as the control voltage V1 for causing the VCO 5 to generate the lower limit frequency f1.

  Next, the PLL is locked at the center frequency f0, and Vcont at that time is stored in the memory as a control voltage V0 for causing the VCO 5 to generate the center frequency f0. Finally, the PLL is locked at the upper limit frequency f2, and Vcont at that time is stored in the memory as a control voltage V2 for causing the VCO 5 to generate the upper limit frequency f2.

  According to the present embodiment, the configuration in which the PLL loop is locked at each predetermined frequency (predetermined frequency division ratio) f0, f1, f2 allows the VCO5 to be controlled at the predetermined frequency f0, f1, regardless of the characteristic variation of the VCO5 or temperature change. The control voltages V0, V1, and V2 for oscillating at f2 can be obtained automatically and accurately.

  FIG. 4 is a flowchart of the linearity calibration process according to the first embodiment. The section A connecting the frequencies based on the information of the set of (f1, V1), (f0, V0), (f2, V2) obtained above. The process which calculates | requires the control voltage Vcont for changing the VCO output in -D linearly by fixed frequency (DELTA) f is shown. If the control voltage Vcont obtained in this process is actually output to the VCO 5, an output frequency characteristic as shown in FIG. 5B can be obtained.

In step S31, each information of the control voltages V0 to V2 and the frequencies f0 to f2 acquired in the process of FIG. 2 is used, and the modulation sensitivity of the VCO 5 in each section j (= A to D) obtained by dividing the triangular period T0 into, for example, four. Is approximated to a straight line by the characteristic a (j). FIG. 5C shows a timing chart of the linearity calibration operation.
・ By frequency change f1 → f0 and control voltage change V1 → V0 in section A,
Modulation sensitivity a (A) = (f0−f1) / (V0−V1)
・ By frequency change f0 → f2 and control voltage change V0 → V2 in section B,
Modulation sensitivity a (B) = (f2-f0) / (V2-V0)
・ By frequency change f2 → f0 and control voltage change V2 → V0 in section C,
Modulation sensitivity a (C) =-(f2-f0) / (V2-V0) =-a (B)
・ By frequency change f0 → f1 and control voltage change V0 → V1 in section D,
Modulation sensitivity a (D) = − (f0−f1) / (V0−V1) = − a (A)
It becomes.

  In step S32, each time point is determined according to a triangular wave condition (for example, triangular period: 10 ms, frequency deviation from the center frequency f0: ± 25 MHz) and a CPU condition (for example, Vcont time resolution 50 μs, voltage resolution: 0.005 V). A frequency change Δf at (for example, constant 0.5 MHz per 50 μs) is obtained. In step S33, the timing counter is initialized to k = 0 and the area register j = A. In step S34, for example, the control voltage V1 for generating the lower limit frequency f1 is set in the control voltage Vcont.

In step S35, the control voltage increment ΔVcont (k) is set to
ΔVcont (k) = Δf / a (j)
Ask for. In step S36, the control voltage Vcont (k + 1) at the next time point is
Vcont (k + 1) = Vcont (k) + ΔVcont (k)
Ask for. As a result, the control voltage Vcont necessary for changing the output frequency by Δf is updated. During the radar operation, the updated control voltage Vcont is output to the VCO 5 and this calculation process is periodically performed at a cycle of 50 μs.

  In step S37, the counter k is incremented by 1, and in step S38, it is determined whether k ≧ (T0 / 4) * j. Here, j = A to D correspond to Equations 1 to 4. If k ≧ (T0 / 4) * j is not satisfied, the process returns to step S35 to obtain the control voltage at the next timing.

  Thus, when k ≧ (T0 / 4) * j is satisfied in the determination in step S38, the area counter j is incremented by 1 in step S39, and it is determined whether j> 4 (= D) in step S40. If j> 4 is not true, the process returns to step S35, and the same processing as described above is performed using the modulation sensitivity of the next region. Thus, when j> 4 in the determination of step S40, the control voltage Vcont for one cycle T0 has been obtained, and the process is exited. In the present embodiment, by performing the PLL operation and the VCO linearity calibration process, the linearity of the VCO 5 can be automatically calibrated and used without providing a correction table specific to each device. Become.

  FIG. 5 is a timing chart of the linearity calibration operation according to the first embodiment, and FIG. 5A shows the original frequency modulation characteristics of the VCO 5. The horizontal axis is the control voltage Vcont, and the vertical axis is the oscillation frequency. The modulation sensitivity (Δf / ΔVcont) of the VCO 5 changes nonlinearly. When viewed from the center frequency f0, the modulation sensitivity is high on the low frequency side and low on the high frequency side. With respect to such a modulation characteristic, by adding a control voltage Vcont as shown in FIG. 5C, a characteristic in which the frequency changes linearly as shown in FIG. 5B can be obtained.

  FIG. 5B shows a preferable frequency change as the FM-CW radar. The output frequency of the VCO 5 changes linearly between the lower limit f1 and the upper limit f2. The linearity calibration process is a process for obtaining a control voltage Vcont for causing the VCO 5 of FIG. 5A to output a linearly changing frequency as shown in FIG. 5B according to FIG.

  FIG. 6 is a flowchart of the radar transmission process according to the first embodiment. In a state where the PLL is opened, the CPU 15 generates a continuous triangular wave with reference to V0, and the center of the triangular wave every one or two or more triangular periods. The case where the loop control for maintaining a frequency at f0 is performed intermittently is shown. In step S51, the PLL is once locked at the center frequency f0. As a result, Vpd≈2.5V and Vcont≈V0 (V0 at this time) are stabilized. In step S52, the CPU 15 generates a triangular wave that has been linearly corrected in the T0 cycle with the V0 as a reference, and applies it to the VCO5. Since the triangular wave section opens the PLL loop, the frequency of the VCO output changes linearly as shown in FIG. The release of the PLL loop can be easily realized by the CPU 15 not performing the loop control in this section.

  On the other hand, the PD 13 changes the phase error signal as the frequency of the VCO output changes. However, since the LPF 3 has a time constant sufficiently larger than the triangular wave period (for example, about 10 times), even if a triangular wave is added to the VCO 5, The phase error signal in the section is averaged by the LPF 3, and the output phase error signal Vpd is slightly changed every triangular wave period.

  In step S53, the phase error signal Vpd of the LPF 3 is acquired at the timing of 3T0 / 4 (center frequency). When there is no change in the characteristics of the VCO 5, the phase error signals in this section are averaged and are in the vicinity of Vpd≈2.5 V. However, when the VCO characteristics change, the Vpd gradually changes accordingly. In step S54, it is determined whether or not Vpd≈Vref (= 2.5 V). If Vpd≈Vref, since f0 is within the required range, the process proceeds to step S58. If Vpd≈Vref is not satisfied, it is further determined in step S55 whether Vpd> Vref.

  If Vpd> Vref is not satisfied, the process proceeds to step S56, and, for example, Vcont (for example, V1) at the next time point is offset to the negative side in order to increase Vpd at the next T0 / 4. If Vpd> Vref, in step S57, Vcont (for example, V1) at the next time is offset to the + side in order to reduce Vpd at the next T0 / 4. The CPU 15 determines the offset amount according to the digital filter shown in FIG. The timing for adding the offset to the control voltage may be the timing for adding V1 to the VCO 5, but may be other timing. It should be noted here that an open loop operation is performed within the period of the triangular wave, and the triangular wave characteristic of the VCO output is not deformed. Then, in synchronization with a certain point of the triangular wave cycle, the feedback is performed periodically (intermittently) and the PLL is applied. In step S58 and subsequent steps, a predetermined number of triangular waves without feedback control are output in order to set how many periods of triangular waves are to be fed back. That is, in step S58, it is determined whether or not the number of triangular waves without feedback control has been output a predetermined number of times. If not, the triangular wave without feedback control is output for one cycle in step S59. If it is executed, this process is exited.

  FIG. 7 is a timing chart of the radar transmission operation according to the first embodiment, and shows a case where an offset is added to Vcont (V1) every triangular wave period. According to the present embodiment, since the feedback is applied at the moment when the triangular wave ends, the triangular shape of the output frequency of the VCO 5 does not change. Since the feedback period and the loop gain of the PLL are inversely proportional, there is a method of increasing the feedback period when it is desired to reduce the loop gain and slow down the control response. For example, the control voltage Vcont can be fed back every 10 cycles of the triangular wave and the value of V1 can be offset, or can be fed back every 1000 cycles of the triangular wave and the value of V1 can be offset.

  FIG. 8 is a timing chart of the radar operation operation according to the first embodiment, and shows a case where a stable radar operation can always be maintained by interrupting the linearity calibration operation of the VCO between a series of radar operations. Yes. Since the VCO 5 has temperature characteristics, when the temperature changes during the radar operation, the control voltage V0 for outputting the center frequency f0 also changes. In the present embodiment, a stable radar operation can always be maintained by periodically recalibrating the linearity.

  FIG. 8A shows a case where measurement of the control voltages V1, V0, V2 and a linearity calibration associated therewith are performed between a series of radar operations. In addition, when the temperature change is separately detected and the temperature changes more than a predetermined value, the control voltages V1, V0, and V2 may be measured and linearity calibration may be performed. Further, the measurement order of the control voltage is arbitrary, and for example, the center frequency f0 can be measured last. By doing so, since the PLL loop is already locked at the frequency f0, the process of step S51 described above with reference to FIG. 6 can be omitted when the radar operation is continued.

  FIG. 8B shows a case where the control voltages V1, V0, and V2 are measured in sequence between each series of radar operations, and the linearity calibration of the VCO 5 is performed together with the last measurement of V2. In this way, since the measurement time per control voltage is short, there is an advantage that the dead time of the radar operation can be reduced. Although not shown, this method is particularly advantageous when performing finer linearity calibration by increasing the number of control voltage measurement points in addition to the three control voltages V1, V0, and V2.

  FIG. 9 is a block diagram of the phase-locked oscillator according to the second embodiment, showing a case where two LPFs for radar and VCO calibration are provided to enable high-speed PLL pull-in in each operation. In the figure, the output of PD3 is input to LPFs 3a and 3b via switches 17a and 17b, respectively. The LPF 3a exclusively integrates the phase error signal sampled at the center frequency output timing at the time of driving the VCO, and the LPF 3b is used exclusively for the purpose of integrating the phase error signal at the time of measuring the control voltage. Preferably, the measurement time of the control voltage for each frequency can be shortened by making the time constant of the LPF 3b smaller than the time constant of the LPF 3a.

  Further, the variable frequency dividers 11 and 12 of this example are configured so that the counter can be reset from the CPU 15, and the initial phases of the divided signals φR and φV are forcibly aligned by resetting both counters at the same time. Is possible. Further, the switch SW7a is configured to be able to turn on / off the signal, and the LPF 3a integrates the phase error signal in the section where the SW 7a is ON, and when the SW 7a is turned OFF, the integrated value ( Capacitor charge) can be maintained as it is. The same applies to the switch SW7b and the LPF 3b. In this embodiment, the pull-in time of the PLL loop can be significantly shortened by effectively utilizing such a configuration. Details will be described below.

  FIG. 10 is a flowchart of the high-speed pull-in process of the phase-locked oscillator according to the second embodiment. This process includes, for example, the measurement process of the control voltage V1 in the first half and the radar operation process in the second half. For example, after the previous radar operation is completed, this processing is input. In step S61, the frequency dividing ratio of the variable frequency dividers 11 and 12 is set to f1. In step S62, V1 acquired and stored in the previous measurement of V1 is set as the control voltage Vcont. As a result, the VCO 5 generates the lower limit frequency f1 when locked in the previous measurement of V1 from the beginning regardless of temperature fluctuations. In step S63, the counters of the variable frequency dividers 11 and 12 are reset, so that the initial phases of both frequency divided signals φR and φV are quickly aligned.

  In step S64, when the preparation for the V1 measurement is completed, the switch control signal SW2 is turned on to enable the PLL operation via the LPF 3b. At this time, the LPF 3b holds the phase error voltage Vpd2 (≈2.5 V) when the internal capacitor is locked in the previous control voltage measurement. This phase error voltage Vpd2 Regardless of V1, V0 or V2, in the locked state, it is about Vref (for example, about 2.5 V). Therefore, since the current PLL loop can also be started from a state close to the lock, it can converge to the lock state at an earlier time regardless of the time constant of the loop. In step S65, Vpd2 is acquired. In step S66, it is determined whether or not Vpd2≈Vref. If NO, Vcont is updated in the direction in which Vpd2 approaches Vref in step S67, and the process returns to step S65.

  Thus, when Vpd2≈Vref is determined in the determination in step S66, Vcont at that time is acquired and stored in the memory for storing the control voltage V1 in step S68. In step S69, the switch control signal SW2 is turned OFF, so that the phase error voltage Vpd2 at the time of locking this time is held in the capacitor in the LPF 3b.

  Next, the radar operation is started, and in step S71, the frequency dividing ratio of the variable frequency dividers 11 and 12 is set to the center frequency f0. In step S72, a triangular wave signal centered on V0 is superimposed on Vcont. In step S73, the counters of the variable frequency dividers 11 and 12 are reset, and the initial phase between both frequency divided signals φR and φV is quickly adjusted. In step S74, when the radar operation is ready, the switch control signal SW1 is turned on to enable the PLL operation via the LPF 3a. At this time, the LPF 3a holds the phase error voltage Vpd1 (about 2.5 V) when the internal capacitor is maintained in the substantially locked state by the previous radar operation.

  In step S75, the radar transmission control as described above with reference to FIG. 6 is performed, and in step S76, it is determined whether or not triangular wave transmission for a predetermined number of cycles has been performed. If not completed, a triangular wave without feedback control is output for one cycle in step S77. Thus, when the transmission for a predetermined number of cycles is completed in the determination in step S76, the switch control signal SW1 is turned off in step S78, so that the phase error voltage Vpd1 when the lock is maintained in the current radar operation becomes the capacitor in the LPF 3a. Retained.

  FIG. 11 is a timing chart of the high-speed pull-in operation of the phase-locked oscillator according to the second embodiment, and shows a case where the measurement process of the control voltage V1 is interrupted between each series of radar operations. When the previous radar operation is completed, the switch control signal SW1 is turned OFF (L), and Vpd1 of the LPF 3a is held. The CPU 15 sets a frequency division ratio for obtaining f1 in the variable frequency dividers 11 and 12, and outputs the previously measured V1 as Vcont. Further, the counters of the variable frequency dividers 11 and 12 are reset to match the initial phase. Now that the measurement operation is ready, the switch control signal SW2 is turned ON (H), and the PLL operation is performed according to the phase error signal Vpd2 of the LPF 3b. Thus, when it is confirmed that Vpd2 is within the lock range, the CPU 15 stores the current Vcont as a new V1. When the measurement of V1 is completed, the switch control signal SW2 is turned OFF and Vpd2 at that time is held.

  When the next radar operation is started, a frequency division ratio for obtaining f0 is set in the variable frequency dividers 11 and 12. Further, the CPU 15 outputs a triangular waveform centered on V0. Note that the triangular wave calibration in this example is performed after the measurement of V2. Further, the counter of the variable frequency divider is reset to match the initial phase. Since the radar operation is ready, the switch control signal SW1 is turned on to operate the PLL with the radar Vpd1. Thereafter, V0 and V2 are acquired in the same manner, and linearity configuration data is updated.

  FIG. 12 is a block diagram of a phase-locked oscillator according to the third embodiment, which includes two PLL circuits, which are controlled by a single CPU 15 and simultaneously execute radar operation using one loop. In this example, linearity calibration of the VCO circuit is performed using the other loop, and these are alternately performed by the PLL circuits of both systems. Thereby, it is possible to eliminate the dead time of the radar operation.

  FIG. 13 shows an operation timing chart of the phase-locked oscillator according to the third embodiment. The radar operation is performed by the PLLa, and the measurement of V1, V0, and V2 and the linearity calibration of the VCO 5b are performed by the PLLb. Next, the radar operation is performed by the PLLb, and the measurement of V1, V0, and V2 and the linearity calibration of the VCO 5a are performed by the PLLa. The switching may be performed periodically, for example, every 5 minutes, or may be performed when the temperature change of the outside air exceeds a certain range.

  FIG. 14 is a diagram for explaining a phase-locked oscillator according to the fourth embodiment. The oscillation frequency of the VCO circuit drifts due to temperature change, but it is suitable for application to a VCO circuit whose modulation sensitivity does not change much with temperature. Shows the case. In practice, there are many VCO circuits having such characteristics. The PLL circuit may be the same as that described in FIG. 1, FIG. 9, or FIG. FIG. 14A shows the modulation characteristics of this type of VCO circuit. Assuming that the modulation curve at room temperature is a, the curve shifts to the curve b side at high temperatures and shifts to the curve c side at low temperatures. In such a VCO circuit, even when the same control voltage V0 is applied, the oscillation frequency changes from f0 ′ to f0 ″ depending on the temperature, but the modulation sensitivity in the vicinity of V0 does not change, so the frequency is changed by Δf. Therefore, ΔVcont does not change with temperature. This is true for the entire control voltage range Vmin to Vmax.

  FIG. 14B shows a flowchart of linearity calibration processing for this VCO circuit. In step S81, by changing the frequency dividing ratios Nr and Nc of the variable frequency divider PLL, the lock frequency is gradually increased and swept, and the control voltage Vcont is measured each time. In step S82, for each of the measured control voltages Vcont, the control voltage possible fluctuation ranges Vmin to Vmax are divided, for example, every 1V, and modulation sensitivities a01, a12, a23,. In step S83, a frequency change Δf (constant in this example) at each time point is obtained based on the triangular wave condition and the CPU condition. Thus, a sensitivity table that can be used in common regardless of temperature fluctuations is obtained.

  Although not shown, at the time of radar transmission, the control voltage V0 at that time is obtained by first locking the PLL to f0. Thereafter, for example, Vcont is increased by Δf from V0 to the upper limit frequency f2. At that time, it is determined in which voltage section the Vcont of each time point is, and the voltage change of the section is obtained by using the modulation sensitivity of each corresponding section. Thus, when f2 is reached, Vcont is then decreased to the lower limit frequency f1 and then increased to f0. Then, such control is repeated. Therefore, according to the present embodiment, it is possible to always transmit a radar wave in an appropriate frequency range regardless of temperature fluctuations. Further, since it is not necessary to perform linearity calibration processing for temperature fluctuations, the radar operation can be operated without interruption.

  FIGS. 15 and 16 are diagrams (1) and (2) for explaining the phase-locked oscillator according to the fifth embodiment. FIG. 15 is replaced with PLL control for aligning the phase between both the divided signals φR and φV. In this example, so-called FLL (frequency locked loop) control is performed in which it is not necessary to align the phases if only the frequencies are aligned. In general, when the control voltage Vcont is D / A converted and applied to the VCO 5, the output frequency of the VCO 5 changes stepwise by at least the 1-bit voltage resolution of the D / A 16 × the magnitude of the modulation sensitivity. On the other hand, the PLL loop (that is, LPF3) operates in an analog manner so that the average frequency of the radar transmission wave driven by the triangular wave becomes f0. Will occur frequently. In the fifth embodiment, in order to solve this problem, FLL control is performed instead of PLL control. The circuit configuration may be the same as that shown in FIG. 1, for example, but it is assumed that the counter of the variable frequency dividers 11 and 12 can be reset from the CPU 15.

  In general, the phase between both frequency-divided signals φR and φV is the same even when the frequencies of both frequency-divided signals φR and φV are equal in the state where VCO 5 is free-running (that is, the PLL loop is open). These phases gradually shift (slip). However, by resetting the counters of the variable frequency dividers 11 and 12 every cycle according to the fifth embodiment, within one cycle of the triangular wave. It is possible to effectively avoid the occurrence of a large phase difference. However, if the oscillation frequency of the VCO 5 deviates from the required value, the phase difference between the two signals φR and φV also spreads quickly in a short time, so this state is that the phase error signal Vpd is observed every cycle. Can be detected reliably.

  In FIG. 15, in the present embodiment based on FLL control, the frequency of the VCO 5 output only needs to be within a predetermined range even if the phase between both frequency-divided signals φR and φV is not aligned. When the counters of the counters 11 and 12 are reset, for example, every period of the triangular wave, and when it is detected that the Vpd has changed more than a predetermined value within a unit interval (for example, one period), the output frequency is outside the predetermined range. The control voltage Vcont is offset. FIG. 16 shows the operation of the phase comparison unit 2. As a method of realizing the FLL control, it can be easily realized by resetting the counters of the variable frequency dividers 11 and 12 periodically (one or more cycles of a triangular wave).

  FIG. 17 is a diagram for explaining a phase-locked oscillator according to the sixth embodiment, and shows a case where the CPU 15 generates a binary wave signal subjected to linearity calibration instead of generating a triangular wave signal. The configuration of the phase-locked oscillator may be the same as that shown in FIG. 1, FIG. 9 or FIG. In the figure, the VCO 5 in this example periodically outputs frequencies f1 and f2 alternately as time t progresses. The center frequency is f0. Such a phase-locked oscillator is suitable for application to a two-frequency CW radar device.

  18 and 19 are diagrams (1) and (2) for explaining the failure detection operation according to the embodiment. FIG. 18 (A) shows a case where the phase error signal Vpd is in an abnormal level during normal operation. . When this device is used for in-vehicle use, it is necessary to constantly monitor the operation state because it is related to human life. In the present embodiment, the lock error is detected when the phase error signal Vpd is out of the normal voltage range in which the PLL can be pulled in during normal operation.

  FIG. 18B shows a case where the central control voltage V0 during normal operation is at an abnormal level. Under severe use environment, the center frequency f0 (that is, the control voltage V0) may fluctuate significantly due to, for example, water intrusion into the casing or condensation. In the present embodiment, an abnormality in the VCO operation is detected when the control voltage V0 is out of the normal range during normal operation.

  FIG. 19 shows a case where the linearity calibration result when the power is turned on is abnormal. VCO characteristics also deteriorate with time. In this embodiment, when the apparatus is turned on or periodically, a PLL loop is formed and linearity calibration is performed. For example, Vcont measured values V0, V2, and V1 for f0, f2, and f1 when the power is turned on, and factory shipment When it is detected that any one or more of these values have deviated from a predetermined value or more by comparing these values with time, it is determined that there is an abnormality. In this example, it is compared whether the absolute voltage is within the specified range, but it may be compared whether the relative voltage value between the voltages is within the specified range.

  In FIG. 1, FIG. 9, or FIG. 12, when this circuit is used for a millimeter wave band FM-CW radar or the like, the millimeter wave band variable frequency divider 12 is used. When the frequency divider is difficult to obtain or expensive, the variable frequency divider 12 having a lower frequency may be used, and the output of the VCO 5 may be multiplied to the millimeter wave band by the frequency multiplier (MULTI) 7 and output. .

  Further, the signal generated by the CPU 15 can generate various signal waveforms (sine wave, sawtooth wave, etc.) in addition to the triangular wave signal and the binary wave signal.

  In the above embodiment, the modulation sensitivity of the VCO 5 is linearly approximated over the three measurement points f1, f0, and f2. However, the present invention is not limited to this. By increasing the number of measurement points, higher-precision approximation is possible, and the accuracy of linearity calibration can be increased.

  Moreover, in the said embodiment, although the modulation sensitivity in several area was represented by the linear approximation in each area, it is not restricted to this. The curve in each section may be approximated by a higher-order function or an exponential function that can be approximated more faithfully.

In the above embodiment, the clock signal CK of the phase comparison unit 2 and the CPU 15 is shared, but a clock signal of a different system may be used for the CPU 15.
(Multi radar system)
Hereinafter, a multi-radar system provided with a plurality of radars using the above-described phase-locked oscillator will be described.

  FIG. 20 is a diagram illustrating a schematic configuration example of a multi-radar system according to the seventh embodiment. The multi-radar system includes a plurality of FM-CW radars (hereinafter simply referred to as radars) 100-1, 100-2, 100-3, and 100-4 (hereinafter, when the radars are not distinguished from each other) Called). In the following description, a multi-radar system including four radars will be described as an example. However, the number of radars is not limited to four, and a plurality of radars can be provided as necessary. Further, the configuration of FIG. 20 is a multi-radar system as one apparatus equipped with a plurality of radars.

  One of the plurality of radars (for example, the radar 100-1) functions as the master radar M, and generates a synchronization signal according to the output of the triangular wave and outputs the synchronization signal, as will be described later. The remaining radars (for example, radars 100-2 to 100-4) function as slave radars S (S1 to S3) that receive a synchronization signal from the master radar M and output a triangular wave in accordance with the synchronization signal.

  FIG. 21 is a diagram illustrating a schematic configuration example of each radar. In each radar 100 constituting the multi-radar system, the oscillation unit 101 generates a transmission signal frequency-modulated with a triangular wave, and the transmission signal is radiated from the antenna. The oscillation unit 101 is a phase-locked oscillator according to the above-described embodiment of the present invention. The signal reflected by the target is received by the antenna as a reception signal, and mixed with the transmission signal by the mixer 102 to obtain a beat signal. The frequency of the transmission signal that has been frequency-modulated with a triangular wave changes with time, and the reception signal is a reflected wave of the transmission signal that was radiated only a round-trip time earlier. Use this to calculate the distance to the target. Further, in order to calculate the relative speed with the target, the fact that the reflected wave shifts in frequency due to the Doppler effect is used. The distance to the target and the relative speed with the target are obtained by analyzing the beat signal and using a known calculation method.

  FIG. 22 is a diagram illustrating a configuration of the oscillation unit 101 of each radar 100 in the multi-radar system according to the seventh embodiment. The oscillation unit 101-1 is the oscillation unit of the radar 100-1, the oscillation unit 101-2 is the oscillation unit of the radar 100-2, the oscillation unit 101-3 is the oscillation unit of the radar 100-3, and the oscillation unit 101-4 is The oscillation unit of the radar 100-4 is shown (when each oscillation unit is not distinguished, it is called the oscillation unit 101). Each oscillation unit 101 is configured by, for example, a phase-locked oscillator according to the first embodiment shown in FIG. The CPU 15-1 of the oscillator 101-1 of the radar 100-1 functioning as a master radar outputs a synchronization signal at a predetermined timing for generating a triangular wave.

  FIG. 23 is a diagram for explaining the output of the synchronization signal. As illustrated, for example, the synchronization signal is output for each period of the triangular wave.

  In FIG. 22, the synchronization signal output from the CPU 15-1 is the CPU 15- of each oscillation unit 101-2, 101-3, 101-4 of the radar 100-2, 100-3, 100-4 functioning as a slave radar. 2, 15-3, 15-4. And CPU15-2, 15-3, 15-4 also outputs a triangular wave synchronizing with a synchronizing signal.

  In FIG. 23, each CPU 15-1 to 15-4 (referred to as CPU 15 when not distinguishing each CPU) starts to output a triangular waveform control voltage Vcont when detecting the rising edge of the input synchronization signal, As a result, the transmission signal is frequency-modulated with a triangular wave shape of one cycle. By continuing to input the synchronization signal at a triangular wave period, the transmission signal is continuously subjected to triangular wave frequency modulation.

  As described above, the CPUs 15-1 to 15-4 and the like are provided as examples of triangular wave generating units that generate a plurality of synchronized triangular waves, and each of the plurality of triangular waves is used as a control signal according to each control signal. A plurality of VCOs that output a frequency-modulated signal, and a plurality of voltage-controlled oscillators output frequency-modulated signals having different center frequencies, and are generated based on at least one triangular wave By setting the output frequency so that the upper limit frequency of the frequency modulated signal generated based on at least one other triangular wave is larger than the lower limit frequency of the generated signal, each frequency modulated signal The frequency interval can be shortened.

  At this time, as shown in FIG. 24, all the other (one (the one closest to the center frequency)) and two (the one closest to the center frequency) are transmitted as multi-radars with respect to the lower limit frequency of one frequency-modulated signal. It is also possible to set the upper limit frequency of the frequency-modulated signal of the first and second closest) or higher) to be a high frequency.

  FIG. 24 is a diagram illustrating a frequency change of a transmission signal frequency-modulated in each oscillation unit 101. Since the triangular wave-like frequency change of each transmission signal is synchronized with the synchronization signal, the frequency of each transmission signal changes synchronously. That is, the timings of the upper limit frequency and the lower limit frequency by frequency modulation of each transmission signal coincide. The frequency increase / decrease direction also coincides.

  Further, in the frequency region of FIG. 24, the center frequency of each oscillating unit 101 is assigned with a predetermined frequency interval (channel interval) shifted, and the control voltage Vcont is controlled so that the frequency shift amount of the triangular wave modulation of each radar is constant. As a result, the frequency increase / decrease speeds coincide with each other, and the frequency interval is always constant at any timing.

  Therefore, in the case of adjacent transmission signals, even if the lower limit frequency of the higher center frequency is lower than the upper limit frequency of the lower center frequency, the frequencies of the transmission signals do not overlap and interfere with each other. Does not occur. For example, the lower limit frequency of the transmission signal of the oscillating unit 101-1 is lower than the upper limit frequency of the transmission signal of the oscillating unit 101-2 adjacent thereto, but the timing does not overlap, and the transmission signal of the oscillating unit 101-1 The transmission signal of the oscillation unit 101-2 does not interfere. Similarly, other transmission signals do not interfere with each other.

  In the multi-radar system according to the embodiment of the present invention, frequency modulation is performed using triangular waves synchronized with each other, and the frequency deviation amount of the modulation is matched, whereby the predetermined frequency interval (channel interval) does not depend on the frequency deviation amount. Channel setting is possible with.

  That is, more channels can be set in a certain frequency band without changing the amount of frequency shift of the transmission signal, and the frequency band can be used more effectively. In this specification, a frequency assigned to a transmission signal of a deployed radar may be referred to as a channel.

  The channel interval is determined in consideration of the items shown in Table 1 below.

  Specifically, when the usable frequency band is 1 GHz width of 76 GHz to 77 GHz (item 1), the frequency deviation between the reference signals which is the frequency error of the transmission signal of each radar (item 2), the steady state of the PLL circuit Considering frequency error (item 3), frequency deviation calibration error (item 5), Doppler deviation (item 7), frequency deviation due to round trip time (item 11), etc. The required channel spacing is twice (because each fluctuation width occurs in the vertical direction from the center frequency). In the example of Table 1, the value is twice the sum (3.7225 MHz) of the fluctuation ranges of items 2, 3, 5, 7, and 11, that is, about 7.45 MHz.

  Since the frequency shift amount is set to 200 MHz (item 4), in the frequency band 76 GHz to 77 GHz, the band in which the center frequency can be set is a 600 MHz band from 76.2 GHz to 76.8 GHz, and the channel interval is set to 7. Assuming 45 MHz, 81 channels can be set in this band.

  FIG. 25 is a diagram illustrating an example in which 81 channels are set in the frequency band of 76 GHz to 77 GHz. In the conventional case shown in FIG. 22 (c), when the band is 1 GHz and the frequency shift amount is 200 MHz, two channels cannot be set. However, in the embodiment of the present invention, 81 under almost the same conditions. Channels can be set, and the number of channels can be greatly increased.

  FIG. 26 is a diagram illustrating a schematic configuration example of a multi-radar system according to the eighth embodiment. The multi-radar system according to the eighth embodiment is a modification of the seventh embodiment in FIG. 20, and shows a case where a synchronization signal is supplied from the outside. Specifically, a synchronization signal having a triangular wave cycle is radiated from an external radio wave source using, for example, an AM broadcast or FM broadcast radio wave. A receiver 110 of the multi-radar system receives the radio wave, and a synchronization signal having a predetermined frequency included in the radio wave is supplied to each of the radars 100-1 to 100-4. As shown in the figure, the synchronization signal may be supplied to each of the slave radars 100-2 to 100-4 through the master radar 100-1, or from the receiver 110 to the master radars 100-1 to 100-4 in parallel. The structure supplied may be sufficient. Further, each radar 100 may include a receiver 110, and each radar may receive a synchronization signal. By supplying the synchronization signal from the outside, it is possible to eliminate the synchronization signal shift due to the individual difference between the individual master radars that generate the synchronization signal, and to synchronize the triangular wave among a plurality of multi-radar systems.

  In particular, when at least one radar is mounted on each of a plurality of vehicles to form a multi-radar system, a receiver 110 is mounted for each vehicle, and the radar of each vehicle is synchronized with the receiver 110. A triangular wave is output based on the signal. Thereby, the triangular wave of each radar in the multi-radar system composed of a plurality of spaced radars can be synchronized. In addition, the mounting of car navigation systems using GPS on vehicles has become widespread, and it has become easier to obtain GPS signals with vehicles. With this GPS signal, for example, a 1 pps signal output at intervals of 1 second can be used as a synchronization signal. In this case, since the 1 pps signal is output at 1 pulse per second, when the frequency of the triangular wave is 100 Hz, when the 1 pps signal is input, 100 pulses of the triangular wave may be output.

  FIG. 27 is a diagram illustrating a configuration example of the oscillation unit 101 in each radar of the multi-radar system according to the ninth embodiment. The multi-radar system according to the ninth embodiment is a modification of the seventh embodiment in FIG. 22 and shows a case where a reference signal is shared by each radar. Specifically, the clock oscillator 1 that generates the reference signal is shared by the oscillators of the radars. As a result, it is not necessary to consider the frequency deviation of the reference signal (item 2 in Table 1), and the channel frequency interval can be further reduced. Specifically, in the case of Table 1, about 7.45 MHz can be reduced to about 5.93 MHz ((3.7225 MHz−0.76 MHz) × 2 = 5.9225 MHz).

  FIG. 28 is a diagram illustrating a frequency allocation example of transmission signals of each radar in the multi-radar system according to the ninth embodiment. In FIG. 28, as an example, four radars are mounted on each of four vehicles A, B, C, and D, and the clock oscillators 1 of the four radars in one vehicle are shared. Thus, the frequency interval in each vehicle can be 5.93 MHz, and the frequency interval between vehicles is about 7.45 MHz.

  FIG. 29 is a diagram illustrating a configuration example of the oscillation unit 101 in each radar of the multi-radar system according to the tenth embodiment. The multi-radar system according to the tenth embodiment is a modification of the seventh embodiment shown in FIG. 22, eliminates the master radar and the slave radar, and generates and outputs a synchronization signal independent of the CPU 15. A synchronization signal control unit (synchronization signal generation means) 111 is provided. The synchronization signal generated by the synchronization signal control unit 111 is supplied to each of the radars 100-1 to 100-4. In addition, the synchronization signal control unit 111 performs centralized detection of any abnormality or failure related to the synchronization signal, such as stop of input / output of the synchronization signal.

  FIG. 30 is a diagram illustrating an application example in which the frequency band of the channel is divided according to the traveling direction of the vehicle. When the multi-radar system according to the embodiment of the present invention is applied to a vehicle of an automobile, when two vehicles pass each other and the channels assigned to the radars of the vehicles are the same, transmission from the other radar is performed. The signal is not received and correct measurement cannot be performed. Therefore, as an example, as shown in FIG. 30, the frequency band is divided into an upstream band and a downstream band, and a channel of a band corresponding to the traveling direction of the vehicle is allocated. The traveling direction of the vehicle is acquired using, for example, information on a direction detected by a GPS system mounted on the vehicle. An uplink band channel is allocated to a vehicle traveling in the upward direction, and a downlink band channel is allocated to a vehicle traveling in the downward direction. Thereby, the channel of two vehicles which adjoin by passing each other does not become the same. Note that if the same channel is assigned to two vehicles traveling in the same direction, the possibility that the radio waves of the radars mounted on the two vehicles will be close enough to interfere with each other is compared to the case of passing each other. Low enough. Therefore, as shown in FIG. 30, when the frequency band to which the channel is allocated is divided and the traveling direction of the vehicle is different and there is a high possibility that the vehicles are close to each other such as passing each other, the channel of the different frequency band is allocated depending on the traveling direction of the vehicle. When there is a low possibility that vehicles are close to each other, substantially the same channel can be used by a plurality of vehicles.

  FIG. 31 is a diagram illustrating another application example in which the frequency band of the channel is divided according to the traveling direction of the vehicle. FIG. 31 is an example of dividing into four directions instead of the two directions in FIG. 30. For example, frequency bands are divided in four directions of east, west, south, and north, and channels of different frequency bands are assigned depending on the traveling direction of the vehicle. The directions to be divided are not limited to two directions or four directions, and may be divided more finely, for example, eight directions.

  Each radar constituting the multi-radar system in the embodiment of the present invention is not limited to the FM-CW radar. For example, each radar may be a two-frequency CW radar, and in the case of a two-frequency CW radar, the two frequencies assigned to each radar are different for each radar, and the frequency switching timing is matched for each radar. Thus, interference between transmission signals can be suppressed.

  FIG. 32 is a diagram illustrating an example of frequency allocation in a multi-radar system using a two-frequency CW radar. Hereinafter, the two-frequency CW radar is also simply referred to as a radar, and the reference number 100 is used. In FIG. 32A, the frequency switching timings of the transmission signals of the radars are matched. Thereby, even if the frequency allocated to each radar 100 is in the band between the two frequencies allocated to other radars, the frequencies do not overlap each other. Note that, at the frequency switching timing, the frequencies of the radars instantaneously overlap each other, but the signal at the switching timing is masked and not subjected to signal processing. FIG. 32B is an example of frequency allocation in which interference does not occur even at the frequency switching timing. The switching timing is shifted for each radar so that the frequencies do not overlap. This eliminates the need for mask processing at the frequency switching timing. FIG. 32C shows the frequency switching direction of the radars 100-1 and 100-2 at the frequency switching timing and the frequency switching of the radars 100-3 and 100-4 in the plurality of radars 100-1 to 100-4. In this example, the directions are different from each other. Thereby, the number of channels that can be allocated to the frequency band can be further increased, and the frequency utilization efficiency is improved. Compared to FIGS. 32A and 32B in which the frequency is switched only in the same direction, the number of channels can be increased by a maximum of two times.

  FIG. 33 is a diagram illustrating a large-scale frequency arrangement example of a multi-radar system using a two-frequency CW radar. The frequency band is divided into a plurality of groups, and the frequency arrangement example shown in FIG. 32C is applied to each group. That is, in each group, a plurality of channels having the same frequency switching timing but different frequency switching directions are set.

  FIG. 34 is a diagram illustrating a schematic configuration example of a multi-radar system using a two-frequency CW radar. In the configuration example of FIG. 34, as in the configuration example of FIG. 20, a synchronization signal is output from the master radar to the slave radar at the frequency switching timing, and the slave radar switches the frequency in synchronization with the synchronization signal. The radar can switch the frequency in synchronization. The master radar supplies a polarity signal POL that determines the frequency switching direction to the slave radar. The polarity signal is a signal whose H / L level changes at a frequency switching period, and the frequency switching direction is determined according to the level of the polarity signal. For example, when each slave radar receives a synchronization signal while an H level polarity signal is being supplied, the slave radar switches to a higher one of the two frequencies and is synchronized with an L level polarity signal being supplied. When a signal is received, it switches to a lower frequency. Similar to the embodiment in the FM-CW radar, the polarity signal and the synchronization signal may be supplied from the outside, and the master radar may receive the signal and supply it to the slave radar. A configuration in which each radar receives a polarity signal and a synchronization signal from the outside without distinguishing between the radar and the slave radar may be employed.

  Although a plurality of embodiments suitable for the present invention have been described, it goes without saying that various changes in the configuration, control, processing, and combination of each part can be made without departing from the spirit of the present invention.

(Appendix 1)
A phase comparator that compares the phase of the reference signal and the comparison signal, a low-pass filter that integrates the phase error signal of the phase comparator, and a control unit that performs the main control of the instrument by interposing the latter stage of the low-pass filter; A phase locked loop including a PLL loop including a VCO circuit that generates a signal having a frequency according to a control voltage of the control unit output, and a variable frequency divider that divides the output signal of the VCO circuit to form the comparison signal. An oscillator, wherein the controller is
Control voltage measuring means for locking the PLL loop at a plurality of frequencies and measuring a control voltage at each lock;
A phase-locked oscillator comprising: linearity calibration means for obtaining a modulation sensitivity representing a frequency change in a section connecting the frequencies based on the measured control voltages.

(Appendix 2)
A voltage for causing the VCO circuit to generate a linearity-corrected frequency change centered on the predetermined frequency based on the obtained modulation sensitivity in a state where the PLL loop is opened after the PLL loop is locked. The phase-locked oscillator according to claim 1, further comprising a VCO driving means for generating and outputting a signal (Appendix 3)
The VCO driving means samples the output of the low-pass filter in synchronization with the timing at which the VCO circuit outputs the center frequency, and when the detected phase error signal exceeds a predetermined range, the control voltage is set to decrease the phase error signal. The phase-locked oscillator according to claim 2, wherein the phase-locked oscillator is offset.

(Appendix 4)
A first divider that divides the reference signal; and a second divider that divides the output of the VCO circuit to form the comparison signal;
The VCO driving means periodically resets the counters of the first and second frequency dividers at an integer multiple of the signal period applied to the VCO circuit, and is synchronized with the timing at which the VCO circuit outputs the center frequency. 3. The phase locked oscillator according to claim 2, wherein when the phase error signal of the low-pass filter output sampled exceeds a predetermined range, the control voltage is offset in a direction to reduce the phase error signal.

(Appendix 5)
A first variable frequency divider that divides the reference signal; and a second variable frequency divider that divides the output of the VCO circuit to form the comparison signal. When a predetermined frequency division ratio is set in the second variable frequency divider, a PLL loop is formed to start phase pull-in between the reference signal and the comparison signal, and the VCO circuit corresponds to the predetermined frequency division ratio. 3. The phase-locked oscillator according to claim 1, wherein the control voltage is applied and the counters of the first and second variable frequency dividers are reset.

(Appendix 6)
A phase comparator that compares the phase of the reference signal and the comparison signal, a low-pass filter that integrates the phase error signal of the phase comparator, and a control unit that performs the main control of the instrument by interposing the latter stage of the low-pass filter; A phase locked loop including a PLL loop including a VCO circuit that generates a signal having a frequency corresponding to a control voltage of the control unit output, and a variable frequency divider that divides the output signal of the VCO circuit to form the comparison signal. An oscillator, wherein the controller is
A control voltage measuring means for changing a lock frequency of the PLL at a predetermined interval and measuring a control voltage at the time of each lock for a range covering a predetermined frequency range;
A linearity calibration means for dividing the measured variation range of the control voltage into a plurality of sections and obtaining a modulation sensitivity representing each section;
After the PLL loop is locked at a predetermined frequency, a voltage signal for generating a linearity-corrected frequency change centered on the predetermined frequency in the VCO circuit with the PLL loop opened is controlled at the time of the lock. A phase-locked oscillator comprising: a VCO driving unit that generates and outputs a voltage based on a voltage and a modulation sensitivity representing each of the obtained intervals.

(Appendix 7)
In a multi-radar system configured to include a plurality of FM-CW radars having the phase-locked oscillator according to any one of appendices 1 to 6,
The control unit of each FM-CW radar generates the control voltage that is a control voltage that periodically increases and decreases and that is synchronized with a predetermined synchronization signal so that the increasing and decreasing directions and increasing and decreasing speeds of the control voltage coincide with each other. ,
The VCO circuit of each FM-CW radar is a signal whose frequency is periodically increased or decreased with respect to the center frequency according to the increase or decrease of the control voltage, and the center frequency of each signal is A multi-radar system, characterized in that the signals differing from each other and further having the same frequency increasing / decreasing direction and increasing / decreasing speed coincide with each other.

(Appendix 8)
In Appendix 7,
One of the control units of each FM-CW radar generates the synchronization signal and outputs it to the remaining control units.

(Appendix 9)
In Appendix 7,
One of the control units of each FM-CW radar receives a synchronization signal supplied from the outside, and outputs it to the remaining control units.

(Appendix 10)
In Appendix 7,
The multi-radar system, wherein the control unit of each FM-CW radar receives a synchronization signal supplied from outside.

(Appendix 11)
In Appendix 7,
The multi-radar system, wherein the reference signal is common to each FM-CW radar.

(Appendix 12)
In Appendix 7,
A multi-radar system comprising synchronization signal generation means for generating the synchronization signal, wherein the synchronization signal generated by the synchronization signal generation means is supplied to each control unit.

(Appendix 13)
In a multi-radar system including a plurality of radars that generate and output a signal whose frequency periodically increases and decreases,
Each radar has a predetermined synchronization signal so that the upper and lower limits of the frequency that periodically increase and decrease are different from each other for each radar signal, and the timing at which the upper and lower limits are almost coincident with each other. A multi-radar system that generates the signal in synchronization with

(Appendix 14)
In Appendix 13,
Each radar generates the signal in synchronization with a predetermined synchronizing signal so that the frequency increasing / decreasing direction and speed of the signal coincide with each other.

(Appendix 15)
In Appendix 13,
One of the plurality of radars generates the synchronization signal and outputs it to the remaining radars.

(Appendix 16)
In Appendix 13,
A multi-radar system, wherein one of the plurality of radars receives a synchronization signal supplied from the outside and outputs it to the remaining radars.

(Appendix 17)
In Appendix 13,
The multi-radar system, wherein the plurality of radars receive a synchronization signal supplied from the outside.

(Appendix 18)
In Appendix 13,
The plurality of radars are mounted on each of the plurality of vehicles, and the radar mounted on the vehicle traveling in the first direction generates a signal having a frequency included in the first frequency band. A radar system mounted on a vehicle traveling in a second direction different from the direction generates a signal of a frequency included in a second frequency band different from the first frequency band.

(Appendix 19)
A triangular wave generator for generating a plurality of synchronized triangular waves;
Each of the plurality of triangular waves as a control signal, a plurality of voltage control oscillators that output a signal frequency-modulated according to the control signal,
The plurality of voltage controlled oscillators output frequency-modulated signals having different center frequencies from each other, and with respect to a lower limit frequency of the frequency-modulated signal generated based on at least one triangular wave, The output frequency is set so that the upper limit frequency of the frequency-modulated signal generated based on at least one other triangular wave is increased.
A multi-radar system characterized by that.

1 is a block diagram of a phase locked oscillator according to a first embodiment. FIG. It is a flowchart of the control voltage measurement process by 1st Embodiment. It is a timing chart of control voltage measurement operation by a 1st embodiment. It is a flowchart of the linearity calibration process by 1st Embodiment. It is a timing chart of the linearity calibration operation | movement by 1st Embodiment. It is a flowchart of the radar transmission process by 1st Embodiment. It is a timing chart of radar transmission operation by a 1st embodiment. It is a timing chart of radar operation operation by a 1st embodiment. It is a block diagram of the phase locked oscillator by 2nd Embodiment. It is a flowchart of the high-speed drawing-in process of the phase-locked oscillator by 2nd Embodiment. 6 is a timing chart of a high-speed pull-in operation of the phase-locked oscillator according to the second embodiment. FIG. 5 is a block diagram of a phase locked oscillator according to a third embodiment. 10 is a timing chart of the operation of the phase-locked oscillator according to the third embodiment. It is a figure explaining the phase locked oscillator by 4th Embodiment. It is a figure (1) explaining the phase locked oscillator by 5th Embodiment. FIG. 10 is a diagram (2) illustrating a phase locked oscillator according to a fifth embodiment. It is a figure explaining the phase locked oscillator by 6th Embodiment. It is a figure (1) explaining the failure detection operation by an embodiment. It is FIG. (2) explaining the failure detection operation | movement by embodiment. It is a figure which shows the schematic structural example of the multi-radar system by 7th Embodiment. It is a figure which shows the example of schematic structure of each radar. It is a figure which shows the structure of the oscillation part 101 of each radar 100 in the multi radar system by 7th Embodiment. It is a figure explaining the output of a synchronizing signal. FIG. 6 is a diagram illustrating a frequency change of a transmission signal that is frequency-modulated in each oscillation unit 101. It is a figure which shows the example by which 81 channels were set to the frequency band of 76 GHz-77 GHz. It is a figure which shows the schematic structural example of the multi-radar system by 8th Embodiment. It is a figure which shows the structural example of the oscillation part 101 in each radar of the multi radar system by 9th Embodiment. It is a figure which shows the example of frequency allocation of the transmission signal of each radar in the multi-radar system in 9th Embodiment. It is a figure which shows the structural example of the oscillation part 101 in each radar of the multi radar system by 10th Embodiment. It is a figure which shows the application example which divides | segments the frequency band of a channel according to the advancing direction of a vehicle. It is a figure which shows another application example which divides | segments the frequency band of a channel according to the advancing direction of a vehicle. It is a figure which shows the example of a frequency allocation in the multi radar system by 2 frequency CW radar. It is a figure which shows the example of a large-scale frequency arrangement | positioning of the multi radar system by 2 frequency CW radar. It is a figure which shows the example of schematic structure of the multi-radar system by 2 frequency CW radar. It is a figure explaining a prior art. It is a figure explaining the frequency allocation of each of several radar in the conventional multi-radar system. It is a figure explaining the fluctuation | variation of the center frequency and frequency shift of a transmission signal.

Explanation of symbols

1 Clock Oscillator 2 Phase Comparison Unit 3 Low Pass Filter (LPF)
4 Processor unit (PU)
5 Voltage controlled oscillator (VCO)
6 RF switch (SW)
7 Frequency multiplier 11, 12 Variable frequency divider 13 Phase comparator (PD)
14 A / D converter 15 CPU
16 D / A converter 100 Radar 101 Oscillator 102 Mixer 110 Receiver 111 Synchronization signal controller

Claims (5)

In a multi-radar system including a plurality of radars that generate and output a modulation signal that is frequency-modulated so that the frequency is periodically increased or decreased using each of the synchronized triangular waves as a control signal ,
The modulation signals output by the radars have different center frequencies, and the upper and lower limits of the frequency that periodically increases and decreases are different for each modulation signal output by the radar and have timings that become the upper and lower limits. each modulated signal is output in synchronization with the predetermined synchronization signal to match so to each other,
Further, the upper limit frequency of another modulation signal generated based on at least one other triangular wave is set to be larger than the lower limit frequency of the modulation signal generated based on at least one triangular wave. A featured multi-radar system. In claim 1,
Each radar generates the modulation signal in synchronization with a predetermined synchronization signal so that the frequency increase / decrease direction and speed of the modulation signal coincide with each other. In claim 1,
One of the plurality of radars generates the synchronization signal and outputs it to the remaining radars. In claim 1,
A multi-radar system, wherein one of the plurality of radars receives a synchronization signal supplied from the outside and outputs it to the remaining radars. In claim 1,
The plurality of radars are mounted on each of the plurality of vehicles, and the radar mounted on the vehicle traveling in the first direction generates a modulation signal having a frequency included in the first frequency band. A radar mounted on a vehicle traveling in a second direction different from the first direction generates a modulation signal having a frequency included in a second frequency band different from the first frequency band. system.

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