JP2013042244A - Oscillation circuit and electronic apparatus using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a spectral peak.SOLUTION: An oscillation circuit 2 receives a reference clock signal CKto generate an output clock signal CK. A programmable frequency divider 18 whose frequency division ratio is switchable to at least two values divides the frequency of the output clock signal CKat the set frequency division ratio to generate a frequency-divided clock signal CK. A phase comparator 10 generates a phase difference signal S1 depending on a phase difference between the reference clock signal CKand the frequency-divided clock signal CK. A loop filter 12 smooths the phase difference signal S1. A VCO (voltage-controlled oscillator) 14 oscillates at a frequency depending on a phase difference signal S2 output from the loop filter 12 to generate the output clock signal CK. A control section 20 switches the frequency division ratio of the programmable frequency divider 18 on a time division basis to spread the spectrum of the output clock signal CK.

Description

  The present invention relates to an oscillation circuit.

  Microcomputers, switching power supplies, motor drivers, liquid crystal drivers, and the like mounted on electronic devices such as home appliances and video devices operate in synchronization with a clock signal. On the other hand, such electronic devices are required to have sufficient EMI (Electro Magnetic Interference) measures. In particular, due to recent advances in wireless communication technology, the demand for EMI countermeasures is increasing.

In some cases, the spectrum of the clock signal is intentionally spread as an EMI countermeasure. FIG. 1 is a circuit diagram showing a PLL circuit capable of spread spectrum studied by the present inventors. The PLL circuit 2r receives the reference clock signal CK _REF and generates an output clock signal CK _OUT . The PLL circuit 2r includes a phase comparator 10, a loop filter 12, a VCO (Voltage Controlled Oscillator) 14, a frequency divider 16, and a modulator 30.

The frequency divider 16 _divides the output clock signal CK _OUT having the frequency f _OUT by the frequency division ratio M, and generates the _divided clock signal CK _DIV having the frequency f _DIV (= f _OUT / M). The phase comparator 10 generates a phase difference signal S1 corresponding to the phase difference between the reference clock signal CK _OUT and the _divided clock signal CK _DIV . The loop filter 12 smoothes the phase difference signal S1.

  The modulator 30 includes a modulation signal generation unit 30a and a superimposing circuit 30b, and modulates the input voltage of the VCO 14. The modulation signal generation unit 30a generates a modulation signal S3 that changes periodically. The superimposing circuit 30b superimposes the modulation signal S3 on the phase difference signal S2 output from the loop filter 12.

The VCO 14 oscillates at a frequency corresponding to the phase difference signal S4 on which the modulation signal S3 is superimposed, and generates an output clock signal CK _OUT . If a linearly changing triangular wave signal is used as the modulation signal S3, the spectrum peak can be suppressed.

JP 2006-95330 A

  However, since the input voltage of the VCO changes sharply at the peak and bottom of the triangular wave signal, this sharp change causes another peak in the spectrum.

  In the middle of the slope of the triangular wave signal, the PLL circuit is locked for a moment and the operation of releasing the lock is repeated. The present inventor has come to recognize that when the PLL circuit locks, the input voltage of the VCO is distorted, which causes a peak in the spectrum.

  The present invention has been made in view of these problems, and one of exemplary objects of an embodiment thereof is to provide an oscillation circuit in which a spectrum peak is suppressed.

  One embodiment of the present invention relates to an oscillation circuit that receives a reference clock signal and generates an output clock signal. The oscillation circuit is configured so that the division ratio can be switched between at least two values, the output clock signal is divided by a set division ratio, and a programmable divider that generates the divided clock signal, a reference clock signal, A phase comparator that generates a phase difference signal corresponding to the phase difference of the divided clock signal, a loop filter that smoothes the phase difference signal, and an oscillator that outputs at a frequency corresponding to the phase difference signal output from the loop filter A VCO (voltage controlled oscillator) that generates a clock signal, and a control unit that spreads the spectrum of the output clock signal by switching the frequency division ratio of the programmable frequency divider in a time-division manner.

  According to this aspect, the lock frequency of the oscillation circuit changes according to the switching of the division ratio. As a result, the frequency of the output clock signal gradually changes between a plurality of lock frequencies corresponding to each division ratio, and the spectrum can be spread.

The control unit may switch the frequency division ratio of the programmable frequency divider so that the oscillation circuit does not lock.
By not locking the oscillation circuit, distortion due to the lock can be removed, so that the spectrum peak can be reduced.

  The period at which the control unit switches the frequency division ratio of the programmable frequency divider may be shorter than the lock time of the oscillation circuit. The period at which the control unit switches the frequency division ratio of the programmable frequency divider may be shorter than the time constant of the loop filter.

The control unit may switch the division ratio of the programmable frequency divider so that the input voltage of the VCO changes linearly.
By making the period for switching the frequency division ratio shorter than the time constant of the loop filter, the input voltage of the VCO changes linearly, and its waveform becomes close to a triangular wave. Thereby, distortion can be further reduced.

  Another embodiment of the present invention relates to an electronic device. This electronic device includes any one of the above-described oscillation circuits and a processor that operates in response to an output clock signal generated by the oscillation circuit.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, the spectrum peak of the oscillation circuit can be suppressed.

FIG. 3 is a circuit diagram showing a PLL circuit capable of spread spectrum studied by the present inventors. It is a circuit diagram which shows the structure of the oscillation circuit which concerns on embodiment. FIGS. 3A and 3B are operation waveform diagrams of the first and second control methods, respectively. FIGS. 4A and 4B are diagrams showing measured values of the spectrum of current consumption of the oscillation circuit in the first and second control methods, respectively. It is a block diagram which shows the structure of an electronic device provided with the oscillation circuit of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

FIG. 2 is a circuit diagram showing a configuration of the oscillation circuit 2 according to the embodiment. The oscillation circuit 2 receives the reference clock signal CK _REF and generates an output clock signal CK _OUT . The oscillation circuit 2 includes a phase comparator 10, a loop filter 12, a VCO 14, a programmable frequency divider 18, and a control unit 20.

The programmable frequency divider 18 is configured so that the frequency division ratio can be switched between at least two values. In the present embodiment, it is assumed that the frequency division ratio is switched between two values of M1 and M2. The programmable frequency divider 18 _divides the output clock signal CK _OUT having the frequency f _OUT by a set value of the frequency division ratios M1 and M2, and generates the _divided clock signal CK _DIV having the frequency f _DIV . That is, when the frequency division ratio is M1, f _DIV = f _OUT / M1, and when the frequency division ratio is M2, f _DIV = f _OUT / M2. The phase comparator 10 generates a phase difference signal S1 corresponding to the phase difference between the reference clock signal CK _OUT and the _divided clock signal CK _DIV . The loop filter 12 smoothes the phase difference signal S1.

The VCO 14 oscillates at a frequency corresponding to the phase difference signal (also referred to as control voltage) S2 smoothed by the loop filter 12, and generates an output clock signal CK _OUT .

The control unit 20 switches the frequency division ratio of the programmable frequency divider 18 in a time division manner, thereby spreading the spectrum of the output clock signal CK _OUT . As will be described later, the control unit 20 switches the frequency division ratio of the programmable frequency divider 18 by the first control method or the second control method.

  The above is the configuration of the oscillation circuit 2. Next, the operation will be described.

  FIGS. 3A and 3B are operation waveform diagrams of the first and second control methods, respectively. The upper stage shows the frequency division ratio M set in the programmable frequency divider 18, and the lower stage shows the control voltage S2 input to the VCO 14. FIGS. 4A and 4B are diagrams showing measured values of current consumption spectra of the oscillation circuit 2 in the first and second control methods, respectively.

First, the first control method will be described with reference to FIGS. 3 (a) and 4 (a). In the first control method, as shown in FIG. 3A, after the division ratio is set to a certain value and the oscillation circuit 2 is locked, the operation of switching the division ratio to another value is repeated. That is, the oscillation circuit 2 is locked, and repeat the unlock state, period T _S for switching the dividing ratio M of the control unit 20 is programmable divider 16 is substantially the lock time of the oscillation circuit 2 T _L It is about the same or longer.

  In the first control method, the control voltage S2 for the VCO 14 transitions between two voltages V1 and V2 corresponding to the two frequency division ratios M1 and M2. The voltage waveform is a waveform corresponding to the time constant of the loop filter 12.

  According to the first control method, the control voltage S2 with respect to the VCO 14 can be temporally varied, so that the spectrum can be spread as shown in FIG.

(Second control method)
In many applications, the first control method can provide sufficient characteristics, but the second control method is effective for spreading the spectrum more suitably.

In the first control method, the oscillation circuit 2 repeatedly locks and unlocks. On the other hand, in the second control method, the control unit 20 switches the frequency division ratio M of the programmable frequency divider 16 with a shorter cycle than the first control method so that the oscillation circuit is not locked. In other words, the frequency division ratio M of the switches period T _S of the control unit 20 is programmable divider 16 is shorter than the locking time of the oscillation circuit 2 T _L. Viewed from another perspective, the division ratio M of the switches period T _S of the control unit 20 is programmable divider 16 is shorter than the time constant of the loop filter 12.

  According to the second control method, similarly to the first control method, the input voltage S2 of the VCO 14 can be temporally changed, and the spectrum can be spread.

  In the first control method, an unnecessary peak occurs in the spectrum due to waveform distortion of the control voltage S2 when the oscillation circuit 2 is locked. On the other hand, in the second control method, the peak of the spectrum can be suppressed as compared with the first control method by operating the oscillation circuit 2 without locking.

In the second control method, the control unit 20 at period T _S as a control voltage S2 for VCO12 is linearly changed, may switch the dividing ratio M of the programmable frequency divider 16. When the loop filter 12 is formed of a CR filter, the control voltage S2 changes exponentially as shown in FIG. 3A, and the control voltage S2 immediately after switching the frequency division ratio M can be linearly approximated. That is, by setting sufficiently shorter than the CR time constant period T _S switching of the frequency dividing ratio M, the control voltage S2 is linearly changed as shown in FIG. 3 (b), close to a triangular wave. Thereby, the peak of a spectrum can be suppressed further than the 1st control method.

The above is the operation of the oscillation circuit 2. Subsequently, a suitable application of the oscillation circuit 2 will be described.
FIG. 5 is a block diagram illustrating a configuration of the electronic apparatus 1 including the oscillation circuit 2 of FIG.
The electronic device 1 includes a speaker SPK, a microphone MIC, an oscillation circuit 2, a front end IC (Integrated Circuit) 4, and a DSP (Digital Signal Processor) 6.

  The electronic device 1 is a device having audio playback and recording functions such as a mobile phone terminal, a digital camera, and an audio player.

  The microphone MIC converts the input acoustic signal into an analog electrical signal (analog audio signal) S10. The front end IC 4 receives the analog audio signal S10 and converts it into a digital audio signal S12 by the A / D converter 42. The interface circuit 44 transmits the digital audio signal S14 to the DSP 6 via the bus 5.

  The interface circuit 44 of the front end IC 4 receives the digital audio signal S22 reproduced by the DSP 6. The D / A converter 46 converts the received digital audio signal S24 into an analog audio signal S26. The analog audio signal S26 is output to the speaker SPK through an amplifier or the like (not shown).

The DSP 6 is a CODEC (Code-DECode) -IC that performs encoding and decoding of a digital audio signal, and has a recording function and a reproduction function.
The interface circuit 62 of the DSP 6 receives the digital audio signal S14 from the front end IC4. The CODEC circuit 64 receives the digital audio signal S16 (S14) transmitted from the front end IC 4, compresses and encodes it into a predetermined format, and stores it in a memory (not shown) (recording function).

  The CODEC circuit 64 reads a digital audio signal stored in a memory (not shown), decodes the read data, and converts it into a digital audio signal S20. The interface circuit 62 transmits the digital audio signal S20 to the front end IC 4 via the bus 5 (reproduction function).

  Here, the clock signal CK1 supplied to the A / D converter 42 and the D / A converter 46 of the front-end IC 4 is required to have low jitter for recording and reproduction with high sound quality.

  The clock signals CK2a and CK2b supplied to the interface circuit 44 of the front end IC 4 and the interface circuit 62 of the DSP 6 are required to be synchronized with each other.

On the other hand, other digital arithmetic processing such as encoding, decoding processing, equalizing processing, and filtering processing performed in the CODEC circuit 64 is highly independent from other circuits, and therefore, a clock signal supplied thereto A certain amount of jitter is allowed for CK3. The oscillation circuit 2 according to the embodiment can be suitably used for the purpose of supplying the clock signal CK3 (CK _OUT ) to the CODEC circuit 64.

The oscillation circuit 2 may be provided outside the DSP 6 or may be built in the DSP 6. Further, the A / D converter 42 and the D / A converter 46 of the front end IC 4 may be built in the DSP 6. In this case, the interface circuit 44 and the interface circuit 62 are unnecessary. Even in this case, the clock signal CK2 of CODEC circuit 64, low-jitter property because they are not required, available clock signal _{CK OUT} of the oscillation circuit 2 is generated.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 ... Electronic device, 2 ... Oscillator circuit, 10 ... Phase comparator, 12 ... Loop filter, 14 ... VCO, 16 ... Divider, 18 ... Programmable divider, 20 ... Control part, 30 ... Modulator, 30a ... Modulation signal generation unit, 30b... Superposition circuit.

Claims (6)

An oscillation circuit that receives a reference clock signal and generates an output clock signal,
A programmable frequency divider configured to generate a divided clock signal by dividing the output clock signal by a set frequency dividing ratio, the frequency dividing ratio being configured to switch between at least two values;
A phase comparator that generates a phase difference signal according to a phase difference between the reference clock signal and the divided clock signal;
A loop filter for smoothing the phase difference signal;
A VCO (voltage controlled oscillator) that oscillates at a frequency corresponding to the phase difference signal output from the loop filter and generates the output clock signal;
A control unit that spreads the spectrum of the output clock signal by switching the frequency division ratio of the programmable frequency divider in a time-division manner;
An oscillation circuit comprising:   The oscillation circuit according to claim 1, wherein the control unit switches a frequency division ratio of the programmable frequency divider so that the oscillation circuit is not locked.   3. The oscillation circuit according to claim 1, wherein a period at which the control unit switches a division ratio of the programmable frequency divider is shorter than a lock time of the oscillation circuit.   3. The oscillation circuit according to claim 1, wherein a period at which the control unit switches a frequency dividing ratio of the programmable frequency divider is shorter than a time constant of the loop filter.   5. The oscillation circuit according to claim 1, wherein the control unit switches a frequency dividing ratio of the programmable frequency divider so that an input voltage of the VCO changes linearly. An oscillation circuit according to any one of claims 1 to 5,
A processor that operates in synchronization with an output clock signal generated by the oscillation circuit;
An electronic device comprising:

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