JP5307531B2 - Dielectric thin film element manufacturing method - Google Patents
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本発明は、誘電体薄膜素子の製造方法に関する。 The present invention relates to a method for manufacturing a dielectric thin film element.
誘電体薄膜素子の誘電率を向上させるために熱処理することが知られているが、この熱処理時に誘電体薄膜にクラックが発生すると、リーク電流が増大しリーク特性が劣化する傾向がある。そこで、クラック発生を抑制するため、例えば以下の特許文献１には、基板上に電極が形成され、この電極の上に誘電体薄膜が形成された誘電体薄膜素子において、誘電体薄膜の熱膨張係数が基板の熱膨張係数より小さくなるように構成することが記載されている。
しかしながら、特許文献１のように誘電体薄膜の熱膨張係数が基板の熱膨張係数より小さくなるよう誘電体薄膜及び基板の材料を選択したとしても、例えば、基板の焼結温度などの製造条件や基板への加熱処理などの前処理条件などによっては、誘電体薄膜のクラック発生の有無が大きく異なる場合があるという問題があった。 However, even if the dielectric thin film and the material of the substrate are selected so that the thermal expansion coefficient of the dielectric thin film is smaller than the thermal expansion coefficient of the substrate as in Patent Document 1, for example, manufacturing conditions such as the sintering temperature of the substrate, Depending on pretreatment conditions such as heat treatment of the substrate, the presence or absence of cracks in the dielectric thin film may vary greatly.
本発明は、上記問題点を鑑みてなされたものであり、クラック発生を抑制できる誘電体薄膜素子の製造方法を提供することを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a dielectric thin film element that can suppress the occurrence of cracks.
鋭意研究を重ねた結果、クラック発生には、誘電体薄膜の熱膨張係数と、この誘電体薄膜を保持するための基板などの保持部材の熱膨張係数との関係よりも、誘電体薄膜の膜厚と、保持部材のビッカース硬度との関係が大きく影響していることが見出された。例えば、同じ熱膨張係数を持つＮｉ箔基板に同じ膜厚の誘電体を形成しても、Ｎｉ箔のビッカース硬度の違いにより、誘電体のクラック有無が大きく異なる。 As a result of intensive research, the occurrence of cracks is caused by the fact that the film of the dielectric thin film is less than the relationship between the coefficient of thermal expansion of the dielectric thin film and the coefficient of thermal expansion of the holding member such as a substrate for holding the dielectric thin film. It has been found that the relationship between the thickness and the Vickers hardness of the holding member has a great influence. For example, even if a dielectric having the same film thickness is formed on a Ni foil substrate having the same thermal expansion coefficient, the presence or absence of cracks in the dielectric varies greatly due to the difference in the Vickers hardness of the Ni foil.
そこで、本発明に係る誘電体薄膜素子の製造方法は、上記課題を解決するために、誘電体薄膜を、当該誘電体薄膜を保持する保持部材が含まれる基体上に形成する形成工程を備え、αを前記保持部材の前記形成工程開始時のビッカース硬度（ＨＶ）とし、ｔを前記誘電体薄膜の膜厚（μｍ）としたとき、
α×ｔ≦１５０
の関係を満たすことを特徴とする。
Therefore, in order to solve the above problems, a method for manufacturing a dielectric thin film element according to the present invention includes a forming step of forming a dielectric thin film on a substrate including a holding member that holds the dielectric thin film. α is Vickers hardness (HV) at the start of the forming step of the holding member, and t is the film thickness (μm) of the dielectric thin film.
α × t ≦ 150
It is characterized by satisfying the relationship.
このような誘電体薄膜素子の製造方法によれば、クラック発生を抑制することができる。 According to such a method for manufacturing a dielectric thin film element, the generation of cracks can be suppressed.
ここで、形成工程において形成された誘電体薄膜を加熱する加熱工程を備えることが好適である。これにより、誘電体薄膜素子の誘電率を向上できる。 Here, it is preferable to include a heating step of heating the dielectric thin film formed in the forming step. Thereby, the dielectric constant of a dielectric thin film element can be improved.
また、誘電体薄膜素子の構成としては、保持部材が基板であり、基体が、基板と、当該基板上に形成される下部電極とを含むのが好適であり、この場合、形成工程において、誘電体薄膜は下部電極上に形成される。同様に、誘電体薄膜素子の構成として、保持部材が、下部電極を兼ねる金属箔であるのも好適であり、この場合、形成工程において、誘電体薄膜は金属箔上に形成される。 Further, as a configuration of the dielectric thin film element, it is preferable that the holding member is a substrate, and the base includes a substrate and a lower electrode formed on the substrate. The body thin film is formed on the lower electrode. Similarly, as a configuration of the dielectric thin film element, it is also preferable that the holding member is a metal foil that also serves as a lower electrode. In this case, the dielectric thin film is formed on the metal foil in the forming step.
本発明に係る誘電体薄膜素子の製造方法によれば、クラック発生を抑制できる。 According to the dielectric thin film element manufacturing method of the present invention, the generation of cracks can be suppressed.
以下、本発明の好適な実施形態について説明する。但し、本発明は以下の実施形態に限定されるものではない。なお、同一又は同等の要素については同一の符号を付し、説明が重複する場合にはその説明を省略する。 Hereinafter, preferred embodiments of the present invention will be described. However, the present invention is not limited to the following embodiments. In addition, the same code | symbol is attached | subjected about the same or equivalent element, and the description is abbreviate | omitted when description overlaps.
図１は、本発明の一実施形態に係る誘電体薄膜素子１０の構造を示す概略断面図である。誘電体薄膜素子１０は、基板１１と、この基板１１の上に設けられた下部電極１２と、下部電極１２の上に設けられた誘電体薄膜１４と、誘電体薄膜１４の上に設けられた上部電極１５とを備えて構成されている。本実施形態では、基板１１及び下部電極１２からなる層１３が、誘電体薄膜を形成する基体として機能している。 FIG. 1 is a schematic sectional view showing the structure of a dielectric thin film element 10 according to an embodiment of the present invention. The dielectric thin film element 10 is provided on a substrate 11, a lower electrode 12 provided on the substrate 11, a dielectric thin film 14 provided on the lower electrode 12, and a dielectric thin film 14. An upper electrode 15 is provided. In this embodiment, the layer 13 composed of the substrate 11 and the lower electrode 12 functions as a base on which a dielectric thin film is formed.
基板１１は、Ｓｉ基板、アルミナ、ＭｇＯ、ムライトなどのセラミックス基板、ＳＴＯ基板、ガラス基板などである。また、セラミックス基板の表面性改善のために、例えばＳｉＯ２膜をコートしたものを使用してもよい。本実施形態では、基板１１は、誘電体薄膜１４の保持部材として機能し、誘電体薄膜１４を保持して十分な強度を確保できる程度の厚さを有しており、具体的には３０〜１０００μｍである。 The substrate 11 is a Si substrate, a ceramic substrate such as alumina, MgO, or mullite, an STO substrate, or a glass substrate. In order to improve the surface properties of the ceramic substrate, for example, a coated SiO 2 film may be used. In the present embodiment, the substrate 11 functions as a holding member for the dielectric thin film 14 and has a thickness sufficient to hold the dielectric thin film 14 and ensure sufficient strength. 1000 μm.
下部電極１２は、本実施形態では、Ｐｔを主成分として構成されるが、下部電極１２を構成する材料はこれに限定されない。例えば、下部電極１２は、Ｎｉ、Ｐｄ、Ｉｒ、Ｒｕ、Ｒｈ、Ｒｅ、Ｏｓ、Ａｕ、Ａｇ、Ｃｕ、ＩｒＯ２、ＲｕＯ２、ＳｒＲｕＯ３、およびＬａＮｉＯ３の少なくともいずれか１つを含むように構成してもよい。また、下部電極１２の厚さは、抵抗値を低減させると共に基板との密着性を保つため、０．０１〜１μｍ、より好ましくは０．０５〜０．５μｍである。さらに、下部電極１２と基板１１の間には、例えば、ＴｉＯ２よりなる密着層を形成してもよい。 In this embodiment, the lower electrode 12 is composed mainly of Pt, but the material constituting the lower electrode 12 is not limited to this. For example, the lower electrode 12 is configured to include at least one of Ni, Pd, Ir, Ru, Rh, Re, Os, Au, Ag, Cu, IrO 2 , RuO 2 , SrRuO 3 , and LaNiO 3. May be. Further, the thickness of the lower electrode 12 is 0.01 to 1 μm, more preferably 0.05 to 0.5 μm, in order to reduce the resistance value and maintain the adhesion to the substrate. Furthermore, an adhesion layer made of, for example, TiO 2 may be formed between the lower electrode 12 and the substrate 11.
誘電体薄膜１４は、本実施形態では、ペロブスカイト型酸化物であるチタン酸バリウムＢａＴｉＯ３（以下ＢＴ）を主成分として構成されるが、誘電体薄膜を構成する材料はこれに限定されない。例えば、ＢＳＴ、すなわちチタン酸バリウムストロンチウム（ＢａＳｒ）ＴｉＯ３、チタン酸ストロンチウムＳｒＴｉＯ３、（ＢａＳｒ）（ＴｉＺｒ）Ｏ３、ＢａＴｉＺｒＯ３を挙げることができる。誘電体薄膜１４は、これらの酸化物のうち一つ以上を含んでいてもよい。誘電体薄膜１４の膜厚は、３０ｎｍ〜５μｍ程度が好ましい。また、誘電体薄膜１４の密度（充填率）は、その値が小さすぎるとクラックは発生しないが、所望の誘電率を得ることができないため、理論密度に対して７０％以上であることが好ましい。 In the present embodiment, the dielectric thin film 14 is composed mainly of barium titanate BaTiO 3 (hereinafter referred to as BT), which is a perovskite oxide, but the material constituting the dielectric thin film is not limited to this. For example, BST, that is, barium strontium titanate (BaSr) TiO 3 , strontium titanate SrTiO 3 , (BaSr) (TiZr) O 3 , and BaTiZrO 3 can be mentioned. The dielectric thin film 14 may contain one or more of these oxides. The thickness of the dielectric thin film 14 is preferably about 30 nm to 5 μm. The density (filling rate) of the dielectric thin film 14 is preferably not less than 70% of the theoretical density because cracks do not occur if the value is too small, but a desired dielectric constant cannot be obtained. .
上部電極１５は、本実施形態では、Ｃｕを主成分として構成されるが、上部電極１５を構成する材料はこれに限定されない。例えば、上部電極１５は、Ｎｉ、Ｐｔ、Ｐｄ、Ｉｒ、Ｒｕ、Ｒｈ、Ｒｅ、Ｏｓ、Ａｕ、Ａｇ、Ｃｕ、ＩｒＯ２、ＲｕＯ２、ＳｒＲｕＯ３、およびＬａＮｉＯ３の少なくともいずれか１つを含むように構成してもよい。 In the present embodiment, the upper electrode 15 is composed mainly of Cu, but the material constituting the upper electrode 15 is not limited to this. For example, the upper electrode 15 includes at least one of Ni, Pt, Pd, Ir, Ru, Rh, Re, Os, Au, Ag, Cu, IrO 2 , RuO 2 , SrRuO 3 , and LaNiO 3. You may comprise.
次に、図２を参照して、誘電体薄膜素子１０の製造方法を説明する。 Next, a manufacturing method of the dielectric thin film element 10 will be described with reference to FIG.
まず、基板１１と、この基板１１の上に設けられた下部電極１２とから成る層１３が、基体として準備される（Ｓ１）。下部電極１２は、例えばスパッタ法などにより、基板１１上に形成される。 First, a layer 13 including a substrate 11 and a lower electrode 12 provided on the substrate 11 is prepared as a base (S1). The lower electrode 12 is formed on the substrate 11 by, for example, sputtering.
次に、基体の下部電極１２の上に誘電体薄膜１４が形成される（Ｓ２：形成工程）。誘電体の成膜方法としては、スパッタ法、ＣＳＤ法などが挙げられる。 Next, the dielectric thin film 14 is formed on the lower electrode 12 of the base (S2: forming step). Examples of the dielectric film forming method include a sputtering method and a CSD method.
ここで、特に本実施形態においては、ステップＳ２の形成工程の開始時における基板１１のビッカース硬度ＨＶ（α）と、形成工程において形成される誘電体薄膜１４の膜厚（ｔ）（μｍ）との関係が、次式により表される。
α×ｔ≦１５０ （１）
Here, particularly in the present embodiment, the Vickers hardness HV (α) of the substrate 11 at the start of the formation process of step S2, and the film thickness (t) (μm) of the dielectric thin film 14 formed in the formation process. Is expressed by the following equation.
α × t ≦ 150 (1)
ここで、誘電体薄膜のクラック発生を抑制するために、上記（１）式に示される条件を設定した理由について説明する。基板の焼結温度などの製造条件や基板への加熱処理などの前処理条件に応じて、同一材料の保持部材でもビッカース硬度ＨＶは異なる値となる。ここで、保持部材及び誘電体の材料や厚みが同一であり、保持部材のビッカース硬度ＨＶが異なる場合を考える。後述する誘電体薄膜への加熱処理において、ビッカース硬度ＨＶが適度に小さいと、誘電体の結晶粒成長に伴う変形に応じて保持部材も変形することができるため、誘電体薄膜にクラックが発生しにくい。一方、保持部材のビッカース硬度ＨＶが大きすぎると、保持部材の変形が小さくなるため、誘電体薄膜にひずみが過度にかかりクラックが発生しやすくなる。 Here, the reason why the condition shown in the above equation (1) is set in order to suppress the occurrence of cracks in the dielectric thin film will be described. Depending on the manufacturing conditions such as the sintering temperature of the substrate and the pretreatment conditions such as the heat treatment of the substrate, the Vickers hardness HV varies depending on the holding member made of the same material. Here, a case is considered where the holding member and the dielectric have the same material and thickness, and the holding member has different Vickers hardness HV. In the heat treatment of the dielectric thin film described later, if the Vickers hardness HV is moderately small, the holding member can be deformed in accordance with the deformation accompanying the crystal grain growth of the dielectric, so that the dielectric thin film is cracked. Hateful. On the other hand, when the Vickers hardness HV of the holding member is too large, the deformation of the holding member is reduced, so that the dielectric thin film is excessively strained and cracks are likely to occur.
また、誘電体薄膜の膜厚が厚すぎると、後述する誘電体薄膜への加熱処理において、誘電体の結晶粒成長に伴う変形に応じて誘電体薄膜にかかるひずみが大きくなり、たとえ保持部材のビッカース硬度ＨＶが適度に小さくてもクラックが発生しやすくなる。 In addition, if the dielectric thin film is too thick, in the heat treatment of the dielectric thin film, which will be described later, the strain on the dielectric thin film increases in accordance with the deformation accompanying the crystal grain growth of the dielectric. Even if the Vickers hardness HV is moderately small, cracks are likely to occur.
このように、保持部材のビッカース硬度ＨＶと、誘電体薄膜の膜厚とが、クラック発生に大きく影響するものであると考え、両者の適切な設定値の組み合わせを見出すことができれば、熱処理時に誘電体に生じるひずみを抑制しクラック発生を抑制できるものと考えた。そして、鋭意研究を重ねた結果、誘電体薄膜が形成される形成工程の開始時における保持部材のビッカース硬度ＨＶ（α）と、形成工程において形成される誘電体薄膜の膜厚ｔとが、上記（１）式に示すα×ｔ≦１５０なる関係を満たす場合に、ビッカース硬度及び膜厚がそれぞれ適切に設定され、クラック発生が抑制されることを見出すに至った。 As described above, if the Vickers hardness HV of the holding member and the film thickness of the dielectric thin film are considered to greatly affect the occurrence of cracks, and if an appropriate combination of the two values can be found, the dielectric during heat treatment can be found. It was considered that the strain generated in the body can be suppressed and the generation of cracks can be suppressed. As a result of extensive research, the Vickers hardness HV (α) of the holding member at the start of the formation process in which the dielectric thin film is formed and the film thickness t of the dielectric thin film formed in the formation process are as described above. When the relationship of α × t ≦ 150 shown in the equation (1) is satisfied, it has been found that the Vickers hardness and the film thickness are appropriately set, and crack generation is suppressed.
図２のフローに戻り、次に、形成工程において形成された誘電体薄膜１４を、酸素雰囲気あるいは減圧雰囲気中などで所定時間にわたって加熱する（Ｓ３：加熱工程）。このアニール処理により、誘電体薄膜１４の結晶性が改善され、誘電率が向上する。雰囲気の温度は５００〜１２００℃であることが好ましい。 Returning to the flow of FIG. 2, next, the dielectric thin film 14 formed in the forming step is heated for a predetermined time in an oxygen atmosphere or a reduced pressure atmosphere (S3: heating step). By this annealing treatment, the crystallinity of the dielectric thin film 14 is improved and the dielectric constant is improved. The temperature of the atmosphere is preferably 500 to 1200 ° C.
そして、加熱処理された誘電体薄膜１４の上に上部電極１５が形成される（Ｓ４）。上部電極１５の形成方法としては、例えばスパッタ法などが挙げられる。上部電極１５形成後、必要に応じて酸素雰囲気あるいは減圧雰囲気中などで所定時間にわたってリカバリーアニールが行われる（Ｓ５）。 Then, the upper electrode 15 is formed on the heat-treated dielectric thin film 14 (S4). Examples of a method for forming the upper electrode 15 include a sputtering method. After the upper electrode 15 is formed, recovery annealing is performed for a predetermined time in an oxygen atmosphere or a reduced pressure atmosphere as required (S5).
このように、本実施形態に係る誘電体薄膜素子１０の製造方法によれば、基体の下部電極１２の上に誘電体薄膜１４が形成される形成工程の開始時における基板１１のビッカース硬度ＨＶ（α）と、形成工程において形成される誘電体薄膜１４の膜厚（ｔ）（μｍ）との関係が、α×ｔ≦１５０となるように、誘電体薄膜１４が形成されるため、クラック発生を抑制することができる。 As described above, according to the method for manufacturing the dielectric thin film element 10 according to the present embodiment, the Vickers hardness HV of the substrate 11 at the start of the forming process in which the dielectric thin film 14 is formed on the lower electrode 12 of the base body ( Since the dielectric thin film 14 is formed such that the relationship between α) and the film thickness (t) (μm) of the dielectric thin film 14 formed in the forming process satisfies α × t ≦ 150, cracks are generated. Can be suppressed.
また、形成工程において形成された誘電体薄膜１４を加熱する加熱工程を行うため、誘電体薄膜素子１０の誘電率を向上できる。 Moreover, since the heating process which heats the dielectric thin film 14 formed in the formation process is performed, the dielectric constant of the dielectric thin film element 10 can be improved.
なお、上記実施形態では、基板１１が誘電体薄膜１４を保持する保持部材として設けられ、かつ、基板１１と下部電極１２とから成る層１３が基体として設けられているが、この代わりに、図３に示すように、誘電体薄膜１４を保持する保持部材としての機能と、下部電極としての機能とを兼ね備える金属箔１６を、基体として設けてもよい。図３はこのような変形が施された誘電体薄膜素子２０を示す概略断面図である。金属箔１６は、Ｎｉ箔、Ｃｕ箔、Ａｌ箔、Ｐｔ箔などが好ましく、また、これらを含む合金でもよい。金属箔１６の膜厚は５〜５００μｍであることが好ましい。 In the above embodiment, the substrate 11 is provided as a holding member for holding the dielectric thin film 14, and the layer 13 including the substrate 11 and the lower electrode 12 is provided as a base body. As shown in FIG. 3, a metal foil 16 having both a function as a holding member for holding the dielectric thin film 14 and a function as a lower electrode may be provided as a base. FIG. 3 is a schematic sectional view showing the dielectric thin film element 20 subjected to such a modification. The metal foil 16 is preferably a Ni foil, a Cu foil, an Al foil, a Pt foil or the like, and may be an alloy containing these. The film thickness of the metal foil 16 is preferably 5 to 500 μm.
保持部材のビッカース硬度は、Ｓｉ基板については添加物、熱酸化膜の膜厚、製造条件、加熱処理等の前処理条件などにより、セラミックス基板については焼結密度、組成比、添加物、製造条件、加熱処理等の前処理条件などにより、金属箔については添加物、合金化、製造条件（圧延、めっき加工など）、加熱処理等の前処理条件などにより、調整することが可能である。尚、本発明は以上のようなビッカース硬度調整方法に限定されない。 The Vickers hardness of the holding member depends on the additive for the Si substrate, the film thickness of the thermal oxide film, the production conditions, pretreatment conditions such as heat treatment, etc., and the sintered density, composition ratio, additive, and production conditions for the ceramic substrate. Depending on pretreatment conditions such as heat treatment, the metal foil can be adjusted by additives, alloying, production conditions (rolling, plating, etc.), pretreatment conditions such as heat treatment, and the like. In addition, this invention is not limited to the above Vickers hardness adjustment methods.
以下、実施例を挙げて本発明についてより具体的に説明する。ただし、本発明は以下の実施例に限定されるものではない。 Hereinafter, the present invention will be described more specifically with reference to examples. However, the present invention is not limited to the following examples.
（実施例１）
熱酸化膜付きＳｉ基板（ビッカース硬度ＨＶ：８５０）上にスパッタ法にて密着層およびＰｔ下部電極を形成し、その上にスパッタ法にてＢＴ薄膜０．１５μmを形成し、８００℃酸素雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、誘電率及びリーク特性を測定し、不良率を求めた。
Example 1
An adhesion layer and a Pt lower electrode are formed by sputtering on a Si substrate with a thermal oxide film (Vickers hardness HV: 850), and a BT thin film of 0.15 μm is formed thereon by sputtering, in an oxygen atmosphere at 800 ° C. After heat treatment for 30 minutes, a Cu upper electrode having a thickness of 1 mmφ and a film thickness of 200 nm was formed by sputtering, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured, and the defect rate was calculated | required.
誘電率は、室温下で誘電体薄膜素子の下部電極及び上部電極間に周波数１ｋＨｚ、振幅１Ｖの交流電圧を印加することにより測定した。リーク特性は、室温下で誘電体薄膜素子の下部電極及び上部電極間に直流電圧を印加することにより測定したリーク電流値を電極面積で除して得られる値をリーク電流密度（Ａ／ｃｍ２）として求めた。 The dielectric constant was measured by applying an AC voltage having a frequency of 1 kHz and an amplitude of 1 V between the lower electrode and the upper electrode of the dielectric thin film element at room temperature. The leakage characteristic is obtained by dividing a leakage current value measured by applying a DC voltage between the lower electrode and the upper electrode of the dielectric thin film element at room temperature by the electrode area, and calculating a leakage current density (A / cm 2). ).
また、測定したリーク特性の結果から不良率も求めた。不良率は、電界強度１００ｋＶ／ｃｍ（印加した直流電圧を誘電体薄膜素子の膜厚で除した値）時のリーク電流密度の値が５×１０−6Ａ／ｃｍ２以上であれば不良とし、誘電体薄膜素子１００個についてリーク特性を確認した。そして、不良が認められた素子の割合を百分率で示したものを不良率とした。不良率が２０％以下であれば、優れたリーク特性を有し、クラック発生を好適に抑制できているものとした。 Also, the defect rate was obtained from the result of the measured leak characteristics. The defect rate is determined to be defective if the value of the leakage current density when the electric field intensity is 100 kV / cm (value obtained by dividing the applied DC voltage by the film thickness of the dielectric thin film element) is 5 × 10 −6 A / cm 2 or more. The leakage characteristics of 100 dielectric thin film elements were confirmed. And what showed the ratio of the element by which the defect was recognized in percentage was made into the defect rate. If the defect rate is 20% or less, it has excellent leakage characteristics, and cracks can be suitably suppressed.
なお、ビッカース硬度ＨＶの測定は、ビッカース硬度測定装置（株式会社アカシ製、ＨａｒｄｎｅｓｓＴｅｓｔｅｒ ＭＶＫ−Ｇ３）を用いて行った。誘電体薄膜（ＢＴ薄膜）の形成開始時における保持部材（熱酸化膜付きＳｉ基板）の表面に、ダイヤモンド正四角錘（対面角θ＝１３６度）のビッカース圧子を所定荷重Ｆ（１〜５０ｇｆ（サンプルの主成分により変更される））で２０秒間押し込み、荷重を取り除いた後に保持部材表面に残った圧痕の対角線距離の平均値ｄ（μｍ）を計測した。そしてこの対角線距離の平均値ｄと、荷重Ｆとに基づき、ビッカース硬度ＨＶを次式により算出した。
HV＝2000Fsin（θ／2）／d2 ＝1854.4F／d2 （kgf／mm2）
In addition, the measurement of Vickers hardness HV was performed using the Vickers hardness measuring apparatus (Akashi Co., Ltd. make, HardnessTester MVK-G3). On the surface of the holding member (Si substrate with a thermal oxide film) at the start of the formation of the dielectric thin film (BT thin film), a Vickers indenter of diamond regular square pyramid (face angle θ = 136 degrees) is applied with a predetermined load F (1 to 50 gf ( The average value d (μm) of the diagonal distance of the indentation remaining on the surface of the holding member after removing the load was measured for 20 seconds. And based on the average value d of this diagonal distance, and the load F, Vickers hardness HV was computed by following Formula.
HV = 2000Fsin (θ / 2) / d 2 = 1854.4F / d 2 (kgf / mm 2 )
（実施例２）
熱酸化膜付きＳｉ基板（ビッカース硬度ＨＶ：９５０）上にスパッタ法にて密着層およびＰｔ下部電極を形成し、その上にスパッタ法にてＢＴ薄膜０．１２μｍを形成し、８００℃酸素雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Example 2)
An adhesion layer and a Pt lower electrode are formed by sputtering on a Si substrate with thermal oxide film (Vickers hardness HV: 950), and a BT thin film of 0.12 μm is formed thereon by sputtering, and in an oxygen atmosphere at 800 ° C. After heat treatment for 30 minutes, a Cu upper electrode having a thickness of 1 mmφ and a film thickness of 200 nm was formed by sputtering, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
（実施例３）
表面を研磨したアルミナ基板（ビッカース硬度ＨＶ：５００ アルミナ含有量、添加物、焼結密度等により調整）上にＳｉＯ２表面平滑層５μｍを形成した。その上にスパッタ法にて密着層およびＰｔ下部電極を形成し、その上にスパッタ法にてＢＴ薄膜０．２５μｍを形成し、８００℃酸素雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Example 3)
A smooth SiO 2 surface layer of 5 μm was formed on an alumina substrate whose surface was polished (Vickers hardness HV: 500, adjusted by alumina content, additives, sintering density, etc.). An adhesion layer and a Pt lower electrode are formed thereon by sputtering, and a BT thin film of 0.25 μm is formed thereon by sputtering, and after heat treatment in an oxygen atmosphere at 800 ° C. for 30 minutes, 1 mmφ is formed by sputtering. A Cu upper electrode with a thickness of 200 nm was formed, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
（実施例４）
１０００℃で加熱処理を施したＮｉ箔（ビッカース硬度ＨＶ：８０ Ｎｉ箔は電解法により作製）上にスパッタ法にてＢＴ薄膜１．５μｍを形成し、８００℃の１０−３Ｐａ減圧雰囲気で３０分間熱処理を行った。次に、ＢＴ薄膜上にメタルマスクを用いスパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定した。
Example 4
A BT thin film of 1.5 μm is formed by sputtering on Ni foil (Vickers hardness HV: 80 Ni foil is produced by electrolytic method) that has been heat-treated at 1000 ° C., and 30 ° C. in a 10 −3 Pa reduced pressure atmosphere at 800 ° C. Heat treatment was performed for a minute. Next, a Cu upper electrode having a thickness of 1 mmφ and a thickness of 200 nm was formed on the BT thin film by sputtering using a metal mask, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. The dielectric constant and leakage characteristics of the manufactured dielectric thin film element were measured in the same manner as in Example 1.
（実施例５）
５００℃で加熱処理を施したＮｉ箔（ビッカース硬度ＨＶ：１００ Ｎｉ箔は電解法により作製）上にスパッタ法にてＢＴ薄膜１．０μｍを形成し、８００℃の１０−３Ｐａ減圧雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ真空雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Example 5)
A BT thin film of 1.0 μm was formed by sputtering on a Ni foil (Vickers hardness HV: 100 Ni foil produced by an electrolytic method) subjected to heat treatment at 500 ° C., and 30 ° C. in a reduced pressure atmosphere of 10 −3 Pa at 800 ° C. After heat treatment for 1 minute, a Cu upper electrode having a thickness of 1 mmφ and a film thickness of 200 nm was formed by a sputtering method, and recovery annealing was performed in a 10 −1 Pa vacuum atmosphere at 300 ° C. for 30 minutes. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
（実施例６）
圧延法により作製したＮｉ箔（ビッカース硬度ＨＶ：２００ 熱処理なし）表面を研磨、洗浄した後、スパッタ法にてＢＴ薄膜０．５μｍを形成し、８００℃の１０−３Ｐａ減圧雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Example 6)
After polishing and cleaning the surface of Ni foil (Vickers hardness HV: 200 without heat treatment) produced by rolling, a BT thin film of 0.5 μm is formed by sputtering, and heat treated for 30 minutes in a reduced pressure atmosphere of 10 −3 Pa at 800 ° C. Thereafter, a Cu upper electrode having a thickness of 1 mmφ and a thickness of 200 nm was formed by sputtering, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
（実施例７）
９００℃で加熱処理を施したＣｕ箔（ビッカース硬度ＨＶ：５０）上にスパッタ法にてＢＴ薄膜２．０μｍを形成し、９００℃の低酸素分圧（ｐＯ２＝１０−５Ｐａ）雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Example 7)
A BT thin film of 2.0 μm was formed by sputtering on a Cu foil (Vickers hardness HV: 50) subjected to heat treatment at 900 ° C., and in a low oxygen partial pressure (pO 2 = 10 −5 Pa) atmosphere at 900 ° C. After heat treatment for 30 minutes, a Cu upper electrode having a thickness of 1 mmφ and a film thickness of 200 nm was formed by sputtering, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
（比較例１）
熱酸化膜付きＳｉ基板（ビッカース硬度ＨＶ：８５０）上にスパッタ法にて密着層およびＰｔ下部電極を形成し、その上にスパッタ法にてＢＴ薄膜０．１９μmを形成し、８００℃酸素雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Comparative Example 1)
An adhesion layer and a Pt lower electrode are formed by sputtering on a Si substrate with thermal oxide film (Vickers hardness HV: 850), and a BT thin film of 0.19 μm is formed thereon by sputtering, and in an oxygen atmosphere at 800 ° C. After heat treatment for 30 minutes, a Cu upper electrode having a thickness of 1 mmφ and a film thickness of 200 nm was formed by sputtering, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
（比較例２）
表面を研磨したアルミナ基板（ビッカース硬度ＨＶ：５００ アルミナ含有量、添加物、焼結密度等により調整）上にＳｉＯ２表面平滑層５μｍを形成した。その上にスパッタ法にて密着層およびＰｔ下部電極を形成し、その上にスパッタ法にてＢＴ薄膜０．３５μｍを形成し、８００℃酸素雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Comparative Example 2)
A smooth SiO 2 surface layer of 5 μm was formed on an alumina substrate whose surface was polished (Vickers hardness HV: 500, adjusted by alumina content, additives, sintering density, etc.). An adhesion layer and a Pt lower electrode are formed thereon by sputtering, and a BT thin film of 0.35 μm is formed thereon by sputtering, and after heat treatment in an oxygen atmosphere at 800 ° C. for 30 minutes, 1 mmφ is formed by sputtering. A Cu upper electrode with a thickness of 200 nm was formed, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
（比較例３）
１０００℃で加熱処理を施したＮｉ箔（ビッカース硬度ＨＶ：８０ Ｎｉ箔は電解法により作製）上にスパッタ法にてＢＴ薄膜２．０μmを形成し、８００℃の１０−３ Ｐａ減圧雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Comparative Example 3)
A BT thin film of 2.0 μm was formed by sputtering on a Ni foil (Vickers hardness HV: 80 Ni foil produced by an electrolytic method) subjected to heat treatment at 1000 ° C., and 30 ° C. in a reduced pressure atmosphere of 10 −3 Pa at 800 ° C. After heat treatment for 1 minute, a Cu upper electrode having a thickness of 1 mmφ and a film thickness of 200 nm was formed by sputtering, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
（比較例４）
熱処理を施していないＮｉ箔（ビッカース硬度ＨＶ：４００ Ｎｉ箔は電解法により作製）上にスパッタ法にてＢＴ薄膜０．４μmを形成し、８００℃の１０−３Ｐａ減圧雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Comparative Example 4)
BT thin film 0.4 μm is formed by sputtering on Ni foil (Vickers hardness HV: 400 Ni foil is produced by electrolysis) that has not been heat-treated, and then heat-treated in a 10 −3 Pa reduced pressure atmosphere at 800 ° C. for 30 minutes. Then, a Cu upper electrode having a thickness of 1 mmφ and a film thickness of 200 nm was formed by sputtering, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
（比較例５）
３００℃で加熱処理を施したＣｕ箔（ビッカース硬度ＨＶ：１００）上にスパッタ法にてＢＴ薄膜２．０μｍを形成し、９００℃の低酸素分圧（ｐＯ２＝１０−５Ｐａ）雰囲気で３０分間熱処理後、スパッタ法にて１ｍｍφ、膜厚２００ｎｍのＣｕ上部電極を形成し、３００℃の１０−１Ｐａ減圧雰囲気で３０分間リカバリーアニールを行った。作製した誘電体薄膜素子について、実施例１と同様に誘電率及びリーク特性を測定し、不良率を求めた。
(Comparative Example 5)
A BT thin film of 2.0 μm was formed by sputtering on a Cu foil (Vickers hardness HV: 100) that had been heat-treated at 300 ° C., and in a low oxygen partial pressure (pO 2 = 10 −5 Pa) atmosphere at 900 ° C. After heat treatment for 30 minutes, a Cu upper electrode having a thickness of 1 mmφ and a film thickness of 200 nm was formed by sputtering, and recovery annealing was performed for 30 minutes in a 10 −1 Pa reduced pressure atmosphere at 300 ° C. About the produced dielectric thin film element, the dielectric constant and the leak characteristic were measured similarly to Example 1, and the defect rate was calculated | required.
上述の実施例１〜７、比較例１〜５について、ビッカース硬度ＨＶ（α）と誘電体膜厚（ｔ）との積α×ｔ、不良率（％）、誘電率及び電界強度１００ｋＶ／ｃｍ時のリーク電流密度（Ａ／ｃｍ２）について表１に示す。なお、誘電率およびリーク電流密度は測定した誘電体薄膜素子１００個の平均値である。
For Examples 1 to 7 and Comparative Examples 1 to 5 described above, the product α × t of Vickers hardness HV (α) and dielectric film thickness (t), defect rate (%), dielectric constant and electric field strength 100 kV / cm Table 1 shows the leakage current density (A / cm 2 ) at the time. The dielectric constant and the leakage current density are average values of 100 measured dielectric thin film elements.
表１に示すように、保持部材（基板、金属箔）のビッカース硬度ＨＶ（α）と誘電体膜厚（ｔ）との関係がα×ｔ≦１５０となるように調整して作製された実施例１〜７の誘電体薄膜素子は、高温熱処理を行っても不良率が２０％以下であり、クラック発生が好適に抑制されることが確認された。また、誘電率が十分に高く、リーク電流密度が十分に低いことが確認された。 As shown in Table 1, the embodiment was prepared by adjusting the relationship between the Vickers hardness HV (α) of the holding member (substrate, metal foil) and the dielectric film thickness (t) to satisfy α × t ≦ 150. The dielectric thin film elements of Examples 1 to 7 have a defect rate of 20% or less even when subjected to high-temperature heat treatment, and it was confirmed that generation of cracks was suitably suppressed. It was also confirmed that the dielectric constant was sufficiently high and the leakage current density was sufficiently low.
これに対して、α×ｔ＞１５０となる比較例１〜５は、不良率が実施例よりも著しく大きかった。図４は、比較例２の誘電体薄膜の表面に発生したクラックを示すＳＥＭ写真である。上記比較例では、実施例と比べて、誘電体薄膜の表面に図４に例示したようなクラックが多く発生する。 On the other hand, in Comparative Examples 1 to 5 where α × t> 150, the defect rate was remarkably larger than that of the example. FIG. 4 is a SEM photograph showing cracks generated on the surface of the dielectric thin film of Comparative Example 2. In the comparative example, more cracks as illustrated in FIG. 4 occur on the surface of the dielectric thin film than in the example.
すなわち、本発明によれば、クラック発生を抑制でき、誘電率が十分に高く、リーク特性にも優れる誘電体薄膜素子が提供されることが確認された。 That is, according to the present invention, it was confirmed that a dielectric thin film element that can suppress the occurrence of cracks, has a sufficiently high dielectric constant, and has excellent leak characteristics is provided.
さらに、上記実施例１〜７、比較例１〜５を含み、ビッカース硬度ＨＶ及び誘電体膜厚の他の組み合わせを含む試験条件のそれぞれについて、クラック発生を十分に抑制できているか否かを評価した結果を表２〜５に示す。評価の判断基準としては、不良率が２０％以下となる場合に合格とした。表２〜５では、保持部材がそれぞれ熱酸化膜付きＳｉ基板、セラミックス基板、Ｎｉ箔、Ｃｕ箔であった。そして、表２〜５では、ビッカース硬度ＨＶ（α）及び誘電体膜厚（ｔ）のそれぞれの設定値の組ごとに、α×ｔの値が示されており、上記判断基準で合格と判定されたビッカース硬度ＨＶ及び誘電体膜厚の組が太枠で囲まれている。
Furthermore, it is evaluated whether crack generation can be sufficiently suppressed for each of the test conditions including Examples 1 to 7 and Comparative Examples 1 to 5 and including other combinations of Vickers hardness HV and dielectric film thickness. The results are shown in Tables 2-5. As a criterion for evaluation, the test was accepted when the defect rate was 20% or less. In Tables 2-5, the holding member was a Si substrate with a thermal oxide film, a ceramic substrate, a Ni foil, and a Cu foil, respectively. And in Tables 2-5, the value of (alpha) xt is shown for every set value set of each of Vickers hardness HV ((alpha)) and dielectric material film thickness (t), and it determines with a pass by the said criteria. The set of Vickers hardness HV and dielectric film thickness is surrounded by a thick frame.
表２〜５に示すように、不良率が２０％以下となる保持部材（基板、金属箔）のビッカース硬度ＨＶ（α）と誘電体膜厚（ｔ）との組み合わせは、全てα×ｔの値が１５０より小さくなることが確認された。すなわち、本発明に係る誘電体薄膜素子は、α×ｔ≦１５０となるように調整して作製されたため、不良率が２０％以下となり、クラック発生が好適に抑制されることが確認された。 As shown in Tables 2 to 5, the combinations of the Vickers hardness HV (α) and the dielectric film thickness (t) of the holding member (substrate, metal foil) having a defect rate of 20% or less are all α × t. It was confirmed that the value was smaller than 150. That is, since the dielectric thin film element according to the present invention was prepared by adjusting so that α × t ≦ 150, the defect rate was 20% or less, and it was confirmed that the occurrence of cracks was suitably suppressed.
また、表４及び表５に示すように、保持部材に金属箔を用いた場合は、ビッカース硬度を幅広く調整することが可能であり、不良率が２０％以下となる誘電体膜厚の範囲が広くなる。誘電体材料の種類により所望の電気特性（誘電率及びリーク特性など）を得るための最適な膜厚が異なるため、保持部材として熱酸化膜付きＳｉ基板やセラミックス基板を用いるより、誘電体膜厚を幅広く調整することが可能である金属箔を用いる方がより好ましい。 In addition, as shown in Tables 4 and 5, when a metal foil is used for the holding member, the Vickers hardness can be widely adjusted, and the range of the dielectric film thickness where the defect rate is 20% or less Become wider. Since the optimum film thickness for obtaining desired electrical characteristics (dielectric constant, leak characteristics, etc.) differs depending on the type of dielectric material, the dielectric film thickness is more than using a Si substrate with a thermal oxide film or a ceramic substrate as a holding member. It is more preferable to use a metal foil that can be adjusted widely.
１０，２０…誘電体薄膜素子、１１…基板、１２…下部電極、１４…誘電体薄膜、１６…金属箔。 DESCRIPTION OF SYMBOLS 10,20 ... Dielectric thin film element, 11 ... Board | substrate, 12 ... Lower electrode, 14 ... Dielectric thin film, 16 ... Metal foil.
Claims (1)
前記形成工程の次に、該形成工程において形成された前記誘電体薄膜を加熱する加熱工程と、
を備え、
前記保持部材が、ビッカース硬度が調整された基板であり、
前記基体が、前記基板と、当該基板上に形成される下部電極とを含み、
前記形成工程において、αを前記形成工程開始時の前記保持部材のビッカース硬度（ＨＶ）とし、ｔを前記誘電体薄膜の膜厚（μｍ）としたとき、
α×ｔ≦１５０
の関係を満たすように調整して前記誘電体薄膜を前記下部電極上に形成する、
誘電体薄膜素子の製造方法。 Forming a dielectric thin film on a substrate including a holding member for holding the dielectric thin film; and
Next to the forming step, a heating step of heating the dielectric thin film formed in the forming step;
With
The holding member is a substrate having an adjusted Vickers hardness;
The base includes the substrate and a lower electrode formed on the substrate,
In the forming step, the Vickers hardness of said retaining member prior SL forming step at the start of the alpha (HV), when the said t dielectric thin film having a thickness ([mu] m),
α × t ≦ 150
The dielectric thin film is formed on the lower electrode by adjusting so as to satisfy the relationship of
A method for manufacturing a dielectric thin film element.
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