JP5301004B2 - Storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a storage device capable of enhancing the reliability by solving the problems of write disturbances and read disturbances. <P>SOLUTION: Data are first read in step S4, when data are written in a phase-change memory. In step S5, whether the read data are "1" or "0" is determined. If the read data are "0", the processing proceeds to step S6, and applies a current in order to write "1" in a memory cell. If the read data are determined as being "1" in step S5, the processing proceeds to step S10, without performing any writing operation. Preferably, when the write data are "0", the data "0" are written without reading the data. Since the data "1" are not rewritten to a high-resistance state (state of holding "1"), the resistance ratio of the memory cell can be taken large, the reading signal can be enlarged, and reading access time becomes fast. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a storage device, and more particularly to high reliability of a phase change memory.

  Japanese Patent Laid-Open No. 2003-100085 (Patent Document 1) relates to a phase change nonvolatile memory device using a phase change material as a memory cell, before recording information in the memory cell, reading the recording state of the memory cell, It is described that a write pulse optimum for transition is selected and applied. At this time, if no transition is required, the write pulse may not be applied. Alternatively, the crystallization holding time is controlled by adjusting the waveform at the falling edge of the pulse in accordance with whether the transition is to the amorphous state or the crystalline state.

JP 2003-100085 A

  The conventional phase change memory using chalcogenide glass (GeSbTe) has the following two problems in the memory access operation.

  The first is the problem of write disturb. The phase change memory cell is in an amorphous state (a state in which data “1” is held) is a state in which the resistance value of the cell is high. When the data “1” is rewritten (overwritten) when the memory cell holds “1”, the cell resistance is high. There's a problem.

  That is, when data “1” is written when data “0” is held, a high current can be applied, but when data “1” is held, data “1” is rewritten. Cannot be applied with high current. Therefore, in this case, the memory cell cannot be rapidly cooled, but rather, the memory cell is heated in a state where the recrystallization temperature is exceeded and the melting temperature is not reached. Such heating is referred to herein as slow heating.

  When the cell is gradually heated, the memory cell holding the data “1” is heated to be in a polycrystalline state, and the data “1” is destroyed. This destruction of data at the time of writing is referred to as write disturb in this specification.

  In order to prevent write disturb, the resistance value Rcell (H) of the memory cell in the high resistance state cannot be increased too much. However, if the resistance value Rcell (H) of the memory cell is not increased too much, the resistance ratio of the memory cell corresponding to the data “1” and “0” cannot be increased. If the resistance ratio of the memory cell cannot be increased, there is a problem that the read signal at the time of read access is reduced and the read access time is delayed.

Second is the problem of read disturb. When reading from the memory cell, a read current Iread flows through the heater and the phase change element, and a certain amount of heat is generated. If the write current Iwrite / read current Iread is not kept large by more than 3 digits, the heat generated by the read current Iread becomes gradual and data “1” is destroyed. When the cell is gradually heated, the memory cell holding the data “1” is heated to be in a polycrystalline state, and the data “1” is destroyed. This destruction of data at the time of reading is referred to as read disturb in this specification. Therefore, it is necessary to increase the resistance Rcell (H) of the memory cell in order to keep the read current value when reading data “1” small, and writing of data “0” is delayed.

  An object of the present invention is to provide a storage device that solves the problems of write disturb and read disturb and has improved reliability.

  In summary, the present invention is a memory device including a memory cell, a current application circuit, a read circuit, and a write circuit. By applying heat, the memory cell has a first resistance value corresponding to the first logic value and a second resistance value having a resistance higher than the first resistance value corresponding to the second logic value. The resistance value changes and data is accumulated. The current application circuit outputs a current for writing data by applying heat to the memory cell. The read circuit reads data corresponding to the resistance value of the memory cell. When writing the second logic value to the memory cell, the writing circuit writes the second logic value to the current application circuit when the read data read by the reading circuit is the first logic value. An instruction is given, and when the read data has the second logic value, an instruction to write the second logic value to the current application circuit is not given. When writing the first logic value into the memory cell, the write circuit instructs the current application circuit to write the first logic value regardless of the value of the read data.

  In the present invention, when the phase change element is in the high resistance state, the data corresponding to the high resistance state is not rewritten, so that the problem of write disturb does not occur. Therefore, there is no restriction on the resistance of the memory cell, and the resistance value of the memory cell in the high resistance state can be increased. As a result, the resistance ratio of the memory cell resistors corresponding to the two logical values can be increased, the read signal can be increased, and the read access time can be increased.

1 schematically shows an entire configuration of a storage device according to an embodiment of the present invention. FIG. FIG. 2 is a circuit diagram showing a configuration of a memory cell MC in FIG. 1. It is sectional drawing for demonstrating the phase change element in FIG. 3 is a flowchart showing one cycle of a write operation of a phase change memory in the first embodiment. FIG. 5 is a diagram showing a data write cycle corresponding to the flowchart shown in FIG. 4. It is a modification of the flowchart shown in FIG. FIG. 7 is a diagram for illustrating a write cycle corresponding to the flowchart shown in FIG. 6. It is a flowchart for demonstrating the other modification of write-in operation | movement. FIG. 9 is a diagram for explaining a write cycle corresponding to the flowchart shown in FIG. 8. It is a flowchart for demonstrating the modification of another write cycle. It is a figure for demonstrating the data write cycle by the flowchart shown in FIG. 10 is a flowchart for illustrating a read cycle according to the second embodiment. It is a figure for demonstrating the read cycle of the flowchart of FIG. 13 is a flowchart showing a modification of the operation shown in FIG. It is a figure for demonstrating the read cycle of the flowchart of FIG. It is the figure which showed the further modification of the flowchart shown in FIG. It is a figure showing a write current waveform of data writing. FIG. 5 is a diagram showing a configuration of a memory array for explaining a write operation of a phase change memory. FIG. 19 is a circuit diagram showing the configuration of the variable current source 208 of FIG. 18 in more detail. FIG. 20 is an operation waveform diagram for illustrating the operation of the variable current source shown in FIG. 19. FIG. 21 is an operation waveform diagram showing a waveform obtained by improving the write operation shown in FIG. 20. It is a circuit diagram showing a configuration in the case where a plurality of bits are simultaneously written in the same memory mat. FIG. 23 is an operation waveform diagram for describing a write operation of the configuration shown in FIG. It is the circuit diagram which showed the structure in the case of writing data by another method. FIG. 25 is an operation waveform diagram for illustrating the operation of the circuit shown in FIG. 24. It is the circuit diagram which showed the structure in the case of writing data by another method. FIG. 27 is an operation waveform diagram for illustrating the operation of the circuit shown in FIG. 26. It is the figure which showed the example of improvement regarding the data reading of a phase change memory. FIG. 29 is an operation waveform diagram for describing a read operation of the configuration shown in FIG. 28. It is the figure which expanded and showed the bit line current in FIG. FIG. 10 is a circuit diagram showing a configuration related to data writing in a fourth embodiment. FIG. 32 is an operation waveform diagram showing a waveform during a write operation of the configuration shown in FIG. 31. It is the figure which showed the relationship between the output signal of a comparison circuit, and an input signal. FIG. 4 is a circuit diagram showing a modification of the memory cell MC in FIG. 2. It is a figure for demonstrating the cooling time of a memory cell. It is a figure showing inserting an external NOP cycle at the end of a write cycle. It is the figure which showed other operating conditions (2nd method). It is a flowchart for demonstrating the operation | movement with respect to the continuous writing to the same address. It is the figure which showed the operation | movement corresponding to the flowchart of FIG. FIG. 20 is a block diagram showing a configuration of a phase change memory according to a seventh embodiment. 18 is a flowchart for explaining an operation of the phase change memory according to the seventh embodiment. FIG. 41 is a circuit diagram showing a phase change memory cell array 512 and its peripheral circuits in FIG. 40. FIG. 43 is a circuit diagram showing a configuration of a variable current source 561 in FIG. 42. FIG. 11 is an operation waveform diagram for describing a write operation to a memory cell. FIG. 43 is a circuit diagram showing a configuration of a sense amplifier 541 in FIG. 42. It is an operation waveform diagram for explaining a read operation. FIG. 46 is a diagram showing a modification of the sense amplifier shown in FIG. 45. FIG. 48 is an operation waveform diagram for illustrating the operation of the sense amplifier shown in FIG. 47. It is a figure for demonstrating the case where writing to 2 cells is performed simultaneously. It is a figure which shows the structure which solves the problem of the overheating by heat_generation | fever of an adjacent memory cell. FIG. 51 is a diagram for describing selection of a memory cell in the configuration shown in FIG. 50. It is a figure which shows the structure which improved the problem of thermal interference further.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 schematically shows a whole structure of a storage device according to an embodiment of the present invention.
Referring to FIG. 1, the storage device includes a memory cell array 100 in which memory cells MC are arranged in a matrix. Memory cell MC includes a variable resistance element including a phase change element and a selection transistor for selecting the variable resistance element.

  In memory cell array 100, word lines WL are arranged corresponding to the rows of memory cells MC, and bit lines BL are arranged corresponding to the respective columns of memory cells MC.

  The memory device further decodes the word line address signal ADX, generates a word line selection signal for designating a word line in the memory cell array 100, and the word line selection signal from the word line decoder 102. The word line drive circuit 104 that drives the selected word line to the selected state, and activated when the write instruction signal WR is activated, the bit line address signal ADY is decoded, and the bit line to be written is A write driver decoder 106 to be selected and a bit line drive circuit 108 for supplying a write voltage (current) pulse when data is written to a selected bit line according to an output signal of the write driver decoder 106 are included.

  Write driver decoder 106 selects a write target bit line and supplies a write current pulse to the write target bit line in accordance with a write control signal applied from write circuit 114 in accordance with write data. A control signal for generating Bit line drive circuit 108 supplies a write current pulse to the selected bit line in accordance with the output signal of write driver decoder 106 at the time of data writing. The bit line drive circuit 108 is maintained in the output high impedance state during a period other than during the data write operation.

  Write circuit 114 generates a write control signal for the selected bit line based on the write data in accordance with activation of write activation signal WE. The write control signal from write circuit 114 is applied to write driver decoder 106, and data writing is executed for the selected bit line.

  Write activation signal WE is activated when data is actually written to the selected memory cell when write instruction signal WR is activated. Write instruction signal WR indicates that the operation mode is the data write mode.

  The memory device further decodes the bit line address signal ADY to generate a bit line selection signal designating the selected bit line, and the corresponding bit line according to the bit line selection signal from the bit line decoder 110. Column selection circuit 112 that couples the bit line of the selected column to internal data bus 120, and read circuit 116 that generates internal read data based on the data read on internal data bus 120 when data is read. And an input / output circuit 118 coupled to internal data bus 120 for inputting / outputting external data DQ.

FIG. 2 is a circuit diagram showing a configuration of memory cell MC in FIG.
Referring to FIG. 2, memory cell MC is provided corresponding to the intersection of word line WL and bit line BL. Memory cell MC includes an access transistor AT having a word line connected to the gate and one end connected to the bit line, a heater element HE connected in series between the other end of access transistor AT and the ground node, and a phase change. And element PE.

FIG. 3 is a cross-sectional view for explaining the phase change element in FIG.
Referring to FIG. 3, heater element 156 and polycrystalline chalcogenide 152 are connected, and a programmable volume 154 corresponding to the phase change element is formed at the connection portion. When the polycrystalline chalcogenide 152 is heated by the heater element 156 to a certain temperature or higher and then rapidly cooled, the programmable volume 154 is in an amorphous state and has a high resistance value.

  On the other hand, the programmable volume 154 once in an amorphous state changes from an amorphous state to a polycrystalline state having a low resistance value when heating by the heater element 156 exceeds a recrystallization temperature for a certain period of time. For example, the resistance value of the memory cell in the polycrystalline state is 2.0 KΩ, and the resistance value of the memory cell in the amorphous state is 85 KΩ. The polycrystalline state corresponds to data “0”, and the amorphous state corresponds to data “1”.

  The current value Icell given to make the transition from the amorphous state to the polycrystalline state is 0.3 mA, for example, and the applied current Icell is, for example, 0.75 mA to make the transition of the programmable volume 154 from the polycrystalline state to the amorphous state. The application time is 85 ns, for example.

[Embodiment 1]
FIG. 4 is a flowchart showing one cycle of the write operation of the phase change memory according to the first embodiment.

  Referring to FIG. 4, the writing operation is started in step S1. In step S2, it is determined whether the write data is “1” or “0”.

  If the write data is “1”, the process proceeds to step S3 and a cell selection operation is performed. In step S4, data reading from the memory cell is performed. In step S5, it is determined whether the read data is “1” or “0”. If the read data is "0", the process proceeds to step S6, and current is applied to write "1" to the memory cell. When step S6 ends, the process proceeds to step S10.

  On the other hand, when it is determined in step S5 that the read data is “1”, the writing operation is not performed and the process proceeds to step S10.

  If it is determined in step S2 that the write data is “0”, the process proceeds to step S7. In step S7, a memory cell to which data is written is selected in accordance with the write address, and subsequently, in step S8, data is read to determine what data is currently written in the memory cell to be written. Subsequently, an operation of writing data “0” is performed in step S9. When step S9 ends, the process proceeds to step S10.

  Although the data read operation in step S8 is not necessarily required, it is easier to use as a memory device if it is easier to avoid different cycle times when writing "1" and "0". It is what.

  In step S10, the memory cell selection and the like are reset, and the write cycle ends in step S11.

  FIG. 5 shows a data write cycle corresponding to the flowchart shown in FIG.

  Referring to FIG. 5, first in the “1” write cycle, when “0” is read in the read operation at time t1 to t2, an operation of writing “1” is performed at time t2 to t3. On the other hand, when “1” is read at time t1 to t2, no operation is performed (NOP: no operation).

  On the other hand, in the cycle in which “0” is written, “0” is written at time t2 to t3 regardless of whether “0” is read or “1” is read in the read operation at time t1 to t2. Perform the operation. The time t1 to t3 is one data write cycle.

  Conventionally, in order to prevent write disturb, the resistance value Rcell (H) of the memory cell in the high resistance state cannot be increased so much. However, if the resistance value Rcell (H) of the memory cell is not increased too much, the resistance ratio of the memory cell corresponding to the data “1” and “0” cannot be increased. If the resistance ratio of the memory cell cannot be increased, there is a problem that the read signal at the time of read access is reduced and the read access time is delayed.

  In the present invention, such a write cycle does not cause a write disturb problem. This is because “1” is not rewritten to the high resistance state (the state where “1” is held). Therefore, there is no restriction on the resistance of the memory cell, and the resistance value Rcell (H) of the memory cell when data “1” is held can be increased. The resistance ratio of the memory cells corresponding to the data “1” and “0” can be increased, the read signal can be increased, and the read access time can be increased.

FIG. 6 is a modification of the flowchart shown in FIG.
Referring to FIG. 6, a write cycle is started in step S21, and a memory cell to be written is selected in step S22 according to the input address. Subsequently, in step S23, data currently held in the memory cell to be written is read.

  In step S24, it is determined whether the read data and the write data match. If the read data and the write data do not match, data writing is performed in step S25. On the other hand, if the read data and the write data match in step S24, the data write in step S25 is not performed. In step S26, the selection of the memory cell and the like are reset, and the write cycle ends in step S27.

  FIG. 7 is a diagram for explaining a write cycle corresponding to the flowchart shown in FIG.

  Referring to FIG. 7, a read operation is performed at times t1 to t2, and a write operation is performed only when necessary at times t2 to t3.

  In the cycle of writing “1”, when “0” is read during the read operation at time t1 to t1, the operation of writing “1” is continued at time t2 to t3. On the other hand, if “1” is read in the read operation from time t1 to t2 in the cycle of writing “1”, the data “1” is already held in the memory cell, so it is not necessary to write. No operation (NOP).

  On the other hand, if “0” is read during the read operation from time t1 to t2 in the cycle in which “0” is written, the data to be written is already held in the memory cell, so that no operation (NOP) is performed. On the other hand, when “1” is read during the read operation from time t1 to t2 in the cycle of writing “0”, the operation of writing “0” is performed from time t2 to t3.

  By performing the operation shown in FIG. 6 and FIG. 7, rewriting (overwriting) data “1” in a case where a problem of write disturb occurs, that is, in a high resistance state (a state where data “1” is held). Since no writing is performed, the resistance of the memory cell is not limited, and the resistance value Rcell (H) in the high resistance state can be increased.

  Further, by avoiding unnecessary writing operations as much as possible, it is possible to reduce the problem of reliability due to heat generation.

FIG. 8 is a flowchart for explaining another modified example of the writing operation.
Referring to FIG. 8, a write cycle is started in step S31, and it is determined in step S32 whether the write data is “0” or “1”.

  If it is determined in step S32 that the write data is “1”, the process proceeds to step S33, where a cell selection operation is performed, followed by a read operation of data currently held in the cell selected as the write target. This is performed in step S34. In step S35, it is determined whether the data read in step S34 is “0” or “1”.

  If it is determined in step S35 that the data is "0", the process proceeds to step S36 and an operation for writing data "1" is performed. Then, the process proceeds to step S39. On the other hand, if it is determined in step S35 that the read data is “1”, the process proceeds to step S39 without going through step S36.

  If it is determined in step S32 that the write data is “0”, the process proceeds to step S37, and the memory cell to be written is selected. In step S38, data "0" is written. In this case, data reading is not performed. When the writing operation in step S38 is completed, the process proceeds to step S39.

  In step S39, the memory cell selection and the like are reset, and the write cycle ends in step S40.

  FIG. 9 is a diagram for explaining a write cycle corresponding to the flowchart shown in FIG.

  Referring to FIG. 9, in the cycle of writing “1”, a read operation is performed at times t1 to t2. When “0” is read in the read operation at time t1 to t2, the held data is different from the data to be written, and therefore, an operation of writing “1” is performed at time t2 to t4. .

  When “1” is read in the read operation at times t1 to t2 of the cycle in which “1” is written, the data already held in the memory cell is equal to the data to be written, and thus the write operation is performed. No (NOP).

  On the other hand, in the cycle in which “0” is written, the read operation at time t1 to t2 is not performed, and the operation to write “0” is performed immediately at time t1 to t3. This is because the state where “0” is held does not cause a write disturb problem because the resistance of the memory cell is low.

  The problem of write disturb can also be solved by performing the operations described in FIGS. That is, since the data rewriting of “1” to the high resistance state (the state holding data “1”) is not performed, there is no restriction on the memory cell resistance, and the memory cell resistance value Rcell (H) is increased. Can do. Further, in the cycle of writing “1”, an unnecessary write operation can be avoided as much as possible to reduce the reliability problem due to heat generation.

FIG. 10 is a flowchart for explaining another modified example of the write cycle.
Referring to FIG. 10, a write cycle is started in step S51, and it is determined in step S52 whether the write data is “1” or “0”.

  If it is determined in step S52 that the data is "1", the memory cell is selected in step S53, and the data currently held in the write target memory cell is read in step S54.

  Subsequently, in step S55, it is determined whether the read data is “0” or “1”.

  If it is determined in step S55 that the read data is “0”, the process proceeds to step S56, and a write operation of “1” is performed. Then, the process proceeds to step S61.

  On the other hand, if it is determined in step S55 that the read data is “1”, an operation of once writing “0” is performed in step S57 and then an operation of writing “1” in step S58. Then, the process proceeds to step S61. The reason why “0” is once written in step S57 is that the resistance value of the memory cell is thereby lowered and the operation of writing “1” is facilitated.

  If it is determined in step S52 that the write data is “0”, the process proceeds to step S59, and the memory cell to be written is selected. Thereafter, a write operation of “0” is performed in step S60, and the process proceeds to step S61.

  In step S61, the memory cell selection and the like are reset, and in step S62, the write cycle ends.

  FIG. 11 is a diagram for explaining a data write cycle according to the flowchart shown in FIG.

  Referring to FIG. 11, in the cycle of writing data “1”, a read operation is performed at times t1 to t2. When “0” is read in this read operation, an operation of writing “1” is performed at times t2 to t4.

  When “1” is read in the read operation from time t1 to t2 in the cycle in which data “1” is written, the read “1” data is temporarily changed to “0” data at times t2 to t4. Rewrite to As a result, the resistance value of the memory cell is reduced and “1” is written reliably.

Then, an operation of writing “1” is performed from time t4 to t5.
Accordingly, it is possible to prevent the data from being rewritten due to the slow heating of the memory cell due to the heating by the reading operation at the time t1 to t2.

  On the other hand, in the cycle of writing “0”, the read operation is not performed, and the operation of writing “0” is performed at times t1 to t3.

  The write cycle described with reference to FIG. 10 eventually becomes one data write cycle from time t1 to time t5 in FIG.

  The write disturb problem described in FIGS. 10 and 11 can also solve the write disturb problem. That is, the rewriting of “1” data to the high resistance state (the state holding “1”) is realized by performing the operation of writing “1” after writing “0” once. . Therefore, there is no restriction on the memory cell resistance, and the memory cell resistance value Rcell (H) can be increased.

  Further, by avoiding unnecessary writing operations as much as possible, it is possible to reduce the problem of reliability due to heat generation.

[Embodiment 2]
In the second embodiment, the problem of read disturb is solved.

FIG. 12 is a flowchart for illustrating the read cycle of the second embodiment.
Referring to FIG. 12, a read cycle is started in step S71. In step S72, a memory cell to be read is selected.

  Subsequently, a data read operation is performed in step S73, and it is determined in step S74 whether the read data is “0” or “1”.

  If the read data is “0”, the read disturb problem does not occur, and the process proceeds to step S76. On the other hand, if the read data is “1”, the data may be rewritten to “0” due to heating of the memory cell in the read operation, and the process proceeds to step S75. In step S75, an operation of writing "1" again is performed, and the process proceeds to step S76.

  In step S76, the memory cell selection and the like are reset, and in step S77, the write operation is completed.

FIG. 13 is a diagram for explaining the read cycle of the flowchart of FIG.
Referring to FIG. 13, a read operation is performed at times t1-t2 in the read cycle. When the read result is “0”, no operation is performed (NOP).

  On the other hand, if the data read at time t1 to t2 is “1”, the operation of writing data “1” is performed at time t2 to t3.

FIG. 14 is a flowchart showing a modification of the operation shown in FIG.
14 is different from FIG. 12 in that step S81 is provided between step S74 and step S75, and this data is temporarily rewritten to “0” when the memory cell holds “1”. Since the other steps have been described with reference to FIG. 12, description thereof will not be repeated.

FIG. 15 is a diagram for explaining the read cycle of the flowchart of FIG.
Referring to FIG. 15, a read operation is performed at times t1 to t2. When the read result is “0”, no operation is performed after time t2 (NOP).

  On the other hand, when “1” is read at times t1 to t2, an operation of writing “0” is performed at times t2 to t3, and an operation of subsequently writing “1” is performed at times t3 to t4. It is. As a result, when the memory cell holds “1”, erroneous data rewriting due to heating of the memory cell due to the read current is less likely to occur.

  That is, by providing step S81, the operation of writing “1” in step S75 for once reducing the resistance value of the memory cell can be performed more reliably.

FIG. 16 is a diagram showing a further modification of the flowchart shown in FIG.
The flowchart shown in FIG. 16 differs from the flowchart of FIG. 14 in that step S82 for performing an operation of writing “0” is provided between steps S74 and S76. Since the other steps have been described with reference to FIGS. 12 and 14, description thereof will not be repeated. Thus, the same data as the read data may be rewritten in both cases where the read data is “0” and “1”.

  As described above, when “1” is read from the memory cell, at least “1” is set in order to prevent the cell from being heated by the read current and destroying the data “1” held in the memory cell. After reading, the operation of writing “1” is performed. Thereby, there is no restriction on the resistance of the memory cell, and the resistance value Rcell (H) in the high resistance state of the memory cell does not have to be increased so much, so that reading is facilitated. Preferably, after “1” is read, “0” is once written and then “1” is written, thereby further simplifying the writing operation of “1”. In addition, when “0” is read, “0” may be rewritten.

[Embodiment 3]
In the third embodiment, a specific example and an improved example of the read / write circuit of the phase change memory will be described. These can be appropriately applied as improved examples of the conventional read operation and write operation, and as read and write circuit examples for the first and second embodiments, respectively.

FIG. 17 shows a write current waveform for data writing.
FIG. 18 is a diagram showing a configuration of a memory array for explaining a write operation of the phase change memory.

  17 and 18, memory cell 201 is provided corresponding to the intersection of word line WL1 and bit line BL1 of the memory cell array, and memory cell 202 is provided corresponding to the intersection of word line WL2 and bit line BL1. Is provided. Since the configuration of memory cells 201 and 202 has been described with reference to FIG. 2, description thereof will not be repeated.

  Switch 204 for connecting bit line BL1 to write data bus WDB is rendered conductive in response to activation of column select line CSL1. Bit line BLn is connected to write data bus WDB when switch 206 is turned on in response to activation of column select line CSLn. A variable current source 208 is provided between write data bus WDB and the power supply node. The variable current source 208 changes the current value and the current application time in accordance with the signal φ indicating the write data.

  The optimum current value and current pulse width for writing differ depending on whether the write data is “0” or “1”. As shown in FIG. 17, when "1" is written, the waveform WA1 is applied to the memory cell. In the waveform WA1, when a write current I1 is supplied in a short time from time t0 to time t1 and the memory cell is then rapidly cooled, a part of the memory cell becomes amorphous and the resistance value becomes high.

  On the other hand, when 0 is written in the memory cell, the write current I2 is supplied to the memory cell between times t0 and t3 as shown by the waveform WA2. The write current I2 has a smaller current value than the write current I1.

  As a result, the memory cell is recrystallized from the amorphous state to become a polycrystalline state. Then, the resistance value of the memory cell becomes low.

FIG. 19 is a circuit diagram showing the configuration of the variable current source 208 of FIG. 18 in more detail.
Variable current source 208 is connected between a power supply node and write data bus WDB, and has a gate connected to node N11 and a P-channel MOS transistor 210 connected between the power supply node and node N11 and has a gate connected to node N11. P channel MOS transistor 212 connected to node N, N channel MOS transistor 214 connected between node N11 and the ground node and receiving signal φ0 at the gate, and signal φ0 connected to the gate connected between node N11 and the ground node N channel MOS transistor 216 for receiving. N-channel MOS transistor 216 has a gate width W1, and N-channel MOS transistor 216 has a gate width W2. There is a relationship of W1 <W2 between these two gate widths. Signal φ0 is a signal that is activated when write data is 0, and signal φ1 is a signal that is activated when write data is 1.

  Variable current source 208 further includes NOR circuit 222 that receives signals φ0 and φ1, inverter 220 that receives and inverts the output of NOR circuit 222, and is connected between the power supply node and node N11 and has the gate output of inverter 220. P channel MOS transistor 218 for receiving.

FIG. 20 is an operation waveform diagram for explaining the operation of the variable current source shown in FIG.
Referring to FIG. 19 and FIG. 20, data writing is performed by storing current pulses having two types of current peak values and pulse widths according to the case where write data is “1” and “0”. This is done by flowing the cell. This current pulse is controlled by the variable current source 208.

  That is, a memory cell is selected by a word line WL, and a write current is applied through an access transistor included in the selected memory cell and a selection switch 204 selected by a column selection line CSL. During time t1 to t4, the word line WL and the column selection line CSL are activated. At this time, when “0” is written, the signal φ0 is activated between times t1 and t3. On the other hand, when “1” is written, the signal φ1 is activated instead of t1 to t2.

  When “0” is written, the current value in that case is determined by the gate width of the N-channel MOS transistor 214. When “1” is written, the write current value is determined by the gate width of N-channel MOS transistor 216. Since there is a relationship of W1 <W2, the current value when writing “1” is larger than the current value when writing “0”.

FIG. 21 is an operation waveform diagram showing a waveform obtained by improving the write operation shown in FIG.
In the circuit operation as shown in FIG. 20, since the memory cell must be rapidly cooled by “1” writing, it is not preferable to discharge the write data bus capacity or bit line capacity in the memory cell. This is because the time constant at the falling edge of the write current is large, so that the time during which the current flows becomes long and the phase change element may not be amorphized correctly without being rapidly cooled. Therefore, as shown by the solid line in FIG. 21, when “0” is written, the activation period of the word line WL and the column selection line CSL is set to be equal to the activation period of the signal φ0.

  On the other hand, when “1” is written, the activation period of the word line WL and the column selection line CSL is also between the times t1 and t2 in accordance with the activation period of the signal φ1, as shown by the broken line in FIG. Just do it. As a result, the memory cells 201 and 202 are disconnected from the bit line at time t2, so that the bit line is not discharged between time t2 and t3 via the memory cell.

  However, in the circuit operation as shown in FIG. 21, in the case of a memory configuration in which a plurality of bits are simultaneously written in the same memory mat, the memory cell in which “1” is written and the memory cell in which “0” is written are the same. When it exists on the memory mat, the timing for lowering the word line is not compatible.

  FIG. 22 is a circuit diagram showing a configuration when a plurality of bits are simultaneously written in the same memory mat.

  Referring to FIG. 22, memory cell 201A is provided corresponding to the intersection between bit line BLA and word line WL1, and memory cell 202A is provided corresponding to the intersection between bit line BLA and word line WL2. . In response to activation of column selection line CSLA, column selection switch 204A connects bit line BLA to write data bus WDBA. Variable current source 208A is provided corresponding to bit line BLA and write data bus WDBA. The configuration of variable current source 208A is similar to that of variable current source 208 shown in FIG. 9, and description thereof will not be repeated.

  A memory cell 201B is provided corresponding to the intersection between the word line WL1 and the bit line BLB, and a memory cell 202B is provided corresponding to the intersection between the word line WL2 and the bit line BLB. In order to connect bit line BLB to write data bus WDBB, column select switch 204B which is turned on in response to activation of column select line CSLB is provided. A variable current source 208B is provided corresponding to write data bus WDBB. Since the internal configuration of variable current source 208B is the same as that of variable current source 208A, description thereof will not be repeated.

FIG. 23 is an operation waveform diagram for describing a write operation of the configuration shown in FIG.
The operations of writing data “0” and data “1” are not performed at the same time, and these operations may be performed separately in time.

  Referring to FIG. 23, specifically, at time t1-t2, word line WL1 is activated, memory cell 201A in which data “0” is written is connected to the bit line, and column selection line CSLA is activated. This is connected to the variable current source 208A, and a predetermined current is applied to the memory cell 201A.

  At time t3 to t4, the word line WL1 is similarly activated, and the memory cell 201B in which data “1” is written is connected to the variable current source 208B via the bit line.

  As described above, the data “0” write operation and the “1” write operation are performed separately in time, so that the word line is quickly deselected according to the data, and the memory cell is quickly removed from the bit line. A plurality of data can be simultaneously written while being separated.

  In the circuit operation as shown in FIG. 19 to FIG. 23, the current source is a circuit that generates two kinds of current values. However, an equivalent operation can be realized by other methods.

FIG. 24 is a circuit diagram showing a configuration when data is written by another method.
24, the word line drive circuit 104A changes the activation potential of the word lines WL1, WL2,... Corresponding to the data φ0, φ1. Instead, the current source 208C may have a simpler configuration than the current source 208 of FIG.

  Specifically, current source 208C is connected between a power supply node and write data bus WDB, and has a gate connected to node N21, and is connected between the power supply node and node N21. P-channel MOS transistor 312 having a gate connected to node N21, N-channel MOS transistor 314 connected between node N21 and the ground node and receiving signal φw activated at the time of writing to the gate, power supply node and N21 And a P channel MOS transistor 313 receiving a signal φw at its gate. N-channel MOS transistor 314 has a gate width W2 similar to that of N-channel MOS transistor 216 in FIG. 19, and current supply capability of current source 208C itself is set to the capability of writing “1”. .

FIG. 25 is an operation waveform diagram for explaining the operation of the circuit shown in FIG.
Referring to FIG. 25, at time t1-t2, word line WL, column select line CSL and signals φw, φ0 are activated. During the period in which φ0 is activated, the word line drive circuit 104A sets the activation potential of the word line WL to be low, for example, 0.5V. Thereby, the current supplied from the current source 208C is limited, and the heating state of the memory cell is set low.

  On the other hand, from time t3 to t4, the word line WL, the column selection line CSL, and the signals φw and φ1 are activated. When signal φ1 is activated, word line drive circuit 104A sets the activation potential of the word line to be high, for example, 1.5V. As a result, the current supplied from the current source 208C is applied to the memory cell as it is without much current limitation, and the heating state of the memory cell is set high.

FIG. 26 is a circuit diagram showing a configuration when data is written by still another method.
In FIG. 26, the column selection circuit 112A changes the activation potential of the column selection line CSL corresponding to the data φ0 and φ1. As in the case of FIG. 24, the current source 208C may have a simpler configuration than the current source 208 of FIG. Since the configuration of current source 208C has been described with reference to FIG. 24, description thereof will not be repeated.

FIG. 27 is an operation waveform diagram for explaining the operation of the circuit shown in FIG.
Referring to FIG. 27, at time t1-t2, word line WL, column select line CSL and signals φw, φ0 are activated. During the period in which φ0 is activated, the column selection circuit 112A sets the activation potential of the column selection line CSL to be low, for example, 0.5V. Thereby, the current supplied from the current source 208C is limited, and the heating state of the memory cell is set low.

  On the other hand, from time t3 to t4, the word line WL, the column selection line CSL, and the signals φw and φ1 are activated. When signal φ1 is activated, column selection circuit 112A sets the activation potential of column selection line CSL to a high value, for example, 1.5V. As a result, the current supplied from the current source 208C is applied to the memory cell as it is without much current limitation, and the heating state of the memory cell is set high.

FIG. 28 is a diagram showing an improvement example regarding data reading of the phase change memory.
Referring to FIG. 28, memory cell 401 is provided corresponding to the intersection of word line WL1 and bit line BL, and memory cell 402 is provided corresponding to the intersection of word line WL2 and bit line BL. The bit line BL is connected to the read data bus RDB when the column selection line CSL is activated by the switch circuit 404.

  In order to initialize the potential of bit line BL to the ground potential, an N channel MOS transistor 410 connected between bit line BL and the ground node and receiving signal BL-RESET at its gate is provided.

  Sense amplifier 412 is connected between a power supply node and a node N31 and receives a signal φSA at its gate, and P channel MOS transistor whose gate and drain are connected to node N31 and whose source is connected to the power supply node. 416, and an N channel MOS transistor connected between node N31 and read data bus RDB and receiving reference potential Vref at its gate.

  Sense amplifier 412 further includes a P channel MOS transistor 418 connected between a power supply node and node N32 and having a gate connected to node N31, and an N channel MOS connected in series between node N32 and the ground node. Transistors 422 and 424. N channel MOS transistor 422 has its gate coupled to reference potential Vref. N channel MOS transistor 424 has its gate receiving signal φSA. Read output signal Dout is output from node N32.

FIG. 29 is an operation waveform diagram for describing a read operation of the configuration shown in FIG.
Referring to FIGS. 28 and 29, signal BL-RESET is deactivated from H level to L level at time t1, and then word line WL, column selection line CSL and signal φSA are activated at time t2. . Then, the potential of the bit line BL that has been reset to the L level by the N-channel MOS transistor 410 changes according to the data held in the selected memory cell. Data is read as a bit line potential and a bit line current.

  When the memory cell holds “0”, the bit line potential, the bit line current, and the output data Dout are read as shown by the solid line in FIG. On the other hand, when the memory cell holds data “1”, the bit line potential, the bit line current, and the signal Dout are output as shown by the broken line in FIG.

  At time t3 when reading ends, word line WL, column select line CSL and signal φSA are deactivated, and then signal BL-RESET is activated to H level at time t4.

As a result, the bit line potential is fixed at the L level after time t4.
FIG. 30 is an enlarged view of the bit line current in FIG.

  Referring to FIG. 30, when “0” is read from the memory cell, read current I-READ has a large current value. This is because the memory cell is in a low resistance state.

  On the other hand, when “1” is read from the memory cell, read current I-READ is small. This is because the memory cell is in a high resistance state.

  That is, the sense amplifier 412 of FIG. 28 converts the difference in resistance of the memory cell from the memory cell via the bit line and the read data bus into a read voltage as a current difference and outputs it.

[Embodiment 4]
FIG. 31 is a circuit diagram showing a configuration related to data writing according to the fourth embodiment.

  In addition to the configuration shown in FIG. 19, the configuration shown in FIG. 31 compares the potential Vcont of the write data bus WDB with the reference potential Vref and outputs the signal Vwrite, and the signal φ1 and the comparison circuit. AND circuit 454 receiving the output of 452. Note that the output of the AND circuit 454 is applied to the N channel MOS transistor 216 instead of the signal φ1.

FIG. 32 is an operation waveform diagram showing waveforms during the write operation of the configuration shown in FIG.
FIG. 33 is a diagram showing the relationship between the output signal of the comparison circuit and the input signal.

  Referring to FIGS. 32 and 33, data writing is performed by applying to the memory cell current pulses having two kinds of current peak values and pulse widths according to write data “1” / “0”. . A memory cell is selected by a word line WL, and a write current is applied to the phase change element via an access transistor in the memory cell and a selection switch 204 selected by a column selection line CSL. Selection by the word line and the column selection line is performed between times t1 and t4. When data “0” is written, the signal φ0 is activated between times t1 and t3. On the other hand, when data “1” is written, the signal φ1 is activated between times t1 and t2.

  At this time, it is desirable to perform a write operation on the memory cell storing the data regardless of the stored data in order to realize a high-speed write cycle. However, when “1” data is written in a memory cell that stores “1” (a memory cell in a high resistance state), the memory cell resistance is “0”, which is about 10 times. Is getting bigger. For this reason, a current required for sufficient heating cannot be supplied to the memory cell.

  Therefore, when a write operation is performed regardless of the data held in the memory cell, as a result, when “1” is held, a small current is passed and the result is gradually heated. The slow heating of the memory cell is the direction in which data “0” is written. Therefore, the intention of writing data “1” is changed, which causes data destruction.

  As a countermeasure against this, it is preferable to detect that the voltage near the current source increases when no current flows in the memory cell, and to interrupt the writing operation. This detection is performed by the comparison circuit 452. As a result, the memory cell temperature can be prevented from rising to a transition temperature at which it transitions from amorphous to polycrystalline due to gradual heating, and data destruction can be prevented. Further, it is not necessary to perform a read operation for grasping the data holding state of the memory cell in the write cycle.

  The operation of the variable current source 208 will be described more specifically. When the resistance value of the memory cell is small, that is, when the phase change element is in a polycrystalline state, the current value determined by the gate width of N channel MOS transistors 214 and 216 is constituted by P channel MOS transistors 210 and 212. It flows to the memory cell by the current mirror. Corresponding to this current value, the memory cell becomes polycrystalline or amorphous.

  On the other hand, when the resistance value of the memory cell is large, that is, when the phase change element is in an amorphous state, the potential Vcont rises to the upper limit before the current value determined by the N-channel MOS transistors 214 and 216 flows through the memory cell. Therefore, P channel MOS transistors 210 and 212 do not operate as a current mirror. Therefore, when data “1” is written when the resistance value of the memory cell is large, a small current flows through the memory cell as a result. If this small current flows for a long time, the phase change element changes from an amorphous state to a polycrystalline state. In order to prevent this, when the potential Vcont exceeds the reference potential Vref in FIG. 33, the output potential Vwrite changes from the H level to the L level, and the gate of the N-channel MOS transistor 216 is deactivated. Therefore, when the potential Vcont exceeds the reference potential Vref, the operation of the current source 208 is stopped. Thereby, an amorphous state is maintained.

[Embodiment 5]
In the fifth embodiment, implementation of memory cell parameters for solving the problem of write disturb and read disturb will be described.

The current setting required for rewriting the memory cell is
Icell (“1” Write)> Icell (“0” Write) (1)
It is.

In Expression (1), Icell (“1” Write) is a memory cell current for rewriting a memory cell holding data “0” to data “1”. Further, Icell (“0” Write) is a memory cell current for rewriting a memory cell holding data “0” or “1” to “0”.

  When the memory cell holds “0”, the phase change element is in a polycrystalline state, and the memory cell is in a low resistance state. On the other hand, in a state where data “1” is held, the phase change element is in an amorphous state and the memory cell is in a high resistance state. The resistance value of the memory cell in the high resistance state is about 10 times that in the low resistance state. In order to overwrite “1” to the memory cell in the high resistance state, it is necessary to pass a predetermined current through the memory cell.

  In order to pass a predetermined current through the memory cell in the high resistance state, it is necessary to apply a voltage about 10 times the voltage applied to the memory cell in the low resistance state. However, under the condition that a constant operating power supply voltage is used, the voltage cannot be applied 10 times, and the current is limited to a small value by the Ids of the access transistor of the memory cell (it also depends on the area of the memory cell). For example, I <200 μA). Therefore, when “1” is overwritten in a memory cell in which data “1” is held, it is not usually a predetermined current for amorphization, and only slow heating is performed because the current value is small. It will end. However, if the memory cell reaches a temperature at which polycrystallization progresses somewhat while repeating this slow heating many times, "1" data is destroyed and "0" is maintained.

  More specifically, when the memory cell data is “1” (amorphous state), the flowing current is small even when the same voltage is applied as when the memory cell data is “0” (polycrystalline state). Even if the cell is heated a little, the temperature should not reach the temperature at which polycrystallization progresses and the amorphous state should be maintained. However, if the degree of heating exceeds the expected level due to variations in memory cell characteristics, variations in applied current value, etc., it may be possible to reach a temperature at which polycrystallization proceeds to some extent. There is a problem that data that should be “1” may be rewritten to “0”.

  In order to avoid such a problem, the amount of heat generated when “1” is overwritten in a memory cell holding data “1” does not rise to the transition temperature at which the memory cell becomes polycrystallized. Set as appropriate. For example, the current value is made small and the width of the current pulse is made sufficiently short.

  Next, considering the case of reading, when data “1” is read, a current is passed through the memory cell for reading the memory cell data.

The current flowing at this time is Icell (“1” Read). The larger the current for reading, the better for speeding up the read access. However, if the current is too large, the memory cell is gradually heated by passing the current through the memory cell. While this is repeated many times, the “1” data is destroyed and becomes “0” data. In order to avoid such a read disturb problem, Icell (“1” Read) is set to be sufficiently small so that the amount of generated heat does not reach the transition temperature at which the memory cell becomes polycrystallized. For this purpose, the current value is made small and the current pulse width is made sufficiently short. at least,
Icell (“0” Write)> Icell (“1” Read) (2)
To satisfy.

From Equations (1) and (2), the upper limit of Icell (“1” Read) is determined. This and the following formula Icell (“0” Read)> Icell (“1” Read)
Icell (“0” Read) determined by the above determines the read access speed. In order to increase the speed of read access, for example, Icell (“0” Read)> 10 μA is required.

From the formulas (1) and (2),
Icell (“1” Write)> Icell (“0” Write)> Icell (“1” Read) (3)
Is guided. The inequality sign in equation (3) is not a relationship of the absolute value of the current but a comparison in terms of the amount of heat generated including the current application time. The memory cell arrival temperature when writing “1” and “0” is Tcell (“0” Write), the memory cell arrival temperature when reading “1” is Tcell (“1” Read), and “1” is “1”. The memory cell arrival temperature when overwriting “T” is Tcell (“1” Overwrite), and the temperature at which the phase change element of the memory cell undergoes phase change is T (transition).
Tcell (“1” Write)> Tcell (“0” Write)> Tcell (“1” Read) (4)
Tcell (“1” Read) <T (transition) (5)
Tcell (“1” Overwrite) <T (transition) (6)
These are summarized in the following three formulas.

  Setting the material / structure / resistance value of the memory cell element, setting the material / structure / resistance value of the heater element, and the memory cell operating voltage / current to satisfy these conditions can avoid the problem of write disturb and read disturb. A change memory can be realized. Thereby, the reliability of the data of the phase change memory cell can be improved.

  All of the above embodiments can be applied regardless of the configuration of the memory cell. 2 illustrates the configuration of the memory cells arranged in the order of bit line BL-transistor AT-heater element HE-phase change element PE-ground node. For example, as shown in FIG. 34, bit line BL-phase change element The configuration of the memory cell may be modified so as to be arranged in the order of PE-heater element HE-transistor AT-ground node.

[Embodiment 6]
In the conventional phase change memory using chalcogenide glass or the like, there is a problem that in the memory cell access operation, the temperature rise of the memory cell due to the heat generated during writing affects the operation of the next cycle.

  That is, in the phase change memory, when data is written to a selected memory cell, the temperature of the memory cell rises to 500 ° C. or more at the end of the write operation. The cell is heated to 500 ° C or higher, whether it is amorphous after heating (high resistance = writing data "1") or polycrystallizing by removing heat (low resistance = writing data "0") The temperature rise is similar.

  Therefore, when the next cycle is performed immediately after the end of the write operation, if the operation for accessing the same memory cell as the memory cell for which selective writing has been performed, that is, the operation for reading or writing, the cell is normally Unlike the cell, since the temperature is high, the following problems (1) and (2) occur.

  (1) When the next cycle is reading, the resistance of the normal cell at normal temperature and the memory cell are different, and the resistance is small. For this reason, in the data sense read operation, whether the reference level is applied or the dummy cell is used, it is conceivable that the reference level and the dummy level are not suitable and the sense margin is impaired.

  (2) When the next cycle is writing, the temperature of the memory cell at the start of the next cycle is higher than usual. On the other hand, when a normal write current is applied, the temperature of the memory cell at the time of writing becomes higher than the target, and the memory cell is excessively heated, resulting in a decrease in reliability and a decrease in write margin. To.

In the sixth to eighth embodiments, these problems are solved.
In the sixth embodiment, means for effectively solving the problem without impairing actual timing use, that is, without significantly impairing the data rate as a memory device will be described.

  For this reason, at the end of the write cycle, a cooling time sufficient for cooling the written memory cell to a predetermined temperature is ensured.

  As a method of ensuring, first, it is conceivable to insert a cell cooling time inside at the end of the write cycle operation.

FIG. 35 is a diagram for explaining the cooling time of the memory cell.
Referring to FIG. 35, a case where “1” is written (rapid cooling) will be described first. A cell write current is applied at time t1 to t2, and the temperature of the memory cell is slightly delayed after the increase of the applied current. The outside air temperature Temp (Amb) rises to the temperature Temp (A). At time t2, the supply of the write current is stopped, and accordingly, the temperature of the memory cell decreases from the temperature Temp (A) to near the outside air temperature Temp (Amb) between times t2 and t3. The time between the times t2 and t3 is defined as a cooling time Tcool (A).

  On the other hand, a case where data “0” is written (heat removal) will be described. A current smaller than that at the time of writing “1” is applied at time t1, and accordingly, the temperature of the memory cell rises from the outside air temperature Temp (Amb) to the temperature Temp (P) between times t1 and t2. By maintaining the memory cell that has been made amorphous at this temperature Temp (P) for a while, the phase of the memory cell changes from the amorphous state to the polycrystalline state.

  At time t4, the application of the write current to the memory cell is stopped, and accordingly, the temperature of the memory cell decreases from temperature Temp (P) to near the outside air temperature Temp (Amb) between times t4 and t5. The cell cooling period in this case is a time Tcool (P) from time t4 to time t5.

  In FIG. 35, the falling waveform of the cell temperature described on the upper side is not similar to the falling waveform of the cell writing current shown on the upper side, and the change in temperature follows the current with a slight delay. Need to be careful.

  A description will be given of inserting the cell cooling time inside at the end of the write cycle operation. After the end of the internal write cycle, that is, after the application of the write current to the memory cell is completed, the self-timing is set so that the next cycle acceptance is started after the cooling period of the memory cell has passed. The cooling time of the memory cell is determined based on the balance between the temperature reached by the memory cell at the time of writing and the heat dissipation capability of the memory cell.

  Assuming that the cell arrival temperature in amorphization is Temp (A) and the cell arrival temperature in polycrystallization is Temp (P), Temp (A)> Temp (P), so the necessary cooling time in amorphization is the same as in polycrystallization. It is longer than the required cooling time after polycrystallization.

  That is, if the required cooling time at the end of the amorphization cycle is Tcool (A) and the required cooling time at the end of the polycrystallization cycle is Tcool (P), then Tcool (A)> Tcool (P). Here, amorphization is a case where data “1” is written, and polycrystallization is a case where data “0” is written.

Therefore, the amorphization write cycle time is T (A), the polycrystallization write cycle time is T (P), the amorphization write time is Tc (A), and the polycrystallization write time is If Tc (P),
Tc (A) = T (A) + Tcool (A)
Tc (P) = T (P) + Tcool (P)
T (A) <T (P), Tcool (A)> Tcool (P)
It becomes.

Tcool (A) and Tcool (P) are obtained from the temperature reached during writing and the heat dissipation time constant τ. For example, when the outside air temperature is Temp (Amb), the time during which the temperature rise during writing is cooled to Temp (Amb) + α is as follows:
Temp (Amb) + (Temp (A) −Temp (Amb)) * exp (−Tcool (A) / τ) = Temp (Amb) + α
Is established.

If you change the expression,
Tcool (A) = τ * log [(temp (A) −Temp (Amb)) / α)]
Similarly, Tcool (P) = τ * log [(Temp (P) −Temp (Amb)) / α)] is also established.

  From the above equation, Tcool (A) −Tcool (P) = τ * log [(Temp (A) −Temp (amb) / (Temp (A) −Temp (Amb))] holds.

The cooling time may be ensured while maintaining this relationship.
These cooling times are started when the application of the write current to the memory cell is finished. For example, when the word line falls and the cell application current ends, or when the word line is in a selected state but the current application to the cell is stopped from the bit line system.

  Actually, since Tcool (A)> Tcool (P), the time to reach the normal temperature is set at the end of the amorphization cycle (data “1” write cycle), and this is set at the end of the polycrystallization cycle. If it is applied, it will be enough time.

  FIG. 36 shows inserting an external NOP cycle at the end of the write cycle.

  FIG. 36 shows the number of clock cycles required for reading = 1, the number of clock cycles required for writing “1” = 2, the number of clock cycles required for writing “0” = 4, and the NOP required for cooling the memory cells after the writing cycle. It is written on the assumption that cycle = 1, but it is not limited to this.

  First, in operation content # 1A, a write “1” cycle is performed in clock cycles 1 and 2. Subsequently, in clock cycle 3, a NOP cycle (no operation cycle) is performed. Thereby, the memory cell heated at the time of writing is cooled to a necessary temperature. Subsequently, data reading from the memory cell is performed in clock cycle 4. Then, a write “0” cycle is performed in clock cycles 5 to 8. Since writing has been performed, a NOP cycle is inserted in clock cycle 9. In subsequent clock cycle 10, a read operation is performed.

In operation content # 1B, a write “1” cycle is performed in clock cycles 1 and 2. Subsequently, in clock cycle 3, a NOP cycle (no operation cycle) is performed. Thereby, the memory cell heated at the time of writing is cooled to a necessary temperature. Subsequently, a write “0” cycle is performed in clock cycles 4 to 7. Since writing has been performed, a NOP cycle is inserted in clock cycle 8.

  Thus, the cooling time is ensured by the NOP cycle after the write operation is performed. Ensuring sufficient cooling time to satisfy the relationship as described above is realized by inserting a NOP cycle. For simplicity, the operation cycle after writing may be limited by using an external input timing standard (spec) that one cycle of NOP must be inserted after the writing cycle.

FIG. 37 is a diagram showing another operating condition (second method).
37 also shows the number of clock cycles required for reading = 1, the number of clock cycles required for writing “1” = 2, the number of clock cycles required for writing “0” = 4, and the NOP required for cooling the memory cells after the writing cycle. It is written on the assumption that cycle = 1, but it is not limited to this.

  First, in operation content # 3A, a NOP cycle is first provided in clock cycle 1. A write “1” cycle is performed in clock cycles 2 to 3. Subsequently, data reading from the memory cell is performed in clock cycle 4. Subsequently, a NOP cycle is performed in clock cycle 5. Thus, subsequent writing is performed after the heated memory cell is cooled to a necessary temperature. In clock cycles 6 to 9, a write “0” cycle is performed. In subsequent clock cycle 10, a read operation is performed. Since reading is not heated as much as writing, it is not necessary to provide a NOP cycle for cooling before reading.

  In operation content # 3B, a NOP cycle is first provided in clock cycle 1. A write “1” cycle is performed in clock cycles 2 to 3. Subsequently, a NOP cycle is performed in clock cycle 4. Thus, subsequent writing is performed after the heated memory cell is cooled to a necessary temperature. Then, a write “0” cycle is performed in clock cycles 5 to 8.

  Thus, the cooling time is secured in advance by the NOP cycle before the writing operation is performed. Ensuring sufficient cooling time to satisfy the relationship as described above is realized by inserting a NOP cycle. For simplicity, the operation cycle after writing may be limited by using an external input timing standard (spec) that one cycle of NOP must be inserted before the writing cycle.

  That is, as described with reference to FIG. 36, the cooling time may be entered at the end of the write cycle, but the same effect can be obtained even if it is entered before the start of the write cycle as shown in FIG. In other words, it is possible to prevent a decrease in margin and a decrease in reliability during the write operation in the next operation cycle due to the temperature rise of the write cell.

  As a third method, when writing to the same address continues, there is a method of inserting an external NOP cycle or a read cycle between them.

  FIG. 38 is a flowchart for explaining the operation for continuous writing to the same address.

  Referring to FIG. 38, when a writing cycle is started, it is determined in step S101 whether or not writing is continued twice. If writing is not continued twice, step S103 is entered. Then, a normal write operation is performed on the selected cell. On the other hand, if the writing is continued twice in step S101, the process proceeds to step S102. In step S102, it is determined whether or not the first address Add1 and the second address Add2 are the same as the access address.

  If the access addresses are not equal, the process proceeds to step S103 and a normal write operation to the selected cell is performed. On the other hand, if the access addresses are equal, the process proceeds to step S104, and the write operation to the selected cell is performed after the cooling time. When step S103 or S104 ends, the process proceeds to the next cycle.

FIG. 39 is a diagram showing operations corresponding to the flowchart of FIG.
Referring to FIG. 39, in clock cycles 1 and 2, the operation of writing “1” to address Add1 is performed. Subsequently, in clock cycles 3 to 6, a write “0” operation is performed for address Add2 whose address is different from the previous address. Between clock cycles 2 and 3, since it is a continuous write to different addresses, a NOP cycle is not inserted. On the other hand, it is assumed that the write “1” operation is instructed to the same address following the write “0” in clock cycles 3 to 6. In this case, since continuous writing to the same address Add2 is performed, a NOP cycle is inserted in clock cycle 7. For example, a read cycle may be used instead of the NOP cycle. Then, in clock cycles 8 to 9, the operation of writing “1” to address Add2 is performed.

  As shown in FIG. 39, if the input timing standard is to avoid continuous writing to the same address and to secure a cooling time if necessary, it is possible to maintain high speed operation in the case of continuous writing with different addresses. The same cooling time as in the first and second methods described above can be ensured by an external NOP or readout cycle.

  The memory cell to which data has been selected and written by any one of the first to third methods waits until it returns to the vicinity of the normal temperature, and then the next cycle is performed. It is possible to prevent a decrease in margin and a decrease in reliability during access to the same cell during recycling due to a temperature rise.

[Embodiment 7]
Other than the example shown in the sixth embodiment, the same operation is performed according to the cycle operation of the continuous cycle of writing and reading (the same address, different addresses) and the continuous cycle of writing and writing (the same address, different addresses) An example that solves the problem is described below.

In the seventh embodiment, problem solving in a read cycle after a write cycle will be described.
FIG. 40 is a block diagram showing a configuration of the phase change memory according to the seventh embodiment.

  Referring to FIG. 40, phase change memory 500 includes address input terminal 521, address input buffer 501, WE input terminal 522, WE signal input buffer 502, data input terminal 523, data input buffer 503, data An output terminal 524 and a data output buffer 504 are included.

  Phase change memory 500 further receives write address register 507 that temporarily holds the address output from address input buffer 501 in response to signal WE, and the address of the previous cycle from write address register 507, and receives the current cycle. An address match comparison circuit 508 that receives an address from the address input buffer 501 and compares them, a write data register 509, switches 505 and 506, an X decoder & WL driver 510, a Y decoder & data I / O circuit 511, Phase change memory cell array 512.

X decoder & WL driver 510 performs decoding operation and word line driving in accordance with the output of address input buffer 501. The switch 505 selects and outputs one of the two systems of the write data register and the Y decoder & data I / O circuit 511 according to the signal WE. The switch 506 selects either the output of the write data register 509 or the output of the Y decoder & data I / O circuit according to the signal WE and the output of the address coincidence comparison circuit 508 and outputs it to the data output buffer 504 To do.

  As shown in FIG. 40, a write data register 509 and a write address register 507 are provided, and data is written to the selected memory cell and stored in the registers 509 and 507 during the write cycle. .

  FIG. 41 is a flowchart for explaining the operation of the phase change memory according to the seventh embodiment.

  Referring to FIG. 41, when a write cycle is first started, a cycle (# 1) of writing data into a selected cell is performed in step S111. In this case, the input address is Add1, and the data is data # 1.

  Subsequently, in step S112, it is determined whether or not (# 2) access address Add2 is equal to Add1. If the addresses are equal, the process proceeds to step S113, and if the addresses are different, the process proceeds to step S116.

  In step S113, it is determined whether the next cycle (# 2) is reading or writing. If the next cycle (# 2) is reading, the process proceeds to step S114. Since the write data when the same address continues is temporarily held in the write data register, the data is read from the write data register and output to the outside in step S114.

  On the other hand, if it is determined in step S113 that the next cycle (# 2) is writing, the process proceeds to step S115. In this case, the write operation to the selected memory cell is performed after the cooling time.

  On the other hand, also in step S116, it is determined whether the next cycle (# 2) is reading or writing. If the cycle is read, the process proceeds to step S117, and a read operation from the selected cell is performed. If the next cycle is a write cycle, the process proceeds to step S118 to perform a write operation to the selected cell. In this case, since the access addresses are different, it is not necessary to set a cooling time for writing and reading.

  When step S114 is completed and when step S117 is completed, the process proceeds to step S119, and it is determined whether the next cycle (# 3) is reading or writing. When the next cycle (# 3) is read, the operation of the next cycle is performed as a normal operation as it is.

  On the other hand, if it is determined in step S119 that the next cycle (# 3) is a write operation, or after a write operation is performed as in steps S115 and S118, the process proceeds to * 1.

  As described with reference to FIG. 41, data is written to the selected memory cell and this data and address are stored in the register during the write cycle. If the next cycle is a read and the same address as the write in the previous cycle is input, the write data stored in the register is accessed as read data, and the memory corresponding to the address The cell is not written with data.

  On the other hand, when the next cycle is a read operation, when an address different from the write operation of the previous cycle is input, the memory cell data is read as usual.

  FIG. 42 is a circuit diagram showing phase change memory cell array 512 and its peripheral circuits in FIG.

  Referring to FIG. 42, memory cell array 512 is connected to read circuit 531 and current application circuit 532. Read circuit 531 and current application circuit 532 are circuits included in Y decoder & data I / O circuit 511 of FIG.

  The memory cell array 512 is connected to the word line WL1 and connected to the bit lines BL1 to BL4, respectively, and the memory cells 621 to 614 connected to the word line WL2 and connected to the bit lines BL1 to BL4, respectively. 624.

  Memory cell array 512 further includes memory cells 631 to 634 connected to word line WL3 and connected to bit lines BL1 to BL4, respectively, and memory cells connected to word line WL4 and connected to bit lines BL1 to BL4, respectively. 641-644.

  The word lines WL1 to WL4 are selectively driven by the X decoder & WL driver 510 of FIG.

  Memory cells 611 to 614 and memory cells 621 to 624 are connected to source line SL1, and memory cells 631 to 634 and memory cells 641 to 644 are connected to source line SL2.

  Each of memory cells 611-644 includes a heater element 650, a phase change element 651, and an access transistor 652 connected in series between the corresponding bit line and source line. Access transistor 652 has its gate connected to the corresponding word line. The order in which the three elements of the heater element 650, the phase change element 651, and the access transistor 652 are connected in series is not limited to the case shown in FIG. 42. For example, the order shown in FIGS. May be.

  Read circuit 531 includes switches 551 to 554, read data lines RDB1 and RDB2 that are selectively connected to bit lines BL1 to BL4 by switches 551 to 554, and sense amplifiers 541 that are connected to read data lines RDB1 and RDB2, respectively. , 542.

  Switch 551 connects read data line RDB1 and bit line BL1 in response to signal RCSL1. Switch 552 connects read data line RDB2 and bit line BL2 in response to signal RCSL1. Switch 553 connects read data line RDB1 and bit line BL3 in response to signal RCSL2. Switch 554 connects read data line RDB2 and bit line BL in response to signal RCSL2.

  The current application circuit 532 outputs a current for writing data by applying heat to the memory cells 611 to 644. Current application circuit 532 is connected to switches 571 to 574, write data lines WDB1 and WDB2 that are selectively connected to bit lines BL1 to BL4 by switches 571 to 574, and write data lines WDB1 and WDB2, respectively. Variable current sources 561 and 562.

FIG. 43 is a circuit diagram showing a configuration of variable current source 561 in FIG.
Referring to FIG. 43, variable current source 561 has a P channel MOS transistor 661 connected between the power supply node and write data line WDB1, a source connected to the power supply node, and a gate and drain connected to P channel MOS. P-channel MOS transistor 662 connected to the gate of transistor 661, P-channel MOS transistor 663 whose source is connected to the power supply node, and whose drain is connected to the gate of P-channel MOS transistor 661, and the gate of P-channel MOS transistor 661 And N-channel MOS transistors 667 and 668 connected in parallel to each other and receiving signals φ0 and φ1 at their gates, respectively. N channel MOS transistor 667 has a gate width W1, and N channel MOS transistor 668 has a gate width W2. There is a relationship of W1 <W2 between W1 and W2.

  Variable current source 561 further includes a NOR circuit 665 that receives signals φ0 and φ1, and an inverter 664 that receives and inverts the output of NOR circuit 665 and outputs the inverted signal to the gate of P-channel MOS transistor 663.

  42 is different in that the variable current source 562 is connected to WDB2 in place of the write data line WDB1 in the configuration of the variable current source 561, but the internal configuration is the same, and therefore description thereof will not be repeated.

FIG. 44 is an operation waveform diagram for describing a write operation to a memory cell.
Referring to FIG. 44, at time t1, the potential of the corresponding word line WL and the signal CSL for selecting the corresponding bit line are activated from the L level to the H level. When "0" is written, signal φ0 is activated to H level between times t1 and t3. On the other hand, when “1” writing is performed, signal φ1 is activated to H level between times t1 and t2. In this case, signal φ1 is inactivated to L level between times t2 and t3. At time t4, the word line is deactivated and the bit line is disconnected from the variable current source, thereby completing the write cycle.

FIG. 45 is a circuit diagram showing a configuration of sense amplifier 541 in FIG.
Referring to FIG. 45, sense amplifier 541 has a P channel MOS transistor 671 connected between read data line RDB1 and the power supply node, a source connected to the power supply node, and a gate and a drain connected to P channel MOS transistor 671. P channel MOS transistor 672 connected to the gate of P channel, and a P channel MOS transistor 673 having a source connected to the power supply node and a drain connected to the gate of P channel MOS transistor 671. P channel MOS transistor 673 has its gate receiving signal φRead.

  Sense amplifier 541 is further connected between the gate of P-channel MOS transistor 671 and the ground node, N-channel MOS transistor 675 receiving signal φRead at the gate, -input node connected to read data line RDB1, and + input Comparing circuit 674 having a node connected to the drain of N channel MOS transistor 675 and outputting signal SAOUT. N-channel MOS transistor 675 has a gate width W1.

  Sense amplifier 541 further includes a comparison circuit 674 having a negative input node connected to read data line RDB1, a positive input node connected to the gate of P channel MOS transistor 671, and outputting signal SAOUT.

  Sense amplifier 542 in FIG. 42 is different in that read data line RDB2 is connected instead of read data line RDB1, but the internal configuration is the same as that of sense amplifier 541, and therefore description thereof will not be repeated.

FIG. 46 is an operation waveform diagram for describing a read operation.
Referring to FIG. 46, at time t1, corresponding word line WL is activated from L level to H level, and signal CSL is at L level in order to connect corresponding bit line BL to corresponding read data line RDB. To H level. Thereafter, signal φRead is activated from L level to H level, P channel MOS transistor 673 of sense amplifier 541 is turned off, N channel MOS transistor 675 is turned on, and sense amplifier 541 is activated. Data is read out.

  At time t2, the signal φRead is deactivated from the H level to the L level, the sense amplifier 541 finishes the operation, and then the word line WL is deactivated at the time t3, and the corresponding bit line BL is read correspondingly. Disconnected from the data line RDB.

The configurations and operations described in FIGS. 42 to 46 are characterized by the following points.
First, the data line is divided into a write system (WDB) and a read system (RDB). Each of the writing system and the reading system has a plurality of paths. As a result, the load capacity of the data bus can be reduced and a high-speed access operation can be performed.

  Second, at the time of reading, a signal φRead is activated by a one-shot operation as shown in FIG. 46, thereby causing a read current to flow to the memory cell via the bit line. As a result, a read current flows for a time required for the sense operation of the sense amplifier. Then, a read current is not allowed to flow between times t2 and t3. Thereby, the heat generation of the memory cell due to an unnecessary read current can be suppressed, and the memory cell data can be prevented from being destroyed.

FIG. 47 is a diagram showing a modification of the sense amplifier shown in FIG.
Referring to FIG. 47, sense amplifier 680 is connected between a power supply node and read data line RDBn, has a gate connected to P channel MOS transistor 681 receiving signal φRead, and read data line RDBn. And an inverter 682 that outputs SAOUT.

FIG. 48 is an operation waveform diagram for illustrating the operation of the sense amplifier shown in FIG.
47 and 48, signal φRead changes from the L level to the H level at time t1, whereby P channel MOS transistor 681 is rendered non-conductive. As a result, the precharge state of read data line RDBn is released.

  Then, word line WL is activated and signal CSL changes from L level to H level, whereby the memory cell is connected to read data line RDB through the corresponding bit line. Then, the electric charge of read data line RDB precharged to H level is discharged from the memory cell via the bit line, so that the potential of bit line BL changes. After this change, the potential of the bit line BL becomes high when the resistance of the memory cell is high, and becomes low when the resistance value of the memory cell is low.

  Accordingly, the potential of read data line RDB is high when the resistance of the memory cell is high, and the potential is low when the resistance of the memory cell is low. This potential is inverted and amplified by the inverter 682, and the signal SAOUT becomes L level when the resistance of the memory cell is high, and becomes H level when the resistance of the memory cell is low.

  At time t2, the word line is deactivated, the signal CSL is deactivated to the L level, and the signal φRead changes to the L level, so that the read data line RDB is disconnected from the bit line and is pre-charged by the transistor 681 again. It is in a charged state.

  47 and FIG. 48, the read voltage is generated by discharging the precharge charge of the read data line (RDB) at the time of reading. Therefore, only a current that flows through the memory cell at most is sufficient to discharge the charge accumulated in the parasitic capacitance of the read data line. In this case, since the charge is automatically limited so that the read operation is completed, heat generation of the memory cell due to an unnecessary read current can be suppressed, and destruction of the memory cell data can be prevented.

  As described above, according to the configuration described in the seventh embodiment, it is possible to prevent a decrease in margin and a decrease in reliability during the read operation in the next cycle due to the temperature increase of the write cell.

  In addition, when the write data register 509 and the write address register 507 are provided in preparation for the case where the write cycle and the read cycle are continuously performed as described in FIG. 40, these registers are provided as follows. Can also be used when two write cycles are consecutive.

  The first cycle is writing, and at that time, data and address are stored in a register. If the subsequent second cycle is a write, first, when the next cycle is written to the same data at the same address as the write of the previous cycle, the internal processing is In the NOP cycle, the operation of writing data in the memory cell specified by the address is not performed. In the case where two write cycles are continued, even if the address is the same address as the write in the previous cycle, if the data to be written is different from the data in the previous cycle, the operation of writing the data into the memory cell is performed. Cooling time is inserted at the beginning.

  Thirdly, in the case where two write cycles are continued, if the address of the previous circle is different from the input address, an operation of writing data into the memory cell is performed. In this case, the cooling time is not inserted into the cycle.

  By doing so, it is possible to prevent a decrease in margin and a decrease in reliability during the write operation in the next cycle due to the temperature rise of the write cell.

[Embodiment 8]
In general, a memory device normally has a configuration in which input / output is simultaneously performed from a plurality of terminals. For example, data of 16-bit width or 32-bit width is often read or written simultaneously.

FIG. 49 is a diagram for describing a case where writing is simultaneously performed on two cells.
The configuration shown in FIG. 49 is the same as that shown in FIG. When word line WL2 and signal WCSL1 or signal RCSL1 are selected, memory cells 621 and 622 indicated by thick broken lines in FIG. 49 are selected. That is, two adjacent cells may be selected. Therefore, in this configuration, memory cells to be simultaneously written may be adjacent to each other, whereby the heat generated by these two cells affects other cells, and the write operation margin is reduced due to overheating of the memory cells and the reliability. May cause degradation problems.

  FIG. 50 is a diagram showing a configuration for solving the problem of overheating due to heat generation of adjacent memory cells.

  The configuration shown in FIG. 50 includes a readout circuit 531A instead of the readout circuit 531 in the configuration described in FIG. 42, and a current application circuit 532A instead of the current application circuit 532. Different.

42, the switch 552 is controlled according to the signal RCSL2 instead of the signal RCSL1, and the switch 553 is controlled according to the signal RCSL1 instead of the signal RCSL2. Different from the readout circuit 531.

  The current application circuit 532A is different from the current application circuit 532 in that the switch 572 is controlled according to WCSL2 instead of the signal WCSL1, and the switch 537 is controlled according to the signal WCSL1 instead of the signal WCSL1. Different from the application circuit 532A. Other configurations are the same as those in FIG. 2, and description thereof will not be repeated.

FIG. 51 is a diagram for explaining selection of a memory cell in the configuration shown in FIG.
FIG. 51 shows a case where the word line WL2 is activated and the signal WCSL2 is activated. In this case, the memory cell 624 and the memory cell 622 indicated by thick broken lines in the drawing are selected. As in the case described with reference to FIG. 49, 2 bits are selected, but the selected memory cells are not adjacent. That is, one unselected memory cell exists between two selected memory cells. Therefore, the problem of thermal interference between memory cells that are simultaneously written is reduced.

FIG. 52 is a diagram showing a configuration in which the problem of thermal interference is further improved.
In the configuration shown in FIG. 52, 531B is provided as a readout circuit, and a current application circuit 532B is provided as a current application circuit.

  Read circuit 531B includes read data lines RDB1 to RDB4 selectively connected to bit lines BL1 to BL7 via switches 711 to 717, and sense amplifiers 701 to 704 connected to read data lines RDB1 to RDB4, respectively. Including.

  Switch 711 connects bit line BL1 and read data line RDB1 in response to activation of signal RCSL1. Switch 712 connects bit line BL2 and read data line RDB2 in response to activation of signal RCSL2. Switch 713 connects bit line BL3 and read data line RDB3 in response to activation of signal RCSL3. Switch 714 connects bit line BL4 and read data line RDB4 in response to activation of signal RCSL4.

  Switch 715 connects bit line BL5 and read data line RDB1 in response to activation of signal RCSL1. Switch 716 connects bit line BL6 and read data line RDB2 in response to activation of signal RCSL2. Switch 717 connects bit line BL7 and read data line RDB3 in response to activation of signal RCSL3.

  Current application circuit 532B is connected to switches 731 to 737, write data lines WDB1 to WDB4 and write data lines WDB1 to WDB4 that are selectively connected to bit lines BL1 to BL7 via switches 731 to 737, respectively. Variable current sources 721 to 724.

  Switch 731 connects bit line BL1 and write data line WDB1 in response to activation of signal WCSL1. Switch 732 connects bit line BL2 and write data line WDB2 in response to activation of signal WCSL2. Switch 733 connects bit line BL3 and write data line WDB3 in response to activation of signal WCSL3. Switch 734 connects bit line BL4 and write data line WDB4 in response to activation of signal WCSL4.

  Switch 735 connects bit line BL5 and write data line WDB1 in response to activation of signal WCSL1. Switch 736 connects bit line BL6 and write data line WDB2 in response to activation of signal WCSL2. Switch 737 connects bit line BL7 and write data line WDB3 in response to activation of signal WCSL3.

  According to the configuration shown in FIG. 52, memory cells to be simultaneously written are, for example, memory cell 622 and memory cell 626 indicated by hatching when word line WL2 is activated and signal WCSL2 is activated. is there. The two selected memory cells have a relationship in which three non-selected memory cells are sandwiched therebetween. In the case described with reference to FIG. 51, the memory cell 623 sandwiched between the memory cells 622 and 624 is thermally affected by the two memory cells to be heated. On the other hand, in the structure shown in FIG. 52, the memory cell 623 is affected by the heating of the memory cell 622, but is not easily affected by the heating of the memory cell 626. Therefore, the influence of the temperature rise of the write memory cell exerts a synergistic effect between the simultaneous write cells, and the memory cell is overheated, which is further advantageous in preventing a decrease in reliability and a decrease in write margin. .

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  100 memory cell array, 102 word line decoder, 104, 104A word line drive circuit, 106 write driver decoder, 108 bit line drive circuit, 110 bit line decoder, 112, 112A column selection circuit, 114 write circuit, 116, 531, 531A , 531B readout circuit, 118 input / output circuit, 120 internal data bus, 152 polycrystalline chalcogenide, 154 programmable volume, 156, 650, HE heater element, 201, 201A, 201B, 202, 202A, 202B, 401, 402, MC, 611-647 memory cells, 204, 204A, 204B, 206, 505, 506, 537, 551-554, 571, 572, 711-717, 731-737 switches, 208, 208A, 2 8B, 208C current source, 222, 665 NOR circuit, 404 switch circuit, 412 sense amplifier, 452, 674 comparison circuit, 454 AND circuit, AT, 652 access transistor, BL, BL1 to BLn, BLA, BLB bit line, CSL, CSL1, CSLA, CSLB column select line, PE phase change element, RDB read data bus, WDB, WDBA, WDBB write data bus, WL, WL1-WL4 word line, 500 phase change memory, 501 address input buffer, 502 signal input Buffer, 503 Data input buffer, 504 Data output buffer, 507 Write address register, 508 Address match comparison circuit, 509 Write data register, 510 X driver & WL driver, 511 Y decoder & data / O circuit, 512 phase change memory cell array, 521 address input terminal, 522 WE input terminal, 523 data input terminal, 524 data output terminal, 532, 532A, 532B current application circuit, 541, 542, 680, 701 sense amplifier, 561 , 562, 721 variable current source, 651 phase change element, 661-664, 682 inverter, 667, 668, 671-673, 675, 681 transistor, RDB, RDB1-RDBn read data line, SL1, SL2 source line, WDB1- WDBn Write data line.

Claims (3)

By applying heat, a resistance value is generated between the first resistance value corresponding to the first logic value and the second resistance value corresponding to the second logic value, the resistance value being greater than the first resistance value. A plurality of memory cells that change and store data;
A current application circuit for supplying a write current to a selected memory cell of the plurality of memory cells in order to write data by applying heat to the memory cell;
The current application circuit is required to cool the selected memory cell to a temperature required to start a next write operation after removing the write current to the selected memory cell. During the time, no current is applied to the selected memory cell ,
The storage device, wherein the cooling time is ensured by inserting a NOP instruction after a write cycle . By applying heat, a resistance value is generated between the first resistance value corresponding to the first logic value and the second resistance value corresponding to the second logic value, the resistance value being greater than the first resistance value. A plurality of memory cells that change and store data;
A current application circuit for supplying a write current to a selected memory cell of the plurality of memory cells in order to write data by applying heat to the memory cell;
The current application circuit is required to cool the selected memory cell to a temperature required to start a next write operation after removing the write current to the selected memory cell. During the time, no current is applied to the selected memory cell,
The cooling device is secured by inserting a NOP instruction before a write cycle. If the memory device does not have an operation cycle in which no current is applied to the selected memory cell after the write cycle to the selected memory cell, the next write to the selected memory cell is not performed. 3. The storage device according to claim 1, wherein, although not allowed, a write cycle is continuously allowed for a memory cell different from the selected memory cell after a write cycle to the selected memory cell. .

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