JP5294319B2 - Multilayer chip balun element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To further reduce a device size with a coupled line being easily shortened to a length of &lambda;/4 or shorter, and to eliminate deterioration of characteristics, as well as to carry out adjustment of a used frequency with ease and at low cost. <P>SOLUTION: In a multilayer chip balun device, there are buried a set of a first coupled line 30 and a third coupled line 34 and a set of a second coupled line 20 and a fourth coupled line 16, each of which is electromagnetically coupled with the other and has a length of &lambda;/4 or shorter (&lambda;: used wavelength) in such a manner that the sets of lines are overlaid vertically with respect to a mounting surface inside a dielectric chip. One end of the first coupled line is connected to an unbalanced terminal and the other end of it is led to the second coupled line. The other end of the second coupled line is open, and both ends of the third and fourth coupled lines are connected between balanced terminals and ground terminals, respectively. The first coupled line is connected to the second coupled line via an inductor pattern 26. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a chip-type laminated balun element used to mutually convert an unbalanced signal and a balanced signal in a high-frequency circuit. More specifically, the present invention relates to a set of λ / 4 coupled lines that are electromagnetically coupled to each other. The present invention relates to a multilayer chip balun element in which two sets are embedded in a dielectric chip and the unbalanced coupling lines are connected by an inductor pattern.

  As is well known, the balun element is a converter used to mutually convert an unbalanced signal and a balanced signal in a high-frequency circuit. In recent years, with the demand for miniaturization of various electronic devices, multilayer chip balun elements having a structure in which coupling lines that are electromagnetically coupled to each other are embedded in a dielectric chip are used.

  As an example of the prior art, two sets of λ / 4 coupled lines (λ: used wavelength) that are electromagnetically coupled to each other are mounted on the mounting surface (the surface facing the mounting substrate) in the dielectric chip. There is a configuration in which the coupling line is embedded in a vertically superposed state and the coupling line end located in the dielectric chip and the external electrode are connected by a lead pattern (see Patent Document 1). Specifically, the first λ / 4 coupled line and the third λ / 4 coupled line that are electromagnetically coupled to each other, the second λ / 4 coupled line that is electromagnetically coupled to each other, and the first 4 λ / 4 coupled lines are embedded in the dielectric chip so as to be superposed in the direction perpendicular to the mounting surface, and one end of the first λ / 4 coupled line serves as an unbalanced terminal. Connected, the other end is connected to one end of the second λ / 4 coupled line, the other end of the second λ / 4 coupled line is open (open), while the third and fourth λ / Both ends of the four coupled lines are connected between the balanced terminal and the ground terminal.

  Since this structure uses two sets of λ / 4 coupled lines that are electromagnetically coupled to each other, not a combination of one λ / 2 coupled line and two λ / 4 coupled lines, a large chip area is obtained. This is advantageous for downsizing. Recently, however, there is an increasing demand for further downsizing of chip elements.

As a solution to the demand for miniaturization,
(1) The width of the coupled line and the line interval are reduced, the number of turns of the spiral pattern constituting the coupled line is increased, and the same line length can be secured even for a small chip area.
(2) Increase the dielectric constant of the dielectric material and shorten the required line length.
There are methods. However, in the measure of (1), there is a possibility that inconvenience such as disconnection may occur in order to reduce the line width and the line interval. Therefore, it is difficult to secure the same line length. In addition, the measure (2) requires development of a new material, which not only takes time and cost, but also requires a wide variety of materials. In addition, if the dielectric constant increases, the distance between the couplings must be increased. It becomes difficult to turn up. Furthermore, in both cases (1) and (2), if the conventional frequency is to be changed, it is necessary to redesign the pattern for all four λ / 4 coupled lines, which increases the cost. Also occurs.

  Therefore, as another solution, there has been proposed a configuration in which a capacitance is formed in parallel with the series connection of the first coupled line and the second coupled line (see Patent Document 2). Here, a capacitance forming electrode is provided in the dielectric chip to form a necessary capacitance with the second coupling line. If the capacitance is added in this way, the length of the coupled line can be reduced to λ / 4 or less, and the element size can be reduced accordingly. However, for that purpose, it is necessary to add a large capacitance, and it is necessary to increase the area of the capacitance forming electrode, which may hinder downsizing.

JP 2003-198221 A JP 2006-94462 A

  The problem to be solved by the present invention is to make it possible to easily reduce the length of the coupled line to λ / 4 or less so that the element size can be further reduced, and to prevent characteristic deterioration. Another problem to be solved by the present invention is to enable adjustment of the used frequency easily and at low cost.

In the present invention, two sets of coupled lines each having a length of λ / 4 or less that are electromagnetically coupled to each other are embedded in a dielectric chip in a state of being superimposed in a direction perpendicular to the mounting surface. In the multilayer chip balun element, a first coupling line whose one end is connected to an unbalanced terminal and a second coupling line whose one end is open (open) are connected by an inductor pattern, and the inductor pattern is a coupling line. It is formed of a separate sheet . In this way, on the unbalanced side, the first coupling line and the second coupling line are connected by an inductor pattern, and the inductor pattern is formed by a single sheet different from the coupling line . This is the main feature of the present invention. The inductor pattern is preferably a spiral shape, but may be a meander shape.

  Since the multilayer chip balun element of the present invention connects the unbalanced first coupling line and the second coupling line with an inductor, the operating frequency can be lowered. Accordingly, if the same frequency is used, the coupled line length can be shortened as compared with the prior art, and the device can be downsized accordingly.

  In the present invention, if the inductance value by the inductor pattern is changed, the operating frequency is changed. Therefore, in the present invention, the adjustment of the operating frequency can be realized simply by changing the portion of the inductor pattern without changing all the patterns of the four coupled lines.

Explanatory drawing of the internal structure of one Example of the multilayer chip balun element based on this invention. The external appearance perspective view of the multilayer chip balun element. The equivalent circuit diagram of the multilayer chip balun element. Explanatory drawing which shows the other example of an inductor pattern. Comparison explanatory drawing of the frequency characteristic of the output of a prior art and this invention product.

  In the present invention, both of the first coupling line and the third coupling line having a length equal to or shorter than λ / 4 (λ: used wavelength) are electromagnetically coupled to each other. The second coupled line and the fourth coupled line set having a length of λ / 4 or less are embedded in the dielectric chip so as to be superposed in the direction perpendicular to the mounting surface. One end of the coupled line is connected to the unbalanced terminal, the other end is led to one end of the second coupled line, the other end of the second coupled line is open (open), and the third and fourth In the laminated chip balun element having a structure in which both ends of the coupled line are connected between the balanced terminal and the ground terminal, respectively, the other end of the first coupled line has an inductor pattern embedded in the dielectric chip. A multilayer chip balun characterized by being connected to one end of the second coupled line via It is a child.

  For example, a spiral shape is preferable as the inductor pattern. In the case of the spiral shape, the spiral winding direction is set to be the same as the spiral winding direction of the first coupled line. In addition, the inductor pattern may have a meander shape.

  FIG. 1 is an explanatory view showing an embodiment of a multilayer chip balun device according to the present invention, and shows an exploded internal structure. This is an example in which a necessary conductor pattern is printed and laminated on a dielectric sheet. Dielectric sheets are stacked in the following order from bottom to top.

  The lowermost layer (mounting surface side) is a dielectric sheet 10 on which an external electrode pattern similar to the uppermost layer described later is printed on the lower surface (the external electrode pattern is not shown because it is formed on the lower surface of the sheet).

  On top of that, the dielectric sheet 14 printed with the first lead pattern 12 and the dielectric sheet 18 printed with the fourth coupled line 16 are positioned in that order. The fourth coupling line 16 has a rectangular spiral pattern, the inner peripheral end thereof is located at the center of the sheet, and the outer peripheral end reaches the vicinity d of the sheet trailing edge right end. On the other hand, the first drawing pattern 12 is linear and is provided so as to extend from the sheet center to the sheet leading edge center b. At the center of the sheet, the first lead pattern 12 and the fourth coupling line 16 are connected by via hole connection (indicated by a dotted line).

  On top of this, the dielectric sheet 22 on which the second coupled line 20 is printed is located. The second coupling line 20 has a rectangular spiral pattern, and an inner peripheral end thereof is located at the center of the sheet, and an outer peripheral end reaches the vicinity f of the left end of the sheet trailing edge. Further, a blank (no conductor pattern) dielectric sheet 24 is disposed thereon as necessary.

  A dielectric sheet 28 on which the inductor pattern 26 is printed and a dielectric sheet 32 on which the first coupling line 30 is printed are positioned thereon. The inductor pattern 26 is also a rectangular spiral pattern, and the inner peripheral edge thereof is located at the sheet center, and the outer peripheral edge reaches the vicinity f of the left end of the sheet trailing edge. The inductor pattern 26 is a spiral pattern of one or more turns that circulates greatly along the outer periphery of the sheet. The first coupling line 30 has a rectangular spiral pattern, the inner peripheral end thereof is located at the center of the sheet, and the outer peripheral end reaches the vicinity a of the left end of the front edge of the sheet. Here, a via hole connection (indicated by a dotted line) is made between the inner peripheral end of the inductor pattern 26 and the inner peripheral end of the first coupling line 30. As shown in the figure, the first coupling line 30 is a spiral that is counterclockwise from the vicinity of the left edge a of the front edge of the sheet toward the center of the sheet, and the inductor pattern 26 is also adjacent to the vicinity of the left edge of the rear edge of the sheet f. Again, a counterclockwise swirl.

  Furthermore, a dielectric sheet 36 printed with the third coupling line 34 and a dielectric sheet 40 printed with the second lead pattern 38 are positioned thereon. The third coupling line 34 is a rectangular spiral pattern, and an inner peripheral end thereof is located at the sheet center, and an outer peripheral end reaches the sheet leading edge center b. On the other hand, the second drawing pattern 38 has a crank shape and is provided so as to extend from the sheet center to the vicinity c of the right end of the sheet front edge. At the center of the sheet, the second lead pattern 38 and the third coupling line 34 are connected by via hole connection (indicated by a dotted line).

  A dielectric sheet 44 on which the external electrode pattern 42 is printed is provided as the uppermost layer. The external electrode patterns 42 have a rectangular shape, and are arranged in a uniform manner by a printing method, with a total of six, three at a time between two opposing sides (front side and rear side in FIG. 1). The uppermost external electrode pattern and the lowermost external electrode pattern may be different in size.

  It should be noted that an arbitrary number of blank dielectric sheets may be interposed between the layers to be laminated as necessary.

  The lengths of the first coupled line to the fourth coupled line are all set to a predetermined length of λ / 4 or less. The first coupled line 30 and the third coupled line 34 are mostly in the same shape and are in a positional relationship such that they overlap each other, and the second coupled line 20 and the fourth coupled line 16 are mostly Are in the same shape and are in a positional relationship such that they overlap each other, whereby the corresponding coupled lines are electromagnetically coupled to each other.

  The dielectric sheets are laminated and integrated in the order as described above, and fired to obtain a chip element. Two sets of coupled lines that are electromagnetically coupled to each other (a set of the first coupled line 30 and the third coupled line 34, and a set of the second coupled line 20 and the fourth coupled line 16), dielectric The structure is embedded in the body chip in a state of being superimposed in the direction perpendicular to the mounting surface. That is, the portion of the rectangular spiral pattern common to each set substantially constitutes a coupling line corresponding to λ / 4, and the other portion is a connection pattern.

  Finally, as shown in FIG. 2, six external electrodes 52 are provided on the outer surface of the dielectric chip 50, and the ends of the coupling lines and the ends of the lead lines are connected on the side of the chip. Accordingly, each external electrode 52 is formed so as to extend from the side surface where the end portion of the conductor pattern is exposed to both the upper surface and the lower surface (mounting surface). Then, the inductor pattern 26 and the second coupled line 20 are connected to each other by the external electrode (indicated by reference numeral f) located at the far left of the six external electrodes 52. Although not shown, some direction identification marker is provided so that the unbalanced terminal can be clearly shown. By incorporating the inductor pattern 26 in this way, the operating frequency moves to the low frequency side.

  As described above, the length of the coupled line (the length of the rectangular spiral pattern having the same shape between the coupled lines constituting the set) is all equal to or less than ¼ of the wavelength λ used. Is set to Therefore, this multilayer chip balun element can be expressed as shown in FIG. 3 in terms of an equivalent circuit. The symbols of the terminals correspond to the symbols indicating the positions in FIG. 1 and the symbols of the external electrodes in FIG. a is an unbalanced terminal, b and e are ground terminals (GND), c and d are balanced terminals, and f is an internal connection terminal connecting the inductor pattern and the second coupling line. The reference numerals of the respective coupled lines also correspond to those in FIG.

  The dielectric sheet used is made of alumina, for example. A material with a large relative dielectric constant is desirable for miniaturization. As a typical manufacturing method, an unfired dielectric ceramic sheet (green sheet) is used, on which a desired conductor pattern is printed with a conductor paste (for example, silver paste) by screen printing, and laminated in a predetermined order. In addition, there is a sheet lamination method in which after pressure integration, firing is performed.

  In addition, it is also possible to manufacture by a printing lamination method. In the printing lamination method, a ceramic pattern using a ceramic paste (for example, a slurry containing powders such as alumina and glass) and a conductive pattern using a conductive paste (silver paste, etc.) are screen-printed and overlapped. It is a method to do. In this way, a laminated and integrated chip element can be obtained. In practice, in order to increase the production efficiency, a multi-cavity method is employed in which the same pattern is printed so that it is regularly arranged in the front, rear, left, and right directions, and after stacking, cut vertically and horizontally into chips. And the method of providing an external terminal in a side surface after baking may be sufficient, or the method of baking after forming an external terminal in a side surface conversely may be used. The multi-cavity method is also used in the sheet lamination method.

  Alternatively, the conductive pattern may be formed on the dielectric substrate, and the layers may be laminated and integrated via an adhesive layer in a predetermined order. In this method, a sintered dielectric ceramic substrate can be used, and other resin substrates can be used.

  A feature of the present invention is that the first coupling line 30 and the second coupling line 20 on the unbalanced side are connected by an inductor pattern 26. The inductor pattern 26 preferably has a spiral shape. As described above, in the example of FIG. 1, the inductor pattern 26 is a rectangular spiral pattern of one or more turns that wraps around the outer periphery of the dielectric sheet. The spiral winding direction is set to be the same as the spiral winding direction of the first coupling line 30. That is, the first coupling line 30 is a counterclockwise spiral pattern from the left end a of the sheet leading edge (unbalanced terminal) toward the center of the sheet, and the inductor pattern 26 connected by the via hole so as to be continuous therewith. The counterclockwise spiral pattern from the sheet center toward the vicinity f of the left end of the sheet trailing edge. By the way, according to the result of the prototype experiment, it is known that in the case of the spiral shape, if the winding direction of the inductor pattern is different from the winding direction of the first coupled line, necessary characteristics cannot be obtained.

  The difference between the inductor pattern and the simple lead pattern is that the lead pattern connects the necessary connection points linearly or simply in a crank shape at the shortest distance, whereas the inductor pattern has a gap between the necessary connection points. It is designed to be connected by a deliberate route. The inductance value can be adjusted by the pattern length (the length of the bypass route). Therefore, in the present invention, the operating frequency can be easily changed by changing only one dielectric sheet on which the inductor pattern is printed.

  Another example of the inductor pattern is shown in FIG. (A) is the rectangular spiral inductor pattern 54, which is an example in which the pattern length is shortened (the dotted line indicates the inductor pattern in FIG. 1). By reducing the pattern length, the inductance value is reduced. The degree of transition to the low frequency side increases as the inductance value increases. Therefore, in the example of (A), the degree of transition to the low frequency side is greater when the inductor pattern indicated by the dotted line is used than the inductor pattern indicated by the solid line. . In other words, the operating frequency can be adjusted by the pattern shape and the inductance value. (B) is an example of a meander-shaped inductor pattern 56. In principle, such a meander shape may be used for the inductor pattern. However, when a small chip element is actually configured, since the chip area is limited, the spiral shape is easier to manufacture than the meander shape considering the required pattern width and pattern interval.

  FIG. 5 shows an example of measurement results for the prototype. (A) shows a conventional example, and (B) shows frequency characteristics of a balanced output according to the present invention. The conventional example of (A) is a case where the first coupling line and the second coupling line are connected in a crank-shaped lead pattern as shown in the drawing. On the other hand, as shown in the figure, the product of the present invention in (B) connects the first coupled line and the second coupled line with a spiral inductor pattern. Except for the inductor pattern (drawer pattern), such as the material, chip shape, and shape and length of each coupled line, all are the same. In the conventional example of (A), the center frequency is about 3.6 GHz, whereas in the product of the present invention of (B), the center frequency is about 2.4 GHz, and the center frequency is lowered by about 1.2 GHz. I understand that.

16 Fourth coupled line 20 Second coupled line 26 Inductor pattern 30 First coupled line 34 Third coupled line

Claims (3)

Any of the first coupling line and the third coupling line having a length equal to or shorter than λ / 4 (λ: used wavelength) are electromagnetically coupled to each other, and both are electromagnetically coupled to each other. The second coupled line and the fourth coupled line set having the following length are embedded in the dielectric chip so as to be superposed in the vertical direction with respect to the mounting surface. One end is connected to the unbalanced terminal, the other end is led to one end of the second coupled line, the other end of the second coupled line is open, and both ends of the third and fourth coupled lines are balanced In the multilayer chip balun element having a structure connected between the terminal and the ground terminal,
The other end of the first coupled line is connected to one end of the second coupled line via an inductor pattern embedded in a dielectric chip, and the inductor pattern is a separate sheet from the coupled line. A multilayer chip balun element characterized by being formed of a sheet of   The multilayer chip balun element according to claim 1, wherein the inductor pattern has a spiral shape, and the spiral direction of the spiral is set to be the same as the spiral direction of the first coupling line.   The multilayer chip balun element according to claim 1, wherein the inductor pattern has a meander shape.

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