JP2002260931A - Stacked chip balun element and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize further downsizing and manufacture a large quantity at a low cost. SOLUTION: An unbalanced coil pattern 22 formed in meandering or spiral state and first and second balanced coil patterns 26 and 30 sandwiching it with a dielectric material interposed are stacked and buried in a dielectric material. In such a structure, an earth electrode pattern is preferably arranged outside the first and second balanced coil patterns. In addition, the connection ends of the first and second balanced coil pattern on the earth side are preferably arranged on side faces opposite to each other.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a balun element used for converting an unbalanced signal and a balanced signal in a high-frequency circuit and a method for manufacturing the same, and more particularly to a chip-type laminated balun element and a method for manufacturing the same. The present invention relates to a multilayer chip balun element having a structure in which balanced coil patterns are arranged so as to sandwich a meandering or spiral unbalanced coil pattern, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A balun element is a converter used in a high-frequency circuit for smoothly connecting a balanced circuit and an unbalanced circuit. FIG. 4 schematically shows an example of a conventional balun element having a laminated structure. An unbalanced pattern 12 is formed on one dielectric substrate 10 and another dielectric substrate 14
Are formed on top of each other, and the dielectric substrates 10 and 12 are stacked so that the unbalanced pattern 12 and the two balanced patterns 16 and 18 are electromagnetically coupled. Structure.

Here, the unbalanced pattern 12 has a length of 使用 of the used wavelength λ, and the balanced patterns 16 and 18 have a length of １ ／ of the used wavelength λ. ing.

[0004]

Therefore, in the case of such a linear pattern, for example, when the operating frequency is 1 GHz and the relative permittivity of the dielectric substrate is about 5, the 1/4 wavelength is about 3
5 mm, and the total length of the element is about 70 mm. in this way,
The conventional structure has a disadvantage that the element shape becomes large.

Therefore, recently, a structure has been proposed in which the unbalanced side pattern and the balanced side pattern are formed in a meandering or spiral shape (see Japanese Patent Application Laid-Open No. 7-176918). According to this structure, each pattern does not become longer in one direction and can be reduced in size.

However, the above example employs a configuration in which two balanced coil patterns are juxtaposed on the same dielectric substrate, and there is naturally a limit to miniaturization.

An object of the present invention is to provide a multilayer chip balun element which can be further miniaturized and can be manufactured at low cost, and a method for manufacturing the same.

[0008]

According to the present invention, there is provided an unbalanced coil pattern formed in a meandering or spiral shape, and first and second uninterrupted coil patterns interposed therebetween via a dielectric material.
Is a laminated chip balun element laminated and embedded in a dielectric material. The first balanced coil pattern overlaps with a pattern of approximately half the length of the unbalanced coil pattern, and the second balanced coil pattern overlaps with the pattern of approximately half the length of the unbalanced coil pattern. In this configuration, it is preferable that the ground electrode pattern is disposed outside the first and second balanced coil patterns.

The ground connection ends of the first and second balanced coil patterns may be drawn on the same side of the chip, but are preferably arranged on opposite sides. This is because the possibility of occurrence of unnecessary electromagnetic coupling can be avoided.
Note that external terminal electrodes are formed on one or both main surfaces of the outer surface, and are connected to terminals drawn on the side surfaces.

According to the present invention, an unbalanced coil pattern is formed in a meandering or spiral shape on a first dielectric substrate,
A balanced coil pattern is formed on each of the first and third dielectric substrates, and the second and third dielectric substrates are provided with the first and second dielectric substrates.
A method for producing a laminated chip balun element for laminating the dielectric substrate so as to sandwich integrated. The dielectric material may be sintered after lamination and integration, or a sintered body may be laminated and bonded.

In these, a ground electrode pattern is formed on each of the fourth and fifth dielectric substrates, and they are laminated and integrated so that they are located outside the second and third dielectric substrates. Is preferred.

Further, the present invention provides a whole dielectric ceramic pattern, a lead conductor pattern, a dielectric ceramic pattern, a first balanced coil pattern, a whole dielectric ceramic pattern, a meandering or spiral unbalanced coil pattern, a whole dielectric. This is a method for manufacturing a laminated chip balun element in which a ceramic pattern, a second balanced coil pattern, a dielectric ceramic pattern, a lead conductor pattern, and an entire dielectric ceramic pattern are printed and laminated in that order and fired. Alternatively, the present invention relates to a whole dielectric ceramic pattern, a ground electrode pattern, a whole dielectric ceramic pattern, a lead conductor pattern, a dielectric ceramic pattern, a first balanced coil pattern, a whole dielectric ceramic pattern, a meandering or spiral shape. Balanced coil pattern, whole surface dielectric ceramic pattern, 2nd
Balanced coil pattern, dielectric ceramic pattern,
Leader conductor pattern, whole surface dielectric ceramic pattern,
This is a method for manufacturing a laminated chip balun element in which an earth electrode pattern and a whole-surface dielectric ceramic pattern are printed and laminated in that order and fired. In these, at the time of printing lamination,
It is preferable that an external terminal electrode pattern is simultaneously printed and formed on the lowermost layer and / or the uppermost layer of the dielectric ceramic pattern. It goes without saying that the terminal reaching the side of the chip is connected to the lowermost and / or uppermost external terminal electrode patterns.

[0013]

FIG. 1 is an explanatory view showing one embodiment of a multilayer chip balun element according to the present invention. Here, A shows an exploded internal structure, and B shows the appearance of the final product.

An unbalanced coil pattern 22 is formed in a spiral shape on the first dielectric substrate 20, the inner terminal is opened, and the outer terminal is extended so as to be drawn out to the side edge of the substrate. . The balanced coil pattern 26 is formed on the second dielectric substrate 24, the inside of the terminal reaches the back surface through the substrate, the outer terminal extending so as to be drawn to the substrate edge. This second dielectric substrate 2
The balanced coil pattern 26 on the upper part 4 is formed so as to overlap a portion (about half the entire length) near the inner periphery of the unbalanced coil pattern 22. Third dielectric substrate 2
8, a balanced coil pattern 30 is formed, and the outer terminal is extended so as to be drawn out to the edge of the substrate. The balanced coil pattern 30 on the third dielectric substrate 28 is provided so as to overlap a portion near the outer periphery of the unbalanced coil pattern 22 (about half of the entire length). On another dielectric substrate 32, a lead conductor pattern 34 continuous to the inside terminal of one balanced coil pattern 26 is formed, and on another dielectric substrate 36, continuous with the inside terminal of the other balanced coil pattern 30. The lead conductor pattern 38 penetrating from the back surface to the front surface and reaching the side edge of the substrate is formed. Then, the second and third dielectric substrates 24, 28
The dielectric substrate 20 is sandwiched from below and above, and the dielectric substrates 32 and 36 are located outside the dielectric substrate 20 and the dielectric substrate 40 is located on the uppermost layer. Note that two broken lines indicate a relationship in which terminals are connected during stacking.

Finally, as shown in FIG. 1B, six external terminal electrodes 44 (represented by reference numerals a to f) are provided on the outer surface of the chip 42 and connected to the ends of the lead conductor pattern. I do. Here, a and c are balanced terminals, b and e are ground terminals (GND), d is an unbalanced terminal, and f is unconnected (N
C) is set. Each external terminal electrode 44 is formed so as to reach one or both main surfaces of the outer surface from the side surface where the end of the conductor pattern is exposed. Although not shown, some mark is added to indicate the direction of the chip.

The unbalanced coil pattern is 1/1 / λ of the used wavelength λ.
2 and the balanced coil pattern is
Is set to a length of の. As described above, the unbalanced coil pattern and the first and second balanced coil patterns positioned via the dielectric material so as to sandwich the unbalanced coil pattern are laminated and embedded in the dielectric material to constitute a laminated chip balun element. are doing.

The dielectric substrate used is made of, for example, alumina or the like. A material having a large relative dielectric constant is desirable for miniaturization. As a manufacturing method, an unfired dielectric ceramic sheet (green sheet) is used, a conductor pattern is printed thereon with a conductor paste (for example, silver paste) by a screen printing method or the like, and laminated in a predetermined order.
There is a method of baking after pressure integration. Other, a conductor pattern formed on a dielectric substrate, laminated through an adhesive layer in a predetermined order, or a method of integrating. In this method, a sintered dielectric ceramic substrate can be used, or another plastic substrate can be used.

According to the present invention, the unbalanced coil pattern can be reduced in size by making it spiral, and the occupied area can be reduced by arranging the balanced coil pattern so as to sandwich the unbalanced coil pattern to generate electromagnetic coupling. Almost half can be reduced. Therefore, when a large number of devices are to be obtained, more elements can be cut out, which is suitable for mass production and can be reduced in cost.

In this embodiment, the ground-side connection ends of the first and second balanced coil patterns 26 and 30 are arranged on opposite side surfaces. It can be pulled out to the same side, but doing so can lead to electromagnetic coupling due to proximity to each other. The configuration of the present embodiment that is pulled out to the opposite side can avoid such a possibility.

FIG. 2 is an exploded perspective view showing the internal structure of another embodiment of the multilayer chip balun element according to the present invention. The basic configuration may be similar to the embodiment shown in FIG.
Corresponding parts have the same reference characters allotted, and description thereof will not be repeated.

A second dielectric substrate 24 having a balanced coil pattern 26 and a third dielectric substrate having a balanced coil pattern 30
Dielectric substrate 28 sandwiches first dielectric substrate 20 having unbalanced coil pattern 22 from below and from above, and dielectric substrate 3 having lead conductor patterns 34 and 38 on the outside thereof.
2 and 36, and dielectric substrates 48 and 49 having earth electrode patterns 46 and 47 on the outside thereof, and the dielectric substrate 40 on the uppermost layer. And Here, the dielectric substrate 48,
The ground electrode patterns 46 and 47 formed on the
The pattern is such that almost the entire surface is covered except for a small frame portion, and a drawer portion extending to the side edge is continuous at the center of both sides.

FIG. 3 is an explanatory view showing one embodiment of a method for manufacturing a multilayer chip balun element according to the present invention, and shows a manufacturing process by a printing lamination method. In the printing lamination method, a ceramic pattern using a ceramic paste (a slurry containing a powder of alumina and glass, etc.) and a conductor pattern using a conductor paste (such as a silver paste) are screen-printed and laminated to form a laminate. It is.

(1) The external terminal electrode pattern 50 is printed. (2)-(3) The ceramic pattern 51 is overprinted over the entire surface to a predetermined thickness. (4) The lead conductor pattern 52 is printed with a conductor paste so as to cross the center part, one end remains inside, and the other end reaches the end part. (5) The ceramic pattern 5 is partially exposed so that only the inner end of the lead conductor pattern 52 is exposed and most of the conductor pattern 52 is hidden.
Print 3. (6) The spiral first balanced coil pattern 54 is printed with the conductive paste so that the inner end is connected to the inner end of the lead conductor pattern 52.

(7)-(8) The ceramic pattern 55 is printed over the entire surface to a predetermined thickness. (9) Print the unbalanced coil pattern 56 with the conductive paste. The inner end is open and the outer end is pulled out to the side edge. (10)-(11) The ceramic pattern 57 is printed over the entire surface to a predetermined thickness. (12) Print the balanced coil pattern 58 with the conductive paste. The inner edge is left open for the time being, and the outer edge is pulled out to the side edge.

(13) The ceramic pattern 59 is partially printed so as to cover almost half of the outer end of the balanced coil pattern 58. (14) The lead conductor pattern 60 is printed on the partially printed ceramic pattern 59. One end is connected to the inner end of the balanced coil pattern 58, and the other end reaches the side edge. (15)-(16) The ceramic pattern 61 is overprinted over the entire surface to a predetermined thickness. (17) The external terminal electrode pattern 62 is printed. (18) The marker 63 indicating the direction (direction) is printed.

Thus, a laminated and integrated chip is obtained. Actually, in order to increase the production efficiency, the same pattern is printed so as to be regularly arranged in front, rear, right and left, and after lamination, it is cut in a vertical and horizontal direction and cut into individual chips. Then, a method of providing an external electrode on the side surface after baking or a method of baking after forming an external electrode pattern on the side surface may be used.

In the above-described manufacturing method, when the ground electrode pattern is incorporated, the method is performed while the ceramic pattern of (2)-(3) is overprinted and (15)-(1).
6) During the overprinting of the entire ceramic pattern,
What is necessary is just to print the earth electrode pattern as shown in FIG.

In each of the above embodiments, a spiral unbalanced coil pattern and a balanced coil pattern are employed, but it is needless to say that a meandering unbalanced coil pattern and a balanced coil pattern may be employed. No. The external terminal electrodes are formed on both main surfaces of the outer surface in each of the above embodiments, but may be formed on only one main surface. The shape and width of the conductor pattern including the unbalanced and balanced coil patterns may be appropriately changed.

[0029]

As described above, the present invention has a structure in which balanced coil patterns are arranged above and below so as to sandwich a meandering or spiral unbalanced coil pattern and embedded in a dielectric material. It is possible to reduce the size, so that it can be manufactured in large quantities and at low cost.

[Brief description of the drawings]

FIG. 1 is an explanatory view showing one embodiment of a multilayer chip balun element according to the present invention.

FIG. 2 is an exploded perspective view showing another embodiment of the multilayer chip balun element according to the present invention.

FIG. 3 is an explanatory view showing one embodiment of a method for manufacturing a multilayer chip balun element according to the present invention.

FIG. 4 is an explanatory diagram showing an example of a conventional technique.

DESCRIPTION OF SYMBOLS 20 First dielectric substrate 22 Unbalanced coil pattern 24 Second dielectric substrate 26 Balanced coil pattern 28 Third dielectric substrate 30 Balanced coil pattern 32 Dielectric substrate 34 Leading conductor pattern 36 Dielectric Substrate 38 Lead-out conductor pattern 40 Dielectric substrate

Claims (9)

[Claims] An unbalanced coil pattern formed in a meandering or spiral shape, and first and second balanced coil patterns sandwiching the unbalanced coil pattern via a dielectric material are laminated in a dielectric material. A multilayer chip balun element which is buried. 2. The multilayer chip balun element according to claim 1, wherein the ground electrode pattern is arranged outside the first and second balanced coil patterns. 3. The multilayer chip balun element according to claim 1, wherein the ground-side connection ends of the first and second balanced coil patterns are arranged on opposite side surfaces. 4. The multilayer chip balun element according to claim 1, wherein external terminal electrodes are formed on one or both main surfaces of the external surface. 5. An unbalanced coil pattern is formed on a first dielectric substrate in a meandering or spiral shape, and the second and third unbalanced coil patterns are formed.
Wherein a balanced coil pattern is formed on each of the dielectric substrates, and the second and third dielectric substrates are laminated and integrated so as to sandwich the first dielectric substrate. Production method. 6. A ground electrode pattern is formed on each of the fourth and fifth dielectric substrates, and the ground electrode patterns are stacked and integrated so as to be located outside the second and third dielectric substrates. A manufacturing method of the multilayer chip balun element according to the above. 7. An overall dielectric ceramic pattern, a lead conductor pattern, a dielectric ceramic pattern, a first unbalanced coil pattern, an overall dielectric ceramic pattern, a meandering or spiral unbalanced coil pattern,
A method of manufacturing a laminated chip balun element, comprising printing, laminating, and firing an entire dielectric ceramic pattern, a second unbalanced coil pattern, a dielectric ceramic pattern, a lead conductor pattern, and an entire dielectric ceramic pattern in that order. . 8. A whole dielectric ceramic pattern, a ground electrode pattern, a whole dielectric ceramic pattern, a lead conductor pattern, a dielectric ceramic pattern, a first balanced coil pattern, a whole dielectric ceramic pattern, a meandering or spiral shape. Balanced coil pattern,
The whole dielectric ceramic pattern, the second balanced coil pattern, the dielectric ceramic pattern, the lead conductor pattern, the whole dielectric ceramic pattern, the ground electrode pattern, and the whole dielectric ceramic pattern are printed, laminated and fired in this order. Manufacturing method of the laminated chip balun element. 9. The method for manufacturing a multilayer chip balun element according to claim 7, wherein an external terminal electrode pattern is simultaneously printed and formed on the lowermost layer and / or the uppermost layer of the dielectric ceramic pattern during printing and lamination.