JP5292779B2 - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP5292779B2
JP5292779B2 JP2007304092A JP2007304092A JP5292779B2 JP 5292779 B2 JP5292779 B2 JP 5292779B2 JP 2007304092 A JP2007304092 A JP 2007304092A JP 2007304092 A JP2007304092 A JP 2007304092A JP 5292779 B2 JP5292779 B2 JP 5292779B2
Authority
JP
Japan
Prior art keywords
terminal
wiring
semiconductor device
external connection
screwing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2007304092A
Other languages
Japanese (ja)
Other versions
JP2009130163A (en
Inventor
伸 征矢野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2007304092A priority Critical patent/JP5292779B2/en
Publication of JP2009130163A publication Critical patent/JP2009130163A/en
Application granted granted Critical
Publication of JP5292779B2 publication Critical patent/JP5292779B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001—Core members of the connector
    • H01L2224/37099—Material
    • H01L2224/371—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401—Disposition
    • H01L2224/40135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/40137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73221—Strap and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/842—Applying energy for connecting
    • H01L2224/8421—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/84214—Applying energy for connecting with energy being in the form of electromagnetic radiation using a laser
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Inverter Devices (AREA)

Description

本発明は半導体装置に関し、特に複数の半導体素子を樹脂ケースにより包容した半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a plurality of semiconductor elements are enclosed by a resin case.

インバータ装置、無停電電源装置、工作機械、産業用ロボット等では、その本体装置とは独立して、パワー半導体素子を搭載した半導体装置（汎用モジュール）が使用されている。そして、このような半導体装置は、複数のパワー半導体素子を樹脂ケース内に封止（パッケージ）させた構造をしている（例えば、特許文献１，２参照）。   Inverter devices, uninterruptible power supply devices, machine tools, industrial robots, and the like, semiconductor devices (general-purpose modules) equipped with power semiconductor elements are used independently of the main body devices. Such a semiconductor device has a structure in which a plurality of power semiconductor elements are sealed (packaged) in a resin case (see, for example, Patent Documents 1 and 2).

このような半導体装置の内部配線は、配線用端子（リードフレーム）で行うのが一般的である（例えば、特許文献３参照）。
例えば、図１１に、パワー半導体素子を樹脂ケース内に封止させた半導体装置の要部模式図を示す。この図では、配線用端子で内部配線を行った半導体装置の一例が示されている。 Such internal wiring of a semiconductor device is generally performed by wiring terminals (lead frames) (see, for example, Patent Document 3).
For example, FIG. 11 shows a schematic diagram of a main part of a semiconductor device in which a power semiconductor element is sealed in a resin case. This figure shows an example of a semiconductor device in which internal wiring is performed with wiring terminals.

図示するように、半導体装置は、樹脂ケース４００内に、ＩＧＢＴ（Insulated Gate Bipolar Transistor）素子１００を配置している。ここで、ＩＧＢＴ素子１００は、縦型のパワー半導体素子であり、その上面にエミッタ電極、下面にコレクタ電極を配設している。そして、ＩＧＢＴ素子１００のエミッタ電極と配線基板２００とは、配線用端子６００を通じて導通している。また、ＩＧＢＴ素子１００のコレクタ電極は、配線基板２００の回路に直接的に導通している。   As shown in the figure, an IGBT (Insulated Gate Bipolar Transistor) element 100 is disposed in a resin case 400 in the semiconductor device. Here, the IGBT element 100 is a vertical power semiconductor element, and an emitter electrode is disposed on the upper surface and a collector electrode is disposed on the lower surface. The emitter electrode of the IGBT element 100 and the wiring substrate 200 are electrically connected through the wiring terminal 600. Further, the collector electrode of the IGBT element 100 is directly conducted to the circuit of the wiring board 200.

そして、配線用端子６００の上記エミッタ電極、配線基板２００との接合は、例えば、半田付け、超音波接合、レーザー溶接にて行うのが一般的である。
特開平６−０４５５１８号公報 特開２００２−３６８１９２号公報 特開２００５−６４４４１号公報 In general, the wiring terminal 600 is bonded to the emitter electrode and the wiring substrate 200 by, for example, soldering, ultrasonic bonding, or laser welding.
JP-A-6-045518 JP 2002-368192 A JP 2005-64441 A

しかし、上述した半田付けの場合には、半田付け中に接合部分に与えられる熱が配線用端子６００内を伝導し、樹脂ケース４００自体を変形させてしまうことがある。
また、超音波接合においては、接合部分を樹脂ケース４００内で中空状態で行う場合があり、その接合が確実でない場合が生じる。 However, in the case of the above-described soldering, heat given to the joint portion during the soldering may be conducted in the wiring terminal 600, and the resin case 400 itself may be deformed.
Further, in ultrasonic bonding, the bonded portion may be hollow in the resin case 400, and the bonding may not be reliable.

また、レーザー溶接の場合は、接合部分から飛散する溶融物（例えば、金属片）が半導体素子の電極に付着したりすると、半導体素子の特性劣化を引き起こす場合がある。このため、レーザー溶接の場合は、配線用端子材に制約を課すこともある。   In the case of laser welding, if a melt (for example, a metal piece) scattered from the joint portion adheres to the electrode of the semiconductor element, the characteristics of the semiconductor element may be deteriorated. For this reason, in the case of laser welding, restrictions may be imposed on the wiring terminal material.

また、配線用端子６００を一旦、被接合部分に接合させてしまうと、その後において、配線用端子６００の配置変更が自由にできないという問題があった。
本発明はこのような点に鑑みてなされたものであり、歩留まりが高く、複数の半導体素子を樹脂ケースにより包容した半導体装置の配線用端子の配置構造を、簡便に変更し得る半導体装置を提供することを目的とする。 Further, once the wiring terminal 600 is bonded to the part to be bonded, there is a problem in that the layout of the wiring terminal 600 cannot be freely changed thereafter.
The present invention has been made in view of the above points, and provides a semiconductor device that has a high yield and can easily change the arrangement structure of wiring terminals of a semiconductor device in which a plurality of semiconductor elements are enclosed in a resin case. The purpose is to do.

上記課題を解決するために、本発明の一態様では、樹脂ケースに固定支持された複数の外部接続用端子と、前記樹脂ケース内に包容された、少なくとも一つの半導体素子と、前記半導体素子に配設された電極に導通する端子台と、前記端子台と前記外部接続用端子との電気的接続をする配線用端子と、前記樹脂ケース内に充填された、少なくとも前記半導体素子を封止し、前記配線用端子が表出している樹脂と、を備え、前記外部接続用端子と前記配線用端子、または、前記端子台と前記配線用端子との少なくとも何れかががねじ止めにより接合されていることを特徴とする半導体装置が提供される。 In order to solve the above problems, in one aspect of the present invention, a plurality of external connection terminals fixedly supported in a resin case, at least one semiconductor element enclosed in the resin case, and the semiconductor element Sealing at least the semiconductor element filled in the resin case, a terminal block electrically connected to the arranged electrode, a wiring terminal for electrical connection between the terminal block and the external connection terminal; A resin exposed by the wiring terminal, and at least one of the external connection terminal and the wiring terminal, or the terminal block and the wiring terminal is joined by screwing. A semiconductor device is provided.

また、本発明の別の一態様では、樹脂ケースに固定支持された複数の外部接続用端子と、前記樹脂ケース内に包容された、少なくとも一つの半導体素子と、前記半導体素子に配設された電極に導通する端子台と、前記端子台と前記外部接続用端子との電気的接続をする配線用端子と、前記樹脂ケース内に充填された、少なくとも前記半導体素子を封止し、前記配線用端子が表出している樹脂と、を備え、前記外部接続用端子と前記配線用端子、または、前記端子台と前記配線用端子とがねじ止めにより接合されている、複数の半導体モジュール間の前記配線用端子を連結したことを特徴とする半導体装置が提供される。
In another aspect of the present invention, a plurality of external connection terminals fixedly supported by a resin case, at least one semiconductor element enclosed in the resin case, and disposed in the semiconductor element A terminal block electrically connected to an electrode; a wiring terminal for electrical connection between the terminal block and the external connection terminal; and at least the semiconductor element filled in the resin case, wherein the semiconductor element is sealed. A resin that a terminal is exposed to, and the external connection terminal and the wiring terminal, or the terminal block and the wiring terminal are joined by screwing. A semiconductor device is provided in which wiring terminals are connected.

本発明によれば、歩留まりが高く、複数の半導体素子を樹脂ケースにより包容した半導体装置の配線用端子の配置構造を、簡便に変更し得る半導体装置が実現する。   According to the present invention, it is possible to realize a semiconductor device that has a high yield and can easily change the arrangement structure of wiring terminals of a semiconductor device in which a plurality of semiconductor elements are enclosed in a resin case.

以下、本実施の形態に係る半導体装置を、図面を参照して詳細に説明する。
＜第１の実施の形態＞
図１は第１の実施の形態に係る半導体装置の要部模式図である。ここで、図（ａ）には、半導体装置の平面模式図が例示され、図（ｂ）には図（ａ）の破線Ｘ−Ｘの位置における断面を矢印の方向に矢視する図が表示されている。尚、図１では、インバータ回路一相分の半導体モジュール（パワーモジュール）の一例が例示されている。 Hereinafter, a semiconductor device according to the present embodiment will be described in detail with reference to the drawings.
<First Embodiment>
FIG. 1 is a schematic diagram of a main part of the semiconductor device according to the first embodiment. Here, FIG. (A) illustrates a schematic plan view of the semiconductor device, and FIG. (B) displays a view of the cross section at the position of the broken line XX in FIG. (A) in the direction of the arrow. Has been. In FIG. 1, an example of a semiconductor module (power module) for one phase of the inverter circuit is illustrated.

図示する半導体装置１は、板厚が数ミリの金属ベース板１０を基体とし、当該金属ベース板１０上に、錫（Ｓｎ）−銀（Ａｇ）系の鉛フリー半田層（図示しない）を介して絶縁基板２０が接合・搭載されている。そして、絶縁基板２０上層には、パワー半導体素子であるＩＧＢＴ素子３０ａ，３０ｂ、並びにＦＷＤ素子３１ａ，３１ｂを、夫々複数個、実装している。更に、半導体装置１は、上記半導体素子等を樹脂ケース４０によりパッケージングし、所謂、汎用ＩＧＢＴモジュールとして機能する。   The illustrated semiconductor device 1 uses a metal base plate 10 having a thickness of several millimeters as a base, and a tin (Sn) -silver (Ag) based lead-free solder layer (not shown) on the metal base plate 10. Thus, the insulating substrate 20 is bonded and mounted. A plurality of IGBT elements 30a and 30b and FWD elements 31a and 31b, which are power semiconductor elements, are mounted on the upper layer of the insulating substrate 20. Furthermore, the semiconductor device 1 functions as a so-called general-purpose IGBT module by packaging the semiconductor element and the like with a resin case 40.

絶縁基板２０は、絶縁板２０ａと、絶縁板２０ａの下面にＤＣＢ（Direct Copper Bonding）法で形成された金属箔２０ｂと、絶縁板２０ａの上面に同じくＤＣＢ法で形成された金属箔２０ｃを備えている。   The insulating substrate 20 includes an insulating plate 20a, a metal foil 20b formed by a DCB (Direct Copper Bonding) method on the lower surface of the insulating plate 20a, and a metal foil 20c also formed by the DCB method on the upper surface of the insulating plate 20a. ing.

更に、夫々の絶縁基板２０の金属箔２０ｃ上には、半田層（図示しない）を介して、少なくとも一つのＩＧＢＴ素子３０ａ，３０ｂがその裏面側（例えば、コレクタ電極側）を接合させた状態にて、金属箔２０ｃ上に搭載されている。   Further, on the metal foil 20c of each insulating substrate 20, at least one IGBT element 30a, 30b is bonded to the back surface side (for example, collector electrode side) via a solder layer (not shown). And mounted on the metal foil 20c.

また、ＩＧＢＴ素子３０ａ，３０ｂのコレクタ電極とは反対側の主面、即ち、ＩＧＢＴ素子３０ａ，３０ｂの上面側には、エミッタ電極が配設されている。更に、ＩＧＢＴ素子３０ａ，３０ｂの上面の一部には、制御電極３０ｇが配設されている。そして、制御電極３０ｇは、金属ワイヤ２１を通じて、樹脂ケース４０にインサート成形（封止）されたピン端子（制御用端子）２２の一端に導通している。また、ピン端子２２のもう一方の端は、半導体装置１の上方へ延出され、樹脂ケース４０の上面より高い位置にまで設定されている。   An emitter electrode is disposed on the main surface opposite to the collector electrodes of IGBT elements 30a and 30b, that is, on the upper surface side of IGBT elements 30a and 30b. Further, a control electrode 30g is disposed on a part of the upper surface of the IGBT elements 30a and 30b. The control electrode 30g is electrically connected to one end of a pin terminal (control terminal) 22 insert-molded (sealed) in the resin case 40 through the metal wire 21. The other end of the pin terminal 22 extends upward from the semiconductor device 1 and is set to a position higher than the upper surface of the resin case 40.

また、ＦＷＤ素子３１ａ，３１ｂにおいては、半田層（図示しない）を介して、カソード側を金属箔２０ｃに接合させた状態にて、金属箔２０ｃ上に搭載されている。そして、ＦＷＤ素子３１ａ，３１ｂの当該カソード側とは反対側の主面、即ち、上面には、アノード側を配置している。   The FWD elements 31a and 31b are mounted on the metal foil 20c with the cathode side bonded to the metal foil 20c via a solder layer (not shown). And the anode side is arrange | positioned at the main surface on the opposite side to the said cathode side of FWD element 31a, 31b, ie, an upper surface.

また、ＩＧＢＴ素子３０ａ，３０ｂのエミッタ電極（ＩＧＢＴ素子３０ａ，３０ｂの上面側）とＦＷＤ素子３１ａ，３１ｂのアノード側（ＦＷＤ素子３１ａ，３１ｂの上面側）には、屈曲構造を備えた端子台２３ａ，２３ｂが半田付けによって架設されている。例えば、端子台２３ａ，２３ｂの断面は、矩形であり、凸形状としている。これにより、ＩＧＢＴ素子３０ａ，３０ｂのエミッタ電極とＦＷＤ素子３１ａ，３１ｂのアノード側との導通が端子台２３ａ，２３ｂを通じて確保されている。   A terminal block 23a having a bent structure is provided on the emitter electrodes of the IGBT elements 30a and 30b (upper surface side of the IGBT elements 30a and 30b) and the anode side of the FWD elements 31a and 31b (upper surface side of the FWD elements 31a and 31b). , 23b are installed by soldering. For example, the terminal blocks 23a and 23b have a rectangular cross section and a convex shape. Thereby, conduction between the emitter electrodes of the IGBT elements 30a and 30b and the anode side of the FWD elements 31a and 31b is ensured through the terminal blocks 23a and 23b.

また、ＩＧＢＴ素子３０ａ，３０ｂのコレクタ電極とＦＷＤ素子３１ａ，３１ｂのカソード側は、ＩＧＢＴ素子３０ａ，３０ｂ並びにＦＷＤ素子３１ａ，３１ｂの下地である金属箔２０ｃを通じて互いに導通している。   Further, the collector electrodes of the IGBT elements 30a and 30b and the cathode side of the FWD elements 31a and 31b are electrically connected to each other through a metal foil 20c which is a base of the IGBT elements 30a and 30b and the FWD elements 31a and 31b.

ここで、絶縁板２０ａは、例えば、アルミナ（Ａｌ2Ｏ3）焼結体のセラミックで構成され、金属箔２０ｂ，２０ｃは、銅（Ｃｕ）を主成分とする金属で構成されている。また、端子台２３ａ，２３ｂは、例えば、銅（Ｃｕ）またはアルミニウム（Ａｌ）またはこれらの合金を主成分とした材質により構成されている。 Here, the insulating plate 20a is made of, for example, an alumina (Al 2 O 3 ) sintered ceramic, and the metal foils 20b and 20c are made of metal having copper (Cu) as a main component. The terminal blocks 23a and 23b are made of, for example, a material mainly composed of copper (Cu), aluminum (Al), or an alloy thereof.

また、金属箔２０ｃに搭載する半導体素子においては、上述したＩＧＢＴ素子３０ａ，３０ｂに限らず、パワーＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）を用いてもよい。   The semiconductor element mounted on the metal foil 20c is not limited to the IGBT elements 30a and 30b described above, and a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) may be used.

また、半導体装置１にあっては、金属ベース板１０の上端縁に、例えば、ＰＰＳ（ポリ・フェニレン・サルファイド）製の樹脂ケース４０が固設されている。そして、樹脂ケース４０の一部には、例えば、ＩＧＢＴ素子３０ａ，３０ｂの主電極に導通する外部接続用端子５０ａ，５１ａ，５２ａ，５３ａがインサート成形されている。   In the semiconductor device 1, a resin case 40 made of, for example, PPS (polyphenylene sulfide) is fixed to the upper end edge of the metal base plate 10. For example, external connection terminals 50a, 51a, 52a, and 53a that are electrically connected to the main electrodes of the IGBT elements 30a and 30b are insert-molded in a part of the resin case 40.

ここで、外部接続用端子５０ａは、例えば、インバータ回路の正極入力端子（Ｐ端子）となり、外部接続用端子５１ａは、例えば、インバータ回路の負極入力端子（Ｎ端子）となる。これらの外部接続用端子５０ａ，５１ａは、半導体装置１の外部に設置された直流電源の正極、負極に夫々電気的に接続される。また、外部接続用端子５２ａは、例えば、インバータ回路の交流出力端子（Ｕ，Ｖ，Ｗ相）となる。尚、外部接続用端子５３ａは、予備端子である。   Here, the external connection terminal 50a is, for example, a positive input terminal (P terminal) of the inverter circuit, and the external connection terminal 51a is, for example, a negative input terminal (N terminal) of the inverter circuit. These external connection terminals 50a and 51a are electrically connected to a positive electrode and a negative electrode of a DC power supply installed outside the semiconductor device 1, respectively. The external connection terminal 52a is, for example, an AC output terminal (U, V, W phase) of the inverter circuit. The external connection terminal 53a is a spare terminal.

そして、外部接続用端子５０ａには、Ｌ字形状の配線用端子（リードフレーム）５０ｂの一端が金属製のねじ６０によるねじ止めにより接合されている。更に、当該配線用端子５０ｂは、別の端を２股に分岐する構成とし、当該２つの端は、ねじ６０によるねじ止めにより、断面が「コ」の字型をした屈曲構造の端子台２４ｂの上面に接合されている。   One end of an L-shaped wiring terminal (lead frame) 50b is joined to the external connection terminal 50a by screwing with a metal screw 60. Further, the wiring terminal 50b has a configuration in which another end is branched into two branches, and the two ends are bent by a screw 60 so that the cross-section of the terminal block 24b has a “U” shape. It is joined to the upper surface of.

尚、端子台２４ｂの下面は、金属箔２０ｃの主面に半田付けまたはレーザー溶接によって接合されている。
即ち、半導体装置１においては、樹脂ケース４０に固設された外部接続用端子５０ａに配線用端子５０ｂの一端が電気的に接続され、当該配線用端子５０ｂのもう一方の端は、端子台２４ｂを通じて、ＩＧＢＴ素子３０ｂのコレクタ電極並びにＦＷＤ素子３１ｂのカソード側に電気的に接続されている。 The lower surface of the terminal block 24b is joined to the main surface of the metal foil 20c by soldering or laser welding.
That is, in the semiconductor device 1, one end of the wiring terminal 50b is electrically connected to the external connection terminal 50a fixed to the resin case 40, and the other end of the wiring terminal 50b is connected to the terminal block 24b. And are electrically connected to the collector electrode of the IGBT element 30b and the cathode side of the FWD element 31b.

また、外部接続用端子５１ａには、Ｌ字形状の配線用端子５１ｂの一端がねじ６０によるねじ止めにより接合されている。そして、配線用端子５１ｂのもう一方の端は、ねじ６０によるねじ止めにより、端子台２３ａの上面に接合されている。   One end of an L-shaped wiring terminal 51 b is joined to the external connection terminal 51 a by screwing with a screw 60. The other end of the wiring terminal 51 b is joined to the upper surface of the terminal block 23 a by screwing with a screw 60.

即ち、半導体装置１においては、樹脂ケース４０に固設された外部接続用端子５１ａに配線用端子５１ｂの一端が電気的に接続され、当該配線用端子５１ｂのもう一方の端は、端子台２３ａを通じて、ＩＧＢＴ素子３０ａのエミッタ電極並びにＦＷＤ素子３１ａのアノード側に電気的に接続されている。   That is, in the semiconductor device 1, one end of the wiring terminal 51b is electrically connected to the external connection terminal 51a fixed to the resin case 40, and the other end of the wiring terminal 51b is connected to the terminal block 23a. Through the emitter electrode of the IGBT element 30a and the anode side of the FWD element 31a.

また、外部接続用端子５２ａには、配線用端子５２ｂの一端がねじ６０によるねじ止めにより接合されている。また、配線用端子５２ｂは、配線用端子５２ｂの中部において、ねじ６０によるねじ止めにより、端子台２３ｂの上面に接合している。そして、外部接続用端子５２ａは配線用端子５０ｂの下方へ潜るように配置され、２股に分岐された別の端をねじ６０によるねじ止めにより、断面が「コ」の字型をした屈曲構造の端子台２４ａの上面に接合している。   One end of the wiring terminal 52b is joined to the external connection terminal 52a by screwing with a screw 60. The wiring terminal 52b is joined to the upper surface of the terminal block 23b by screwing with a screw 60 in the middle of the wiring terminal 52b. The external connection terminal 52a is arranged so as to be diverged below the wiring terminal 50b, and the other end of the bifurcated branch is fastened with a screw 60 so that the cross section has a U-shaped cross section. Are joined to the upper surface of the terminal block 24a.

尚、端子台２４ａの下面は、金属箔２０ｃの主面に半田付けまたはレーザー溶接によって接合されている。
即ち、半導体装置１においては、樹脂ケース４０に固設された外部接続用端子５２ａに配線用端子５２ｂの一端が電気的に接続され、当該配線用端子５２ｂの中部が端子台２３ｂを通じて、ＩＧＢＴ素子３０ｂのエミッタ電極並びにＦＷＤ素子３１ｂのアノード側に電気的に接続されている。更に、当該配線用端子５２ｂのもう一方の端は、端子台２４ａを通じて、ＩＧＢＴ素子３０ａのコレクタ電極並びにＦＷＤ素子３１ａのカソード側に電気的に接続されている。 The lower surface of the terminal block 24a is joined to the main surface of the metal foil 20c by soldering or laser welding.
That is, in the semiconductor device 1, one end of the wiring terminal 52 b is electrically connected to the external connection terminal 52 a fixed to the resin case 40, and the middle part of the wiring terminal 52 b passes through the terminal block 23 b and passes through the IGBT element. The emitter electrode 30b and the anode side of the FWD element 31b are electrically connected. Furthermore, the other end of the wiring terminal 52b is electrically connected to the collector electrode of the IGBT element 30a and the cathode side of the FWD element 31a through the terminal block 24a.

そして、樹脂ケース４０及び金属ベース板１０で取り囲まれた空間には、半導体素子、金属ワイヤ２１等の保護を目的として、配線用端子５０ｂ，５１ｂ，５２ｂの真下にまで、封止用樹脂４１が充填されている。即ち、半導体装置１においては、配線用端子５０ｂ，５１ｂ，５２ｂを封止用樹脂４１から表出させた構造をなしている。   In the space surrounded by the resin case 40 and the metal base plate 10, the sealing resin 41 is provided just below the wiring terminals 50 b, 51 b, 52 b for the purpose of protecting the semiconductor elements, the metal wires 21, and the like. Filled. That is, the semiconductor device 1 has a structure in which the wiring terminals 50 b, 51 b, 52 b are exposed from the sealing resin 41.

ここで、封止用樹脂４１の材質は、例えば、ゲルまたはエポキシ樹脂を主成分とする樹脂により構成されている。
特に、封止用樹脂４１として、エポキシ樹脂を用いた場合は、端子台２３ａ，２３ｂ，２４ａ，２４ｂの外周が当該エポキシ樹脂により封止される。 Here, the material of the sealing resin 41 is made of, for example, a resin mainly composed of gel or epoxy resin.
In particular, when an epoxy resin is used as the sealing resin 41, the outer periphery of the terminal blocks 23a, 23b, 24a, 24b is sealed with the epoxy resin.

これにより、ねじ止めのトルクにより端子台２３ａ，２３ｂ，２４ａ，２４ｂにかかる負荷が抑制され、ねじ６０の脱着を繰り返し行っても、端子台２３ａ，２３ｂ，２４ａ，２４ｂが金属箔２０ｃから剥離することはない。   Thereby, the load applied to the terminal blocks 23a, 23b, 24a, and 24b is suppressed by the screwing torque, and the terminal blocks 23a, 23b, 24a, and 24b are peeled off from the metal foil 20c even when the screw 60 is repeatedly attached and detached. There is nothing.

尚、図（ａ）では、半導体装置１の内部の構造を表示するために、封止用樹脂４１が表示されていない。
また、外部接続用端子５０ａ，５１ａ，５２ａ，５３ａ、配線用端子５０ｂ，５１ｂ，５２ｂ、並びに端子台２４ａ，２４ｂは、例えば、銅（Ｃｕ）またはアルミニウム（Ａｌ）またはこれらの合金を主成分とした材質により構成されている。 In FIG. 1A, the sealing resin 41 is not displayed in order to display the internal structure of the semiconductor device 1.
The external connection terminals 50a, 51a, 52a, 53a, the wiring terminals 50b, 51b, 52b, and the terminal blocks 24a, 24b are mainly composed of, for example, copper (Cu), aluminum (Al), or an alloy thereof. It is comprised with the material which did.

このように、半導体装置１では、樹脂ケース４０に固定支持された複数の外部接続用端子５０ａ，５１ａ，５２ａ，５３ａと、樹脂ケース４０内に包容された、少なくとも一つの半導体素子（例えば、ＩＧＢＴ素子３０ａ，３０ｂ、またはＦＷＤ素子３１ａ，３１ｂ）と、半導体素子に配設された電極（例えば、前記エミッタ電極、前記コレクタ電極、前記アノード、前記カソード）に導通する端子台２３ａ，２３ｂ，２４ａ，２４ｂと、端子台２３ａ，２３ｂ，２４ａ，２４ｂと外部接続用端子５０ａ，５１ａ，５２ａ，５３ａとの電気的接続をする配線用端子５０ｂ，５１ｂ，５２ｂと、を備えている。そして、半導体装置１では、外部接続用端子５０ａ，５１ａ，５２ａと配線用端子５０ｂ，５１ｂ，５２ｂ、または、端子台２３ａ，２３ｂ，２４ａ，２４ｂと外部接続用端子５０ａ，５１ａ，５２ａとが、ねじ６０によるねじ止めにより接合されている。   As described above, in the semiconductor device 1, the plurality of external connection terminals 50 a, 51 a, 52 a, 53 a fixedly supported by the resin case 40 and at least one semiconductor element (for example, IGBT) enclosed in the resin case 40. Element 30a, 30b or FWD element 31a, 31b) and terminal blocks 23a, 23b, 24a connected to electrodes (for example, the emitter electrode, the collector electrode, the anode, and the cathode) disposed in the semiconductor element. 24b, and wiring terminals 50b, 51b, 52b for electrical connection between the terminal blocks 23a, 23b, 24a, 24b and the external connection terminals 50a, 51a, 52a, 53a. In the semiconductor device 1, the external connection terminals 50a, 51a, 52a and the wiring terminals 50b, 51b, 52b, or the terminal blocks 23a, 23b, 24a, 24b and the external connection terminals 50a, 51a, 52a, They are joined by screwing with screws 60.

次に、このような配線用端子構造を有する半導体装置１にもたらされる有利な効果について説明する。尚、以下に示す全ての図では、図１と同一の部材には同一の符号を付し、一度説明した部材の説明の詳細については省略する。   Next, advantageous effects brought about by the semiconductor device 1 having such a wiring terminal structure will be described. In all the drawings shown below, the same members as those in FIG. 1 are denoted by the same reference numerals, and detailed description of the members once described will be omitted.

先ず、半導体装置１においては、樹脂ケース４０内での配線用端子５０ｂ，５１ｂ，５２ｂの引き回しを、半田付け、超音波接合或いはレーザー溶接ではなく、ねじ６０によるねじ止めにより行っている。   First, in the semiconductor device 1, the wiring terminals 50 b, 51 b, 52 b in the resin case 40 are routed by screwing with screws 60 instead of soldering, ultrasonic bonding or laser welding.

これにより、半田付けの場合に起きた樹脂ケース４０自体の変形、レーザー溶接で生じた溶解物（金属片）の発生が抑制される。
また、ねじ６０によるねじ止め部分が樹脂ケース４０内で中空状態であっても、当該ねじ止めにより、確実かつ簡便に各部材同士を接合することができる。 Thereby, generation | occurrence | production of the deformation | transformation of the resin case 40 itself which occurred in the case of soldering, and the melted material (metal piece) which arose by laser welding is suppressed.
Moreover, even if the screwing part by the screw 60 is a hollow state in the resin case 40, each member can be reliably and simply joined by the screwing.

例えば、図２及び図３は配線用端子の脱着の方法を説明するための要部模式図である。ここで、図２には、半導体装置１から配線用端子５０ｂ，５１ｂ，５２ｂを取り除いた状態が例示され、図３には、取り除いた配線用端子５０ｂ，５１ｂ，５２ｂの状態が例示されている。尚、図３には、ねじ６０が配線用端子５０ｂ，５１ｂ，５２ｂに取り付けられた状態が示されている。   For example, FIG.2 and FIG.3 is a principal part schematic diagram for demonstrating the removal method of the terminal for wiring. 2 illustrates the state where the wiring terminals 50b, 51b, and 52b are removed from the semiconductor device 1, and FIG. 3 illustrates the state of the removed wiring terminals 50b, 51b, and 52b. . FIG. 3 shows a state in which the screw 60 is attached to the wiring terminals 50b, 51b, and 52b.

図２に示すように、外部接続用端子５０ａ，５１ａ，５２ａ，５３ａ並びに端子台２３ａ，２３ｂ，２４ａ，２４ｂには、ねじ山を備えた孔部６０ａが設けられている。そして、夫々の孔部６０ａに、図３に示す配線用端子５０ｂ，５１ｂ，５２ｂに取り付けられた、ねじ６０を合わせ込み、夫々のねじ６０を孔部６０ａにねじ止めすることで、配線用端子５０ｂ，５１ｂ，５２ｂを外部接続用端子５０ａ，５１ａ，５２ａ並びに端子台２３ａ，２３ｂ，２４ａ，２４ｂに確実かつ簡便に接合することができる。   As shown in FIG. 2, the external connection terminals 50a, 51a, 52a, 53a and the terminal blocks 23a, 23b, 24a, 24b are provided with holes 60a having threads. Then, the screws 60 attached to the wiring terminals 50b, 51b, and 52b shown in FIG. 3 are fitted into the respective hole portions 60a, and the respective screw 60 is screwed to the hole portion 60a, whereby the wiring terminals are arranged. 50b, 51b and 52b can be reliably and simply joined to the external connection terminals 50a, 51a and 52a and the terminal blocks 23a, 23b, 24a and 24b.

これにより、樹脂ケース４０内の配線用端子の配置、引き回しが簡便になる。また、樹脂ケース４０の変形、レーザー溶接で生じる溶解物が発生せず、半導体装置の生産性が向上する。   Thereby, arrangement | positioning and routing of the wiring terminal in the resin case 40 become easy. Further, the resin case 40 is not deformed, and no melt is generated by laser welding, so that the productivity of the semiconductor device is improved.

また、外部接続用端子５０ａ，５１ａ，５２ａがインサート成形により、樹脂ケース４０内に固定されたとしても、半導体装置１では、外部接続用端子５０ａ，５１ａ，５２ａから引き回す配線用端子５０ｂ，５１ｂ，５２ｂの配置を自由に変更することができる。   Further, even if the external connection terminals 50a, 51a, 52a are fixed in the resin case 40 by insert molding, in the semiconductor device 1, wiring terminals 50b, 51b, which are routed from the external connection terminals 50a, 51a, 52a, The arrangement of 52b can be freely changed.

例えば、図１では、上述したように、外部接続用端子５０ａが正極入力端子であり、外部接続用端子５１ａが負極入力端子である。
しかし、配線用端子５０ｂ，５１ｂ，５２ｂの配置を変更することにより、外部接続用端子５０ａを負極入力端子、外部接続用端子５１ａを正極入力端子とすることができる。即ち、配線用端子５０ｂ，５１ｂ，５２ｂの配置を変更することにより、外部接続用端子５０ａ，５１ａの極を入れ替えることができる。 For example, in FIG. 1, as described above, the external connection terminal 50a is a positive input terminal, and the external connection terminal 51a is a negative input terminal.
However, by changing the arrangement of the wiring terminals 50b, 51b, 52b, the external connection terminal 50a can be used as a negative input terminal and the external connection terminal 51a can be used as a positive input terminal. That is, the poles of the external connection terminals 50a and 51a can be switched by changing the arrangement of the wiring terminals 50b, 51b and 52b.

例えば、図４は配線用端子の配置の変形例を説明するための要部模式図である。
図４に示す配置では、外部接続用端子５０ａには、配線用端子５１ｂの一端がねじ６０によるねじ止めにより接合され、配線用端子５１ｂのもう一方の端は、ねじ６０によるねじ止めにより、端子台２３ａの上面に接合されている。 For example, FIG. 4 is a schematic diagram of a main part for explaining a modification of the arrangement of wiring terminals.
In the arrangement shown in FIG. 4, one end of a wiring terminal 51 b is joined to the external connection terminal 50 a by screwing with a screw 60, and the other end of the wiring terminal 51 b is screwed with a screw 60. It is joined to the upper surface of the base 23a.

即ち、この配置においては、樹脂ケース４０に固設された外部接続用端子５０ａに配線用端子５１ｂの一端が電気的に接続され、当該配線用端子５１ｂのもう一方の端は、端子台２３ａを通じて、ＩＧＢＴ素子３０ａのエミッタ電極並びにＦＷＤ素子３１ａのアノード側に電気的に接続されている。   That is, in this arrangement, one end of the wiring terminal 51b is electrically connected to the external connection terminal 50a fixed to the resin case 40, and the other end of the wiring terminal 51b passes through the terminal block 23a. Are electrically connected to the emitter electrode of the IGBT element 30a and the anode side of the FWD element 31a.

また、外部接続用端子５１ａには、配線用端子５０ｂの一端がねじ６０によるねじ止めにより接合され、２股に分かれた配線用端子５０ｂの別の端は、ねじ６０によるねじ止めにより、端子台２４ｂの上面に接合されている。   Further, one end of the wiring terminal 50 b is joined to the external connection terminal 51 a by screwing with a screw 60, and the other end of the bifurcated wiring terminal 50 b is screwed with the screw 60 to fix the terminal block. It is joined to the upper surface of 24b.

即ち、半導体装置１においては、樹脂ケース４０に固設された外部接続用端子５１ａに配線用端子５０ｂの一端が電気的に接続され、当該配線用端子５０ｂのもう一方の端は、端子台２４ｂを通じて、ＩＧＢＴ素子３０ｂのコレクタ電極並びにＦＷＤ素子３１ｂのカソード側に電気的に接続されている。   That is, in the semiconductor device 1, one end of the wiring terminal 50b is electrically connected to the external connection terminal 51a fixed to the resin case 40, and the other end of the wiring terminal 50b is connected to the terminal block 24b. And are electrically connected to the collector electrode of the IGBT element 30b and the cathode side of the FWD element 31b.

従って、外部接続用端子５０ａを負極入力端子とし、外部接続用端子５１ａを正極入力端子とすることにより、図１に例示する半導体装置１と同様の回路構造を得ることができる。   Therefore, by using the external connection terminal 50a as a negative input terminal and the external connection terminal 51a as a positive input terminal, a circuit structure similar to that of the semiconductor device 1 illustrated in FIG. 1 can be obtained.

更に、図１に例示する半導体装置１においては、配線用端子５０ｂの配置を、別の形態に変更することにより、配線用端子５０ｂの一端を、ねじ止めにて外部接続用端子５２ａに接合することができる。そして、配線用端子５２ｂについても、別の形態に変更することにより、配線用端子５２ｂの一端をねじ止めにて外部接続用端子５０ａに接合することができる。   Further, in the semiconductor device 1 illustrated in FIG. 1, by changing the arrangement of the wiring terminal 50 b to another form, one end of the wiring terminal 50 b is joined to the external connection terminal 52 a by screwing. be able to. Further, by changing the wiring terminal 52b to another form, one end of the wiring terminal 52b can be joined to the external connection terminal 50a by screwing.

これにより、外部接続用端子５２ａを正極入力端子とすることもでき、外部接続用端子５０ａを交流出力端子とすることもできる。
また、同じ要領にて、配線用端子５１ｂの一端をねじ止めにて外部接続用端子５２ａに接合し、配線用端子５２ｂの一端をねじ止めにて外部接続用端子５１ａに接合することができる。 Thus, the external connection terminal 52a can be a positive input terminal, and the external connection terminal 50a can be an AC output terminal.
Further, in the same manner, one end of the wiring terminal 51b can be joined to the external connection terminal 52a by screwing, and one end of the wiring terminal 52b can be joined to the external connection terminal 51a by screwing.

これにより、外部接続用端子５２ａを負極入力端子とすることもでき、外部接続用端子５１ａを交流出力端子とすることもできる。
また、予備端子である外部接続用端子５３ａを、正極入力端子、負極入力端子、交流出力端子の何れかにすることも可能である。 Accordingly, the external connection terminal 52a can be a negative input terminal, and the external connection terminal 51a can be an AC output terminal.
Further, the external connection terminal 53a, which is a spare terminal, can be any of a positive input terminal, a negative input terminal, and an AC output terminal.

このように、図１に例示する半導体装置１は、外部接続用端子５０ａ，５１ａ，５２ａ，５３ａ、または半導体素子の主電極に導通させる配線用端子５０ｂ，５１ｂ，５２ｂの配置をねじ止めにより簡便に変更することができる。また、当該配線用端子５０ｂ，５１ｂ，５２ｂの配置が変更可能になることにより、外部接続用端子５０ａ，５１ａ，５２ａ，５３ａに接続する外部配線の引き回しの自由度が大きく向上する。   As described above, in the semiconductor device 1 illustrated in FIG. 1, the arrangement of the external connection terminals 50a, 51a, 52a, and 53a or the wiring terminals 50b, 51b, and 52b that conduct to the main electrode of the semiconductor element is simplified by screwing. Can be changed. Further, since the arrangement of the wiring terminals 50b, 51b, and 52b can be changed, the degree of freedom in routing the external wiring connected to the external connection terminals 50a, 51a, 52a, and 53a is greatly improved.

即ち、図２に例示した半導体装置の形態までは、半導体モジュールの構成を共通化することができ、使用者側の要望に応じて、配線用端子５０ｂ，５１ｂ，５２ｂの配置を自由に選択することができる。また、外部接続用端子５０ａ，５１ａ，５２ａ，５３ａに接続する外部配線の配置においても、使用者側の要望に応じて自由に選択することもできる。   In other words, the configuration of the semiconductor module can be shared up to the form of the semiconductor device illustrated in FIG. 2, and the arrangement of the wiring terminals 50b, 51b, 52b can be freely selected according to the user's request. be able to. Further, the arrangement of the external wirings connected to the external connection terminals 50a, 51a, 52a, 53a can be freely selected according to the user's request.

また、半導体装置が所定の形態に共通化されていることから、半導体モジュールに費やされる設計時間を短縮させ、更に、開発費用を低減させることができる。
また、配線用端子５０ｂ，５１ｂ，５２ｂの長さ、幅、厚みを調整することにより、配線抵抗、リアクタンス、放熱量等を回路の性能に応じて自由に調整することができる。 Further, since the semiconductor device is shared in a predetermined form, it is possible to shorten the design time spent on the semiconductor module and further reduce the development cost.
Further, by adjusting the length, width, and thickness of the wiring terminals 50b, 51b, and 52b, the wiring resistance, reactance, heat radiation amount, and the like can be freely adjusted according to the performance of the circuit.

尚、半導体装置１にあっては、半導体装置の更なる小型化、軽量化を図るために、金属ベース板１０を取り除き、絶縁基板２０を半導体装置１の基体とした、所謂金属ベースレス構造であってもよい。   The semiconductor device 1 has a so-called metal baseless structure in which the metal base plate 10 is removed and the insulating substrate 20 is used as the base of the semiconductor device 1 in order to further reduce the size and weight of the semiconductor device. There may be.

＜第２の実施の形態＞
次に、半導体装置１の形態を変形させた半導体装置２について説明する。
図５は第２の実施の形態に係る半導体装置の要部断面模式図である。 <Second Embodiment>
Next, a semiconductor device 2 in which the form of the semiconductor device 1 is modified will be described.
FIG. 5 is a schematic cross-sectional view of an essential part of a semiconductor device according to the second embodiment.

図示するように、半導体装置２では、半導体素子、金属ワイヤ２１等の保護を目的として、封止用樹脂４１を樹脂ケース４０内に充填すると共に、当該封止用樹脂４１によりねじ６０を被覆・封止する形態をなしている。   As shown in the figure, in the semiconductor device 2, for the purpose of protecting the semiconductor element, the metal wire 21, etc., the sealing resin 41 is filled in the resin case 40 and the screw 60 is covered with the sealing resin 41. It is in the form of sealing.

このような構造であれば、配線用端子５０ｂ，５１ｂ，５２ｂ同士の絶縁性が確保される。また、ねじ６０が封止用樹脂４１により被覆・封止されていることから、ねじ止めした後のねじ６０に緩みが生じることがない。   With such a structure, the insulation between the wiring terminals 50b, 51b, 52b is secured. Further, since the screw 60 is covered and sealed with the sealing resin 41, the screw 60 after being screwed does not loosen.

＜第３の実施の形態＞
次に、半導体装置１の形態を変形させた別の半導体装置３について説明する。
図６は第３の実施の形態に係る半導体装置の要部模式図である。ここで、図（ａ）には、半導体装置の平面模式図が例示され、図（ｂ）には図（ａ）の破線Ｘ−Ｘの位置における断面を矢印の方向に矢視する図が表示されている。 <Third Embodiment>
Next, another semiconductor device 3 in which the form of the semiconductor device 1 is modified will be described.
FIG. 6 is a schematic diagram of a main part of a semiconductor device according to the third embodiment. Here, FIG. (A) illustrates a schematic plan view of the semiconductor device, and FIG. (B) displays a view of the cross section at the position of the broken line XX in FIG. (A) in the direction of the arrow. Has been.

図示するように、半導体装置３では、樹脂、セラミック材等を基材とする、少なくとも１枚のプリント基板（配線基板）７０が樹脂ケース４０の内側面から延在された支持台４０ａ上に載置されている。また、プリント基板７０は、絶縁体であるスペーサ６１を介して、ねじ６０によるねじ止めにより、外部接続用端子５０ａ，５１ａ，５２ａ，５３ａに固定されている。そして、ピン端子２２がプリント基板７０内を貫通し、ピン端子２２がプリント基板７０の主面に配設された複数の回路パターン（図示しない）に、半田付けにより電気的に接続されている。   As shown in the figure, in the semiconductor device 3, at least one printed circuit board (wiring board) 70 made of resin, ceramic material or the like as a base material is mounted on a support base 40 a extending from the inner surface of the resin case 40. Is placed. The printed circuit board 70 is fixed to the external connection terminals 50a, 51a, 52a, and 53a by screwing with screws 60 through spacers 61 that are insulators. The pin terminals 22 penetrate through the printed circuit board 70, and the pin terminals 22 are electrically connected to a plurality of circuit patterns (not shown) disposed on the main surface of the printed circuit board 70 by soldering.

このようなプリント基板７０には、上記回路パターンに導通するＩＣ回路部、コンデンサ部、抵抗部等が配置されている（図示しない）。このようなＩＣ回路部、コンデンサ部、抵抗部をプリント基板７０の主面に配置することにより、半導体装置３は、温度センサー回路や過電圧・過電流保護回路等を組み込む形態をなしている。即ち、半導体装置３は、ＩＰＭ（Intelligent Power Module）として機能する。   Such a printed circuit board 70 is provided with an IC circuit portion, a capacitor portion, a resistance portion, and the like (not shown) that are electrically connected to the circuit pattern. By disposing such an IC circuit portion, a capacitor portion, and a resistance portion on the main surface of the printed circuit board 70, the semiconductor device 3 is configured to incorporate a temperature sensor circuit, an overvoltage / overcurrent protection circuit, and the like. That is, the semiconductor device 3 functions as an IPM (Intelligent Power Module).

このように半導体装置３では、外部接続用端子５０ａ，５１ａ，５２ａ，５３ａに、ねじ止めにより、プリント基板７０を固定している。このような構造であれば、回路パターンを備えたプリント基板７０を簡便に半導体装置３に脱着することが可能になる。   Thus, in the semiconductor device 3, the printed circuit board 70 is fixed to the external connection terminals 50a, 51a, 52a, and 53a by screwing. With such a structure, the printed circuit board 70 having the circuit pattern can be easily attached to and detached from the semiconductor device 3.

また、ねじ６０は金属製であることから、当該ねじ６０を通じて、配線用端子５０ｂ，５１ｂ，５２ｂに導通する配線パターンをプリント基板７０の主面に引き回してもよい。このような配線パターンをプリント基板７０に配置することにより、正極入力端子、負極入力端子或いは交流出力端子の電位のモニタリング等がプリント基板７０に配設された回路によって実施し得る。   Further, since the screw 60 is made of metal, the wiring pattern that is electrically connected to the wiring terminals 50 b, 51 b, 52 b may be routed to the main surface of the printed board 70 through the screw 60. By arranging such a wiring pattern on the printed circuit board 70, the potential of the positive input terminal, the negative input terminal, or the AC output terminal can be monitored by a circuit disposed on the printed circuit board 70.

＜第４の実施の形態＞
次に、半導体装置１の形態を変形させた、更に別の半導体装置４について説明する。
図７は第４の実施の形態に係る半導体装置の要部模式図である。ここで、図（ａ）には、半導体装置の平面模式図が例示され、図（ｂ）には図（ａ）の破線Ｘ−Ｘの位置における断面を矢印の方向に矢視する図が表示されている。 <Fourth embodiment>
Next, still another semiconductor device 4 in which the form of the semiconductor device 1 is modified will be described.
FIG. 7 is a schematic diagram of a main part of a semiconductor device according to the fourth embodiment. Here, FIG. (A) illustrates a schematic plan view of the semiconductor device, and FIG. (B) displays a view of the cross section at the position of the broken line XX in FIG. (A) in the direction of the arrow. Has been.

図示するように、半導体装置４では、少なくとも１枚の金属板７１が樹脂ケース４０の内側面から延在された支持台４０ａ上に載置されている。また、プリント基板７０は、絶縁体であるスペーサ６１を通じて、ねじ６０によるねじ止めにより、外部接続用端子５１ａ，５３ａに固定されている。また、金属板７１は、ねじ６０を通じて、負極入力端子である外部接続用端子５１ａに導通している。   As shown in the figure, in the semiconductor device 4, at least one metal plate 71 is placed on a support base 40 a extending from the inner surface of the resin case 40. The printed circuit board 70 is fixed to the external connection terminals 51a and 53a by screwing with a screw 60 through a spacer 61 which is an insulator. Further, the metal plate 71 is electrically connected to the external connection terminal 51a which is a negative electrode input terminal through the screw 60.

このような構造であれば、金属板７１は、半導体素子等から発せられる電磁波のシールド板として機能し、例えば、半導体装置４外に取り付ける制御回路等を安定して作動させることができる。   With such a structure, the metal plate 71 functions as a shield plate for electromagnetic waves emitted from a semiconductor element or the like, and can stably operate, for example, a control circuit attached outside the semiconductor device 4.

尚、電磁波のシールド板においては、金属板７１を取り付ける代わりに、外部接続用端子５１ａに導通する金属層（シールド層）を、上述したプリント基板７０の主面に選択的に配置してもよい。   In the electromagnetic wave shield plate, instead of attaching the metal plate 71, a metal layer (shield layer) conducting to the external connection terminal 51a may be selectively disposed on the main surface of the printed circuit board 70 described above. .

＜第５の実施の形態＞
次に、半導体装置１の形態を変形させた、更に別の半導体装置５について説明する。
図８は第５の実施の形態に係る半導体装置の要部模式図である。ここで、図（ａ）には、半導体装置の平面模式図が例示され、図（ｂ）には図（ａ）の破線Ｘ−Ｘの位置における断面を矢印の方向に矢視する図が表示されている。 <Fifth embodiment>
Next, still another semiconductor device 5 in which the form of the semiconductor device 1 is modified will be described.
FIG. 8 is a schematic diagram of a main part of a semiconductor device according to the fifth embodiment. Here, FIG. (A) illustrates a schematic plan view of the semiconductor device, and FIG. (B) displays a view of the cross section at the position of the broken line XX in FIG. (A) in the direction of the arrow. Has been.

図示するように、半導体装置５では、例えば、樹脂またはセラミック材を主成分とする絶縁板７２の主面に配線用端子５０ｂ，５１ｂ，５２ｂを接着部材（図示しない）を介して固着させている。   As shown in the figure, in the semiconductor device 5, for example, wiring terminals 50b, 51b, and 52b are fixed to the main surface of an insulating plate 72 mainly composed of a resin or a ceramic material via an adhesive member (not shown). .

このような構造であれば、絶縁板７２に固着された配線用端子５０ｂ，５１ｂ，５２ｂのユニットを一括して、外部接続用端子５０ａ，５１ａ，５２ａ並びに端子台２３ａ，２３ｂ，２４ａ，２４ｂに、ねじ止めすることができる。即ち、配線用端子５０ｂ，５１ｂ，５２ｂの脱着がより簡便になる。   With such a structure, the wiring terminals 50b, 51b and 52b fixed to the insulating plate 72 are collectively connected to the external connection terminals 50a, 51a and 52a and the terminal blocks 23a, 23b, 24a and 24b. Can be screwed. That is, the attachment / detachment of the wiring terminals 50b, 51b, 52b becomes easier.

＜第６の実施の形態＞
次に、半導体装置１の形態を変形させた、更に別の半導体装置６について説明する。
図９は第６の実施の形態に係る半導体装置の要部平面模式図である。 <Sixth Embodiment>
Next, still another semiconductor device 6 in which the form of the semiconductor device 1 is modified will be described.
FIG. 9 is a schematic plan view of an essential part of a semiconductor device according to the sixth embodiment.

半導体装置６では、例えば、半導体装置１と同じ構成の半導体装置１ａ，１ｂ，１ｃが複数個、並べられ、夫々の配線用端子５０ｂ，５１ｂが連結された構造をなしている。
例えば、夫々の配線用端子５０ｂは、Ｐバスバー５０ｂｂにて連結され、夫々の配線用端子５０ｂの一端がねじ止めにより外部接続用端子５０ａに接合されている。更に、夫々の配線用端子５０ｂのもう一方の端は、ねじ止めにより、端子台２４ｂの上面に接合されている。 In the semiconductor device 6, for example, a plurality of semiconductor devices 1 a, 1 b, 1 c having the same configuration as the semiconductor device 1 are arranged and the wiring terminals 50 b, 51 b are connected to each other.
For example, each wiring terminal 50b is connected by a P bus bar 50bb, and one end of each wiring terminal 50b is joined to the external connection terminal 50a by screwing. Furthermore, the other end of each wiring terminal 50b is joined to the upper surface of the terminal block 24b by screwing.

また、夫々の配線用端子５１ｂは、Ｎバスバー５１ｂｂにて連結され、夫々の配線用端子５１ｂの一端がねじ止めにより外部接続用端子５１ａ接合されている。更に、夫々の配線用端子５１ｂのもう一方の端は、ねじ止めにより、端子台２３ａの上面に接合されている。   Each wiring terminal 51b is connected by an N bus bar 51bb, and one end of each wiring terminal 51b is joined to the external connection terminal 51a by screwing. Furthermore, the other end of each wiring terminal 51b is joined to the upper surface of the terminal block 23a by screwing.

そして、半導体装置６の外部に設置された直流電源の正極を半導体装置１ａ，１ｂ，１ｃに配設された何れかの外部接続用端子５０ａに接続する。また、直流電源の負極を半導体装置１ａ，１ｂ，１ｃに配設された何れかの外部接続用端子５１ａに接続する。   Then, the positive electrode of the DC power supply installed outside the semiconductor device 6 is connected to one of the external connection terminals 50a provided in the semiconductor devices 1a, 1b, and 1c. Further, the negative electrode of the DC power source is connected to any one of the external connection terminals 51a provided in the semiconductor devices 1a, 1b, and 1c.

このような構成により、半導体装置６は、交流出力端子（外部接続用端子５２ａ）を３個備えた３相インバータ回路として機能する。
尚、図９では、Ｐバスバー５０ｂｂと配線用端子５０ｂ、Ｎバスバー５１ｂｂと配線用端子５１ｂとが一体となった構成を例示しているが、当該Ｐバスバー５０ｂｂ、Ｎバスバー５１ｂｂは必要に応じて所定の長さに分断し、継ぎ手部分をねじ６０によるねじ止めにより接続してもよい。また、半導体装置１を配置する数については、３個に限ることはない。使用者側の要望に応じて、半導体装置１を２個配置してもよく、４個以上配置してもよい。 With such a configuration, the semiconductor device 6 functions as a three-phase inverter circuit including three AC output terminals (external connection terminals 52a).
9 illustrates a configuration in which the P bus bar 50bb and the wiring terminal 50b, and the N bus bar 51bb and the wiring terminal 51b are integrated, the P bus bar 50bb and the N bus bar 51bb may be used as necessary. It may be divided into a predetermined length, and the joint portion may be connected by screwing with a screw 60. Further, the number of semiconductor devices 1 arranged is not limited to three. Two semiconductor devices 1 may be arranged, or four or more may be arranged according to the user's request.

また、半導体装置６においては、配線用端子５０ｂ，５１ｂ，５２ｂ、Ｐバスバー５０ｂｂ、並びにＮバスバー５１ｂｂの配置を変更することにより、外部接続用端子５１ａ，５２ａ，５３ａの何れかを正極入力端子とすることもできる。また、外部接続用端子５０ａ，５２ａ，５３ａの何れかを負極入力端子とすることもできる。更に、外部接続用端子５０ａ，５１ａ，５３ａの何れかを交流出力端子とすることもできる。   In the semiconductor device 6, any of the external connection terminals 51a, 52a, and 53a is changed to a positive input terminal by changing the arrangement of the wiring terminals 50b, 51b, and 52b, the P bus bar 50bb, and the N bus bar 51bb. You can also Also, any of the external connection terminals 50a, 52a, 53a can be used as a negative input terminal. Furthermore, any of the external connection terminals 50a, 51a, 53a can be used as an AC output terminal.

＜第７の実施の形態＞
次に、半導体装置１の形態を変形させた、更に別の半導体装置７について説明する。
図１０は第７の実施の形態に係る半導体装置の模式図である。 <Seventh embodiment>
Next, still another semiconductor device 7 in which the form of the semiconductor device 1 is modified will be described.
FIG. 10 is a schematic diagram of a semiconductor device according to the seventh embodiment.

半導体装置７では、例えば、図１に示す端子台２３ａ，２３ｂの代わりに、ヒートスプレッダ２５を用いた構造をなしている。このようなヒートスプレッダ２５は、例えば、ＩＧＢＴ素子３０ａのエミッタ電極（上面側）に接合された放熱部材、伝導体として機能する。   For example, the semiconductor device 7 has a structure using a heat spreader 25 instead of the terminal blocks 23a and 23b shown in FIG. Such a heat spreader 25 functions as, for example, a heat radiating member and a conductor bonded to the emitter electrode (upper surface side) of the IGBT element 30a.

図示するように、ヒートスプレッダ２５には、予めねじ穴２５ａを形成させておく。また、ねじ穴２５ａの内部には、ねじ６０と螺合するねじ山が形成されている。そして、配線用端子５１ｂのねじ穴５１ｂｈの位置を合わせ、当該ねじ６０によるねじ止めにより、配線用端子５１ｂとヒートスプレッダ２５との電気的・熱的な接続を行う。   As shown in the figure, a screw hole 25a is formed in the heat spreader 25 in advance. A screw thread that is screwed into the screw 60 is formed inside the screw hole 25a. Then, the position of the screw hole 51 bh of the wiring terminal 51 b is aligned, and the wiring terminal 51 b and the heat spreader 25 are electrically and thermally connected by screwing with the screw 60.

このような構造によっても、配線用端子５１ｂとＩＧＢＴ素子３０ａとの電気的・熱的な接続を簡便に行うことができる。
尚、このようなヒートスプレッダ２５を備えた素子は、ＩＧＢＴ素子３０ａに限るものではない。上述したＩＧＢＴ素子３０ｂ、ＦＷＤ素子３１ａ，３１ｂにおいても、ヒートスプレッダ２５を備え、対応する配線用端子を接合させてもよい。 Even with such a structure, the electrical and thermal connection between the wiring terminal 51b and the IGBT element 30a can be easily performed.
The element provided with such a heat spreader 25 is not limited to the IGBT element 30a. Also in the IGBT element 30b and the FWD elements 31a and 31b described above, the heat spreader 25 may be provided and the corresponding wiring terminals may be joined.

また更に、複数の半導体素子に跨って、１つのヒートスプレッダを接合し、当該複数の半導体素子の直上部分を避けた位置にねじ穴を形成し、当該部分に配線用端子を接合させてもよい。   Furthermore, one heat spreader may be joined across a plurality of semiconductor elements, a screw hole may be formed at a position avoiding a portion directly above the plurality of semiconductor elements, and a wiring terminal may be joined to the part.

尚、上述した第１乃至第７の実施の形態は、独立した形態ではなく、少なくとも２つ以上の実施の形態を複合させてもよい。   Note that the first to seventh embodiments described above are not independent, and at least two or more embodiments may be combined.

第１の実施の形態に係る半導体装置の要部模式図である。It is a principal part schematic diagram of the semiconductor device which concerns on 1st Embodiment. 配線用端子の脱着の方法を説明するための要部模式図である（その１）。It is a principal part schematic diagram for demonstrating the removal method of the terminal for wiring (the 1). 配線用端子の脱着の方法を説明するための要部模式図である（その２）。It is a principal part schematic diagram for demonstrating the removal method of the terminal for wiring (the 2). 配線用端子の配置の変形例を説明するための要部模式図である。It is a principal part schematic diagram for demonstrating the modification of arrangement | positioning of the terminal for wiring. 第２の実施の形態に係る半導体装置の要部断面模式図である。It is a principal part cross-sectional schematic diagram of the semiconductor device which concerns on 2nd Embodiment. 第３の実施の形態に係る半導体装置の要部模式図である。It is a principal part schematic diagram of the semiconductor device which concerns on 3rd Embodiment. 第４の実施の形態に係る半導体装置の要部模式図である。It is a principal part schematic diagram of the semiconductor device which concerns on 4th Embodiment. 第５の実施の形態に係る半導体装置の要部模式図である。It is a principal part schematic diagram of the semiconductor device which concerns on 5th Embodiment. 第６の実施の形態に係る半導体装置の要部平面模式図である。It is a principal part schematic plan view of the semiconductor device which concerns on 6th Embodiment. 第７の実施の形態に係る半導体装置の要部模式図である。It is a principal part schematic diagram of the semiconductor device which concerns on 7th Embodiment. パワー半導体素子を樹脂ケース内に封止させた半導体装置の要部模式図である。It is a principal part schematic diagram of the semiconductor device which sealed the power semiconductor element in the resin case.

符号の説明Explanation of symbols

１，１ａ，１ｂ，１ｃ，２，３，４，５，６ 半導体装置
１０ 金属ベース板
２０ 絶縁基板
２０ｂ，２０ｃ 金属箔
２０ａ，７２ 絶縁板
２１ 金属ワイヤ
２２ ピン端子
２３ａ，２３ｂ，２４ａ，２４ｂ 端子台
２５ ヒートスプレッダ
２５ａ，５１ｂｈ ねじ穴
３０ａ，３０ｂ ＩＧＢＴ素子
３１ａ，３１ｂ ＦＷＤ素子
３０ｇ 制御電極
４０ａ 支持台
４０ 樹脂ケース
４１ 封止用樹脂
５０ａ，５１ａ，５２ａ，５３ａ 外部接続用端子
５０ｂｂ，５１ｂｂ バスバー
５０ｂ，５１ｂ，５２ｂ 配線用端子
６０ ねじ
６０ａ 孔部
６１ スペーサ
７０ プリント基板
７１ 金属板 1, 1a, 1b, 1c, 2, 3, 4, 5, 6 Semiconductor device 10 Metal base plate 20 Insulating substrate 20b, 20c Metal foil 20a, 72 Insulating plate 21 Metal wire 22 Pin terminal 23a, 23b, 24a, 24b Terminal Base 25 Heat spreader 25a, 51bh Screw hole 30a, 30b IGBT element 31a, 31b FWD element 30g Control electrode 40a Support base 40 Resin case 41 Sealing resin 50a, 51a, 52a, 53a External connection terminal 50bb, 51bb Bus bar 50b, 51b , 52b Wiring terminal 60 Screw 60a Hole 61 Spacer 70 Printed circuit board 71 Metal plate

Claims (10)

樹脂ケースに固定支持された複数の外部接続用端子と、
前記樹脂ケース内に包容された、少なくとも一つの半導体素子と、
前記半導体素子に配設された電極に導通する端子台と、
前記端子台と前記外部接続用端子との電気的接続をする配線用端子と、
前記樹脂ケース内に充填された、少なくとも前記半導体素子を封止し、前記配線用端子が表出している樹脂と、
を備え、
前記外部接続用端子と前記配線用端子、または、前記端子台と前記配線用端子との少なくとも何れかがねじ止めにより接合されていることを特徴とする半導体装置。 A plurality of external connection terminals fixedly supported by the resin case;
At least one semiconductor element enclosed in the resin case;
A terminal block electrically connected to an electrode disposed in the semiconductor element;
A wiring terminal for electrical connection between the terminal block and the external connection terminal;
Resin filled in the resin case, sealing at least the semiconductor element, and exposing the wiring terminals;
With
At least one of the external connection terminal and the wiring terminal or the terminal block and the wiring terminal is joined by screwing. 前記電極が前記半導体素子の主電極であることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the electrode is a main electrode of the semiconductor element. 前記端子台は、前記半導体素子の電極に接合された放熱部材であることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the terminal block is a heat radiating member bonded to an electrode of the semiconductor element. 前記端子台が屈曲構造を備えていることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the terminal block has a bent structure. 前記樹脂ケース内に少なくとも前記半導体素子を封止する樹脂が充填されていると共に、前記樹脂がねじ止めに用いるねじを封止していることを特徴とする請求項１記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the resin case is filled with at least a resin for sealing the semiconductor element, and the resin seals a screw used for screwing. 複数の前記配線用端子が絶縁板に固着されていることを特徴とする請求項１記載の半導体装置。  2. The semiconductor device according to claim 1, wherein the plurality of wiring terminals are fixed to an insulating plate. 前記外部接続用端子と前記配線用端子、または、前記端子台と前記配線用端子とがねじ止めにより接合されていると共に、前記外部接続用端子に、少なくとも温度センサー回路、過電圧保護回路、過電流保護回路、シールド層の何れかを配置した、少なくとも一枚のプリント基板がねじ止めにより固定されていることを特徴とする請求項１記載の半導体装置。  The external connection terminal and the wiring terminal, or the terminal block and the wiring terminal are joined by screwing, and the external connection terminal includes at least a temperature sensor circuit, an overvoltage protection circuit, an overcurrent. 2. The semiconductor device according to claim 1, wherein at least one printed circuit board on which either the protection circuit or the shield layer is disposed is fixed by screwing. 前記プリント基板に、ねじ止めに用いるねじを通じて、前記半導体素子の前記電極に導通する配線パターンが配置されていることを特徴とする請求項７記載の半導体装置。  8. The semiconductor device according to claim 7, wherein a wiring pattern that is electrically connected to the electrode of the semiconductor element is disposed on the printed board through a screw used for screwing. 前記外部接続用端子と前記配線用端子、または、前記端子台と前記配線用端子とがねじ止めにより接合されていると共に、前記外部接続用端子に、少なくとも一枚のシールド板がねじ止めにより固定されていることを特徴とする請求項１記載の半導体装置。  The external connection terminal and the wiring terminal, or the terminal block and the wiring terminal are joined by screwing, and at least one shield plate is fixed to the external connection terminal by screwing. The semiconductor device according to claim 1, wherein: 樹脂ケースに固定支持された複数の外部接続用端子と、  A plurality of external connection terminals fixedly supported by the resin case;
前記樹脂ケース内に包容された、少なくとも一つの半導体素子と、  At least one semiconductor element enclosed in the resin case;
前記半導体素子に配設された電極に導通する端子台と、  A terminal block electrically connected to an electrode disposed in the semiconductor element;
前記端子台と前記外部接続用端子との電気的接続をする配線用端子と、  A wiring terminal for electrical connection between the terminal block and the external connection terminal;
前記樹脂ケース内に充填された、少なくとも前記半導体素子を封止し、前記配線用端子が表出している樹脂と、  Resin filled in the resin case, sealing at least the semiconductor element, and exposing the wiring terminals;
を備え、  With
前記外部接続用端子と前記配線用端子、または、前記端子台と前記配線用端子とがねじ止めにより接合されている、複数の半導体モジュール間の前記配線用端子を連結したことを特徴とする半導体装置。  A semiconductor characterized in that the external connection terminal and the wiring terminal, or the terminal block and the wiring terminal are joined by screwing, and the wiring terminal is connected between a plurality of semiconductor modules. apparatus.
JP2007304092A 2007-11-26 2007-11-26 Semiconductor device Active JP5292779B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2007304092A JP5292779B2 (en) 2007-11-26 2007-11-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007304092A JP5292779B2 (en) 2007-11-26 2007-11-26 Semiconductor device

Publications (2)

Publication Number Publication Date
JP2009130163A JP2009130163A (en) 2009-06-11
JP5292779B2 true JP5292779B2 (en) 2013-09-18

Family

ID=40820778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007304092A Active JP5292779B2 (en) 2007-11-26 2007-11-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JP5292779B2 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5178756B2 (en) * 2010-03-09 2013-04-10 三菱電機株式会社 Pin terminal joining method and apparatus, and power board with pin terminals
JP5789264B2 (en) * 2010-09-24 2015-10-07 セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー Circuit equipment
CN103262238B (en) * 2010-09-24 2016-06-22 半导体元件工业有限责任公司 Circuit arrangement
CN104620377B (en) 2012-10-29 2017-09-01 富士电机株式会社 Semiconductor device
JP5533983B2 (en) * 2012-11-12 2014-06-25 富士電機株式会社 Semiconductor device
JP6112073B2 (en) * 2014-06-20 2017-04-12 株式会社豊田自動織機 Semiconductor device
JP6061967B2 (en) * 2015-03-05 2017-01-18 三菱電機株式会社 Power semiconductor device
CN108447845B (en) * 2018-05-21 2024-06-21 臻驱科技（上海）有限公司 Power semiconductor module substrate and power semiconductor module
KR102645198B1 (en) * 2018-10-24 2024-03-06 현대자동차주식회사 Power module of double-faced cooling
JP6727732B2 (en) * 2018-11-26 2020-07-22 三菱電機株式会社 Power converter
JP7433562B1 (en) 2023-06-14 2024-02-19 三菱電機株式会社 semiconductor equipment

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2956363B2 (en) * 1992-07-24 1999-10-04 富士電機株式会社 Power semiconductor device
JP3552549B2 (en) * 1998-09-08 2004-08-11 株式会社豊田自動織機 Electrode terminal connection structure of semiconductor module
JP2002026246A (en) * 2000-06-30 2002-01-25 Toshiba Corp Semiconductor device
JP4637784B2 (en) * 2006-04-14 2011-02-23 三菱電機株式会社 Power semiconductor device
JP4820233B2 (en) * 2006-08-09 2011-11-24 本田技研工業株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP2009130163A (en) 2009-06-11

Similar Documents

Publication Publication Date Title
JP5292779B2 (en) Semiconductor device
JP5176507B2 (en) Semiconductor device
JP5098951B2 (en) Semiconductor device
US8441117B2 (en) Semiconductor device
US7884455B2 (en) Semiconductor device
EP2833405A1 (en) Semiconductor device, and method for manufacturing semiconductor device
JP3960230B2 (en) Semiconductor module, method for manufacturing the same, and switching power supply device
JP6218898B2 (en) Power semiconductor device
JP2007234690A (en) Power semiconductor module
JP2012004543A (en) Semiconductor unit, and semiconductor device using the same
JP5930980B2 (en) Semiconductor device and manufacturing method thereof
JP2009010252A (en) Semiconductor device
US11600558B2 (en) Plurality of transistor packages with exposed source and drain contacts mounted on a carrier
JP5256994B2 (en) Semiconductor device
EP3584834A1 (en) Semiconductor device
JP2007173703A (en) Semiconductor device
US20240006280A1 (en) Intelligent power module and manufacturing method thereof
WO2019189450A1 (en) Power conversion device
JP5533983B2 (en) Semiconductor device
JP2006303375A (en) Power converting device and method for manufacturing the same
JP5987635B2 (en) Power semiconductor module
CN219269154U (en) Package body
US20220384321A1 (en) Semiconductor module and method for fabricating the same
JP2024020692A (en) Semiconductor device and method for manufacturing semiconductor device
CN203013709U (en) Semiconductor device

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20091112

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20091112

RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20091112

A625 Written request for application examination (by other person)

Free format text: JAPANESE INTERMEDIATE CODE: A625

Effective date: 20101015

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20110422

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20111031

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121009

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121206

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20130514

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20130527

R150 Certificate of patent or registration of utility model

Ref document number: 5292779

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250