JP5291309B2 - High electron mobility transistors and electronic devices - Google Patents

Description

  The present invention relates to a high electron mobility transistor and an electronic device. The present invention particularly relates to a high electron mobility transistor having low distortion and high withstand voltage with respect to a large signal, and an electronic device including such a high electron mobility transistor.

For example, Patent Document 1 describes a single integrated E / D mode HEMT (High Electron Mobility Transistor). In the HEMT described in this document, an undoped GaAs, GaAs / Al _x Ga _1-x As (mixed crystal ratio x is larger than 0 and smaller than or equal to 1) superlattice layer on a semi-insulating GaAs substrate, or A buffer layer combining the two is disclosed. On the buffer layer, a channel layer is formed. In the case of a p-HEMT device, the channel layer is In _x Ga _1-x As which is not doped with impurities (mixed crystal ratio x is greater than 0 and less than or equal to 0.35). It is described that.

In addition, the HEMT of this document discloses that a first barrier layer, a second barrier layer, and a third barrier layer are sequentially stacked on a channel layer. The first barrier layer and the third barrier layer are composed of In _0.5 Ga _0.5 P lattice-matched to GaAs, and the barrier layer is described as being n-type and modulation-doped. . Examples of the doping distribution include a uniform doping structure, a delta doping structure, and a mixed structure of uniform doping and delta doping.
Special table 2004-511913

  For example, in the field of test equipment such as a semiconductor integrated circuit, there is a case where it is desired to test a limit test such as a withstand voltage of a device under test operating at a high clock frequency in an operating state. In such a case, the control device for the test signal applied to the device under test is required to have a high frequency response higher than the operating frequency of the device under test. Further, a withstand voltage that can withstand a high voltage level higher than the withstand voltage of the device under test is required. Furthermore, even when such a high voltage level test signal is input, low distortion is required so that the distortion of the test signal falls within a specified range.

In order to solve the above problems, in the first embodiment of the present invention, a heterojunction is formed between a substrate, a buffer layer above the substrate, a carrier traveling layer above the buffer layer, and a carrier traveling layer. A first carrier supply layer, and a second carrier supply layer formed above the first carrier supply layer and having a carrier density lower than that of the first carrier supply layer , wherein the carrier traveling layer is an intrinsic In _x Ga _1-x As layer, the first carrier supply layer and the second carrier supply layer are n-type In _y Ga _1-y P layers, and the carrier density of the first carrier supply layer is 0.5 × 10 ¹⁸ cm ^−3. or 3 in the range of less than × ¹⁰ 18 ^{cm -3,} the carrier density of the second carrier supply layer is in the range of less than 0.5 × ¹⁰ 17 ^{cm -3} or more 5 × ¹⁰ 17 ^{cm -3,} the first carrier The thickness of the supply layer is In the range of less than 35nm over 15 nm, the thickness of the second carrier supply layer provides high electron mobility transistor area by der less than 5 nm 15 nm.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 shows a cross section of a high electron mobility transistor 10 of the present embodiment. The high electron mobility transistor 10 of this embodiment includes a substrate 100, a buffer layer 110, an intermediate layer 120, a carrier traveling layer 130, a high concentration carrier supply layer 140, a low concentration carrier supply layer 142, and an ohmic layer. 150, a gate electrode 160, a drain electrode 162, a source electrode 164, and a protective layer 170. The buffer layer 110 includes a lower buffer layer 112, a superlattice layer 114, and an upper buffer layer 116.

  The substrate 100 includes a non-doped compound semiconductor that is not doped with impurities at least on its surface. The type of compound semiconductor on the surface of the substrate 100 can be selected in consideration of lattice matching with the semiconductor material formed in the upper layer. In the present embodiment, a GaAs compound semiconductor is exemplified as the carrier traveling layer 130, and thus the substrate 100 having a GaAs surface can be illustrated. The substrate 100 may be a single crystal silicon substrate, a sapphire substrate, or a SiC substrate on which a non-doped GaAs layer is formed.

  The buffer layer 110 is formed on the upper layer of the substrate 100. Here, “formed on the“ upper layer ”of the substrate 100 is formed on the upper surface of the substrate 100 in contact with the substrate 100, and an arbitrary layer is formed between the substrate 100 and the upper surface of the arbitrary layer. It includes the case where it is formed. The same applies to the following description. Note that the upper and lower expressions are for convenience, and the side of the substrate 100 is on the bottom, and the surface side on which processing such as deposition or etching is performed is on the top.

  The buffer layer 110 includes a superlattice layer 114 of an intrinsic compound semiconductor. The buffer layer 110 may be a stacked structure layer formed by stacking an intrinsic GaAs layer and a GaAs / AlGaAs superlattice layer. In this embodiment, as the buffer layer 110, for example, a stacked structure including a lower buffer layer 112, a superlattice layer 114, and an upper buffer layer 116 is employed.

The expression of AlGaAs is precisely Al _x Ga _1-x As, and x represents the mixed crystal ratio of Al. Similarly, InGaAs and InGaP, which will be described later, are exactly In _x Ga _1-x As and In _x Ga _1-x P, and x represents a mixed crystal ratio of In. The mixed crystal ratio x can take an arbitrary range of 0 <x <1, but since the band gap and the lattice constant vary depending on the mixed crystal ratio x, an appropriate mixed crystal ratio x is selected depending on the structure of the device and the underlying material. it can. In the case of AlGaAs, 0.2 can be exemplified as an appropriate Al mixed crystal ratio x.

  The lower buffer layer 112 includes, for example, a non-doped or intrinsic GaAs layer. The lower buffer layer 112 can be formed by an epitaxial growth method such as an MO-CVD (Metal Organic Chemical Deposition) method or an MBE (Molecular Beam Epitaxy) method. An example of the thickness of the lower buffer layer 112 is 100 nm.

  The superlattice layer 114 is formed by repeatedly laminating semiconductor ultrathin films having different band gaps, for example, ultrathin films of GaAs and AlGaAs. The ultrathin films of GaAs and AlGaAs are formed undoped to form intrinsic ultrathin films of GaAs and AlGaAs. Since AlGaAs having a band gap larger than that of GaAs is adopted as one of the ultrathin films having a superlattice structure, the leakage current to the substrate 100 can be reduced as compared with the case where the buffer layer is formed only by the GaAs film.

  Each ultrathin film of GaAs and AlGaAs can be formed by an epitaxial growth method such as MO-CVD method or MBE method. The thickness of each ultrathin film of GaAs and AlGaAs can be exemplified by 5 nm, for example. The number of repeated laminations of the ultrathin films of GaAs and AlGaAs can be exemplified by 20 times, for example. In this case, the total film thickness of the superlattice layer 114 is 200 nm. An example of the Al mixed crystal ratio x in the AlGaAs ultrathin film is 0.2.

  The upper buffer layer 116 includes, for example, a non-doped or intrinsic GaAs layer. The upper buffer layer 116 can be formed by an epitaxial growth method such as an MO-CVD method or an MBE method. An example of the film thickness of the upper buffer layer 116 is 200 nm.

  The intermediate layer 120 includes, for example, a non-doped or intrinsic AlGaAs layer. An example of the Al mixed crystal ratio is 0.2. The intermediate layer 120 can be formed by, for example, an epitaxial growth method such as an MO-CVD method or an MBE method. An example of the film thickness of the intermediate layer 120 is 30 nm.

  The carrier traveling layer 130 is formed on the intermediate layer 120. That is, the carrier traveling layer 130 is formed in the upper layer of the buffer layer 110. The carrier traveling layer 130 includes, for example, a non-doped or intrinsic InGaAs layer. An example of the In mixed crystal ratio is 0.22.

  The carrier traveling layer 130 generates a two-dimensional electron gas in the vicinity of the heterojunction interface with the high concentration carrier supply layer 140. The carrier traveling layer 130 can be formed by an epitaxial growth method such as an MO-CVD method or an MBE method. An example of the film thickness of the carrier traveling layer 130 is 14 nm.

  The high-concentration carrier supply layer 140 is formed on the carrier traveling layer 130 and forms a heterojunction with the carrier traveling layer 130. The high concentration carrier supply layer 140 is an example of a first carrier supply layer. The high concentration carrier supply layer 140 includes, for example, an n-type InGaP layer doped with an impurity serving as a donor. An example of the In mixed crystal ratio is 0.49. The high-concentration carrier supply layer 140 supplies electrons serving as carriers to the two-dimensional electron gas formed in the carrier traveling layer 130 near the heterointerface.

The high concentration carrier supply layer 140 can be formed by an epitaxial growth method such as an MO-CVD method or an MBE method. The carrier density of the high-concentration carrier supply layer 140 can be in the range of 0.5 × 10 ¹⁸ cm ⁻³ or more and less than 3 × 10 ¹⁸ cm ⁻³ , preferably 2 × 10 ¹⁸ cm ^−3. it can. The thickness of the high-concentration carrier supply layer 140 can be in the range of 15 nm or more and less than 35, and preferably 30 nm.

  The low concentration carrier supply layer 142 is formed on the high concentration carrier supply layer 140 and has a lower carrier density than the high concentration carrier supply layer 140. The low concentration carrier supply layer 142 is an example of a second carrier supply layer. The low concentration carrier supply layer 142 includes, for example, an n-type InGaP layer doped with an impurity serving as a donor. An example of the In mixed crystal ratio is 0.49.

  Since the low-concentration carrier supply layer 142 has a lower carrier density than the high-concentration carrier supply layer 140, a Schottky junction with the gate electrode 160 can be ensured. Further, the controllability by the electric field from the gate electrode 160 can be improved by increasing the width of the depletion layer formed by the Schottky junction.

The low concentration carrier supply layer 142 can be formed by an epitaxial growth method such as an MO-CVD method or an MBE method. The carrier density of the low-concentration carrier supply layer 142 can be in the range of 0.5 × 10 ¹⁷ cm ⁻³ or more and less than 5 × 10 ¹⁷ cm ⁻³ , preferably 1 × 10 ¹⁷ cm ^−3. it can. The thickness of the low-concentration carrier supply layer 142 can be in the range of 5 nm to less than 15 nm, and preferably 10 nm.

  The ohmic layer 150 is formed on the low-concentration carrier supply layer 142 and includes, for example, an n-type GaAs layer doped with an impurity serving as a donor. The ohmic layer 150 is doped with a donor impurity to ensure ohmic contact with the drain electrode 162 and the source electrode 164.

The ohmic layer 150 can be formed by an epitaxial growth method such as an MO-CVD method or an MBE method. A region where the gate electrode 160 is to be formed later can be formed by a patterning method using, for example, photolithography and dry etching techniques. An example of the carrier density of the ohmic layer 150 is 5 × 10 ¹⁸ cm ⁻³ . An example of the thickness of the ohmic layer 150 is 50 nm.

  The gate electrode 160 is formed on the low concentration carrier supply layer 142 and is made of a metal that forms a Schottky junction with the low concentration carrier supply layer 142. The gate electrode 160 generates an electric field by a voltage applied from the outside, and controls a depletion layer formed under the gate electrode 160. Accordingly, the conductivity between the source electrode 164 and the drain electrode 162 is controlled by controlling the density of the two-dimensional electron gas formed at the hetero interface of the carrier traveling layer 130.

  Examples of the material of the gate electrode 160 include Ti, Pt, Au, and a laminated film containing these materials. The gate electrode 160 can be formed by, for example, film deposition by a known vapor deposition method or sputtering method and a known patterning method.

  The drain electrode 162 and the source electrode 164 are formed of a metal that is formed on the ohmic layer 150 and forms an ohmic contact with the ohmic layer 150. Examples of the material of the drain electrode 162 and the source electrode 164 include an alloy of gold and germanium. The drain electrode 162 and the source electrode 164 can be formed by, for example, film deposition by a known vapor deposition method or sputtering method and a known patterning method.

  The protective layer 170 is formed so as to cover at least the formation region of the ohmic layer 150 and the gate electrode 160, and prevents oxidation of the material, intrusion of water vapor, and the like. An example of the material of the protective layer 170 is silicon nitride. The protective layer 170 can be formed by film deposition by a known CVD method or sputtering method and a known patterning method.

  According to the high electron mobility transistor 10 of the present embodiment, since the low concentration carrier supply layer 142 is provided in addition to the high concentration carrier supply layer 140 as the carrier supply layer, the thickness of the entire carrier supply layer is increased, The absolute value of the pinch-off voltage of the electron mobility transistor 10 can be increased. That is, even when a gate voltage having a large absolute value is applied, the linear region where the increase in the source-drain current is proportional to the increase in the absolute value of the gate voltage can be expanded without saturation of the source-drain current.

  Further, in the high electron mobility transistor 10 of the present embodiment, the factor for generating a leakage current to the substrate 100 increases in accordance with the increase in the absolute value of the gate voltage. However, since the buffer layer 110 includes the superlattice layer 114, leakage current to the substrate 100 can be suppressed.

  FIG. 2 shows a circuit for measuring the electrical characteristics of the high electron mobility transistor 10. A part of the various members formed on the substrate 100 is not shown. An AC drain voltage Vd is applied to the drain electrode 162 from the AC power source 202, and a negative gate voltage Vg is applied to the gate electrode 160 from the DC power source 204. The source electrode 164 is connected to the ground voltage GND through the load resistor 206. When no current flows through the load resistor 206, the source voltage Vs is 0 V. Therefore, the gate voltage Vg is equal to the source-gate voltage Vgs, and the drain voltage Vd is equal to the source-drain voltage Vds.

  When the amplitude of the drain voltage Vd is sufficiently small with respect to the control voltage (absolute value) of the gate voltage Vg, the extension (opening) of the depletion layer under the gate electrode 160 is dominated by the source-gate voltage Vgs. As a result, the resistance (impedance) Rds between the source and the drain is appropriately controlled by the gate voltage Vg. However, when the amplitude of the drain voltage Vd becomes about one half of the control voltage (absolute value) of the gate voltage Vg, the extension (opening) of the depletion layer under the gate electrode 160 is caused between the source and the gate. The drain-gate voltage Vgd is more dominant than the voltage Vgs. As a result, the resistance Rds between the source and the drain changes depending on the amplitude (Vd) of the input signal, and is observed as distortion of the current Is flowing through the load resistor 206 with respect to Vd as the input signal.

  Distortion can be evaluated at the third order input intercept point (IIP3). The third-order input intercept point is represented by an input level value at which the amplitude of the third-order harmonic that appears at the output level when the input level is increased exceeds the amplitude of the fundamental wave. Needless to say, the larger the value of IIP3, the smaller the distortion is evaluated.

  FIG. 3 shows changes in IIP3 when the pinch-off voltage Vth is changed by changing the thickness of the low-concentration carrier supply layer 142. A triangle mark shows an actual measurement point. Line 302 shows the experimental straight line calculated from the measurement points. It can be seen that IIP3 increases as the absolute value of the pinch-off voltage Vth increases (in the negative direction). That is, it can be seen that the distortion of the high electron mobility transistor 10 can be reduced by increasing the pinch-off voltage Vth in the negative direction by providing the low concentration carrier supply layer 142 and controlling the thickness thereof.

  FIG. 4 shows a current-voltage characteristic between the source and the gate. In FIG. 4, a current-voltage characteristic when the buffer layer 110 includes the superlattice layer 114 is indicated by a line 402. Further, a case where the buffer layer 110 is not provided with the superlattice layer 114 is indicated by a line 404 for comparison. It can be seen that the source-gate current Igs, that is, the gate leakage current, is suppressed lower in the line 402 than in the line 404 up to the source-gate voltage Vgs having a larger absolute value. That is, it can be seen that the line 402 including the superlattice layer 114 can reduce the gate leakage current.

  According to the high electron mobility transistor 10 of the present embodiment, by providing the low concentration carrier supply layer 142, distortion can be improved and an input signal having a large amplitude can be handled. In this case, a gate voltage having a large absolute value (large in the negative direction) is applied for the purpose of appropriately switching an input signal having a large amplitude. Gate leakage that may occur due to application of a gate voltage having a large absolute value can be suppressed by providing the buffer layer 110 with the superlattice layer 114.

  FIG. 5 shows an example of the electronic device 500. The electronic device 500 includes a transistor 520 and a transistor 522 that connect the input terminal IN and the output terminal OUT via the electronic circuit unit 510. Further, a transistor 524 and a transistor 526 that directly connect the input terminal IN and the output terminal OUT are provided. The transistor 520 and the transistor 522, and the transistor 524 and the transistor 526 are switched between connecting the input terminal IN and the output terminal OUT through the electronic circuit unit 510 or directly connecting them.

  The above-described high electron mobility transistor 10 can be used as the transistor 520, the transistor 522, the transistor 524, and the transistor 526. That is, the electronic device 500 can include the substrate 100, the input terminal IN and the output terminal OUT, the electronic circuit unit 510 formed on the substrate 100, and the high electron mobility transistor 10. The high electron mobility transistor 10 can switch whether or not the input terminal IN and the output terminal OUT are electrically connected via the electronic circuit unit 510. The high electron mobility transistor 10 can include a buffer layer 110, a carrier traveling layer 130, a high concentration carrier supply layer 140, and a low concentration carrier supply layer 142.

  Here, the buffer layer 110 may be formed on the substrate 100, and the carrier traveling layer 130 may be formed on the buffer layer 110. The high-concentration carrier supply layer 140 can form a heterojunction with the carrier traveling layer 130. The low concentration carrier supply layer 142 can be formed on the upper layer of the high concentration carrier supply layer 140 to have a carrier density lower than that of the high concentration carrier supply layer 140.

  The transistor 520 and the transistor 522, and the transistor 524 and the transistor 526 are turned on or off by the selection circuit 530. When transistor 520 and transistor 522 are on, transistor 524 and transistor 526 may be off and vice versa. Note that the selection circuit 530 may be included in the electronic device 500.

  When the high electron mobility transistor 10 of this embodiment is applied to the electronic device 500 described above, an input signal having a large amplitude is applied to the input terminal IN, and a test signal having a large amplitude is applied to the electronic circuit unit 510, for example. it can. For example, there may be an effect that the response signal of the electronic circuit unit 510 can be obtained from the output terminal OUT as a test result.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

  For example, in the above-described embodiment, the single electron junction high electron mobility transistor 10 is illustrated, but as illustrated in FIG. 6, the high concentration carrier supply layer 125 which is an example of the third carrier supply layer is replaced with an intermediate layer. The high electron mobility transistor 20 provided between the carrier 120 and the carrier traveling layer 130 may be used. The high concentration carrier supply layer 125 is formed on the upper layer of the buffer layer 110 and forms a heterojunction with the carrier traveling layer 130. In addition to the heterojunction between the high-concentration carrier supply layer 140 and the carrier transit layer 130, a heterojunction is also formed between the high-concentration carrier supply layer 125 and the carrier transit layer 130. It becomes a double heterojunction structure. By double heterojunction, carriers are supplied to the two hetero interfaces of the carrier traveling layer 130 from both the upper and lower directions to form two two-dimensional electron gases. Thereby, the sheet resistance at the hetero interface of the carrier traveling layer 130 can be reduced.

The high concentration carrier supply layer 125 includes, for example, an n-type AlGaAs layer doped with an impurity serving as a donor. An example of the Al mixed crystal ratio is 0.2. The high concentration carrier supply layer 125 can be formed by an epitaxial growth method such as an MO-CVD method or an MBE method. The carrier density of the high-concentration carrier supply layer 125 can be in the range of 0.5 × 10 ¹⁸ cm ⁻³ or more and less than 3 × 10 ¹⁸ cm ⁻³ , preferably 2 × 10 ¹⁸ cm ^−3. it can. The thickness of the high-concentration carrier supply layer 125 can be in the range of 2 nm to less than 20 nm, and preferably 10 nm.

The cross section of the high electron mobility transistor 10 of this embodiment is shown. 3 shows a circuit for measuring electrical characteristics of the high electron mobility transistor 10. A change in IIP3 when the pinch-off voltage Vth is changed by changing the thickness of the low-concentration carrier supply layer 142 is shown. The current-voltage characteristics between source and gate are shown. An example of the electronic device 500 is shown. 6 shows a cross section of a high electron mobility transistor 20, which may be a modification of the embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 High electron mobility transistor 20 High electron mobility transistor 100 Substrate 110 Buffer layer 112 Lower buffer layer 114 Superlattice layer 116 Upper buffer layer 120 Intermediate layer 125 High concentration carrier supply layer 130 Carrier traveling layer 140 High concentration carrier supply layer 142 Low Concentration carrier supply layer 150 Ohmic layer 160 Gate electrode 162 Drain electrode 164 Source electrode 170 Protective layer 202 AC power supply 204 DC power supply 206 Load resistance 500 Electronic device 510 Electronic circuit section 520 Transistor 522 Transistor 524 Transistor 526 Transistor 530 Selection circuit

Claims (7)

A substrate,
An upper buffer layer of the substrate;
An upper carrier running layer of the buffer layer;
A first carrier supply layer forming a heterojunction with the carrier traveling layer;
A second carrier supply layer formed above the first carrier supply layer and having a carrier density lower than that of the first carrier supply layer;
Equipped with a,
The carrier traveling layer is an intrinsic In _x Ga _1-x As layer,
The first carrier supply layer and the second carrier supply layer are n-type In _y Ga _1-y P layers,
The carrier density of the first carrier supply layer is in a range of 0.5 × 10 ¹⁸ cm ⁻³ or more and less than 3 × 10 ¹⁸ cm ⁻³ ,
The carrier density of the second carrier supply layer is in a range of 0.5 × 10 ¹⁷ cm ⁻³ or more and less than 5 × 10 ¹⁷ cm ⁻³ ,
The thickness of the first carrier supply layer is in the range of 15 nm or more and less than 35 nm,
The thickness of the second carrier supply layer, a high electron mobility transistor area by der to less than 15 nm 5 nm. The buffer layer has a superlattice layer of an intrinsic compound semiconductor,
The high electron mobility transistor according to claim 1. The superlattice layer is a GaAs / AlGaAs superlattice layer in which an intrinsic Al _z Ga _1-z As layer and an intrinsic GaAs layer are stacked repeatedly.
The high electron mobility transistor according to claim 2 . The buffer layer is a stacked structure layer formed by stacking an intrinsic GaAs layer and the GaAs / AlGaAs superlattice layer.
The high electron mobility transistor according to claim 3 . A third carrier supply layer which is formed in an upper layer of the buffer layer and forms a heterojunction with the carrier transit layer;
The high electron mobility transistor according to any one of claims 1 to 4 . The third carrier supply layer is an n-type AlGaAs layer, and the carrier density of the third carrier supply layer is in a range of 0.5 × 10 ¹⁸ cm ⁻³ or more and less than 3 × 10 ¹⁸ cm ⁻³ , The thickness of the third carrier supply layer is in the range of 2 nm or more and less than 20 nm.
The high electron mobility transistor according to claim 5 . A substrate,
Input and output ends,
An electronic circuit formed on the substrate;
A buffer layer on the substrate; a carrier travel layer on the buffer layer; a first carrier supply layer that forms a heterojunction with the carrier travel layer; and an upper layer on the first carrier supply layer. A second carrier supply layer having a carrier density lower than that of the first carrier supply layer;
The carrier traveling layer is an intrinsic In _x Ga _1-x As layer,
The first carrier supply layer and the second carrier supply layer are n-type In _y Ga _1-y P layers,
The carrier density of the first carrier supply layer is in a range of 0.5 × 10 ¹⁸ cm ⁻³ or more and less than 3 × 10 ¹⁸ cm ⁻³ ,
The carrier density of the second carrier supply layer is in a range of 0.5 × 10 ¹⁷ cm ⁻³ or more and less than 5 × 10 ¹⁷ cm ⁻³ ,
The thickness of the first carrier supply layer is in the range of 15 nm or more and less than 35 nm,
The thickness of the second carrier supply layer is in the range of 5 nm or more and less than 15 nm,
A high electron mobility transistor for switching whether or not the input end and the output end are electrically connected via the electronic circuit unit; and
An electronic device comprising:

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