JP5287463B2 - Group III nitride substrate with epitaxial layer and semiconductor device using the same - Google Patents

Description

  The present invention relates to a group III nitride substrate with an epitaxial layer and a semiconductor device using the same.

  As the semiconductor substrate, those described in Patent Documents 1 to 5 below are known. Patent Document 1 discloses a semiconductor substrate that has been surface-treated so as to obtain desired electrical characteristics. Specifically, Patent Document 1 discloses a p-type compound semiconductor substrate having p-type impurity atoms on its surface, an n-type compound semiconductor substrate having n-type impurity atoms on its surface, and Fe atoms or C atoms on its surface. A semi-insulating compound semiconductor substrate and a first conductivity type compound semiconductor substrate having a second conductivity type impurity on its surface are disclosed.

Patent Document 2 discloses that the contamination metal substance on the GaN substrate is 10 × 10 ¹⁰ atoms / cm ² or less. Further, in Patent Document 3, in order to form good epitaxial growth on a group III nitride substrate, Si atoms are 3 × 10 ¹³ atoms / cm ^{2 on} the surface of the substrate, and the number of acidic substance atoms is 3 ×. It is disclosed to be 10 ¹⁴ atoms / cm ² . Further, in Patent Document 4, Al _x Ga _y In _z N (0 <y ≦ 1, x + y + z = 1) is set to have a surface roughness of RMS 0.15 nm by CMP in order to obtain a substrate free from defects and contamination. It is disclosed. In this CMP, Al ₂ O ₃ or SiO ₂ is used as abrasive grains, and it is disclosed that pH adjustment is performed by adding an oxidizing agent to a polishing liquid. Patent Document 5 discloses that Si gas and Si pieces are used for dry etching of a gallium nitride compound semiconductor.

JP 2006-344911 A International Publication No. 2005/041283 Pamphlet International Publication No. 2008/047627 Pamphlet US Pat. No. 6,488,767 Japanese Patent No. 2599250

  By the way, when the surface of the nitride substrate is oxidized, the quality of the epitaxial growth layer formed on the surface of the substrate is degraded. As a result, the characteristics of the device using the substrate are deteriorated. In addition, since the epitaxial growth layer grows while being lattice-matched to the substrate surface, the crystal quality of the substrate surface is required to be high. Therefore, a nitride substrate having a stable surface is desired.

  An object of the present invention is to provide a group III nitride substrate having a stable surface. Another object of the present invention is to provide a semiconductor device including such a group III nitride substrate. Furthermore, an object of the present invention is to provide a method for producing such a group III nitride substrate, that is, a surface-treated group III nitride substrate.

The group III nitride substrate of the present invention has a surface layer. This surface layer is 3 at. % To 25 at. % Of containing carbon, and includes a p-type metal element 5 × ^{10 10} atoms ^/ cm 2 ^~200 × ^{10 10} atoms / cm ^2. This surface layer is 3 at. % To 25 at. % Of carbon is measured by Auger Electron Spectroscopy (AES), and a p-type metal element of 5 × 10 ¹⁰ atoms / cm ² to 200 × 10 ¹⁰ atoms / cm ² can be measured by total reflection X-ray fluorescence analysis. It is a layer having. This group III nitride substrate has a stable surface. The surface layer preferably further contains an insulating metal element of 1 × 10 ¹⁰ atoms / cm ^{2 to} 100 × 10 ¹⁰ atoms / cm ² .

  The semiconductor device of the present invention includes a group III nitride substrate having such a surface layer, and at least one or more epitaxial growth layers formed on the surface layer of the substrate. Since such a semiconductor device has a stable group III nitride substrate surface, it has good device characteristics and can be manufactured stably.

The compound semiconductor substrate of the present invention is a group III nitride substrate with an epitaxial layer. This compound semiconductor substrate includes a group III nitride substrate and an epitaxial layer, and the number of C atoms per 1 cm ^{3 at} the interface between the group III nitride substrate and the epitaxial layer is 2 × 10 ¹⁶ or more and 5 × 10 5. and at ¹⁷ or less, the number of atoms in the p-type metal element per 1 cm ³ is 1 × ^{10 17} or less 2 × ^{10 16} or more. The number of C atoms per cm ^{3 at the} interface is more preferably 5 × 10 ¹⁶ or more and 2 × 10 ¹⁷ or less.

In the compound semiconductor substrate of the present invention, the number of O atoms per 1 cm ^{3 at} the interface between the group III nitride substrate and the epitaxial layer is preferably 2 × 10 ¹⁶ or more and 1 × 10 ¹⁸ or less. × and more preferably ^{10 16} or more 5 × ^{10 17} or less.

In the compound semiconductor substrate of the present invention, the number of Si atoms per cm ^{3 at} the interface between the group III nitride substrate and the epitaxial layer is preferably 1 × 10 ¹⁵ or more and 1 × 10 ¹⁹ or less. It is more preferable that the number is from 10 × ¹⁵ to 5 × 10 ¹⁸ .

In another aspect, the present invention includes (a) a step of dry etching the surface of the substrate, and (b) a step of bonding a p-type metal element to the surface of the substrate. In the dry etching step, the surface of the group III nitride substrate is dry etched using a mixed gas in the chamber. The mixed gas is a mixed gas of a first gas containing carbon and a second gas containing chlorine. In the dry etching step, the pressure P (Pa) in the chamber, the flow rate Q (sccm) of the mixed gas, and the chamber volume V (l: liter) satisfy 0.05 ≦ PV / Q ≦ 3.0, The flow rate ratio of the first gas and the second gas is set so as to satisfy 1: 9 to 9: 1. The step of bonding the p-type metal element is a polishing apparatus that is a solution containing an oxide of the p-type metal element and that supplies the solution having a viscosity of 2 (mPa · s) to 30 (mPa · s) as a slurry. It is done using. According to this manufacturing method, 3 at. % To 25 at. It is possible to suitably manufacture a group III nitride substrate having a surface layer containing a p-type metal element containing 5% carbon 10 and 5 × 10 ¹⁰ atoms / cm ² to 200 × 10 ¹⁰ atoms / cm ^2. is there.

  As described above, according to the present invention, a group III nitride substrate having a stable surface is provided, and a semiconductor device including such a group III nitride substrate is provided. Furthermore, according to the present invention, a method for suitably producing such a group III nitride substrate is provided.

It is sectional drawing which shows the group III nitride board | substrate which concerns on one Embodiment of this invention. It is a figure which shows an example of a semiconductor device provided with the group III nitride board | substrate which concerns on one Embodiment of this invention. It is a figure which shows another example of a semiconductor device provided with the group III nitride board | substrate which concerns on one Embodiment of this invention. 3 is a flowchart of a method for manufacturing a surface-treated group III nitride substrate according to an embodiment of the present invention. It is a figure which shows the apparatus which can be used for a dry etching process. It is a figure which shows the apparatus which can be used for a polishing process.

  DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals.

  FIG. 1 is a cross-sectional view of a group III nitride substrate according to an embodiment of the present invention. In the following, a GaN substrate will be described as an example of the group III nitride substrate, but the group III nitride substrate of the present invention is not limited to a GaN substrate.

A GaN substrate 10 shown in FIG. 1 includes a surface layer 10a. This surface layer 10a is formed by 3at. % To 25 at. % Of containing carbon, and includes a p-type metal element 5 × ^{10 10} atoms ^/ cm 2 ^~200 × ^{10 10} atoms / cm ^2.

  The surface layer 10a is 3at. % Of carbon can be maintained, and 25 at. By containing carbon of not more than%, the resistance can be maintained, and the epitaxial growth layer formed on the surface layer 10a can be of high quality.

Examples of the p-type metal element include Cu and Zn. The surface layer 10a may contain one or both of Cu and Zn. The surface layer 10a can maintain its resistance by containing a p-type metal element of 5 × 10 ¹⁰ atoms / cm ² or more, and also has a p-type metal element of 200 × 10 ¹⁰ atoms / cm ² or less. As a result, the resistance can be maintained, and the epitaxial growth layer formed on the surface layer 10a can be of high quality.

The surface layer 10a may further contain an insulating metal element of 1 × 10 ¹⁰ atoms / cm ^{2 to} 100 × 10 ¹⁰ atoms / cm ² . Examples of the insulating metal element include Fe and Ni. The surface layer 10a may contain one or both of Fe and Ni. Thus, the surface layer 10a becomes a more stable surface by including an insulating metal element.

A low resistance layer is formed on the group III nitride substrate due to surface oxidation or adhesion of Si from the atmosphere. The inventor of the present application has found that the amount of oxygen and Si on the surface of the group III nitride substrate needs to be small so that the low resistance layer is not formed. The oxygen concentration of the surface layer is 3 at. % To 15 at. %, Preferably 5 at. % To 10 at. % Is more preferable. The Si concentration in the surface layer is preferably 500 × 10 ¹⁰ atoms / cm ^{2 to} 8000 × 10 ¹⁰ atoms / cm ² , and preferably 1000 × 10 ¹⁰ atoms / cm ^{2 to} 5000 × 10 ¹⁰ atoms / cm. It is more preferable. The surface layer having such oxygen concentration and Si concentration is realized by the surface layer 10a in the present embodiment.

  The surface roughness of the surface layer 10a of the GaN substrate 10 needs to be 3 nm or less on the RMS basis, preferably 1 nm or less, and more preferably 0.1 nm to 0.5 nm. The surface roughness is measured using an AFM with a range of 10 μm square as a reference area. By setting the surface roughness to 3 nm or less, an epitaxial layer having good morphology and crystallinity can be formed on the GaN substrate. In addition, the thickness of the work-affected layer on the surface of the GaN substrate 10 needs to be 50 nm or less, preferably 20 nm or less, and more preferably 1 nm to 10 nm. The work-affected layer is a layer having a disordered crystal lattice formed in the surface region of the crystal by grinding or polishing the crystal surface. The work-affected layer is observed by TEM observation of a cross section obtained by breaking the crystal at the cleavage plane. By comparing the surface area affected by processing with the internal area not affected by processing, the presence and thickness of the work-affected layer is measured. By setting the thickness of the work-affected layer to 50 nm or less, an epitaxial layer having good morphology and crystallinity can be formed on the GaN substrate.

  Hereinafter, semiconductor devices according to embodiments of the present invention will be described. FIG. 2 is a diagram illustrating an example of a semiconductor device including a group III nitride substrate according to an embodiment of the present invention. The HEMT device 1 shown in FIG. 2 includes the above-described GaN substrate 10 and one or more epitaxial layers formed on the surface layer 10a of the GaN substrate 10. That is, the HEMT device 1 includes a compound semiconductor substrate including a GaN substrate 10 and an epitaxial layer.

  Specifically, the HEMT device 1 includes a GaN substrate 10, a GaN layer 12, an AlGaN layer 14, a gate electrode 16, a source electrode 18, and a drain electrode 20.

  In the HEMT device 1, the GaN substrate 10 is an insulating GaN substrate. The GaN layer 12 and the AlGaN layer 14 are sequentially formed on the surface layer 10a. Both the GaN layer 12 and the AlGaN layer 14 are undoped. The gate electrode 16, the source electrode 18, and the drain electrode 20 are formed on the AlGaN layer 14. The gate electrode 16 is provided between the source electrode 18 and the drain electrode 20.

  The HEMT device 1 has a small leakage current because the surface layer 10a can maintain a high resistance. Moreover, since this HEMT device 1 is manufactured using the GaN substrate 10 having the stable surface layer 10a, it can be manufactured stably.

  FIG. 3 is a diagram illustrating another example of a semiconductor device including a group III nitride substrate according to an embodiment of the present invention. The LED 2 shown in FIG. 3 includes the GaN substrate 10 described above and one or more epitaxial layers formed on the surface layer 10 a of the GaN substrate 10.

  Specifically, the LED 2 includes a GaN substrate 10, a buffer layer 22, a first cladding layer 24, an active layer 26, a second cladding layer 28, a contact layer 30, a first electrode 32, and a second electrode. 34 is provided.

  In the LED 2, the GaN substrate 10 is an n-type GaN substrate. The buffer layer 22 is an n-type GaN layer and is formed on the surface layer 10a. The buffer layer 22 can contain Si as a dopant. The first cladding layer 24 is an n-type AlGaN layer and is formed on the buffer layer 22. The first cladding layer 24 can contain Si as a dopant.

  The active layer 26 is formed on the first cladding layer 24. As the active layer 26, for example, an active layer having a multiple quantum well structure obtained by alternately forming GaN barrier layers and GaInN well layers can be used.

  The second cladding layer 28 is formed on the active layer 26. The second cladding layer 28 is a p-type AlGaN layer and can contain Mg as a dopant. The contact layer 30 is formed on the second cladding layer 28. The contact layer 30 is a p-type GaN layer and can contain Mg as a dopant.

  In the LED 2, the first electrode 32 is formed on the surface of the GaN substrate 10 opposite to the surface layer 10 a. A second electrode 34 is formed on the contact layer 30.

  Since such an LED 2 uses the GaN substrate 10 having the surface layer 10a described above, the light output is large and can be manufactured stably.

  Hereinafter, a method for manufacturing a group III nitride substrate according to an embodiment of the present invention will be described. FIG. 4 is a flowchart of a method for manufacturing a surface-treated group III nitride substrate according to an embodiment of the present invention. The manufacturing method shown in FIG. 4 is a manufacturing method capable of suitably obtaining the surface layer 10a described above.

In the case of a GaN crystal, the crystal serving as the base of the group III nitride substrate subjected to the surface treatment shown in FIG. 4 can be grown by the HVPE method, the flux method, or the ammonothermal method. In the case of AlN crystal, it can be grown by HVPE method or sublimation method. Peripheral processing is performed on the grown crystal to obtain an ingot of nitride crystal. The ingot is sliced to obtain a group III nitride substrate. Slicing can be performed with a wire saw or a blade saw. Machining such as grinding and lapping is performed to flatten the substrate. Examples of hard abrasive grains used for lapping include diamond, SiC, BN, Al ₂ O ₃ , and Cr ₂ O ₃ . These are selected from mechanical action, and abrasive grains having high hardness and large particle diameter are used for improving the rate. In order to smooth the surface roughness and reduce the work-affected layer, abrasive grains having a low hardness and a small particle diameter are used. In order to shorten the polishing time and obtain a smooth surface, multi-stage polishing is performed from large abrasive grains to small abrasive grains. Surface finishing treatment is performed to reduce roughness and remove the work-affected layer. As the surface finish, chemical mechanical polishing (CMP) can be performed after mechanical polishing. The work-affected layer can also be removed by dry etching.

  Hereinafter, FIG. 4 will be referred to again. The manufacturing method shown in FIG. 4 includes a dry etching step S1 and a polishing step S2. In the dry etching step S1, the surface of the group III nitride substrate is dry etched. For this dry etching step S1, for example, a dry etching apparatus shown in FIG. 5 can be used. The dry etching apparatus shown in FIG. 5 is an RIE (reactive ion etching) apparatus, but the dry etching that can be used in the dry etching process of the present invention is not limited to RIE, and inductively coupled plasma is used. RIE (ICP-RIE), ECR (electron cyclotron resonance) -RIE, CAIBE (chemically assisted ion beam etching), RIBE (reactive ion beam etching), or the like may be used.

  The dry etching apparatus 50 includes a chamber 52. In the chamber 52, an upper electrode 54, a lower electrode 56, and a substrate support 58 are provided. The chamber 52 is provided with a gas supply port 60 connected to a gas source, and a gas exhaust port 62 connected to a vacuum pump.

  In the dry etching apparatus 50, the group III nitride substrate 10 is mounted on the substrate support 58, gas is supplied from the gas supply port 60, and high frequency power is supplied from the high frequency power supply 64 to the lower electrode 56, thereby Plasma can be generated inside. Thereby, the dry etching apparatus 50 can dry-etch the surface of the group III nitride substrate 10.

In this manufacturing method, in the dry etching step S1, a gas mixture containing a first gas containing carbon (carbon-based gas) and a second gas containing chlorine (chlorine-based gas) is supplied into the chamber 52. Examples of the carbon-based gas include methane, ethane, propane, acetylene, and the like. Examples of the chlorine-based gas include chlorine, BCl ₃ , SiCl _{4 and the} like.

In the dry etching step S1, the pressure P (Pa) in the chamber, the flow rate Q (sccm) of the mixed gas, and the chamber volume V (l: liter) are
0.05 ≦ PV / Q ≦ 3.0 (1)
Is done to meet. By satisfying the condition of the formula (1), it is possible to suitably obtain the carbon concentration of the surface layer 10a described above. Here, 1 sccm is 1.667 × 10 ⁻⁸ m ³ / s.

In order to obtain the flat surface layer 10 a in the dry etching step S <b> 1, it is effective to allow Si-based gas or Si pieces to exist in the chamber 52. However, when the ratio of Si is large, there arises a problem that the amount of Si adhering to the substrate surface after dry etching increases. Therefore, the Si element of _{SiC, Si3 N4,} Si or the like _{6-z Al z O z N} 8-z, C, a compound containing at least one element of the group consisting of N, in the dry etching step S1, the chamber 52 Can be present. Such a compound can be present in the chamber 52 by making the substrate support 58 made of the compound or by placing the compound on the substrate support 58 and in the vicinity of the substrate 10. . Thereby, the flat surface layer 10a can be obtained, and adhesion of Si to the surface layer 10a can be suppressed.

  Next, in this manufacturing method, a polishing step S2 is performed. Polishing process S2 can be performed using the polishing apparatus 70 shown in FIG. 6, for example. The polishing apparatus 70 includes a surface plate 72, a polishing pad 74, a crystal holder 76, a weight 78, and a slurry liquid supply port 80.

  The polishing pad 74 is mounted on the surface plate 72. The surface plate 72 and the polishing pad 74 are rotatable about the center axis X1 of the surface plate 72. The crystal holder 76 is a component for supporting the substrate 10 on its lower surface. A load is applied to the substrate 10 by a weight 78. The crystal holder 76 is substantially parallel to the axis line X1 and has a center axis line X2 at a position displaced from the axis line X1, and is rotatable about the center axis line X2. The slurry liquid supply port 80 supplies the slurry S onto the polishing pad 74.

  According to this polishing apparatus 70, the surface plate 72 and the polishing pad 74 are rotated, the crystal holder 76 is rotated, the slurry S is supplied onto the polishing pad 74, and the surface layer 10 a of the substrate 10 is brought into contact with the polishing pad 74. As a result, the surface layer 10a of the substrate 10 can be polished.

  In this manufacturing method, a solution containing an oxide of a p-type metal element is supplied as a slurry S in the polishing step S2. As the oxide of the p-type metal element, for example, one or both of CuO and ZnO can be used. Moreover, the viscosity of this solution is 2 (mPa · s) to 30 (mPa · s). The viscosity of the solution can be adjusted by adding a highly viscous organic compound such as ethylene glycol or an inorganic compound such as boehmite.

According to this polishing step S2, the p-type metal element can be bonded to the surface layer 10a of the substrate 10 by the mechanochemical effect of the oxide. Moreover, the concentration of the p-type metal element in the surface layer 10a of the substrate 10 is controlled in the range of 5 × 10 ¹⁰ atoms / cm ² to 200 × 10 ¹⁰ atoms / cm ² by using the solution having the above-described viscosity. Can do.

  In order to promote the mechanochemical effect of the metal oxide, it is preferable to use a nonpolar solvent as the solvent of the solution. Examples of the nonpolar solvent include hydrocarbon, carbon tetrachloride, diethyl ether and the like. By using a non-polar solvent, the solid contact between the metal oxide and the substrate can be promoted to promote the reaction, and the metal composition on the substrate surface can be controlled efficiently.

  Hereinafter, a group III nitride substrate manufactured using the method for manufacturing a group III nitride substrate according to the present invention, and a semiconductor device created based on the group III nitride substrate according to the present invention will be described as examples. The present invention will be described in more detail, but the present invention is not limited to the following examples.

<Manufacture of GaN substrate>
A GaN substrate was manufactured by the manufacturing method of the above embodiment. First, an insulating GaN substrate (dopant: Fe) grown by the HVPE method was sliced along a plane parallel to the (0001) plane to obtain a GaN substrate having a diameter of 50 mm and a thickness of 0.5 mm.

  The c-plane ((000-1) plane) on the N atom plane side of this GaN substrate (nitride crystal) was affixed to a ceramic crystal holder with wax. A surface plate with a diameter of 380 mm is installed in the lapping machine, and the surface plate is rotated around the center axis while supplying the slurry in which diamond abrasive grains are dispersed from the slurry supply port to the center plate, and a weight is placed on the crystal holder. The surface of the GaN crystal (the c-plane on the Ga atom plane side, the (0001) plane) was lapped by rotating the GaN substrate about the central axis of the crystal holder while placing and pressing the GaN substrate against the surface plate.

Here, a copper surface plate and a tin surface plate were used as the surface plate. Also, three types of diamond abrasive grains having an abrasive grain size of 9 μm, 3 μm, and 2 μm were prepared, and the abrasive grain size was gradually reduced as lapping progressed. Polishing pressure was ^{100g / cm 2 ~500g / cm 2} , the rotational speed of the GaN substrate and the surface plate were both platen and crystal holder 30 times / Min～60 times / min. By such lapping, the surface of the GaN crystal substrate became a mirror surface.

Next, the GaN substrate after lapping was subjected to chemical mechanical polishing (CMP). Specifically, a polishing pad was installed on a surface plate having a diameter of 380 mm installed in the polishing apparatus. Further, the polishing pad was rotated about the center axis while supplying the slurry in which the abrasive grains were dispersed from the slurry liquid supply port to the polishing pad. At the same time, the GaN substrate was rotated around the center axis of the crystal holder while pressing the GaN substrate against the polishing pad by placing a weight on the crystal holder. Thus, chemical mechanical polishing (CMP) was performed on the surface of the GaN substrate (the c plane on the Ga atom plane side, the (0001) plane). In the slurry, Al ₂ O ₃ particles having a particle diameter of 2 μm are dispersed in water as abrasive grains to make the Al ₂ O ₃ content 5 mass%, HNO ₃ is added as a pH adjuster, and the pH is adjusted to 2-4. It was prepared by adjusting. A polyurethane suede pad was used as the polishing pad, and a stainless steel surface plate was used as the surface plate. Policing pressure was ^{50g / cm 2 ~600g / cm 2} , and any rotational speed of the GaN substrate and polishing pad is a 30 times / Min～70 times / min.

  Next, dry etching was performed on the GaN substrate after CMP using an ICP-RIE apparatus using a carbon-containing gas and a chlorine-containing gas in accordance with the dry etching step S1 described above. As the etching gas, a mixed gas of methane (carbon-based gas) and chlorine (chlorine-based gas) was used. Table 1 shows the chamber volume V, the pressure P in the chamber, the flow rate Q, PV / Q of the mixed gas, the flow rate ratio of the carbon-based gas and the chlorine-based gas, the bias power, the antenna power, and the material of the substrate support. It was as Example 1-10. For reference, as shown in Table 1, these parameters were set as in Comparative Examples 1 and 2.

The carbon concentration on the surface of the GaN substrate obtained by the above steps was quantified by Auger electron spectroscopy (AES). The carbon concentrations of the GaN substrates of the examples and the comparative examples are as shown in Table 1. In Examples 1 to 10, that is, when PV / Q is 0.05 or more and 3.0 or less, the carbon concentration in the surface layer of the GaN substrate is 3 at. % To 25 at. %. On the other hand, when PV / Q is less than 0.05 (Comparative Example 1), the carbon concentration in the surface layer of the GaN substrate is 3 at. %, And when PV / Q is greater than 3 (Comparative Example 2), the carbon concentration in the surface layer of the GaN substrate is 25 at. It became larger than%. Note that the carbon concentration of the surface layer was not affected by the etching time normally applied in the surface treatment. Further, even when the bias power was 50 W to 200 W and the antenna power was 100 to 400 W, the carbon concentration of the surface layer was not affected in the range of these powers.

  Next, the surface layer of the GaN substrate after dry etching was polished with a solution containing an oxide of a p-type metal element using a polishing apparatus equivalent to the above-described CMP, that is, a polishing apparatus shown in FIG. Specifically, the surface layer of the GaN substrate after dry etching was polished with the parameters of Examples 11 to 21 in Table 2. That is, using the solutions containing the metal oxides and solvents of Examples 11 to 21 in Table 2 and having the viscosities of Examples 11 to 21 in Table 2, pressure on the GaN substrates of Examples 11 to 21 in Table 2 In addition, the GaN substrate was polished at the rotational speeds of the surface plates and crystal holders of Examples 11 to 21 in Table 2. For reference, Comparative Examples 3 to 4 in Table 2 were prepared using solutions containing the metal oxides and solvents in Comparative Examples 3 to 4 in Table 2 and having the viscosities in Comparative Examples 3 to 4 in Table 2. Polishing of the GaN substrate was performed at the pressure of the GaN substrate and at the rotation speed of the surface plate and the crystal holder of Comparative Examples 3 to 4 in Table 2. A non-woven pad (compression rate: 3.0%) was used as the polishing pad, and an aluminum surface plate subjected to surface treatment was used as the surface plate.

The concentration of the p-type metal element on the surface of the GaN substrate obtained by the above steps was quantified by total reflection fluorescent X-ray analysis. The Cu concentration and Zn concentration of each example and comparative example were as shown in Table 2. As is apparent from the sum of the Cu concentration and the Zn concentration in Table 2, Examples 11 to 21, that is, containing an oxide of a p-type metal element, and 2 (mPa · s) to 30 (mPa · s). The concentration of the p-type metal element in the surface layer of the GaN substrate can be changed from 5 × 10 ¹⁰ atoms / cm ² to 5 × 10 ¹⁰ atoms / cm ² regardless of the pressure during polishing and the rotation speed of the surface plate and the crystal holder. It was possible to control in the range of 200 × 10 ¹⁰ atoms / cm ² . On the other hand, when the viscosity of the solution is less than 2 (mPa · s) (Comparative Example 3), the concentration of the p-type metal element is greater than 200 × 10 ¹⁰ atoms / cm ^{2 and} the viscosity of the solution is 30 (mPa · s). In the case of larger than s) (Comparative Example 4), the concentration of the p-type metal element was less than 5 × 10 ¹⁰ atoms / cm ² . In addition, when the grain size of the abrasive grains in the polishing solution is large, the surface roughness tends to increase and the thickness of the work-affected layer tends to increase. When the grain diameter of the abrasive grains is small, the effect of surface modification is small. Therefore, the particle size of the abrasive grains is preferably 50 nm to 2000 nm, and more preferably 200 nm to 1000 nm. In such a range of the abrasive grain size, there was no effect on the concentration of the p-type metal element on the surface of the GaN substrate. Also, if the concentration of abrasive grains in the solution is high, the surface roughness increases, the thickness of the work-affected layer increases, and if the concentration of abrasive grains is low, the effect of surface modification is small. 1 wt. % To 10 wt. %, Preferably 2 wt. % To 5 wt. % Was more preferred. In such a range of the abrasive grain concentration, there was no effect on the concentration of the p-type metal element on the surface of the GaN substrate. In addition, if the compression rate of the polishing pad is small, the surface roughness tends to increase and the thickness of the work-affected layer tends to increase. If the compression rate is large, the effect of surface modification is small, so the polishing pad is compressed. The rate is preferably 1% to 20%, more preferably 3% to 15%. In such a range of the compressibility of the polishing pad, there was no influence on the concentration of the p-type metal element on the surface of the GaN substrate. Further, in the polishing time of 3 to 30 minutes that is usually applied in the surface treatment, there was no effect on the concentration of the p-type metal element on the surface of the GaN substrate.

<Evaluation of HEMT device>
The HEMT device of the above-described embodiment was created using the GaN substrate of the above-described embodiment. 200 HEMT devices were prepared for each example. Specifically, first, for the HEMT devices of Examples 22 to 28, an insulating GaN substrate (specific resistance 1 × 10 ⁷ Ωcm), which is the carbon shown in the column of Examples 22 to 28 in Table 3. Those having a concentration and a surface layer of p-type metal elements (Cu and Zn) were prepared for each example.

  Then, these GaN substrates were placed in a reactor of an OMVPE apparatus, and a gas containing hydrogen, nitrogen, and ammonia was supplied into the reactor, and a heat treatment was performed for 20 minutes with the temperature of the GaN substrate being 1100 ° C.

  Next, the temperature of the GaN substrate was raised to 1130 ° C., ammonia and trimethylgallium (TMG) were supplied to the reactor, and a GaN layer having a thickness of 1.5 μm was grown on the GaN substrate. Next, trimethylaluminum (TMA), TMG, and ammonia were supplied to the reactor, and an AlGaN layer having a thickness of 30 nm and an Al composition of 20% was grown on the GaN layer.

  Next, a source electrode and a drain electrode were formed on the AlGaN layer by photolithography, EB deposition, and lift-off. Ti / Al / Ti / Au (20/100/20/300 nm) was used for these electrodes. After lift-off, an alloying heat treatment was performed at 600 ° C. for 1 minute. Next, a gate electrode was manufactured through a process similar to that of the source electrode and the drain electrode. Ni / Au (50/500 nm) was used for the gate electrode. The gate length was 2 μm.

  For reference, a GaN substrate having a surface layer having a carbon concentration and a p-type metal element concentration shown in the columns of Comparative Examples 5 to 10 in Table 3 is prepared for the HEMT devices of Comparative Examples 5 to 10, and the same. A HEMT device was prepared. 200 HEMT devices were prepared for each comparative example.

The gate leakage current of the HEMT device obtained as described above was examined. Here, a condition was adopted in which a HEMT device having a gate current density of 1 × 10 ⁻⁶ A / cm ² when having a gate voltage of 5 V was determined to have good device characteristics. For each example and comparative example, the yield of the HEMT device that satisfies the condition was as shown in Table 3. Examples 22-28, ie, 3 at. % To 25 at. The yield of a HEMT device using a GaN substrate having a surface layer containing a p-type metal element containing 5% 10 ¹⁰ atoms / cm ² to 200 × 10 ¹⁰ atoms / cm ² is 65%. That was all. On the other hand, the yield of the HEMT devices of Comparative Examples 5 to 10 was significantly lower than 65%. The surface roughness RMS of the substrate was 1.5 nm in both the examples and the comparative examples, and the work-affected layer was 30 nm in both the examples and the comparative examples.

Composition of the interface between the group III nitride substrate and the epitaxial growth layer in the HEMT devices of the above-described Example 22, Example 24, Example 26, Comparative Example 5 and Comparative Example 10, that is, the Group III nitride in the compound semiconductor substrate The result of investigating the composition of the interface between the substrate and the epitaxial growth layer by SIMS analysis was as follows.
In Example 22, the number of C atoms per 1 cm ³ is 2 × 10 ^{16, the} number of p-type metal element atoms per 1 cm ³ is 2 × 10 ¹⁶ , and the number of O atoms per 1 cm ³ is 1 ×. 10 ^{18 and the} number of Si atoms were 1 × 10 ¹⁹ .
In Example 24, the number of C atoms per 1 cm ³ is 1 × 10 ^{17, the} number of p-type metal element atoms per 1 cm ³ is 5 × 10 ¹⁶ , and the number of O atoms per 1 cm ³ is 1 ×. The number of Si atoms per 10 ¹⁷ and 1 cm ³ was 5 × 10 ¹⁷ .
In Example 26, the number of C atoms per 1 cm ³ is 5 × 10 ^{17, the} number of p-type metal element atoms per 1 cm ³ is 1 × 10 ¹⁷ , and the number of O atoms per 1 cm ³ is 2 ×. The number of Si atoms per 10 ¹⁶ and 1 cm ³ was 2 × 10 ¹⁷ .
In Comparative Example 5, the number of C atoms per 1 cm ³ is 2 × 10 ^{15, the} number of p-type metal element atoms per 1 cm ³ is 2 × 10 ¹⁶ , and the number of O atoms per 1 cm ³ is 1 ×. The number of Si atoms per 10 ¹⁹ and 1 cm ³ was 1 × 10 ²⁰ .
In Comparative Example 10, the number of C atoms per 1 cm ³ is 5 × 10 ^{18, the} number of p-type metal element atoms per 1 cm ³ is 1 × 10 ¹⁸ , and the number of O atoms per 1 cm ³ is 1 ×. The number of Si atoms per 10 ¹⁶ and 1 cm ³ was 2 × 10 ¹⁷ .
Thus, in Examples 22, 24, and 26 in which the composition of the interface in the compound semiconductor substrate was good, a good yield of the HEMT device was obtained. On the other hand, in the case of the composition of the interface in the compound semiconductor substrate as in Comparative Examples 5 and 10, the yield of the HEMT device was lowered.

Next, for the HEMT devices of Examples 29 to 36, an insulating GaN substrate (specific resistance 1 × 10 ⁷ Ωcm), the carbon concentration and p-type metal shown in the columns of Examples 29 to 36 in Table 4 were used. A material having a surface layer having an element (Cu) concentration and an insulating metal element (Fe) concentration was prepared. And the HEMT device similar to Examples 22-28 was created using these GaN substrates. 200 HEMT devices were prepared for each example. For reference, for the HEMT devices of Comparative Examples 11 to 15, an insulating GaN substrate (specific resistance 1 × 10 ⁷ Ωcm), which is the carbon shown in the columns of Comparative Examples 11 to 15 in Table 4. A device having a surface layer having a concentration, a p-type metal element (Cu) concentration, and an insulating metal element (Fe) concentration was prepared, and a HEMT device was similarly prepared. 200 HEMT devices were prepared for each comparative example. And about the HEMT device of Examples 29-36 and Comparative Examples 11-15, the yield was calculated | required on the same conditions as Examples 22-28 and Comparative Examples 5-10 mentioned above. As shown in Table 4, the yield of the HEMT device was further improved by including an insulating metal element of 1 × 10 ¹⁰ atoms / cm ^{2 to} 100 × 10 ¹⁰ atoms / cm ² in the surface layer of the GaN substrate. The surface roughness RMS of the substrate was 2.2 nm in both the examples and the comparative examples, and the work-affected layer was 40 nm in both the examples and the comparative examples.

<Evaluation of LED>
Using the GaN substrate of the embodiment described above, the LED of the embodiment described above was created. 200 LEDs were prepared for each example. Specifically, n-type GaN substrates having a specific resistance of 1 × 10 ⁻² Ωcm and a carrier density of 3 × 10 ¹⁸ / cm ² were prepared for the LEDs of Examples 37 to 43. As an n-type GaN substrate, a substrate having a surface layer having a carbon concentration and a p-type metal element (Cu and Zn) concentration shown in the columns of Examples 37 to 43 in Table 5 was prepared for each example.

These n-type GaN substrates are arranged in an MOCVD apparatus, and an n-type GaN layer (dopant: Si) having a thickness of 1 μm is formed on one main surface ((0001) surface) side of the n-type GaN substrate by MOCVD. 150 nm thick n-type Al _0.1 Ga _0.9 N layer (dopant: Si), active layer, 20 nm thick p-type Al _0.2 Ga _0.8 N layer (dopant: Mg), and 150 nm thick p-type GaN layer (dopant) : Mg) were sequentially formed to obtain an epitaxial growth layer. Here, as the active layer, four barrier layers formed of a GaN layer having a thickness of 10 nm and three well layers formed of a Ga _0.85 In _0.15 N layer having a thickness of 3 nm were alternately stacked. A multiple quantum well structure was adopted.

For reference, an n-type GaN substrate having a specific resistance of 1 × 10 ⁻² Ωcm and a carrier density of 3 × 10 ¹⁸ / cm ³ for the LEDs of Comparative Examples 16 to 21, which is Comparative Example 16 in Table 5. Those having a surface layer having the carbon concentration and the concentration of the p-type metal element (Cu and Zn) shown in the column of ~ 21 were prepared for each comparative example. 200 LEDs were prepared for each comparative example. And also about Comparative Examples 16-21, the epitaxial growth layer was obtained similarly to Examples 37-43.

  About the epitaxial growth layer obtained as mentioned above, PL intensity | strength evaluation was performed by the photo-luminescence method (PL method). In PL intensity evaluation, a He—Cd laser having a wavelength of 325 nm was used as an excitation light source, and the emission intensity of a wavelength of 460 nm excited by irradiating the sample with laser light was evaluated. The results were as shown in Table 5.

  Next, in each of Examples 37 to 43 and Comparative Examples 16 to 21, as a first electrode on the other main surface ((000-1) plane) side of the n-type GaN crystal substrate, a Ti layer having a thickness of 200 nm, A laminated structure formed of an Al layer having a thickness of 1000 nm, a Ti layer having a thickness of 200 nm, and an Au layer having a thickness of 2000 nm was formed, and heated in a nitrogen atmosphere to form an n-side electrode having a diameter of 100 μm. On the other hand, a laminated structure formed of a 4 nm thick Ni layer and a 4 nm thick Au layer is formed as a second electrode on the p-type GaN layer, and heated in an inert gas atmosphere, so that the p side An electrode was formed. The products of the above steps were processed into 2 mm square to obtain LEDs of Examples 37 to 43 and Comparative Examples 16 to 21.

  The light output of the LED obtained as described above was measured under the condition of an injection current of 4A using an integrating sphere. The light output of the light emitting element was measured as follows. That is, a predetermined current was injected into the light emitting element placed in the integrating sphere, and the light output was measured by a detector that received the light collected from the light emitting element. And the yield of LED of Examples 37-43 and Comparative Examples 16-21 was calculated | required on the conditions which make LED with light output 2W or more into LED which has a favorable characteristic. The results were as shown in Table 5.

As shown in Table 5, the LEDs of Examples 37 to 43, that is, the surface layer was 3 at. % To 25 at. % Of carbon and an LED using a GaN substrate containing a p-type metal element of 5 × 10 ¹⁰ atoms / cm ² to 200 × 10 ¹⁰ atoms / cm ² is compared with the LEDs of Comparative Examples 16 to 21 It was revealed that the PL strength and the yield were excellent. The surface roughness RMS of the substrate was 0.9 nm in both the examples and the comparative examples, and the work-affected layer was 20 nm in both the examples and the comparative examples.

  DESCRIPTION OF SYMBOLS 1 ... HEMT device, 2 ... LED, 10 ... Group III nitride substrate (GaN substrate), 10a ... Surface layer, 12 ... GaN layer, 14 ... AlGaN layer, 16 ... Gate electrode, 18 ... Source electrode, 20 ... Drain electrode 22 ... buffer layer, 24 ... first cladding layer, 26 ... active layer, 28 ... second cladding layer, 30 ... contact layer, 32 ... first electrode, 34 ... second electrode, 50 ... dry etching Device: 52 ... Chamber, 54 ... Upper electrode, 56 ... Lower electrode, 58 ... Substrate support, 60 ... Gas supply port, 62 ... Gas exhaust port, 64 ... High frequency power supply, 70 ... Polishing device, 72 ... Surface plate, 74 ... polishing pad, 76 ... crystal holder, 78 ... weight, 80 ... slurry liquid supply port.

Claims (8)

A group III nitride substrate which is a GaN substrate ;
An epitaxial layer;
With
The number of C atoms per cm ^{3 at} the interface between the group III nitride substrate and the epitaxial layer is 2 × 10 ¹⁶ or more and 5 × 10 ¹⁷ or less, and the number of p-type metal elements per cm ^{3 at the} interface The number of atoms is 2 × 10 ¹⁶ or more and 1 × 10 ¹⁷ or less,
Group III nitride substrate with epitaxial layer.   1 cm at the interface between the group III nitride substrate and the epitaxial layer ³ The number of O atoms per hit is 2 × 10 ¹⁶ 1 x 10 or more ¹⁸ The group III nitride substrate with an epitaxial layer according to claim 1, wherein the number is not more than one.   1 cm at the interface between the group III nitride substrate and the epitaxial layer ³ The number of Si atoms per hit is 1 × 10 ¹⁵ 1 x 10 or more ¹⁹ The group III nitride substrate with an epitaxial layer according to claim 1 or 2, wherein the number is at most.   A semiconductor device provided with the group III nitride board | substrate with an epitaxial layer as described in any one of Claims 1-3.   The semiconductor device according to claim 4, wherein the group III nitride substrate is an n-type GaN substrate.   The semiconductor device according to claim 4, wherein the group III nitride substrate is an insulating GaN substrate.   The semiconductor device according to claim 4, wherein the semiconductor device is an LED.   The semiconductor device according to claim 4, wherein the semiconductor device is a HEMT device.

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