JP2015053482A - Group iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device - Google Patents

Group iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device Download PDF

Info

Publication number
JP2015053482A
JP2015053482A JP2014178036A JP2014178036A JP2015053482A JP 2015053482 A JP2015053482 A JP 2015053482A JP 2014178036 A JP2014178036 A JP 2014178036A JP 2014178036 A JP2014178036 A JP 2014178036A JP 2015053482 A JP2015053482 A JP 2015053482A
Authority
JP
Japan
Prior art keywords
substrate
surface
layer
semiconductor device
pieces
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2014178036A
Other languages
Japanese (ja)
Inventor
石橋 恵二
Keiji Ishibashi
恵二 石橋
Original Assignee
住友電気工業株式会社
Sumitomo Electric Ind Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 住友電気工業株式会社, Sumitomo Electric Ind Ltd filed Critical 住友電気工業株式会社
Priority to JP2014178036A priority Critical patent/JP2015053482A/en
Publication of JP2015053482A publication Critical patent/JP2015053482A/en
Application status is Pending legal-status Critical

Links

Images

Abstract

A group III nitride semiconductor substrate, an epitaxial substrate, and a semiconductor device capable of improving the emission intensity of a semiconductor device are provided. In a semiconductor device 100, a surface 10a has a specific plane orientation, and 30 to 1010 pieces / cm2 to 2000 to 1010 pieces / cm2 of sulfide in terms of S, and 2 at% to about 0 in terms of O The presence of 20 at% oxide in the surface layer 12 can suppress the pile-up of C at the interface between the epitaxial layer 22 and the group III nitride semiconductor substrate 10. Thereby, formation of the high resistance layer at the interface between epitaxial layer 22 and group III nitride semiconductor substrate 10 is suppressed. Therefore, the emission intensity of the semiconductor device 100 can be improved. [Selection] Figure 9

Description

  The present invention relates to a group III nitride semiconductor substrate, an epitaxial substrate, and a semiconductor device.

  In recent years, semiconductors, including compound semiconductors, have expanded their application range by taking advantage of their various characteristics. For example, a compound semiconductor is useful as a base substrate for stacking epitaxial layers, and is used in semiconductor devices such as a light emitting diode (LED) and a laser diode (LD).

  When a semiconductor substrate is used as the base substrate, the surface of the semiconductor substrate needs to be a mirror surface without distortion. Therefore, a semiconductor single crystal ingot is subjected to pre-processing (for example, cutting, lapping, etching) to obtain a semiconductor substrate, and then the surface of the semiconductor substrate is subjected to mirror polishing.

  As the semiconductor substrate, for example, those described in Patent Documents 1 to 3 below are known. In Patent Document 1, a semiconductor substrate obtained by cutting a crystalline group III-V nitride (e.g., (Al, Ga, In) -N) grown by vapor phase epitaxy (VPE) and then performing pre-processing. Is disclosed. Patent Document 1 discloses that as a pre-processing, after the surface of a semiconductor substrate is mechanically polished, chemical polishing (CMP) is performed to remove surface damage caused by the mechanical polishing.

In Patent Document 2, the surface of an Al x Ga y In z N (0 <y ≦ 1, x + y + z = 1) wafer is polished by CMP so that the RMS standard surface roughness is less than 0.15 nm. A semiconductor substrate with reduced defects and contamination is disclosed. Patent Document 2 discloses that when performing CMP, Al 2 O 3 or SiO 2 is used as abrasive grains, and an oxidizing agent is added to a polishing liquid to adjust pH.

Patent Document 3 discloses that Si piled up (accumulated) at the interface between the epitaxial layer and the semiconductor substrate deteriorates the characteristics of the device, and Si at the interface between the epitaxial layer and the semiconductor substrate. A semiconductor substrate having a concentration of 8 × 10 17 cm −3 or less is disclosed.

US Pat. No. 6,596,079 US Pat. No. 6,488,767 Japanese Patent No. 3183335

  However, in a semiconductor device using a stacked body in which an epitaxial layer (well layer) is arranged on the semiconductor substrate described in Patent Documents 1 to 3, there is a limit to improving the emission intensity. Therefore, development of a semiconductor substrate capable of improving the emission intensity of the semiconductor device is strongly desired.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a group III nitride semiconductor substrate, an epitaxial substrate, and a semiconductor device that can improve the emission intensity of the semiconductor device.

  As a result of diligent research, the present inventors have found that when impurities such as C (carbon) are present on the surface of the semiconductor substrate, C is piled up at the interface when an epitaxial layer is formed on the surface of the semiconductor substrate. It has been found that a layer having high electrical resistance (hereinafter referred to as “high resistance layer”) is formed at the layer / semiconductor substrate interface. It has also been found that the formation of a high resistance layer increases the electrical resistance at the epitaxial layer / semiconductor substrate interface, thereby reducing the light emission intensity.

  Furthermore, the present inventors have found that in a group III nitride semiconductor substrate used for a semiconductor device, the substrate surface has a specific plane orientation and a specific amount of sulfide and oxide are present on the substrate surface. The inventors have found that it is possible to suppress the pileup of C at the interface between the epitaxial layer and the semiconductor substrate. Thus, by suppressing the pile-up of C, formation of the high resistance layer at the interface between the epitaxial layer and the semiconductor substrate is suppressed. Thereby, the electrical resistance at the interface between the epitaxial layer and the semiconductor substrate can be reduced, and the crystal quality of the epitaxial layer can be improved. Therefore, the emission intensity of the semiconductor device can be improved.

That is, the present invention is a group III nitride semiconductor substrate used for a semiconductor device, having a surface layer on the surface of the group III nitride semiconductor substrate, and the surface layer is 30 × 10 10 pieces / cm in terms of S. It contains 2 to 2000 × 10 10 pieces / cm 2 of sulfide and 2 at% to 20 at% of oxide in terms of O, and the inclination angle of the surface normal axis with respect to the c axis is 10 ° to 81 °. Here, in the surface layer, sulfides of 30 × 10 10 pieces / cm 2 to 2000 × 10 10 pieces / cm 2 in terms of S are measured by TXRF (total reflection fluorescent X-ray analysis), and 2 at% to in terms of O 20 at% oxide is a layer having a thickness that can be measured by AES (Auger Electron Spectroscopy).

The surface layer preferably contains 40 × 10 10 pieces / cm 2 to 1500 × 10 10 pieces / cm 2 sulfides S terms. In this case, the formation of the high resistance layer at the interface between the epitaxial layer and the semiconductor substrate can be further suppressed, and the light emission intensity of the semiconductor device can be further improved.

  Moreover, it is preferable that a surface layer contains the oxide of 3at%-16at% in O conversion. In this case, the formation of the high resistance layer at the interface between the epitaxial layer and the semiconductor substrate can be further suppressed, and the light emission intensity of the semiconductor device can be further improved.

  Furthermore, the present inventors further suppress the formation of the high resistance layer at the interface between the epitaxial layer and the semiconductor substrate by the presence of the specific amount of chloride or the specific amount of silicon compound on the substrate surface, and the semiconductor It has been found that the emission intensity of the device can be further improved.

That is, the surface layer preferably contains 120 × 10 10 pieces / cm 2 to 15000 × 10 10 pieces / cm 2 of chloride in terms of Cl. The surface layer preferably contains 100 × 10 10 pieces / cm 2 ~12000 × 10 10 pieces / cm 2 of silicon compound calculated as Si.

  Furthermore, the present inventors further suppress the formation of the high resistance layer at the interface between the epitaxial layer and the semiconductor substrate by setting the content of the carbon compound on the substrate surface to a specific amount or less, and increase the emission intensity of the semiconductor device. It has been found that it can be further improved.

  That is, the content of the carbon compound in the surface layer is preferably 22 at% or less in terms of C.

  The present inventors have also found that the copper compound on the substrate surface contributes to the formation of the high resistance layer. Furthermore, by making the content of the copper compound on the substrate surface below a specific amount, the formation of a high resistance layer at the interface between the epitaxial layer and the semiconductor substrate can be further suppressed, and the emission intensity of the semiconductor device can be further improved. I found.

That is, the content of the copper compound in the surface layer is preferably 150 × 10 10 pieces / cm 2 or less in terms of Cu.

  Further, the surface roughness of the surface layer is preferably 5 nm or less on the basis of RMS. In this case, the crystal quality of the epitaxial layer can be further improved, and the light emission intensity of the semiconductor device can be further improved.

The dislocation density of the surface layer is preferably 1 × 10 6 pieces / cm 2 or less. In this case, since the crystal quality of the epitaxial layer can be further improved, the emission intensity of the semiconductor device can be further improved.

  The surface orientations of the surface are {20-21} plane, {20-2-1} plane, {10-11} plane, {10-1-1} plane, {11-22} plane, {11- It is preferably any of 2-2} plane, {22-43} plane, {22-4-3} plane, {11-21} plane, and {11-2-1} plane. In this case, the half width of light emission can be reduced.

  An epitaxial substrate according to the present invention has the above group III nitride semiconductor substrate and an epitaxial layer formed on the surface layer of the group III nitride semiconductor substrate, and the epitaxial layer includes a group III nitride semiconductor.

  Since the epitaxial substrate according to the present invention includes the group III nitride semiconductor substrate, it is possible to suppress the pile-up of C at the interface between the epitaxial layer and the semiconductor substrate. Therefore, the formation of a high resistance layer at the interface between the epitaxial layer and the semiconductor substrate can be suppressed, and the light emission intensity of the semiconductor device can be improved.

  Moreover, it is preferable that the epitaxial substrate has an active layer in which the epitaxial layer has a quantum well structure, and the active layer is provided so as to generate light having a wavelength of 430 nm to 550 nm.

  A semiconductor device according to the present invention includes the epitaxial substrate.

  Since the semiconductor device according to the present invention includes the above-described epitaxial substrate, it is possible to suppress C from being piled up at the interface between the epitaxial layer and the semiconductor substrate. Therefore, the formation of a high resistance layer at the interface between the epitaxial layer and the semiconductor substrate can be suppressed, and the light emission intensity of the semiconductor device can be improved.

  According to the present invention, there are provided a group III nitride semiconductor substrate, an epitaxial substrate and a semiconductor device capable of improving the light emission intensity of the semiconductor device.

It is a schematic sectional drawing which shows the group III nitride semiconductor substrate which concerns on 1st Embodiment. It is a figure which shows the apparatus which can be used for dry etching. It is a figure which shows the apparatus which can be used for polishing. 1 is a schematic cross-sectional view showing an epitaxial substrate according to a first embodiment. It is a schematic sectional drawing which shows the epitaxial substrate which concerns on 2nd Embodiment. It is a top view which shows the epitaxial substrate which concerns on 3rd Embodiment. It is the figure which showed the procedure which produces the epitaxial substrate which concerns on 3rd Embodiment. It is a top view which shows the modification of the epitaxial substrate which concerns on 3rd Embodiment. 1 is a schematic cross-sectional view showing a semiconductor device according to a first embodiment. It is a schematic sectional drawing which shows the semiconductor device which concerns on 2nd Embodiment. It is a schematic sectional drawing which shows the semiconductor device used in the Example.

  Hereinafter, preferred embodiments of a group III nitride semiconductor substrate, an epitaxial substrate, and a semiconductor device according to the present invention will be described in detail with reference to the drawings.

(Group III nitride semiconductor substrate)
FIG. 1 is a schematic cross-sectional view showing a group III nitride semiconductor substrate 10 according to the first embodiment. As shown in FIG. 1, group III nitride semiconductor substrate 10 (hereinafter referred to as “nitride substrate 10”) has a front surface 10a and a back surface 10b facing each other. Is formed.

  The constituent material of the nitride substrate 10 is preferably a crystal having a wurtzite structure, and examples thereof include GaN, AlN, InN, AlGaN, and InGaN. The nitride substrate 10 made of GaN can be manufactured by the HVPE method, the flux method, or the like. The nitride substrate 10 made of AlN can be produced by HVPE method, sublimation method or the like. The nitride substrate 10 made of InN, AlGaN, or InGaN can be produced by the HVPE method or the like.

  The nitride substrate 10 can epitaxially grow a desired semiconductor layer (epitaxial layer) on the surface 10a. The quality of the surface 10a is preferably suitable for forming an epitaxial layer. Unlike the crystal quality in the bulk portion inside the substrate, the quality of the surface 10a is easily affected by the surface composition, roughness, and work-affected layer.

  Here, the work-affected layer refers to a layer in which the crystal lattice formed in the surface side region of the crystal is disturbed by crystal grinding or polishing. The work-affected layer can be confirmed in its presence and thickness by observing a cross section of the crystal fractured at the cleavage plane by SEM observation, TEM observation, or CL (cathode luminescence) observation. The thickness of the work-affected layer is preferably 20 nm or less, and more preferably 10 nm or less. If the thickness of the work-affected layer is large, the morphology and crystallinity of the epitaxial layer tend to decrease.

  CL observation refers to observing visible light emitted from the III nitride semiconductor crystal or light having a wavelength close to the visible wavelength region by making an electron beam incident on the III nitride semiconductor crystal as excitation light. When CL observation of a group III nitride semiconductor crystal is performed, light is observed in a crystal region having a good surface state, light is not observed in a region of a work-affected layer where the crystal is disordered, and is observed as a black linear shadow. The

  When the nitride substrate 10 is used for a semiconductor device, it is preferable to suppress the formation of a high resistance layer at the interface between the nitride substrate 10 and the epitaxial layer. If the electrical resistance at the interface is increased due to the presence of the high resistance layer, the light emission efficiency of the semiconductor device is lowered. In particular, when a large current is injected into a semiconductor device, the light emission efficiency is significantly reduced.

  From the viewpoint of suppressing the formation of such a high resistance layer, the surface layer 12 includes sulfides and oxides.

The surface layer 12 includes 30 × 10 10 pieces / cm 2 to 2000 × 10 10 pieces / cm 2 of sulfide in terms of S and 2 at% to 20 at% of oxide in terms of O. The content of sulfide is preferably 120 × 10 10 pieces / cm 2 to 1500 × 10 10 pieces / cm 2 in terms of S, and more preferably 100 × 10 10 pieces / cm 2 to 500 × 10 10 pieces / cm 2. . The content of the oxide is preferably 3 at% to 16 at% in terms of O, and more preferably 4 at% to 12 at%. When the sulfide content is less than 30 × 10 10 pieces / cm 2 or the oxide content is less than 2 at%, a high resistance layer is formed at the interface between the semiconductor substrate and the epitaxial layer, and the interface height is high. The light emission intensity of the semiconductor device decreases due to resistance. When the content of sulfide exceeds 2000 × 10 10 pieces / cm 2 or the content of oxide exceeds 20 at%, the crystal quality of the epitaxial layer decreases, and the emission intensity of the semiconductor device decreases.

It is preferable that the surface layer 12 contains 120 × 10 10 pieces / cm 2 to 15000 × 10 10 pieces / cm 2 of chloride in terms of Cl. The chloride content is more preferably 350 × 10 10 pieces / cm 2 to 10,000 × 10 10 pieces / cm 2 in terms of Cl, and further 1000 × 10 10 pieces / cm 2 to 5000 × 10 10 pieces / cm 2. preferable. When the chloride content is less than 120 × 10 10 pieces / cm 2 , a high resistance layer is likely to be formed at the interface between the semiconductor substrate and the epitaxial layer, and the emission intensity of the semiconductor device is reduced due to the increase in resistance at the interface. Tend. If the chloride content exceeds 15000 × 10 10 pieces / cm 2 , the crystal quality of the epitaxial layer tends to be lowered, and the emission intensity of the semiconductor device tends to be lowered.

It is preferable that the surface layer 12 contains 200 × 10 10 pieces / cm 2 to 12000 × 10 10 pieces / cm 2 of silicon compound in terms of Si. The content of the silicon compound, 500 × 10 10 pieces in terms of Si / cm 2 ~8000 × 10 10 pieces / cm 2, more preferably, 1000 × 10 10 pieces / cm 2 ~ 5000 × 10 10 pieces / cm 2 is further preferable. When the content of the silicon compound is less than 200 × 10 10 pieces / cm 2 , a high resistance layer is easily formed at the interface between the semiconductor substrate and the epitaxial layer, and the emission intensity of the semiconductor device is lowered due to the increase in resistance at the interface. Tend. When the content of the silicon compound exceeds 12000 × 10 10 pieces / cm 2 , the crystal quality of the epitaxial layer tends to be lowered, and the light emission intensity of the semiconductor device tends to be lowered.

  The surface layer 12 may contain a carbon compound. The content of the carbon compound in the surface layer 12 is preferably 22 at% or less, more preferably 18 at% or less, and further preferably 15 at% or less in terms of C. When the content of the carbon compound exceeds 22 at%, the crystal quality of the epitaxial layer is liable to deteriorate, the light emission intensity of the semiconductor device tends to decrease, and a high resistance layer is formed at the interface between the semiconductor substrate and the epitaxial layer. It tends to be easy, and the emission intensity of the semiconductor device tends to decrease due to the high resistance of the interface.

The surface layer 12 may contain a copper compound. The content of the copper compound in the surface layer 12 is preferably 150 × 10 10 pieces / cm 2 or less in terms of Cu, more preferably 100 × 10 10 pieces / cm 2 or less, and further 50 × 10 10 pieces / cm 2 or less. preferable. When the content of the copper compound exceeds 150 × 10 10 pieces / cm 2 , the crystal quality of the epitaxial layer is liable to deteriorate, and the light emission intensity of the semiconductor device tends to decrease, and at the interface between the semiconductor substrate and the epitaxial layer. A high resistance layer is easily formed, and the emission intensity of the semiconductor device tends to decrease due to the increase in resistance at the interface.

  The composition of the surface layer 12 can be quantified by TXRF (total reflection X-ray fluorescence analysis) for S, Si, Cl and Cu. TXRF evaluates the composition from the depth of X-ray penetration to about 5 nm from the surface. O and C can be quantified by AES (Auger electron spectroscopy). AES has a resolution of 0.1%. AES evaluates a composition of about 5 nm from the surface from the escape depth of Auger electrons. In addition, the surface layer 12 is a layer which has a thickness which can measure a content component by TXRF or AES, for example, has a thickness of about 5 nm.

  The difference in composition between the surface layer 12 and the bulk portion inside the nitride substrate 10 can be evaluated by performing analysis in the depth direction by SIMS (secondary ion mass spectrometry). Further, the difference in composition inside the nitride substrate 10, the interface between the nitride substrate 10 and the epitaxial layer, and the inside of the epitaxial layer can also be evaluated by SIMS.

  The surface roughness of the surface layer 12 in the nitride substrate 10 is preferably 5 nm or less, preferably 3 nm or less on the RMS basis, from the viewpoint of further improving the crystal quality of the epitaxial layer and further improving the integrated intensity of device emission. More preferred is 1 nm or less. Further, from the viewpoint of achieving both excellent productivity and crystal quality of the epitaxial layer, the surface roughness is preferably 1 nm to 3 nm. Here, the RMS-based surface roughness (root mean square roughness) can be measured using an AFM (Atomic Force Microscope) as a 10 μm square region of the surface 10a.

The dislocation density of the surface layer 12 is preferably 1 × 10 6 pieces / cm 2 or less, more preferably 1 × 10 5 pieces / cm 2 or less, and still more preferably 1 × 10 4 pieces / cm 2 or less. When the dislocation density exceeds 1 × 10 6 pieces / cm 2 , the crystal quality of the epitaxial layer tends to be lowered, and the emission intensity of the semiconductor device tends to be lowered. On the other hand, the dislocation density is preferably 1 × 10 2 pieces / cm 2 or more from the viewpoint of excellent cost and productivity at the time of crystal production. The dislocation density can be calculated by performing CL observation and counting the number of non-light emitting points in the 10 μm square region of the surface layer 12.

  The surface 10a of the nitride substrate 10 is a semipolar plane, and the plane orientation of the surface 10a is {20-21} plane, {20-2-1} plane, {10-11} plane, {10-11} plane, { 10-1-1} plane, {11-22} plane, {11-2-2} plane, {22-43} plane, {22-4-3} plane, {11-21} plane, {11- 2-1} plane is preferable. In this case, since the indium (In) incorporation efficiency of the epitaxial layer can be improved, good light emission characteristics can be obtained. The plane orientation of the surface 10a can be measured using, for example, an X-ray diffractometer.

  The inclination angle (off angle) of the normal axis of the surface 10a with respect to the c-axis is 10 ° to 81 °, preferably 17 ° to 80 °, and more preferably 63 ° to 79 °. Since the piezo electric field due to the spontaneous polarization of the wurtzite structure is suppressed when the inclination angle is 10 ° or more, the PL intensity of the light emitting device can be improved. When the tilt angle is 81 ° or less, the dislocation density of the epitaxial layer (well layer) can be reduced, and the emission intensity of the semiconductor device can be improved.

  Next, a method for manufacturing the nitride substrate 10 will be described.

  First, after a group III nitride semiconductor crystal is grown in the c-axis direction or the m-axis direction by the HVPE method or the like, the crystal is subjected to outer periphery processing and shaped to obtain a group III nitride semiconductor ingot. Next, the obtained ingot is cut at a desired angle using a wire saw or a blade saw to obtain a nitride substrate 10 having a desired off-angle on the surface 10a. A semipolar substrate may be used as the base substrate, and a group III nitride semiconductor crystal may be grown on the semipolar substrate, and an ingot having a desired off angle on the surface may be used.

Next, in order to planarize the substrate surface, machining such as grinding (grinding) or lapping is performed. For grinding, a grindstone containing diamond, SiC, BN, Al 2 O 3 , Cr 2 O 3 , ZrO 2 or the like as hard abrasive grains can be used. For lapping, a general abrasive containing diamond, SiC, BN, Al 2 O 3 , Cr 2 O 3 , ZrO 2 or the like as hard abrasive grains can be used.

  The abrasive grains are appropriately selected in consideration of mechanical action and characteristics. For example, from the viewpoint of increasing the polishing rate, abrasive grains having a high hardness and a large particle diameter are used. From the viewpoint of smoothing the surface and suppressing the formation of a work-affected layer, abrasive grains having a low hardness and a small particle diameter are used. Further, from the viewpoint of shortening the polishing time and obtaining a smooth surface, multi-stage polishing in which the abrasive grains having a large particle size are changed to small abrasive grains as the polishing process proceeds is suitable.

  After the nitride substrate 10 is ground or lapped, the surface 10a is subjected to a surface finish such as dry etching or CMP in order to reduce the surface roughness of the surface 10a of the nitride substrate 10 or to remove the work-affected layer. Do. Note that dry etching may be performed before grinding or lapping.

  Dry etching includes RIE (reactive ion etching), inductively coupled plasma RIE (ICP-RIE), ECR (electron cyclotron resonance) -RIE, CAIBE (chemically assisted ion beam etching), RIBE (reactive ion beam etching), etc. Among them, reactive ion etching is preferable. For reactive ion etching, for example, a dry etching apparatus 16 shown in FIG. 2 can be used.

  The dry etching apparatus 16 includes a chamber 16a. In the chamber 16a, a parallel plate type upper electrode 16b and a lower electrode 16c, and a substrate support 16d disposed on the lower electrode 16c so as to face the upper electrode 16b are provided. A gas supply port 16e connected to a gas source and a gas exhaust port 16f connected to a vacuum pump are provided in the chamber 16a. A high frequency power source 16g connected to the lower electrode 16c is disposed outside the chamber 16a.

  In the dry etching apparatus 16, plasma can be generated in the chamber 16a by supplying gas from the gas supply port 16e into the chamber 16a and supplying high frequency power from the high frequency power supply 16g to the lower electrode 16c. By disposing the nitride substrate 10 on the substrate support 16d, the surface 10a of the nitride substrate 10 can be dry-etched.

By using a sulfur-based gas as the etching gas supplied from the gas supply port 16e, a high etching rate can be obtained and the sulfide content of the surface layer 12 can be adjusted. As the sulfur-based gas, for example, H 2 S, SO 2 , SF 4 , SF 6 and the like can be used. Similarly, by using a chlorine-based gas as an etching gas, a high etching rate can be obtained and the chloride content of the surface layer 12 can be adjusted. As the chlorine-based gas, for example, Cl 2 , HCl, CCl 4 , BCl 3 , SiCl 4 , SiHCl 3 can be used. The contents of the silicon compound and the carbon compound in the surface layer 12 can be adjusted by using, for example, SiCl 4 , SiHCl 3 , CH 4 , or C 2 H 2 as an etching gas. It should be noted that the content of the components contained in the surface layer 12 can also be controlled by adjusting the type of gas, the gas flow rate, the pressure in the chamber, and the etching power.

In reactive ion etching, it is preferable to satisfy the following formula (1) when the pressure in the chamber is P (Pa), the gas flow rate is Q (sccm), and the chamber volume is V (L).
0.05 ≦ PV / Q ≦ 3.0 (1)
When PV / Q is smaller than 0.05, the surface roughness tends to increase. When PV / Q is larger than 3.0, the effect of surface modification tends to be small.

  For example, a polishing apparatus 18 shown in FIG. 3 can be used for the CMP. The polishing apparatus 18 includes a surface plate 18a, a polishing pad 18b, a crystal holder 18c, a weight 18d, and a slurry liquid supply port 18e.

  The polishing pad 18b is placed on the surface plate 18a. The surface plate 18a and the polishing pad 18b are rotatable about the central axis X1 of the surface plate 18a. The crystal holder 18c is a component for supporting the nitride substrate 10 on its lower surface. A load is applied to the nitride substrate 10 by a weight 18d placed on the upper surface of the crystal holder 18c. The crystal holder 18c is substantially parallel to the axis line X1 and has a center axis line X2 at a position displaced from the axis line X1, and is rotatable around the center axis line X2. The slurry liquid supply port 18e supplies the CMP solution slurry S onto the polishing pad 18b.

  According to this polishing apparatus 18, the surface plate 18a, the polishing pad 18b, and the crystal holder 18c are rotated, the slurry S is supplied onto the polishing pad 18b, and the surface 10a of the nitride substrate 10 is brought into contact with the polishing pad 18b. Thus, the CMP of the surface 10a can be performed.

The content of the components contained in the surface layer 12 can be adjusted by the additive of the CMP solution, pH, and redox potential. Abrasive grains can be added to the CMP solution. As the material of the abrasive grains, ZrO 2 , SiO 2 , CeO 2 , MnO 2 , Fe 2 O 3 , Fe 3 O 4 , NiO, ZnO, CoO, Co 3 O 4 , GeO 2 , CuO, Ga 2 O 3 , At least one metal oxide selected from the group consisting of In 2 O 3 can be used. A compound such as Si, Cu, Cu—Zn alloy, Cu—Sn alloy, Si 3 N 4 , or SiAlON can also be used. The material of the abrasive grains is preferably a material having a high ionization tendency from the viewpoint of improving the cleaning property, and if the material has a higher ionization tendency than H, the removal efficiency by cleaning can be particularly improved. A CMP solution that does not contain abrasive grains may be used. By using Si, Si 3 N 4 , SiAlON, or the like as the abrasive grains, the content of the silicon compound in the surface layer 12 can be adjusted. By using Cu, Cu—Zn alloy, Cu—Sn alloy, or the like, the content of the copper compound in the surface layer 12 can be adjusted.

  From the viewpoint of sufficiently suppressing abrasive grains from remaining on the surface 10a after CMP, a surfactant can be added to the CMP solution. Examples of the surfactant include a carboxylic acid type, a sulfonic acid type, a sulfate ester type, a quaternary ammonium salt type, an alkylamine salt type, an ester type, and an ether type.

  As a solvent for the CMP solution, a nonpolar solvent is preferred. Nonpolar solvents include hydrocarbons, carbon tetrachloride, diethyl ether and the like. By using a nonpolar solvent, solid contact between the abrasive grains, which are metal oxides, and the substrate can be promoted, so that the metal composition on the substrate surface can be efficiently controlled.

The chemical action (mechanochemical effect) of the CMP solution on the semiconductor substrate can be adjusted by the pH and redox potential of the CMP solution. The pH of the CMP solution is preferably 1 to 6 or 8.5 to 14, and more preferably 1.5 to 4 or 10 to 13. Examples of pH adjusters include inorganic acids such as hydrochloric acid, nitric acid, sulfuric acid and phosphoric acid, organic acids such as formic acid, acetic acid, citric acid, malic acid, tartaric acid, succinic acid, phthalic acid, maleic acid and fumaric acid, KOH, NaOH In addition to alkalis such as NH 4 OH, organic alkalis and amines, salts such as sulfates, carbonates and phosphates can be used. By using an organic acid as a pH adjuster, the effect of removing impurities can be improved even at the same pH as compared with inorganic acids and inorganic salts. As the organic acid, dicarboxylic acid (divalent carboxylic acid) is preferable.

  Adjusting the content of sulfide in the surface layer 12 by using an acid containing a sulfur atom such as sulfuric acid, a sulfate such as sodium sulfate, or a thiosulfate such as sodium thiosulfate as a pH adjusting agent and an oxidizing agent. Can do. Acids containing chlorine atoms such as hydrochloric acid, salts such as potassium chloride, hypochlorite, sodium hypochlorite, hypochlorites such as calcium hypochlorite, chlorinated isocyanuric acids such as trichloroisocyanuric acid, dichloro By using a chlorinated isocyanurate such as sodium isocyanurate, the chloride content of the surface layer 12 can be adjusted. By using an organic acid such as carbonic acid, carbonate, citric acid, oxalic acid, fumaric acid, phthalic acid, malic acid, or an organic acid salt, the content of the carbon compound in the surface layer 12 can be adjusted.

  The oxidation-reduction potential of the CMP solution can be adjusted using an oxidizing agent. By increasing the oxidation-reduction potential by adding an oxidizing agent to the CMP solution, it is possible to improve the polishing rate while maintaining a high abrasive removal effect, and to adjust the oxide content of the surface layer 12. . The oxidizing agent is not particularly limited, but from the viewpoint of sufficiently increasing the oxidation-reduction potential, hypochlorite such as hypochlorous acid, sodium hypochlorite, calcium hypochlorite, trichloroisocyanuric acid, etc. Chlorinated oxidants such as chlorinated isocyanuric acid and chlorinated isocyanurates such as sodium dichloroisocyanurate, sulfur oxidants such as thiosulfates such as sulfuric acid and sodium thiosulfate, and permanganates such as potassium permanganate , Dichromates such as potassium dichromate, bromates such as potassium bromate, thiosulfates such as sodium thiosulfate, persulfates such as ammonium persulfate and potassium persulfate, nitric acid, hydrogen peroxide, ozone etc. Preferably used. Among these, by using a sulfur-based oxidizing agent or a chlorine-based oxidizing agent, the polishing rate is improved, and the content of sulfide or chloride in the surface layer 12 after polishing is adjusted to the above-mentioned preferable content. be able to.

Here, when the value of the pH of the CMP solution is x and the value of the oxidation-reduction potential is y (mV), the relationship between x and y preferably satisfies the following formula (2).
−50x + 1400 ≦ y ≦ −50x + 1900 (2)
If y exceeds the upper limit of formula (2), the corrosive action on the polishing pad and polishing equipment becomes strong, and it tends to be difficult to polish in a stable state, and the oxidation of the substrate surface proceeds excessively. Tend to. If y is less than the lower limit of the formula (2), the oxidizing action on the substrate surface tends to be weakened, and the polishing rate tends to decrease.

  By controlling the viscosity of the CMP solution, the content of the components contained in the surface layer 12 can be adjusted. The viscosity of the CMP solution is preferably 2 mPa · s to 30 mPa · s, and more preferably 5 mPa · s to 10 mPa · s. When the viscosity of the CMP solution is lower than 2 mPa · s, the content of the content component of the surface layer 12 tends to be higher than the desired value described above, and when it exceeds 30 mPa · s, the content of the content component of the surface layer 12 is included. The amount tends to be lower than the desired value described above. The viscosity of the CMP solution can be adjusted by adding a highly viscous organic compound such as ethylene glycol or an inorganic compound such as boehmite.

The sulfide content of the surface layer 12 can be adjusted by the concentration of sulfate ions in the CMP solution and the contact coefficient C. The contact coefficient C is “C = η × V / P” using the viscosity η (mPa · s) of the CMP solution, the peripheral speed V (m / s) during polishing, and the pressure P (kPa) during polishing. Defined by Contact Factor C is preferably 1.0 × 10 -6 m~2.0 × 10 -6 m. If the contact coefficient C is less than 1.0 × 10 −6 m, the load on the semiconductor substrate in CMP tends to be strong, and the sulfide content of the surface layer 12 tends to be excessive, and 2.0 When it exceeds x10 −6 m, the polishing rate tends to decrease and the sulfide content of the surface layer 12 tends to decrease.

  The pressure during polishing is preferably 3 kPa to 80 kPa, and more preferably 10 kPa to 60 kPa. When the pressure is less than 3 kPa, the polishing rate tends to be insufficient in practical use, and when it exceeds 80 kPa, the surface quality of the substrate tends to deteriorate.

According to the nitride substrate 10, the surface 10 a has the specific plane orientation, and is 30 × 10 10 pieces / cm 2 to 2000 × 10 10 pieces / cm 2 of sulfide in terms of S, and O equivalent. Thus, the presence of 2 at% to 20 at% of oxide in the surface layer 12 can suppress the pileup of C at the interface between the epitaxial layer and the nitride substrate 10. Thus, by suppressing the pile-up of C, formation of the high resistance layer at the interface between the epitaxial layer and the nitride substrate 10 is suppressed. Thereby, the electrical resistance at the interface between the epitaxial layer and the nitride substrate 10 can be reduced, and the crystal quality of the epitaxial layer can be improved. Therefore, the emission intensity of the semiconductor device can be improved.

(Epitaxial substrate)
FIG. 4 is a schematic cross-sectional view showing the epitaxial substrate 20 according to the first embodiment. As shown in FIG. 4, the epitaxial substrate 20 has the nitride substrate 10 as a base substrate and an epitaxial layer 22 laminated on the surface 10 a of the nitride substrate 10.

  The epitaxial layer 22 includes, for example, a group III nitride semiconductor. As the group III nitride semiconductor, a crystal having a wurtzite structure is preferable, and examples thereof include GaN, AlN, InN, AlGaN, and InGaN. The epitaxial layer 22 can be formed by vapor phase growth methods such as HVPE method, MOCVD method, VOC method, MBE method, and sublimation method. By providing the epitaxial layer 22 on the nitride substrate 10, the emission intensity of the semiconductor device can be improved.

  FIG. 5 is a schematic cross-sectional view showing an epitaxial substrate 30 according to the second embodiment. As shown in FIG. 5, the epitaxial substrate 30 has an epitaxial layer 32 composed of a plurality of layers formed on the surface 10 a of the nitride substrate 10. By providing the epitaxial layer 32 on the nitride substrate 10, the emission intensity of the semiconductor device can be improved.

The epitaxial layer 32 includes a first semiconductor region 32a, a second semiconductor region 32b, and an active layer 32c provided between the first semiconductor region 32a and the second semiconductor region 32b. The first semiconductor region 32a includes one or a plurality of n-type semiconductor layers, and includes, for example, an n-type GaN layer 32d having a thickness of 1 μm and an n-type Al 0.1 Ga 0.9 N layer 32e having a thickness of 150 nm. The second semiconductor region 32b includes one or a plurality of p-type semiconductor layers, and includes, for example, a p-type Al 0.2 Ga 0.8 N layer 32f having a thickness of 20 nm and a p-type GaN layer 32g having a thickness of 150 nm. In the epitaxial layer 32, an n-type GaN layer 32d, an n-type Al 0.1 Ga 0.9 N layer 32e, an active layer 32c, a p-type Al 0.2 Ga 0.8 N layer 32f, and a p-type GaN layer 32g are formed on the nitride substrate 10. Laminated in order.

The active layer 32c is provided so as to generate light having a wavelength of 430 nm to 550 nm, for example. The active layer 32c has, for example, a multiple quantum well structure (MQW) in which four barrier layers and three well layers are formed, and the barrier layers and the well layers are alternately stacked. The barrier layer is, for example, a GaN layer having a thickness of 10 nm. The well layer is, for example, a Ga 0.85 In 0.15 N layer having a thickness of 3 nm.

The epitaxial layer 32 is formed, for example, by MOCVD (metal organic chemical vapor deposition), using an n-type GaN layer 32d, an n-type Al 0.1 Ga 0.9 N layer 32e, an active layer 32c, a p-type Al 0.2 Ga 0.8 N layer 32f and p. The type GaN layer 32g can be formed by epitaxial growth on the nitride substrate 10 sequentially.

  FIG. 6 is a plan view showing an epitaxial substrate 40 according to the third embodiment. As shown in FIG. 6, epitaxial substrate 40 has an epitaxial layer 42 arranged on surface 10 a of nitride substrate 10.

The epitaxial layer 42 has a plurality of low dislocation density regions 44A having a dislocation density smaller than a predetermined dislocation density, and a plurality of high dislocation density regions 44B having a dislocation density larger than the predetermined dislocation density. This predetermined dislocation density is, for example, 8 × 10 7 cm −2 .

  Each of the low dislocation density region 44A and the high dislocation density region 44B extends in a stripe shape substantially parallel to each other in the plane direction (Y direction in FIG. 6) of the surface 10a of the nitride substrate 10, and the back surface of the epitaxial layer 42 To the surface. The epitaxial layer 42 has a stripe structure in which low dislocation density regions 44A and high dislocation density regions 44B are alternately arranged. The epitaxial layer 42 is made of, for example, GaN, and the dislocation density in the crystal is reduced by the stripe structure. The low dislocation density region 44A and the high dislocation density region 44B can be confirmed by CL observation using a scanning electron microscope (for example, S-4300 manufactured by Hitachi, Ltd.).

Next, the manufacturing method of the epitaxial substrate 40 is demonstrated using FIG. First, as shown in FIG. 7A, a striped mask layer 46 is formed by patterning on the surface 10a of the nitride substrate 10 serving as a base substrate so as to extend in the Y direction of FIG. 7A, for example. The mask layer 46 is made of, for example, SiO 2 .

  Next, as shown in FIG. 7B, the epitaxial layer 42 is facet grown by vapor phase epitaxy on the surface 10a on which the mask layer 46 is formed. As the vapor phase growth method, an HVPE method, an MOCVD method, a VOC method, an MBE method, a sublimation method, or the like can be used. When the epitaxial layer 42 is grown thickly by facet growth, the mask layer 46 is covered with the epitaxial layer 42, and a high dislocation density region 44B is formed in a portion located on the mask layer 46.

  The high dislocation density region 44B is not only the stripe structure, but also a square structure in which the stripe-shaped high dislocation density regions 44B are orthogonal to each other as shown in FIG. 8A, or as shown in FIG. A dot structure in which the dot-like high dislocation density regions 44B are regularly arranged at a predetermined interval may be used. Such a high dislocation density region 44B having a square structure or a dot structure can be obtained by patterning the epitaxial layer 42 using the mask layer 46, similarly to the stripe structure.

(Semiconductor device)
FIG. 9 is a schematic cross-sectional view showing the semiconductor device 100 according to the first embodiment. As shown in FIG. 9, the semiconductor device 100 includes an epitaxial substrate 20, an electrode 90 </ b> A that covers the entire surface 23 of the epitaxial layer 22, and an electrode 90 </ b> B that covers the entire back surface 10 b of the nitride substrate 10. And have. The electrodes 90A and 90B are formed by metal vapor deposition, for example. The formation positions of the electrodes 90A and 90B can be appropriately changed as necessary. If the electrode 90B is electrically connected to the nitride substrate 10 and the electrode 90A is electrically connected to the epitaxial layer 22 Good.

  FIG. 10 is a schematic cross-sectional view showing a semiconductor device 200 according to the second embodiment. As shown in FIG. 10, the semiconductor device 200 includes an epitaxial substrate 30, a first electrode (p-side electrode) 92 </ b> A formed so as to cover the entire surface 33 of the epitaxial layer 32, and a back surface 10 b of the nitride substrate 10. And a second electrode (n-side electrode) 92B formed so as to cover a part of the electrode. The size of the semiconductor device 200 is, for example, 400 μm square or 2 mm square. The conductor 91A is electrically connected to the electrode 92A through the solder layer 93. The conductor 91B is electrically connected to the electrode 92B through the wire 94.

  The semiconductor device 200 can be manufactured by the following procedure. First, the nitride substrate 10 is obtained by the method described above. Next, the epitaxial layer 32 is laminated on the surface 10 a of the nitride substrate 10. Furthermore, an electrode 92 A is formed on the surface 33 of the epitaxial layer 32 and an electrode 92 B is formed on the back surface 10 b of the nitride substrate 10. Subsequently, the electrode 92A is electrically connected to the conductor 91A by the solder layer 93, and the electrode 92B is electrically connected to the conductor 91B by the wire 94.

  The present invention is not limited to the above embodiment. The plane orientations of {20-21} plane, M plane, A plane and the like described in the above description include not only those specified by the description itself but also crystallographically equivalent planes and orientations. For example, the {20-21} plane is not only the {20-21} plane, but also the (02-21) plane, the (0-221) plane, the (2-201) plane, the (−2021) plane, (− 2201) plane.

  EXAMPLES Hereinafter, although an Example explains in full detail this invention, the scope of the present invention is not limited to these Examples.

(1) Production of GaN substrate First, an n-type GaN crystal (dopant: O) was grown in the c-axis direction by the HVPE method. Next, the GaN crystal was sliced perpendicularly or parallel to the c-axis to obtain GaN substrates each having a diameter of 50 mm and a thickness of 0.5 mm. In addition, the GaN crystal was sliced by inclining in the m-axis direction from the c-axis or in the a-axis direction from the c-axis to obtain GaN substrates each having a diameter of 50 mm and a thickness of 0.5 mm.

Subsequently, dry etching was performed on the surface of the GaN substrate and the back surface opposite to the surface to remove the work-affected layer. For dry etching, an RIE apparatus having the same configuration as that shown in FIG. 2 was used. The volume (V) of the vacuum chamber was 20L. The material of the substrate support was SiC. The etching gas was Cl 2 or CH 4 and the gas flow rate (Q) was 30 sccm. Dry etching was performed at a pressure (P) of 4.0 Pa and a power of 50 W to 200 W (PV / Q = 2.67).

(2) Lapping of GaN substrate surface The back surface of the GaN substrate was attached to a ceramic crystal holder with wax. A surface plate having a diameter of 380 mm was installed in the lapping apparatus, and the surface plate was rotated about its rotation axis while supplying slurry in which diamond abrasive grains were dispersed from the slurry supply port to the surface plate. Next, the surface of the n-type GaN crystal was lapped by rotating the GaN substrate around the rotation axis of the crystal holder while pressing the GaN substrate against the surface plate by placing a weight on the crystal holder.

Lapping was performed under the following conditions. As the surface plate, a copper surface plate and a tin surface plate were used. As the abrasive grains, three kinds of diamond abrasive grains having an abrasive grain size of 9 μm, 3 μm, and 2 μm were prepared, and with the progress of lapping, abrasive grains having a small abrasive grain size were used step by step. Polishing pressure was 100g / cm 2 ~500g / cm 2 , the rotational speed of the GaN substrate and the surface plate were both 30 times / Min~60 times / min. It was confirmed that the surface of the GaN crystal substrate became a mirror surface by the above lapping.

(3) CMP of GaN substrate surface
CMP of the surface of the GaN substrate was performed using a polishing apparatus having the same configuration as in FIG. CMP was performed under the following conditions. As the polishing pad, a polyurethane suede pad (Supreme RN-R, manufactured by Nitta Haas Co., Ltd.) was used. As the surface plate, a circular stainless steel surface plate having a diameter of 380 mm was used. Contact coefficient between GaN substrate and the polishing pad C was a 1.0 × 10 -6 m~2.0 × 10 -6 m. The polishing pressure was 10 kPa to 80 kPa, and the rotation speeds of the GaN substrate and the polishing pad were both 30 times / min to 120 times / min. In the slurry (CMP solution), silica particles having a particle size of 200 nm were dispersed as 20% by mass in water as abrasive grains. Citric acid and H 2 SO 4 were added to the slurry as pH adjusting agents, and sodium dichloroisocyanurate was added as an oxidizing agent to adjust the pH and redox potential of the slurry to the range of the following formula (3) (x : PH, y: oxidation-reduction potential (mV)).
−50x + 1400 ≦ y ≦ −50x + 1900 (3)

  GaN substrates having different surface compositions were produced by appropriately changing the dry etching and CMP conditions. Evaluation of the sulfide content on the surface of the GaN substrate was performed by TXRF, and evaluation of the oxide content was performed by AES. For TXRF, a W-encapsulated X-ray tube was used as the X-ray source, the X-ray output was 40 kV, the current was 40 mA, and the incident angle was 0.05 °. AES was measured at an acceleration voltage of 10 keV. Tables 1 to 4 show the surface orientation and surface composition of the GaN substrate.

(4) Production of Laser Diode Including GaN Substrate A laser diode having the configuration shown in FIG. 11 was produced by the following procedure. First, after the GaN substrate 10 was placed on the susceptor in the MOCVD furnace, the epitaxial layer 52 was formed on the surface 10a, and the epitaxial substrate 50 was obtained.

The epitaxial layer 52 was produced by the MOCVD method according to the following growth procedure. First, an n-type GaN 52 a having a thickness of 1000 nm was grown on the GaN substrate 10. Next, an n-type InAlGaN cladding layer 52b having a thickness of 1200 nm was grown. Subsequently, after growing an n-type GaN guide layer 52c having a thickness of 200 nm and an undoped InGaN guide layer 52d having a thickness of 65 nm, a three-period MQW (active layer) 52e composed of a GaN thickness of 15 nm / InGaN thickness of 3 nm is grown. did. Subsequently, an undoped InGaN guide layer 52f having a thickness of 65 nm, a p-type AlGaN blocking layer 52g having a thickness of 20 nm, and a p-type GaN guide layer 52h having a thickness of 200 nm were grown. Next, a p-type InAlGaN cladding layer 52i having a thickness of 400 nm was grown. Finally, a p-type GaN contact layer 52j having a thickness of 50 nm was grown. Note that when manufacturing the epitaxial layer 52, trimethyl gallium as a raw material (TMGa), trimethyl aluminum (TMAl), trimethylindium (TMIn), ammonia (NH 3), silane (SiH 4), cyclopentadienyl magnesium (Cp 2 Mg) was used.

After forming the insulating film 95 of SiO 2 on the contact layer 52j, a stripe window having a width of 10 μm was formed by wet etching using photolithography. Laser stripes were provided so that the c-axis was parallel to the direction projected on the substrate surface.

  After forming the stripe window, a p-side electrode 96A made of Ni / Au and a pad electrode made of Ti / Al were evaporated. Next, the back surface 10b of the GaN substrate 10 was polished with a diamond slurry to produce a substrate product with the back surface 10b in a mirror state. At this time, the thickness of the substrate product was measured using a contact-type film thickness meter. The thickness may be measured by microscopic observation of the sample cross section. As the microscope, an optical microscope or a scanning electron microscope can be used. Further, an n-side electrode 96B made of Ti / Al / Ti / Au was formed on the back surface (polished surface) 10b of the GaN substrate 10 by vapor deposition.

  A laser scriber using a YAG laser with a wavelength of 355 nm was used to manufacture the resonator mirror for the laser stripe. When a break is made using a laser scriber, it is possible to improve the oscillation chip yield compared to the case where diamond scribe is used. The scribe groove was formed under the following conditions: laser light output 100 mW; scanning speed 5 mm / s. The scribe groove was a groove having a length of 30 μm, a width of 10 μm, and a depth of 40 μm. A scribe groove was formed by directly irradiating the surface of the epitaxial layer with laser light at an opening of the insulating film of the substrate at a pitch of 800 μm. The resonator length was 600 μm.

Using a blade, a resonant mirror was prepared by cleaving. A laser bar was produced by breaking on the back side of the substrate by pressing. A dielectric multilayer film was coated on the end face of the laser bar by vacuum deposition. The dielectric multilayer film was configured by alternately laminating SiO 2 and TiO 2 . Each film thickness was adjusted in the range of 50 to 100 nm and designed so that the central wavelength of the reflectance was in the range of 500 to 530 nm. The reflection surface on one side was set to 10 cycles, and the design value of reflectivity was designed to be about 95%. The reflection surface on the other side was set to 6 cycles, and the design value of the reflectance was about 80%.

About LD obtained by the above, evaluation by electricity supply was performed at room temperature. As a power source, a pulse power source having a pulse width of 500 ns and a duty ratio of 0.1% was used, and electricity was applied by dropping a needle on the surface electrode. The current density was 100 A / cm 2 . When observing the LED mode light, the emission spectrum emitted from the surface was measured by arranging the optical fiber on the laser bar surface side. Tables 1 to 5 show the integrated intensity of the LED mode light and the half width calculated from the emission peak of the spectrum measurement. Tables 1 to 3 show the evaluation results of LD using a GaN substrate sliced by tilting a GaN crystal in the m-axis direction from the c-axis. Tables 4 and 5 show the evaluation results of the LD using the GaN substrate sliced by tilting the GaN crystal in the a-axis direction from the c-axis. When observing the laser beam, the emission spectrum emitted from the end face was measured by arranging the optical fiber on the end face side of the laser bar. The emission wavelength of the LED mode light was 500 nm to 550 nm. The oscillation wavelength of the laser was 500 nm to 530 nm.

As shown in Tables 1 to 5, in Examples 1-1 to 1-14 and Examples 2-1 to 2-10, the surface normal axis had a specific inclination angle with respect to the c-axis. In addition, the sulfide content is in the range of 30 × 10 10 pieces / cm 2 to 2000 × 10 10 pieces / cm 2 in terms of S, and the oxide content is in the range of 2 at% to 20 at% in terms of O. Therefore, good emission intensity was obtained. Further, the surface orientation is {20-21} plane, {20-2-1} plane, {10-11} plane, {10-1-1} plane, {11-22} plane, {11- If it is any one of the 2-2} plane, {22-43} plane, {22-4-3} plane, {11-21} plane, and {11-2-1} plane, the spectrum measurement light emission It was confirmed that the full width at half maximum calculated from the peak was small and the spread of the emission wavelength was small. In particular, a high integrated intensity and a small half-value width were obtained on the {20-21} plane, {20-2-1} plane, {11-21} plane, and {11-2-1} plane.

  On the other hand, in Comparative Examples 1-1, 1-3, 1-4, 1-6, 2-1, 2-3, 2-4, and 2-6, the oxide content is out of the above range. It was confirmed that the emission intensity decreased. In Comparative Examples 1-2, 1-5, 2-2, and 2-5, it was confirmed that the light emission intensity decreased because the surface did not have the specific plane orientation. In Comparative Examples 1-7 to 1-10, it was confirmed that the emission intensity decreased because the oxide content or sulfide content was out of the above range.

Furthermore, as Example 1-15 and Example 1-16, the content of chloride, silicon compound, carbon compound and copper compound with the same plane orientation, oxide and sulfide content as in Example 1-5 In addition, substrates having different surface roughness and dislocation density were prepared, and laser characteristics were similarly evaluated. In Example 1-15, the Cl concentration is 5000 × 10 10 pieces / cm 2 , the Si concentration is 2000 × 10 10 pieces / cm 2 , the carbon concentration is 12 at%, the copper concentration is 50 × 10 10 pieces / cm 2 , the surface The roughness was 1.5 nm and the dislocation density was 1 × 10 6 pieces / cm 2 . In Example 1-16, the Cl concentration is 18000 × 10 10 pieces / cm 2 , the Si concentration is 15000 × 10 10 pieces / cm 2 , the carbon concentration is 25 at%, the copper concentration is 200 × 10 10 pieces / cm 2 , the surface The roughness was 6 nm and the dislocation density was 1 × 10 7 pieces / cm 2 . In Example 1-15, the integrated intensity was 17.3 and the half width was 47 nm. In Example 1-16, the integrated intensity was 14.9 and the half width was 50 nm. In Example 1-15, since the contents of oxides, sulfides, chlorides, silicon compounds, carbon compounds and copper compounds, and the surface roughness and dislocation density are in the specific ranges, particularly good characteristics are obtained. Obtained.

  DESCRIPTION OF SYMBOLS 10 ... Nitride substrate (Group III nitride semiconductor substrate), 10a ... Surface, 12 ... Surface layer, 20, 30, 40, 50 ... Epitaxial substrate, 22, 32, 42, 52 ... Epitaxial layer, 32c, 52e ... Active Layer, 100, 200 ... Semiconductor device.

Claims (1)

  1. A group III nitride semiconductor substrate having a surface layer on the surface,
    The surface layer contains 30 × 10 10 pieces / cm 2 to 2000 × 10 10 pieces / cm 2 of sulfide in terms of S and 2 at% to 20 at% of oxide in terms of O;
    A group III nitride semiconductor substrate, wherein an inclination angle of a normal axis of the surface with respect to a c-axis is 10 ° to 81 °.
JP2014178036A 2014-09-02 2014-09-02 Group iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device Pending JP2015053482A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2014178036A JP2015053482A (en) 2014-09-02 2014-09-02 Group iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014178036A JP2015053482A (en) 2014-09-02 2014-09-02 Group iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP2010109490 Division 2010-05-11

Publications (1)

Publication Number Publication Date
JP2015053482A true JP2015053482A (en) 2015-03-19

Family

ID=52702250

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014178036A Pending JP2015053482A (en) 2014-09-02 2014-09-02 Group iii nitride semiconductor substrate, epitaxial substrate, and semiconductor device

Country Status (1)

Country Link
JP (1) JP2015053482A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004502298A (en) * 2000-06-28 2004-01-22 アドバンスド.テクノロジー.マテリアルス.インコーポレイテッド How to achieve an improved optoelectronic devices and electronic devices for aluminum nitride, indium, gallium ((Al, an In, Ga) N) epitaxy quality (surface irregularity and defect density) of the free-standing substrate
JP2009527898A (en) * 2006-02-17 2009-07-30 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニアThe Regents of The University of California Method for growing semipolar (Al, In, Ga, B) N optoelectronic device
JP4333820B1 (en) * 2009-01-19 2009-09-16 住友電気工業株式会社 Compound semiconductor substrate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004502298A (en) * 2000-06-28 2004-01-22 アドバンスド.テクノロジー.マテリアルス.インコーポレイテッド How to achieve an improved optoelectronic devices and electronic devices for aluminum nitride, indium, gallium ((Al, an In, Ga) N) epitaxy quality (surface irregularity and defect density) of the free-standing substrate
JP2009527898A (en) * 2006-02-17 2009-07-30 ザ リージェンツ オブ ザ ユニバーシティ オブ カリフォルニアThe Regents of The University of California Method for growing semipolar (Al, In, Ga, B) N optoelectronic device
JP4333820B1 (en) * 2009-01-19 2009-09-16 住友電気工業株式会社 Compound semiconductor substrate

Similar Documents

Publication Publication Date Title
US8351478B2 (en) Growth structures and method for forming laser diodes on {30-31} or off cut gallium and nitrogen containing substrates
CN100461340C (en) Method for manufacturing group III nitride compound semiconductor
JP5361107B2 (en) Method for improving the epitaxy quality (surface roughness and defect density) of aluminum nitride, indium, gallium ((Al, In, Ga) N) free-standing substrates for optoelectronic devices and electronics devices
US8541869B2 (en) Cleaved facet (Ga,Al,In)N edge-emitting laser diodes grown on semipolar bulk gallium nitride substrates
US7041523B2 (en) Method of fabricating nitride semiconductor device
EP2003696B1 (en) GaN substrate, substrate with epitaxial layer, semiconductor device and method of manufacturing GaN substrate
KR101164349B1 (en) GaN SEMICONDUCTOR OPTICAL ELEMENT, METHOD FOR MANUFACTURING GaN SEMICONDUCTOR OPTICAL ELEMENT, EPITAXIAL WAFER AND METHOD FOR GROWING GaN SEMICONDUCTOR FILM
JP5743127B2 (en) Method and apparatus for growth and fabrication of semipolar (Ga, Al, In, B) N thin films, heterostructures and devices
JP5406871B2 (en) Method of manufacturing nitride semiconductor structure and light emitting diode
CN101515700B (en) Group-iii nitride light-emitting device and method for manufacturing group-iii nitride based semiconductor light-emitting device
JP4792802B2 (en) Surface treatment method of group III nitride crystal
CN101874309B (en) Nitride semiconductor optical device, epitaxial wafer for nitride semiconductor optical device, and method for manufacturing semiconductor light-emitting device
JP3349931B2 (en) The method of manufacturing a semiconductor laser device
JP5379973B2 (en) Fabrication of nonpolar indium gallium nitride thin films, heterostructures and devices by metalorganic vapor phase epitaxy
JP2008285364A (en) GaN SUBSTRATE, AND EPITAXIAL SUBSTRATE AND SEMICONDUCTOR LIGHT-EMITTING ELEMENT USING THE SAME
US6455877B1 (en) III-N compound semiconductor device
JP2008218746A (en) Group iii nitride-system semiconductor light-emitting device
KR101337689B1 (en) Nitride semiconductor laser device and nitride semiconductor device
JP2006005331A (en) Group iii nitride semiconductor crystal and manufacturing method of the same, group iii nitride semiconductor device and manufacturing method of the same, and light emitting device
JP2012507874A (en) Optoelectronic devices based on nonpolar or semipolar AlInN and AlInGaN alloys
JP4244542B2 (en) Gallium nitride compound semiconductor light emitting device and method for manufacturing the same
JP4277826B2 (en) Nitride crystal, nitride crystal substrate, nitride crystal substrate with epi layer, and semiconductor device and method for manufacturing the same
US8513694B2 (en) Nitride semiconductor device and manufacturing method of the device
JP5512046B2 (en) Nitride semiconductor layer growth structure, laminated structure, nitride semiconductor device and light source, and method for manufacturing the same
US20050059229A1 (en) Method of manufacturing Group III nitride crystal substrate, etchant used in the method, Group III nitride crystal substrate, and semiconductor device including the same

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20150520

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20150630

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A132

Effective date: 20160119

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20161004