JP5282762B2 - Method for producing silicon single crystal - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a good silicon single crystal with twin crystal defects suppressed, in manufacturing a non-defect silicon single crystal by a CZ method. <P>SOLUTION: The silicon single crystal is manufactured by pulling up the silicon single crystal from a silicon melt in a chamber in the CZ method. The method is characterized in that the V/G value, the ratio of a speed V of pulling up the silicon single crystal to a crystal temperature gradient G is controlled so as to be larger by 0.2-0.5% than a V/G value at the boundary between a dislocation cluster region formed as an aggregate of interstitial silicon and a defect-free region dominated by interstitial silicon, and so as to be smaller than a V/G value at which an OSF region appears. <P>COPYRIGHT: (C)2012,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a silicon single crystal by a CZ method (hereinafter, including MCZ method) used for manufacturing a semiconductor element.

A Czochralski method (CZ method) in which a silicon single crystal is grown while being grown from a silicon melt accommodated in a quartz crucible in a chamber is widely used as a method for producing a silicon single crystal used for manufacturing a semiconductor element. .
In the CZ method, a seed crystal is immersed in a silicon melt in a quartz crucible under an inert gas atmosphere, and a predetermined silicon single crystal is grown by pulling up the quartz crucible and the seed crystal while rotating. Furthermore, as the size of the crystal increases, the weight of the silicon polycrystal to be filled increases. For this reason, a method (MCZ method) of applying a magnetic field to the silicon melt to suppress thermal convection is disclosed, and is widely applied to the production of silicon single crystals having a diameter of 300 mm or more.

  On the other hand, in recent years, growth defects (grown-in defects) in silicon wafers have become a problem due to the progress of high integration of semiconductor elements and the accompanying miniaturization. Growth defects in a silicon single crystal produced by the CZ method include octahedral void defects (see Non-Patent Document 1), which are vacancy aggregates, and dislocation clusters formed as interstitial silicon aggregates. (See Non-Patent Document 2) and the like are known, and these are factors that deteriorate the characteristics of the semiconductor element.

  It is known that the type and concentration of these defects are determined by the pulling rate V of the silicon single crystal and the ratio of the crystal temperature gradient G near the solid-liquid interface, V / G (see Non-Patent Document 3).

  FIG. 10 shows an example of the relationship between V / G and defect distribution. By changing the pulling speed V (mm / min) during single crystal growth, the ratio with the average value G (° C./mm) of the temperature distribution in the crystal in the pulling axis direction in the temperature range from the silicon melting point to 1300 ° C. This is a case where a certain V / G is changed.

  First, as shown in the schematic diagram of the vertically divided sample of the single crystal ingot in FIG. 10, in the region where the pulling speed V is relatively high, voids that are vacancies that are point defects called vacancy (hereinafter also referred to as Va) are aggregated. There is a vacancy-type grown-in defect called COP or FPD, which is considered as a V-Rich region (V region).

When the pulling speed V is slightly slower than this, OSF is generated in a ring shape from the periphery of the crystal (OSF region), and the OSF shrinks toward the center as the pulling speed decreases, and finally the OSF disappears at the crystal center. To do.
Further, when the pulling rate V is further reduced, there is a neutral (hereinafter also referred to as N) region in which excess or deficiency of interstitial point defects called vacancy or interstitial silicon (hereinafter also referred to as I) is small. Since the N region has a bias of Va and I but is below the saturation concentration, it has been found that the N region does not exist as an agglomerated defect or is so small that the presence of a defect cannot be detected by the current defect detection method.
The N region is divided into an Nv region where vacancies are dominant and an Ni region where interstitial silicon is dominant.

  When the pulling rate V is further decreased, I becomes supersaturated, and as a result, dislocation clusters formed as aggregates of interstitial silicon are generated, and this region is called an I-rich region (I region).

Regarding the determination of the crystal defect region as described above, for example, the determination of the N region and the V region is determined by using both the observation of the FPD density by the optical microscope after the secco etching and the OSF density after the OSF heat treatment. be able to.
In addition, the determination of the I region and the N region can be made because dislocation clusters observed in the I region are observed as pits after seco etching.

In recent years, there has been an increasing demand for a whole surface N region (growth defect free region) crystal, that is, a defect-free crystal. It is disclosed that the amount of introduction is determined by the growth rate of the silicon single crystal and the growth rate of the silicon single crystal is lowered.
Patent Document 2 discloses that the single crystal is pulled at a speed that does not exceed the maximum pulling speed of the single crystal that is substantially proportional to the temperature gradient in the boundary region in the solid phase / liquid phase of the silicon single crystal. Furthermore, an improved CZ method focusing on the temperature gradient G and growth rate V during crystal growth has been reported (see Non-Patent Document 4). It is said that defect-free crystals can be obtained when this V / G ratio is constant.

However, when such a defect-free crystal is manufactured, twin defects are newly generated, and the manufactured silicon single crystal may have a defective portion, resulting in a problem that the product yield decreases. It was. Here, for example, a twin crystal is a defect in which a <511> plane having a different plane orientation is formed in the same crystal when the orientation <111> of the plane perpendicular to the growth direction of the silicon single crystal is used. (See Non-Patent Document 5).
In addition, as a cause of the formation of twin defects, SiO that evaporates from the silicon melt at the time of pulling up the silicon single crystal is deposited at a low temperature portion installed in the upper part of the furnace, and these are separated and fall into the silicon melt. This is known to change the crystal orientation of the silicon single crystal.

  Patent Document 3 discloses a technique for controlling the flow of an inert gas in a single crystal manufacturing apparatus using a rectifying cylinder disposed around a crystal as a measure for improving such twin defects. In other words, twin defects are crystals that differ from the plane orientations grown so far in order to relieve the lattice distortion caused by foreign substances different from the silicon single crystal matrix floating on the silicon melt surface adhering to the crystal growth interface. It was thought to occur when the orientation region grew. Here, in a silicon single crystal for a semiconductor element, the plane orientation is the most important characteristic and a critical characteristic.

  However, in the production of defect-free crystals for miniaturized semiconductor elements, even if the crystals are produced in the absence of foreign matter such as silicon oxide SiO oxide of silicon melt, which was previously considered to be a cause of twin defects, In some cases, twin defects occurred and the product yield decreased.

JP-A-6-56588 JP 7-257991 A JP-A-63-50391

Analysis of side-wall structure of growth-in twin-type octahedral defects in Czochralski silicon, Jpn. J. et al. Appl. Phys. Vol. 37 (1998) p.p. 1667-1670 Evaluation of microdefects in as-grown silicon crystals, Mat. Res. Soc. Symp. Proc. Vol. 262 (1992) p-p51-56 The mechanical of swirl defects formation in silicon, Journal of Crystal growth, 1982, pp 625-643. Japanese Society for Crystal Growth vol. 25 No. 5,1998 Silicon crystal growth and wafer processing

  The present invention has been made in view of the above points, and in a method for producing a defect-free silicon single crystal by the CZ method (including the MCZ method), a method for producing a high-quality silicon single crystal in which twin defects are suppressed. The purpose is to provide.

  In order to solve the above-mentioned problem, in the present invention, in a method for producing a silicon single crystal from a silicon melt in a chamber by a CZ method, in order to obtain a defect-free crystal free of twin defects, The V / G value of the ratio between the pulling rate (hereinafter also referred to as growth rate) V and the crystal temperature gradient G is defined as the boundary V between the dislocation cluster region formed as an interstitial silicon aggregate and the defect-free region dominated by interstitial silicon. The silicon single crystal is manufactured by controlling within a range 0.2 to 0.5% larger than the / G value and within a range smaller than the V / G value at which the OSF region appears. A method for producing a crystal is provided.

Thus, in the method of pulling a silicon single crystal from the silicon melt in the chamber by the CZ method, the V / G value of the ratio of the pulling speed V of the silicon single crystal to the crystal temperature gradient G In order to obtain a dislocation cluster region (I-Rich region) formed as an aggregate of interstitial silicon and a defect-free region (Ni) dominant in interstitial silicon, the range is smaller than the V / G value at which the OSF region appears. By setting the range to a value 0.2 to 0.5% larger than the boundary V / G value of the (region), it is formed as an interstitial silicon dominant region (interstitial silicon aggregate) in which the interstitial silicon concentration is excessive. A defect-free crystal can be produced with a crystal quality excluding the interstitial silicon-dominated defect-free region in the vicinity of the dislocation cluster region.
That is, a defect-free crystal in a V / G value range of 0.2 to 0.5% larger than the boundary V / G value between a dislocation cluster region formed as an interstitial silicon aggregate and a defect-free region dominant in interstitial silicon. Can reduce the concentration of excess interstitial silicon, and therefore can suppress the formation of stacking faults that cause twin defects, and the generation of twin defects is suppressed. A silicon single crystal, in particular, a high-quality defect-free crystal including an interstitial silicon dominant region in which generation of twin defects is suppressed can be manufactured.

  Further, at this time, the control of the V / G value of the ratio of the pulling rate V of the silicon single crystal to the crystal temperature gradient G is made constant, the pulling rate V is set as an interstitial silicon aggregate. This can be done by setting the rate to 0.2 to 0.5% higher than the maximum growth rate at which the formed dislocation cluster region appears.

  Thus, the V / G value of the ratio of the pulling rate V of the silicon single crystal to the crystal temperature gradient G is defined as the boundary V between the dislocation cluster region formed as an interstitial silicon aggregate and the defect-free region dominated by the interstitial silicon. As a method of controlling in a range 0.2 to 0.5% larger than the / G value, a dislocation cluster region is formed in which the crystal temperature gradient G is constant and the pulling rate V is formed as an aggregate of interstitial silicon. It can be carried out by making it 0.2 to 0.5% faster than the maximum growth rate.

  At this time, the control of the V / G value of the ratio of the pulling rate V of the silicon single crystal to the crystal temperature gradient G is made constant, the pulling rate V is constant, and the crystal temperature gradient G This can be achieved by adopting an in-chamber structure in which the crystal temperature gradient is 0.2 to 0.5% smaller than the lowest crystal temperature gradient in the chamber where dislocation cluster regions formed as aggregates appear.

  Thus, the V / G value of the ratio of the pulling rate V of the silicon single crystal to the crystal temperature gradient G is defined as the boundary V between the dislocation cluster region formed as an interstitial silicon aggregate and the defect-free region dominated by the interstitial silicon. / G value is controlled within a range of 0.2 to 0.5% larger than the G value, the pulling rate V is constant, and the crystal temperature gradient G is formed as a dislocation cluster region formed by agglomerates of interstitial silicon as a chamber. This can also be achieved by adopting a structure in the chamber that provides a crystal temperature gradient that is 0.2 to 0.5% smaller than the minimum crystal temperature gradient in the chamber in which appears.

  As described above, according to the method for producing a silicon single crystal of the present invention, in the growth of a defect-free crystal (particularly, a defect-free crystal including an interstitial silicon dominant region), the generation of twin defects is suppressed. Quality silicon single crystals can be manufactured. In particular, in the case where the width of twin defects in a defect-free crystal is very narrow and difficult to detect, the cost of quality judgment can be saved, and there is a great effect on quality stabilization.

It is explanatory drawing which shows the relationship between the V / G value controlled in the silicon single crystal manufacturing method of this invention, and defect distribution. It is the observation result by the particle | grain measuring apparatus of the silicon wafer extract | collected from the defect-free crystal obtained by the conventional manufacturing method. It is an observation result by the transmission electron microscope of the sample of the cross-sectional direction of a defect-free crystal. It is the observation figure (a) by a transmission electron microscope of a twin defect, and this schematic diagram (b). An example of a silicon single crystal manufacturing apparatus that can be used in the silicon single crystal manufacturing method of the present invention is shown. It is a figure which shows the growth rate during the single crystal growth in the comparative example 1 and Example 1. FIG. 6 is a diagram comparing the incidence of twin defects in Example 1 and Comparative Example 1. FIG. It is the figure which compared the incidence rate of the twin defect of the comparative example 1 and the comparative example 2. FIG. It is the figure which compared the incidence rate of the twin defect of the comparative example 1 and Example 2. FIG. It is explanatory drawing which shows an example of the relationship between V / G value and defect distribution.

Hereinafter, the present invention will be described more specifically.
As described above, in the manufacture of a defect-free crystal for a miniaturized semiconductor device, even if the crystal is manufactured in the absence of foreign matter such as SiO oxide of silicon melt, twin defects are generated and the product yield is reduced. There was a problem of declining.

  In order to achieve the above-mentioned problems, the present inventors have investigated the details of twin defects as follows. The twin defects are also caused by a cause different from that of a generally distributed document (Non-patent Document 5). Found that formed.

  An in-plane map of a 300 mm diameter silicon wafer taken from a boron-doped defect-free crystal having a surface orientation <100> manufactured using a conventional silicon single crystal manufacturing method and a specific resistance of 10 Ω · cm, and finished by surface polishing, FIG. 2 shows the results of observation with a particle measuring apparatus (KLA Tencor model name = SP2 particle size is 0.037 μm up). The apparatus used for producing defect-free crystals obtained from this silicon wafer has an Ar gas shielding cylinder, and the oxide adheres to the in-furnace parts by the evaporation of SiO from the melt surface. Any drop on the melt surface has no problem.

  From FIG. 2, sparsely adhered particles were observed on the entire wafer surface, but a 22 mm long linear defect was observed in the lower right. Even if this wafer is measured after cleaning this wafer with a mixed solution of hydrofluoric acid and hydrogen peroxide solution, and a mixed solution of hydrochloric acid and hydrogen peroxide solution, which are used for normal wafer cleaning, The 22 mm long linear defect confirmed in the lower right did not change. In other words, it was found that the surface defects formed slight irregularities on the wafer surface and were observed as pseudo particles by a laser type particle counter.

  In order to investigate the actual condition of the 22 mm long linear defect observed as a pseudo particle, a sample in the cross-sectional direction including the surface was taken from the corresponding region. The observation result of this sample with a transmission electron microscope is shown in FIG. Although this observation was an observation result from the <110> direction, a region with a changed orientation could be observed in a very narrow region having a width of 9.5 nm from FIG. That is, it was confirmed that the 22 mm long defect observed by the particle counter was twinned.

  In order to investigate the cause of this twin defect, the origin of the twin defect was investigated. A high-resolution transmission electron microscope (TEM) was used for the analysis. The sample was not heat-treated, and the result of the TEM photograph is shown in FIG. 4 (a), and the schematic diagram is shown in FIG. 4 (b). From these results, it was confirmed that twins were formed from the terminal portion of the stacking fault.

  Here, in general, stacking faults in silicon wafers are defects that become the core of stacking faults by interstitial silicon diffusing into the wafer from the oxide film interface on the silicon wafer surface by thermal oxidation treatment in the wafer state. It is disclosed that the interstitial silicon aggregates to form an excessive lattice plane (Silicon oxidation and lattice defects, Applied Physics Vol. 46, No. 11, 1977, p1056, or CZ silicon wafer). Ring-shaped distributed stacking faults, Applied Physics, Vol. 57, No. 19, 1988, p1542.

However, this sample is not heat-treated. That is, the formation of stacking faults can be seen despite the absence of interstitial silicon supplied by heat treatment.
As a result, during the growth of defect-free crystals, excessive interstitial silicon aggregates to form stacking faults, particularly during growth of the interstitial silicon dominant region, and twin defects continue from the formed stacking faults. It was guessed that it was formed.
That is, it has been found that the twins observed in the above sample are different from the twins formed by the adhesion of foreign substances to the crystal growth interface disclosed in general.

  As described above, defect-free crystals have two defect-free regions (hereinafter also referred to as Nv regions) and defect-free regions (hereinafter also referred to as Ni regions) where interstitial silicon is dominant. Is known (Advanced Czochralski Single Crystal Growth, Journal of Crystal Growth Vol. 27, No. 2). Among these, when crystal growth is performed in a region (Ni region) where interstitial silicon is dominant in the vicinity of the dislocation cluster region (I-rich region) formed as an aggregate of interstitial silicon, a stacking fault is formed at the growth interface. A twin structure is formed from the terminal portion. The formed twin crystal continues to grow along the <111> plane, passes through the outer periphery of the crystal side surface, and becomes crystal growth in a normal orientation. That is, the present inventor has found that the origin of the generation of twin defects in defect-free crystals is a stacking fault (SF) formed to reduce the concentration of dominant interstitial silicon.

  And, in order to suppress the occurrence of such twin defects, it has been found that it is important to reduce the concentration of dominant interstitial silicon and suppress the formation of stacking faults. Was completed.

  That is, the method for producing a silicon single crystal according to the present invention is a method for producing a silicon single crystal from a silicon melt by a CZ method in order to obtain a defect-free crystal free of twin defects. The V / G value of the ratio of the pulling speed V and the crystal temperature gradient G is 0.2 from the boundary V / G value between the dislocation cluster region formed as an interstitial silicon aggregate and the defect-free region dominated by the interstitial silicon. A silicon single crystal is manufactured by controlling within a range that is larger by 0.5% and smaller than the V / G value at which the OSF region appears.

A defect-free crystal is achieved by making the ratio of V / G constant (Japan Crystal Growth Society vol.25 No.5, 1998), but when the value of V / G increases, the vacancy dominant region (Nv On the contrary, when the value of V / G decreases, the crystal quality on the interstitial silicon dominant region (Ni region) side is obtained.
That is, in the present invention, the value of V / G is in a range smaller than the V / G value at which the OSF region appears in order to obtain a defect-free crystal, and the dislocation cluster region is formed as an interstitial silicon aggregate. A region having a high concentration of dominant interstitial silicon by making the range 0.2 to 0.5% larger than the boundary V / G value between the (I-rich region) and the interstitial silicon dominant defect-free region (Ni region) Reduces the concentration of interstitial silicon and suppresses stacking faults by reducing the concentration of interstitial silicon as a defect-free crystal containing no interstitial silicon-dominated defect-free region in the vicinity of dislocation cluster regions formed as an interstitial silicon aggregate Thus, the occurrence rate of twin defects can be improved.

  When the ratio of increasing the value of V / G to be larger than the boundary V / G value between the dislocation cluster region formed as an interstitial silicon aggregate and the defect-free region predominantly of interstitial silicon is less than 0.2%, The interstitial silicon concentration is not sufficiently lowered, and the generation of stacking faults cannot be completely suppressed, that is, the generation of twin defects cannot be suppressed. On the other hand, if the ratio is larger than 0.5%, the manufacturing margin for defect-free crystals decreases, the product yield in crystal growth decreases, and there is a problem that efficient production cannot be performed.

  Here, the V / G value of the ratio of the pulling speed V of the silicon single crystal to the crystal temperature gradient G is defined as the boundary V / between the dislocation cluster region formed as an interstitial silicon aggregate and the defect-free region dominated by the interstitial silicon. In order to make the range 0.2 to 0.5% larger than the G value, the crystal temperature gradient G is kept constant without changing the structure in the chamber for determining the crystal temperature gradient G, and the pulling rate V is set to be between the lattices. This can be achieved by setting the speed to 0.2 to 0.5% higher than the maximum growth rate at which dislocation cluster regions formed as silicon aggregates appear.

  That is, as shown in FIG. 1, the control of the V / G value of the ratio of the pulling speed V of the silicon single crystal and the crystal temperature gradient G to obtain a defect-free crystal is performed without changing the crystal temperature gradient G. The rate V can be increased by 0.2 to 0.5% faster than the maximum growth rate at which dislocation cluster regions formed as interstitial silicon aggregates appear.

In the method for producing a silicon single crystal of the present invention, a single crystal pulling apparatus 10 as shown in FIG.
As shown in FIG. 5, the single crystal pulling apparatus 10 includes a quartz crucible 3 that contains a silicon melt 2 and a graphite crucible 4 that protects the quartz crucible 3 in a chamber 1. The heater 5 and the heat insulating material 6 are disposed so as to surround the crucibles 3 and 4. Further, a rectifying cylinder 7 is provided inside the chamber 1, and a heat shielding material 8 is installed in the lower part of the rectifying cylinder 7.
Using such an apparatus, the silicon single crystal 9 is pulled up from the silicon melt 2 contained in the quartz crucible 3 in the chamber 1 while growing.

  Specifically, the method for producing a silicon single crystal of the present invention is based on an interstitial pattern by gradually decreasing the pulling speed V as the silicon single crystal grows using a silicon single crystal pulling apparatus as described above as a simulation in advance. The maximum growth rate at which dislocation cluster regions formed as silicon aggregates appear is determined. The structure in the chamber of the silicon single crystal pulling apparatus used in the simulation is kept constant without changing the crystal temperature gradient G, and the pulling rate V is 0.2 to 0.5% faster than the maximum growth rate obtained by the simulation. Can be done.

  Thus, by suppressing the generation of twin defects formed in a very narrow region within the wafer surface of defect-free crystals, the product yield of high-quality silicon single crystals is improved. Furthermore, distribution determination (particle measurement) for quality evaluation is not required, which is effective for reducing the inspection cost in quality determination of wafer products and further stabilizing the quality of high-quality silicon wafer crystals.

  In another embodiment of the present invention, the V / G value of the ratio of the pulling rate V of the silicon single crystal to the crystal temperature gradient G is set to the dislocation cluster region formed as an interstitial silicon aggregate and the interstitial silicon. The crystal temperature gradient G is controlled so that the value of V / G becomes large when the pulling rate V is constant in order to make it 0.2 to 0.5% larger than the boundary V / G value of the dominant defect-free region. It will be good.

That is, the pulling rate V is constant, and the crystal temperature gradient G is 0.2 to 0.5% smaller than the lowest crystal temperature gradient in the chamber where the dislocation cluster region in which the chamber is formed as an interstitial silicon aggregate appears. By adopting an in-chamber structure that provides a crystal temperature gradient, the V / G value of the ratio of the pulling rate V of the silicon single crystal to the crystal temperature gradient G can be determined by the dislocation cluster region formed between the interstitial silicon aggregates and the interstitial lattice. The boundary V / G value of the silicon-dominated defect-free region can be increased by 0.2 to 0.5%.
The crystal temperature gradient can be changed, for example, by setting the distance between the tip of the heat shielding material arranged around the crystal and the silicon melt to be wide.

  The method for producing a silicon single crystal of the present invention is not limited to the production of a single crystal having a specific crystal diameter, and can be developed in a timely manner, such as production of a single crystal having a crystal diameter of 450 mm.

  Hereinafter, although the manufacturing method of the silicon single crystal of this invention is demonstrated more concretely, showing an Example and a comparative example, this invention is not limited to this.

(Comparative Example 1)
As shown in FIG. 5, an apparatus provided with a rectifying cylinder for rectifying Ar gas and a heat shielding material for controlling thermal radiation to cool the crystal at the tip of the rectifying cylinder was used.
Using this single crystal manufacturing apparatus, 380 kg of raw material polycrystalline silicon was filled in a quartz crucible having a diameter of 81 cm, and a boron-doped silicon single crystal having a crystal orientation <100> and a diameter of 300 mm (P type, specific resistance 10 Ω · cm) was grown. . At this time, a silicon single crystal was manufactured at a growth rate as shown in FIG.
Under the growth conditions of Comparative Example 1, the rate of twin defects was high when the length ratio in the crystal growth direction was 0.2 to 0.4. As shown in FIG. 5, the heat shielding material for controlling the heat radiation in the furnace cannot be directly applied to the silicon melt due to installation restrictions. Therefore, there is a region where the crystal cannot be cooled in the section from the silicon melt to the heat shielding material. This length ratio in the direction of crystal growth is in the range of 0.2 to 0.4 in the region where the crystal reaches the heat shielding material provided at the tip of the rectifying cylinder, where the temperature gradient in the crystal suddenly changes. is there. Therefore, it becomes a region that tends to become a dislocation cluster region formed as an aggregate of interstitial silicon, that is, a region of the highest growth rate at which the dislocation cluster region appears.

Example 1
Using an apparatus having the same chamber structure as in Comparative Example 1, the silicon single crystal was grown under the condition of 0.4% speedup with respect to the growth rate profile in which a defect-free crystal was obtained in the growth direction in Comparative Example 1. Nurtured. The conditions were the same as in Comparative Example 1 except for the difference in growth rate.

  FIG. 7 shows the result of comparison of the occurrence rate of twin defects in Example 1 and Comparative Example 1. Improve the twinning defect rate by increasing the pulling speed V by 0.4% faster than the boundary V / G value between the dislocation cluster region formed as an interstitial silicon aggregate and the interstitial silicon dominant defect-free region We were able to. Thereby, the product yield of the grown high quality silicon single crystal was improved, and a defect-free crystal could be obtained efficiently.

In Comparative Example 1, the growth rate profile in which a defect-free crystal is obtained in the growth direction is 0.2% faster, and further 0.5% faster. It was possible to improve the defect rate of twinning.
However, when the growth rate profile in which the defect-free crystal is obtained in the growth direction in Comparative Example 1 is set to be 0.1% faster, the interstitial silicon concentration is not sufficiently lowered, and twin crystals The generation of defects could not be suppressed. In addition, when the growth rate profile in which the defect-free crystal is obtained in the growth direction in Comparative Example 1 is set to a condition where the speed is increased by 0.6%, the production yield of the defect-free crystal is reduced, There was a problem that efficient production was not possible.

(Comparative Example 2)
For epitaxial wafers, using an apparatus having the same in-chamber structure as in Comparative Example 1, the pulling rate is about twice that of the growth rate profile in which defect-free crystals are obtained in the growth direction in Comparative Example 1. We investigated twin defects in wafers obtained from high-growth crystals that were pulled up and manufactured in the vacancy-dominated region.
FIG. 8 shows a comparison diagram of the occurrence rate of twin defects in Comparative Example 1 and Comparative Example 2. As shown in FIG. 8, in the wafer obtained from the fast growth crystal (Comparative Example 2), the generation of twin defects was not observed, and it was confirmed that the defect rate of twin generation was high during the production of defect-free crystals.

(Example 2)
In order to reduce the concentration of interstitial silicon by controlling the crystal temperature gradient, the crystal temperature gradient was reduced, that is, the value of V / G was increased in the apparatus shown in FIG. Specifically, a silicon single crystal having a diameter of 300 mm was grown under the condition that the distance from the tip of the heat shielding material to the silicon melt was increased by 1 mm.
The crystal temperature gradient at this time is 0.4% lower than the lowest crystal temperature gradient in the chamber in which dislocation cluster regions formed as aggregates of interstitial silicon appear. The conditions other than those described above were the same as the conventional growth conditions of Example 1.

FIG. 9 shows the result of comparison of the occurrence rate of twin defects in Comparative Example 1 and Example 2.
The V / G value of the ratio of the pulling rate V of the silicon single crystal to the crystal temperature gradient G is determined from the boundary V / G value between the dislocation cluster region formed as an interstitial silicon aggregate and the defect-free region dominated by interstitial silicon. Crystals that are 0.4% smaller than the lowest crystal temperature gradient in the chamber in which dislocation cluster regions appear as aggregates of interstitial silicon appear by increasing 0.4%, that is, without changing the pulling rate V. By adjusting the internal structure of the chamber so that the temperature gradient G is obtained, the twin generation failure rate could be improved. Thereby, the product yield of the grown high quality silicon single crystal was improved, and it was confirmed that this was an efficient manufacturing method.

Similarly, the pulling speed V is not changed, and is 0.2% smaller than the lowest crystal temperature gradient in the chamber where dislocation cluster regions formed as interstitial silicon aggregates appear, and 0.5%. By adjusting the internal structure of the chamber so as to obtain a small crystal temperature gradient G, it was possible to improve the twin generation failure rate.
On the other hand, when the structure in the chamber is adjusted so that the crystal temperature gradient G is 0.1% smaller than the lowest crystal temperature gradient in the chamber in which dislocation cluster regions formed as interstitial silicon aggregates appear, When the crystal temperature gradient G cannot be suppressed and the crystal temperature gradient G is adjusted to be 0.6% smaller, the production yield of defect-free crystals is reduced, and the efficient production of defect-free crystals is reduced. The problem of not being able to occur.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

  DESCRIPTION OF SYMBOLS 1 ... Chamber, 2 ... Silicon melt, 3 ... Quartz crucible, 4 ... Graphite crucible, 5 ... Heating heater, 6 ... Heat insulation material, 7 ... Rectification cylinder, 8 ... Heat shielding material, 9 ... Silicon single crystal, 10 ... Single Crystal pulling device.

Claims (1)

In a method of manufacturing a silicon single crystal from a silicon melt in a chamber by the CZ method, in order to obtain a defect-free crystal free of twin defects, the ratio of the pulling rate V of the silicon single crystal to the crystal temperature gradient G is V / G value
The crystal temperature gradient G is constant, and the pulling rate V is 0.2 to 0.5% faster than the maximum growth rate at which dislocation cluster regions formed as interstitial silicon aggregates appear, or
The pulling rate V is constant, and the crystal temperature gradient G is 0.2 to 0.5% of the minimum crystal temperature gradient in the chamber in which dislocation cluster regions appear in which the chamber is formed as an interstitial silicon aggregate. By having a structure in the chamber that results in a small crystal temperature gradient,
V / G in which the OSF region appears in a range 0.2 to 0.5% larger than the boundary V / G value between the dislocation cluster region formed as an interstitial silicon aggregate and the defect-free region dominant in interstitial silicon. By controlling within a range smaller than the G value, the silicon single crystal is produced as a defect-free crystal that does not include a defect-free region predominantly of interstitial silicon in the vicinity of dislocation cluster regions formed as an interstitial silicon aggregate. A method for producing a silicon single crystal, comprising:

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