JP5277843B2 - Package body and electronic device - Google Patents

Package body and electronic device Download PDF

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Publication number
JP5277843B2
JP5277843B2 JP2008252605A JP2008252605A JP5277843B2 JP 5277843 B2 JP5277843 B2 JP 5277843B2 JP 2008252605 A JP2008252605 A JP 2008252605A JP 2008252605 A JP2008252605 A JP 2008252605A JP 5277843 B2 JP5277843 B2 JP 5277843B2
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Japan
Prior art keywords
package
package body
solder
mounting
electronic component
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Expired - Fee Related
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JP2008252605A
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Japanese (ja)
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JP2009188375A (en
JP2009188375A5 (en
Inventor
洋二 永野
英雄 棚谷
達也 安齊
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Seiko Epson Corp
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Seiko Epson Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a package which can improve a connection strength between a package for electronic component and a circuit board and withstand a severe temperature change at a solder connection part. <P>SOLUTION: The package includes a square package body 6 made of stacked ceramic wherein an electronic component 20 can be mounted on its upper surface and a cover member 30 which airtightly seals an opening space on the upper surface of the package body 6 including the electronic component 20. The package body 6 includes a pair of electrode pads 15 which are formed on the bottom of a recess on the upper surface side and connects the electronic component 20 and a pair of mounting terminals 10 and 11 which are formed on both side in the direction of width of the bottom and have a plurality of bumps 10b, 10c, 11b and 11c on the mounting surface. The package includes a plurality of connection electrodes 14 for connecting the pair of electrode pads 15 with a pair of mounting terminals 10 and 11, respectively. <P>COPYRIGHT: (C)2009,JPO&amp;INPIT

Description

本発明は、電子部品用パッケージと圧電振動子に関し、特に回路基板との接続強度を高
めるように実装端子の構造を改善した電子部品用パッケージと、それを用いた圧電振動子
に関する。
The present invention relates to an electronic component package and a piezoelectric vibrator, and more particularly to an electronic component package having an improved structure of mounting terminals so as to increase the connection strength with a circuit board, and a piezoelectric vibrator using the same.

圧電振動子、中でも表面実装型水晶振動子は小型であること、高精度、高安定な周波数
が容易に得られ、経年変化が小さいこと等のため、通信用機器から民生用機器の基準周波
数源として広く用いられている。近年、機器が小型化、軽量化されると共に表面実装型水
晶振動子のさらなる小型化への要求が強くなっている。
周知のように、表面実装型水晶振動子は、水晶板の両主面に、真空蒸着法、あるいはス
パッタリング法を用いて金属膜(励振電極)を形成し、パッケージ本体内に収容し、該パ
ッケージ本体の周縁部に蓋をシーム溶接等で気密封止して構成される。
Piezoelectric vibrators, especially surface-mounted quartz vibrators, are small in size, easily obtain high-precision and high-stable frequencies, and have little secular change. Is widely used. In recent years, devices have become smaller and lighter, and the demand for further miniaturization of surface-mounted crystal units has been increasing.
As is well known, a surface-mount crystal unit is formed by forming a metal film (excitation electrode) on both main surfaces of a crystal plate using a vacuum deposition method or a sputtering method, and accommodating the metal film in a package body. A lid is hermetically sealed by seam welding or the like at the periphery of the main body.

水晶振動子が車載用機器に用いられる場合、回路基板との接続強度が特に重要となる。
この理由は、車載用機器では低温から高温までの厳しい温度環境にさらされ、圧電振動子
のパッケージの線膨張係数と、圧電振動子が実装される回路基板とのそれとに差があると
、繰り返しの温度変化によりパッケージと回路基板とを接続する半田に歪みが掛かり、半
田の疲労破壊が生じる虞があるためである。更に、近年表面実装型水晶振動子の形状が小
型化され、パッケージの実装端子の面積も一段と小さくなっている。実装端子(端子電極
)と回路基板との接続強度を強化した表面実装型水晶振動子の一例が特許文献1に開示さ
れている。図10(a)は表面実装型水晶振動子の側面断面図、同図(b)は底面図であ
る。表面実装型水晶振動子70は上部が開口した凹部を有する平面矩形状のパッケージ本
体71と、当該パッケージ本体71の中に収容される水晶振動素子75と、パッケージ本
体71の上部開口部に接合される蓋72とからなる。表面実装型水晶振動子70は回路基
板90の配線パターン91上に半田85を介して接続される。
When a crystal resonator is used for a vehicle-mounted device, the connection strength with the circuit board is particularly important.
The reason for this is that in-vehicle devices are exposed to severe temperature environments from low temperature to high temperature, and the linear expansion coefficient of the piezoelectric vibrator package and the circuit board on which the piezoelectric vibrator is mounted are different. This is because the solder connecting the package and the circuit board is distorted due to the temperature change, and the solder may be fatigued. Further, in recent years, the shape of the surface-mounted crystal resonator has been reduced in size, and the area of the package mounting terminal has been further reduced. Patent Document 1 discloses an example of a surface-mounted crystal resonator in which the connection strength between a mounting terminal (terminal electrode) and a circuit board is reinforced. FIG. 10A is a side sectional view of the surface-mount type crystal resonator, and FIG. 10B is a bottom view. The surface-mounted crystal resonator 70 is bonded to a planar rectangular package body 71 having a recess with an upper opening, a crystal resonator element 75 housed in the package body 71, and an upper opening of the package body 71. And a lid 72. The surface mount type crystal unit 70 is connected to the wiring pattern 91 of the circuit board 90 via the solder 85.

図10(b)の底面図に示すように、パッケージ本体71の底面の対向辺に沿って形成
された一対の端子電極82、83は、互いに対向して形成される領域82a、83aと、
一方の端子電極のみが形成されない領域82b、83bとを有している。これらの領域は
、パッケージ本体71の中心点に対して点対称に配置されている。また、パッケージ本体
71の四隅にはキャスタレーションC1〜C4が形成され、キャスタレーションC1、C
3は夫々端子電極82、83と接続されている。このようなパッケージ本体71を構成す
ることにより、温度環境が変化し、パッケージ本体71と回路基板90との熱膨張差によ
り端子電極82、83に応力が生じても、一方の端子電極が形成されない角領域82b、
83bに向かって相互に応力を逃がすので、パッケージ本体71の中心点で平面的に回転
させるように応力が発生し、応力が緩和される。その結果、半田クラック等の発生を飛躍
的に抑制することができると開示されている。
また、特許文献2にはパッケージ裏面の四隅に4つの端子電極を形成し、各端子電極の
中央部に小さな凸部を形成したパッケージが開示されている。このパッケージを用いた圧
電振動子を回路基板上に搭載すると、端子電極と回路基板との間に間隙が得られ、十分な
量と厚みの半田がこの間隙に入るため、十分な接合強度が得られると開示される。
特開2005−108923公報 特開2006−186667公報
As shown in the bottom view of FIG. 10B, the pair of terminal electrodes 82 and 83 formed along the opposing sides of the bottom surface of the package main body 71 are formed by opposing regions 82a and 83a,
It has the area | regions 82b and 83b in which only one terminal electrode is not formed. These regions are arranged point-symmetrically with respect to the center point of the package body 71. Further, castellations C1 to C4 are formed at four corners of the package body 71, and castellations C1 and C4 are formed.
3 is connected to terminal electrodes 82 and 83, respectively. By configuring the package body 71 as described above, even if the temperature environment changes and a stress is generated in the terminal electrodes 82 and 83 due to a difference in thermal expansion between the package body 71 and the circuit board 90, one terminal electrode is not formed. Corner region 82b,
Since the stresses are released from each other toward 83b, the stress is generated so as to be rotated in a plane at the center point of the package body 71, and the stress is relieved. As a result, it is disclosed that the occurrence of solder cracks and the like can be remarkably suppressed.
Patent Document 2 discloses a package in which four terminal electrodes are formed at the four corners of the back surface of the package, and a small protrusion is formed at the center of each terminal electrode. When a piezoelectric vibrator using this package is mounted on a circuit board, a gap is obtained between the terminal electrode and the circuit board, and a sufficient amount and thickness of solder enters this gap, so that sufficient bonding strength is obtained. Will be disclosed.
JP 2005-108923 A JP 2006-186667 A

しかしながら、特許文献1に記載されたパッケージ本体71では、端子電極82、83
が夫々パッケージ本体の角部に形成した1つのキャスタレーションC1、C3を経由して
パッケージ内部に収容した圧電振動素子と導通するように構成されているため、端子電極
82、83とキャスタレーションC1、C3との接続部にクラックが発生すると、水晶振
動子が機能しない虞があるという問題があった。
特許文献2の手法では、パッケージの端子電極面と回路基板のランド電極面との間の半
田量は多くなるものの、歪みが集中する箇所の半田量が必ずしも多くないという問題があ
った。
本発明は、上記問題を解決するためになされたもので、パッケージの実装端子と回路基
板のランド電極との接続強度を高め、半田接合部の亀裂を防止する電子部品用パッケージ
と、それを用いた圧電振動子を提供することにある。
However, in the package main body 71 described in Patent Document 1, the terminal electrodes 82 and 83 are used.
Are electrically connected to the piezoelectric vibration element housed inside the package via one castellation C1 and C3 formed at the corners of the package body, respectively, so that the terminal electrodes 82 and 83 and the castellation C1 and When a crack occurs in the connection portion with C3, there is a problem that the crystal unit may not function.
The technique of Patent Document 2 has a problem in that although the amount of solder between the terminal electrode surface of the package and the land electrode surface of the circuit board increases, the amount of solder at a location where distortion concentrates is not necessarily large.
The present invention has been made to solve the above-described problems. An electronic component package that enhances the connection strength between a package mounting terminal and a land electrode of a circuit board and prevents cracks in a solder joint, and uses the same. It is to provide a piezoelectric vibrator.

本発明は、上記の課題の少なくとも一部を解決するためになされたものであり、以下の
形態又は適用例として実現することが可能である。
SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[適用例1]電子部品を搭載可能な矩形状のパッケージ本体と、前記電子部品を含む前
記パッケージ本体を気密封止する蓋部材と、からなる電子部品用パッケージであって、前
記パッケージ本体の内部に形成された一対の電極パッドと、前記パッケージ本体の底面の
短手方向両側に形成され、かつ実装面に複数の段差部を有する一対の実装端子と、前記一
対のパッドと前記一対の実装端子をそれぞれ電気的に接続する複数の接続電極と、を備え
た電子部品用パッケージを特徴とする。
Application Example 1 An electronic component package comprising a rectangular package main body on which an electronic component can be mounted and a lid member that hermetically seals the package main body including the electronic component, and the interior of the package main body A pair of electrode pads, a pair of mounting terminals formed on both sides of the bottom surface of the package body and having a plurality of step portions on the mounting surface, the pair of pads and the pair of mounting terminals An electronic component package comprising a plurality of connection electrodes that are electrically connected to each other.

このようにパッケージを構成すると、パッケージ実装端子の周縁部の半田を厚くして、
パッケージと回路基板との接続強度を高めると共に、発生する半田接合部内の歪みを複数
の段差部のエッジ領域で分散させることにより、半田の亀裂を防止できるという効果があ
る。
When the package is configured in this way, the solder on the periphery of the package mounting terminal is thickened,
In addition to increasing the connection strength between the package and the circuit board and dispersing the generated distortion in the solder joints in the edge regions of the plurality of stepped portions, it is possible to prevent cracking of the solder.

[適用例2]前記パッケージ本体の四隅にキャスタレーションを形成し、該キャスタレ
ーションにそれぞれ前記接続電極を形成した適用例1に記載の電子部品用パッケージを特
徴とする。
Application Example 2 An electronic component package according to Application Example 1 in which castellations are formed at four corners of the package body, and the connection electrodes are formed on the castellations, respectively.

このようにパッケージを構成すると、キャスタレーションによるパッケージ内部の圧電
振動素子と実装端子との導通のみならず、パッケージと回路基板との接続強度を高めるこ
とができるという効果がある。
By configuring the package in this way, there is an effect that the connection strength between the package and the circuit board can be increased as well as conduction between the piezoelectric vibration element inside the package and the mounting terminal by castellation.

[適用例3]前記段差部は、前記パッケージ本体の周縁部側の面が、曲面である適用例
1又は2に記載の電子部品用パッケージを特徴とする。
Application Example 3 In the electronic component package according to Application Example 1 or 2, the step portion has a curved surface on the peripheral edge side of the package body.

このようにパッケージを構成すると、環境温度の変化に起因して発生する歪みを段差部
形状に基づいて形成される半田の曲面に沿って分散させることで、半田の亀裂を防止する
ことができるという効果がある。
When the package is configured in this manner, it is possible to prevent cracking of the solder by dispersing the distortion generated due to the change of the environmental temperature along the curved surface of the solder formed based on the shape of the stepped portion. effective.

[適用例4]前記一対の実装端子の各々において、前記段差部は少なくとも2個の段差
部を有し、一方の前記段差部はパッケージ本体の中央部寄りに形成され、他方の前記段差
部は端部寄りに形成され、前記一方の段差部と他方の段差部とは、高さが異なる適用例1
乃至3の何れか一項に記載の電子部品用パッケージを特徴とする。
Application Example 4 In each of the pair of mounting terminals, the stepped portion has at least two stepped portions, one of the stepped portions is formed near the center of the package body, and the other stepped portion is Application example 1 is formed near the end, and the one stepped portion and the other stepped portion have different heights.
The package for electronic components as described in any one of thru | or 3 is characterized.

このようにパッケージを構成すると、大きな歪みが掛かるパッケージの中心から離れた
位置と、パッケージの中央部寄りを除く実装端子の周縁部の半田を厚くすることで、実装
端子と回路基板のランド電極との接続強度が高められると共に、実装面に設けた段差部に
より、環境温度の変化に起因して発生する歪みを複数の段差部のエッジ領域に分散させる
ことで、半田の亀裂を防止することができるという効果がある。
When the package is configured in this way, the mounting terminals and the land electrodes of the circuit board are thickened by thickening the solder on the periphery of the mounting terminals excluding the position near the center of the package and the position away from the center of the package where a large strain is applied. In addition to increasing the connection strength of the mounting surface, it is possible to prevent cracks in the solder by dispersing the distortion generated due to changes in the environmental temperature to the edge region of the plurality of stepped portions by the stepped portion provided on the mounting surface. There is an effect that can be done.

[適用例5]前記一方の段差部は、前記他方の段差部よりも高さが高い適用例4に記載
の電子部品用パッケージを特徴とする。
Application Example 5 The electronic component package according to Application Example 4 is characterized in that the one stepped portion is higher than the other stepped portion.

このようにパッケージを構成すると、各段差部の半田の厚みを変えることにより、環境
温度の変化に起因して発生する歪みを各段差部の半田に分散させることで、半田の亀裂を
防止することができるという効果がある。
By configuring the package in this way, by changing the thickness of the solder at each stepped portion, the distortion generated due to the change in environmental temperature is dispersed in the solder at each stepped portion, thereby preventing cracking of the solder. There is an effect that can be.

[適用例6]前記パッケージ本体に段差部を有するダミー電極を形成した適用例1乃至
5の何れか一項に記載の電子部品用パッケージを特徴とする。
[Application Example 6] The electronic component package according to any one of Application Examples 1 to 5, wherein a dummy electrode having a stepped portion is formed on the package body.

このようにパッケージを構成すると、ダミー電極によりパッケージと回路基板の接続強
度が大きくなると共に、ダミー電極の段差部により温度変化で生じる歪みを分散させるこ
とができるので、環境温度の変化に強いパッケージが得られるという効果がある。
When the package is configured in this manner, the connection strength between the package and the circuit board is increased by the dummy electrode, and the distortion caused by the temperature change can be dispersed by the step portion of the dummy electrode. There is an effect that it is obtained.

[適用例7]適用例1乃至6の何れか一項に記載の電子部品用パッケージを備える圧電
振動子を特徴とする。
Application Example 7 A piezoelectric vibrator including the electronic component package according to any one of Application Examples 1 to 6 is characterized.

このように圧電振動子を構成すると、圧電振動子を車載用等の電子機器に実装した場合
、圧電振動子のパッケージと電子機器の回路基板との接続強度が大きいと共に、温度変化
により生じる歪みを段差部のエッジ領域で分散させるので、大きな温度変化、振動、衝撃
に耐えられる電子機器が構成できるという効果がある。
When the piezoelectric vibrator is configured in this way, when the piezoelectric vibrator is mounted on an electronic device such as a vehicle, the connection strength between the package of the piezoelectric vibrator and the circuit board of the electronic device is large, and distortion caused by a temperature change is reduced. Since dispersion is performed in the edge region of the stepped portion, there is an effect that an electronic device that can withstand a large temperature change, vibration, and shock can be configured.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。図1(a)、(b)は本
発明に係る第1の実施の形態の電子部品用パッケージと、これを用いた圧電振動子の構造
を示す概略図で、同図(a)は断面図、同図(b)は底面図である。電子部品用パッケー
ジ1は、図1(a)に示すように、上面側に電子部品20を搭載可能な矩形状の積層セラ
ミック製のパッケージ本体6と、電子部品20を含むパッケージ本体6の上面側の開口部
空間を気密封止する蓋部材30と、からなる。パッケージ本体6は、図1(a)に示すよ
うに、上面側の凹部の内底部に形成され、電子部品20を接続する一対の電極パッド15
と、同図(b)に示すように、底面の短手方向両側に形成され、実装面に複数の段差部(
バンプ)10b、10c、11b、11cを有する一対の実装端子10、11と、を備え
ている。更に、図1(a)に示すように、一対の電極パッド15と一対の実装端子10、
11とをそれぞれ電気的に接続する複数の接続電極14と、を備えている。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIGS. 1A and 1B are schematic views showing the structure of the electronic component package according to the first embodiment of the present invention and the structure of a piezoelectric vibrator using the same, and FIG. FIG. 4B is a bottom view. As shown in FIG. 1A, the electronic component package 1 includes a rectangular multilayer ceramic package body 6 on which an electronic component 20 can be mounted on the upper surface side, and an upper surface side of the package body 6 including the electronic component 20. And a lid member 30 that hermetically seals the opening space. As shown in FIG. 1A, the package body 6 is formed on the inner bottom portion of the concave portion on the upper surface side, and a pair of electrode pads 15 that connect the electronic component 20.
As shown in FIG. 4B, a plurality of step portions (on the mounting surface are formed on both sides in the short direction of the bottom surface.
Bump) 10b, 10c, 11b, 11c, and a pair of mounting terminals 10, 11. Furthermore, as shown in FIG. 1A, a pair of electrode pads 15 and a pair of mounting terminals 10,
And a plurality of connection electrodes 14 that are electrically connected to each other.

図1(a)に示した例は、電子部品20として音叉型水晶振動素子を用いた場合で、音
叉型水晶振動素子20の図示しない一対のリード電極は、パッケージ本体6の一対の電極
パッド15に導電性接着剤を用いて接着、固定される。そして、蓋部材30として金属製
の蓋を用いる場合、蓋部材30はパッケージ本体6の上部周縁部に形成したシールリング
部に抵抗溶接(シーム溶接)等の手段を用いて溶接され、パッケージ本体6は気密封止さ
れる。また、図1(b)に示すように、パッケージ本体6の四隅にキャスタレーションC
1、C2、C3、C4を形成し、該キャスタレーションC1、C2、C3、C4はそれぞ
れ実装端子10、11に接続され、実装端子10、11と電極パッド15とを導通する接
続電極14として機能する。一方、キャスタレーションC1〜C4はパッケージ1を回路
基板に搭載する際、半田の這い上がり(フィレット)により回路基板とパッケージ1との
接続強度を強める効果がある。
また、図1(c)に示すように、キャスタレーションC’はパッケージ本体6底面の短
手方向両側の中央部にそれぞれ1カ所ずつ設けた構成であってもよい。
The example shown in FIG. 1A is a case where a tuning fork crystal resonator element is used as the electronic component 20, and a pair of lead electrodes (not shown) of the tuning fork crystal resonator element 20 is a pair of electrode pads 15 of the package body 6. Are bonded and fixed using a conductive adhesive. When a metal lid is used as the lid member 30, the lid member 30 is welded to a seal ring formed on the upper peripheral edge of the package body 6 using means such as resistance welding (seam welding), and the package body 6. Is hermetically sealed. Further, as shown in FIG. 1B, castellations C are formed at the four corners of the package body 6.
1, C 2, C 3, C 4 are formed, and the castellations C 1, C 2, C 3, C 4 are connected to the mounting terminals 10, 11, respectively, and function as a connection electrode 14 that conducts the mounting terminals 10, 11 and the electrode pad 15. To do. On the other hand, the castellations C1 to C4 have an effect of strengthening the connection strength between the circuit board and the package 1 by soldering up (fillet) when the package 1 is mounted on the circuit board.
Further, as shown in FIG. 1C, the castellation C ′ may have a configuration in which one is provided at each of the center portions on both sides in the short direction of the bottom surface of the package body 6.

パッケージ本体6の底面に設ける実装端子10、11は、図1(b)に示すように、短
手方向両側の中央部にそれぞれ1カ所ずつ設ける。そして、これらの実装端子10、11
は、始めに実装端子ベース10a、11aをスクリーン印刷等の手法を用いてパッケージ
本体6に塗布し、該実装端子ベース10a、11aの面上でパッケージ本体6の中心部寄
りに、それぞれ矩形状の大きな段差部(バンプ)10b、11bと、該実装端子ベース1
0a、11aの面上でパッケージ本体6の端部寄りにそれぞれ矩形状の小さな段差部10
c、11cと、をスクリーン印刷等の手法を用いて塗布し、パッケージ本体6と同時に焼
成して形成する。つまり、実装端子10(11)は実装端子ベース10a(11a)と、
矩形状の2つの大小の段差部10b、10c(11b、11c)とからなる。スクリーン
印刷の一回の塗布で焼成後の段差部の厚さは10μm〜15μm程度となるので、適切な
厚さの段差部(バンプ)10b、10c、11b、11cを形成する。
As shown in FIG. 1B, the mounting terminals 10 and 11 provided on the bottom surface of the package body 6 are provided at one location at each of the center portions on both sides in the short direction. And these mounting terminals 10 and 11
First, the mounting terminal bases 10a and 11a are applied to the package main body 6 by using a method such as screen printing, and each of the mounting terminal bases 10a and 11a has a rectangular shape on the surface of the mounting terminal bases 10a and 11a. Large stepped portions (bumps) 10b and 11b and the mounting terminal base 1
Small step portions 10 each having a rectangular shape near the edge of the package body 6 on the surfaces 0a and 11a.
c and 11c are applied by using a method such as screen printing, and are fired at the same time as the package body 6. That is, the mounting terminal 10 (11) is connected to the mounting terminal base 10a (11a),
It consists of two rectangular steps 10b and 10c (11b and 11c). Since the thickness of the stepped portion after firing is about 10 μm to 15 μm by one application of screen printing, the stepped portions (bumps) 10b, 10c, 11b, and 11c having appropriate thicknesses are formed.

図2は、パッケージ1を回路基板25のランド電極26に実装した場合の実装端子11
、つまり実装端子ベース11aと段差部11b、11cとの要部拡大側面図である。図2
から分かるように、半田28の厚さは、h2(段差部11b、11cの下の半田の厚み)
に比べ、h1(実装端子ベース11aの下の半田の厚み)が大きくなるようにパッケージ
の実装端子11を構成する。
パッケージを回路基板に実装した場合、周囲の温度変化によりパッケージと回路基板と
の線膨張係数の差に起因して、半田接合部に歪みが生じる。パッケージの実装端子の形状
と発生する歪みとの関係を調べるべく、パッケージの実装端子10、11の種類として、
図3(a)〜(d)の底面図に示すような4種類を選んだ。図3(a)は、実装端子10
、11が標準の面積を有するパッケージ、同図(b)は(a)より大きな実装端子面積を
有するパッケージ、同図(c)は、(a)のパッケージにそれぞれ2カ所の段差部(バン
プ)10b、11bを設けたパッケージ、同図(d)は短手方向両側の中央部にそれぞれ
1カ所のキャスタレーションC’を設けたパッケージである。図3(a)〜(d)に示す
パッケージを回路基板に半田を介して実装する場合に、接合材の半田に生じる歪みの大き
さとその領域をシミュレーションにより求めた。図3(a)、(b)、(d)に示すパッ
ケージの場合、接合部の半田の厚さh(図4(a)に示す)を70μmとし、図3(c)
のように段差部10b、11bを設けた場合の接合部の半田の厚さh1(図4(b)に示
す)を100μmとした。また、シミュレーションの条件は、半田の凝固点(+218℃
)を応力の出発点(応力フリー)と仮定し、温度サイクルの温度条件(−40℃⇔+12
5℃)において、温度変化が最も大きい+218℃から−40℃を荷重条件として、半田
にかかる歪みの大きさと歪みの大きな領域とをシミュレーションにより求めた。つまり、
半田の凝固点(+218℃)ではパッケージと回路基板とには歪みは生じないが、温度が
常温に戻ると歪みは発生し、−40℃では歪みは最大となる。なお、温度変動については
モデル内で一様に起きるものとし、パッケージを構成する材料の残留応力は考慮しなかっ
た。
FIG. 2 shows mounting terminals 11 when the package 1 is mounted on the land electrode 26 of the circuit board 25.
That is, it is an essential part enlarged side view of the mounting terminal base 11a and the step portions 11b and 11c. FIG.
As can be seen, the thickness of the solder 28 is h2 (the thickness of the solder under the step portions 11b and 11c).
The package mounting terminal 11 is configured such that h1 (thickness of solder under the mounting terminal base 11a) is larger than that in FIG.
When the package is mounted on a circuit board, distortion occurs in the solder joint due to a difference in linear expansion coefficient between the package and the circuit board due to a change in ambient temperature. In order to investigate the relationship between the shape of the package mounting terminals and the distortion generated, the types of package mounting terminals 10 and 11 are as follows:
Four types were selected as shown in the bottom views of FIGS. FIG. 3A shows the mounting terminal 10.
, 11 is a package having a standard area, FIG. 11B is a package having a larger mounting terminal area than FIG. 11A, and FIG. 10C is a step portion (bump) at two locations on the package of FIG. A package provided with 10b and 11b, and FIG. 11D shows a package provided with one castellation C ′ at the center on both sides in the lateral direction. When the packages shown in FIGS. 3A to 3D are mounted on a circuit board via solder, the magnitude of distortion generated in the solder of the bonding material and its region were obtained by simulation. In the case of the package shown in FIGS. 3A, 3B, and 3D, the solder thickness h (shown in FIG. 4A) of the joint is set to 70 μm, and FIG.
When the stepped portions 10b and 11b are provided as described above, the solder thickness h1 (shown in FIG. 4 (b)) at the joint is set to 100 μm. Also, the simulation condition is that the solder freezing point (+ 218 ° C.
) Is the starting point of stress (stress free) and the temperature condition of the temperature cycle (−40 ° C. + 12
5 ° C.), the magnitude of strain applied to the solder and the large strain region were obtained by simulation under the load condition of + 218 ° C. to −40 ° C. where the temperature change was the largest. That means
At the solder freezing point (+ 218 ° C.), no distortion occurs in the package and the circuit board, but distortion occurs when the temperature returns to room temperature, and the distortion is maximum at −40 ° C. Note that temperature fluctuations occur uniformly in the model, and the residual stress of the material constituting the package was not considered.

図3(a)の右側の実装端子上に重ね書きした図は、パッケージを回路基板に実装し、
−40℃〜+125℃の温度サイクル試験を加えた場合に生じる歪みの大きな領域を示し
たもので、A、B、C、D、Eで示す領域、特にD、Eで示す領域に大きな歪みが生じる
ことがシミュレーションの結果分かった。図3(a)の左側の実装端子にも右側の歪みと
対称な歪みが生じることは説明するまでもない。また、図3(b)〜(d)のパッケージ
についても大きな歪みの生じる領域は、図3(a)の右側の図とほぼ同様の領域であった

また、−40℃〜+125℃の温度サイクルを加えた場合に実装端子のキャスタレーシ
ョンC1〜C4に生じる最大歪みを、図3(a)〜(d)のそれぞれの実装端子の形状に
ついて求めた。図3(e)は、同図(a)に示す実装端子の形状のキャスタレーションに
生じる最大歪みを100とした場合の、同図(b)〜(d)の実装端子のキャスタレーシ
ョンに生じる最大歪みを相対値で示した図で、横軸に実装端子の形状を示す図番(a)〜
(d)を、縦軸は相対半田歪みを示す図である。図3(e)より同図(c)のパッケージ
のように実装端子10、11に段差部10b、11bを設けた場合が、キャスタレーショ
ンに生じる最大歪みが一番小さくなることを見出した。
In the figure overwritten on the mounting terminal on the right side of FIG. 3A, the package is mounted on the circuit board,
This shows a large strain region generated when a temperature cycle test of −40 ° C. to + 125 ° C. is applied, and a large strain is generated in the regions indicated by A, B, C, D, and E, particularly the regions indicated by D and E It was found as a result of simulation that this occurs. Needless to say, distortion on the left side of the mounting terminal in FIG. In addition, in the packages of FIGS. 3B to 3D, the region where the large distortion occurs was almost the same as the right side of FIG.
Moreover, the maximum distortion which arises in the castellations C1-C4 of a mounting terminal when the temperature cycle of -40 degreeC- + 125 degreeC was added was calculated | required about the shape of each mounting terminal of FIG. FIG. 3 (e) shows the maximum generated in the caster of the mounting terminal in FIGS. (B) to (d) when the maximum distortion generated in the castellation of the mounting terminal shape shown in FIG. In the figure which showed distortion by relative value, the figure number (a) which shows the shape of a mounting terminal on a horizontal axis
In (d), the vertical axis represents relative solder strain. From FIG. 3 (e), it was found that when the stepped portions 10b, 11b are provided on the mounting terminals 10, 11 as in the package of FIG. 3 (c), the maximum distortion generated in the castellation is minimized.

これは、実装端子の一部に段差部10b、11bを設けることにより、回路基板と実装
端子の底面との間に介在する半田が厚くなり、歪みが緩和されるのも一因とされる。また
、半田の厚みと接続強度との関係は特開平5−308179号公報に開示されており、半
田厚みに対し接続強度には極大値があり、適切な厚さがある。以上のシミュレーションの
結果を踏まえ、歪みが大きい領域、つまりパッケージの中心から最も離れた位置と、パッ
ケージの中央部寄りを除く実装端子の周縁部の半田厚を厚くするように実装端子の形状を
設計する。更に、図3(a)の右側の実装端子上に示す歪みの分布図のように、実装端子
の境界部に歪みが集中するので、実装端子ベース10a、11a上に複数の段差部10b
、10c、11b、11cを設け、該段差部のエッジ部分で歪みを分散させるような実装
端子を有するパッケージを種々製作した。そして、それらのクラック率(ある断面におけ
る、はんだ全長に対するクラック長さの割合)を調査した。その結果、図1に示すパッケ
ージの実装電極を採用した場合、断面はんだクラック率が低く、すなわち、よりクラック
の発生を低減できることがわかった。
This is also due to the fact that by providing the stepped portions 10b and 11b in a part of the mounting terminal, the solder interposed between the circuit board and the bottom surface of the mounting terminal becomes thick, and the distortion is alleviated. Further, the relationship between the thickness of the solder and the connection strength is disclosed in Japanese Patent Laid-Open No. 5-308179, and the connection strength has a maximum value with respect to the solder thickness and has an appropriate thickness. Based on the results of the above simulation, the mounting terminal shape is designed to increase the solder thickness at the area where the distortion is large, that is, the position farthest from the center of the package and the peripheral edge of the mounting terminal excluding the part near the center of the package To do. Further, as shown in the distribution diagram of distortion on the right side mounting terminal in FIG. 3A, since strain concentrates on the boundary portion of the mounting terminal, a plurality of step portions 10b on the mounting terminal bases 10a and 11a.
10c, 11b, and 11c were provided, and various packages having mounting terminals that disperse the strain at the edge portion of the stepped portion were manufactured. And the crack rate (ratio of the crack length with respect to the solder full length in a certain cross section) was investigated. As a result, it was found that when the mounting electrode of the package shown in FIG. 1 was adopted, the cross-sectional solder crack rate was low, that is, the generation of cracks could be further reduced.

図4(a)は、従来の電子部品用パッケージ1’を回路基板25に実装したものの要部
拡大側面図であり、回路基板25のランド電極26と、パッケージ1’の実装端子11a
との間には厚さhの半田層が介在する。上記のシミュレーションより環境温度が変化する
とパッケージ1’の端部のPで示す領域の歪みが最大になることがシミュレーションの結
果分かった。図4(b)は本発明に係る電子部品用パッケージ1を回路基板25に実装し
たものの要部拡大側面図であり、環境温度が変化するとパッケージ1の端部のPで示す領
域と、段差部11b、11cのそれぞれの境界のQ1、Q2で示す領域で歪みが最大にな
ることがシミュレーションの結果判明した。このように複数の段差部11b、11cを設
けることにより、パッケージ1と回路基板との線膨張係数に違いに起因する歪みを、各領
域P、Q1、Q2に分散することが可能となるので、環境温度の繰り返し変化による半田
の劣化、即ち半田の亀裂を防止することができる。
FIG. 4A is an enlarged side view of a main part of a conventional electronic component package 1 ′ mounted on a circuit board 25. The land electrode 26 of the circuit board 25 and the mounting terminal 11a of the package 1 ′ are shown in FIG.
Between the two, a solder layer having a thickness h is interposed. As a result of the simulation, it was found from the above simulation that when the environmental temperature changes, the distortion of the region indicated by P at the end of the package 1 ′ is maximized. FIG. 4B is an enlarged side view of the main part of the electronic component package 1 according to the present invention mounted on the circuit board 25. When the environmental temperature changes, a region indicated by P at the end of the package 1 and a stepped portion. As a result of simulation, it has been found that the distortion is maximized in the regions indicated by Q1 and Q2 at the boundaries of 11b and 11c. By providing the plurality of step portions 11b and 11c in this way, it becomes possible to disperse the distortion caused by the difference in the linear expansion coefficient between the package 1 and the circuit board in each of the regions P, Q1, and Q2. It is possible to prevent solder deterioration due to repeated changes in environmental temperature, that is, solder cracking.

本発明の第1の特徴は、実装端子10、11の実装端子ベース10a、11aと、段差
部(バンプ)10b、10c、11b、11cとの位置関係にある。実装端子11を例に
して説明すると、図1(b)の底面図に示すように、実装端子ベース11aの図中右端と
、大きな方の矩形状の段差部11bの右端をほぼ一致させ、図中上下方向(短辺方向)で
は端子ベース11aのほぼ中央に段差部11bを位置させる。小さな方の矩形状の段差部
11cは、段差部11bと間隔を隔してパッケージ本体6の端部寄りに配置する。つまり
、段差部11b、11cは、実装端子11を半田により回路基板側のランド電極に接合し
たときに、電子部品用パッケージ1の中心から最も離れた位置と、パッケージの中央部寄
りを除く実装端子11の周縁部との半田が厚くなるような形状とする。このように歪みが
大きく掛かる領域の半田を厚くするのが第1の特徴である。
本発明の第2の特徴は、複数の段差部10b、10c、11b、11cを設けることに
より、パッケージ短手方向に比べて長手方向に強く働く歪みを、該段差部10b、10c
、11b、11cのエッジ部分で分散させることが可能となり、半田の亀裂破壊を防止す
ることができる。
The first feature of the present invention is the positional relationship between the mounting terminal bases 10a and 11a of the mounting terminals 10 and 11 and the step portions (bumps) 10b, 10c, 11b and 11c. The mounting terminal 11 will be described as an example. As shown in the bottom view of FIG. 1B, the right end in the drawing of the mounting terminal base 11a and the right end of the larger rectangular step portion 11b are substantially aligned. In the middle / up / down direction (short side direction), the stepped portion 11b is positioned substantially at the center of the terminal base 11a. The smaller rectangular step portion 11c is disposed closer to the end of the package body 6 with a space from the step portion 11b. That is, the step portions 11b and 11c are the mounting terminals excluding the position farthest from the center of the electronic component package 1 and the center of the package when the mounting terminal 11 is joined to the land electrode on the circuit board side by soldering. The shape is such that the solder with the peripheral edge of 11 becomes thicker. The first feature is to increase the thickness of the solder in the region where the distortion is greatly applied.
The second feature of the present invention is that by providing a plurality of step portions 10b, 10c, 11b, and 11c, distortion that acts more strongly in the longitudinal direction than in the package short direction is reduced.
, 11b and 11c can be dispersed at the edge portions, and cracking of the solder can be prevented.

図1に示した本発明に係るパッケージを実装基板に実装した場合、つまりパッケージの
実装端子を実装基板のランド電極に半田を介して接合した場合に、ランド電極と実装端子
間の導通抵抗が−40℃〜+125℃の温度サイクル(ヒートサイクル)の回数により、
どのように変化するか実験した。図5(a)はパッケージを搭載する基板上の測定用パタ
ーン40であり、41a、41bはランド電極、42a、42bは配線導体、43a、4
3bは導通抵抗測定用の端子電極である。図5(b)は、複数の測定用パターン40を格
子状に配した、導通抵抗測定に実際に用いた基板45の平面図である。
導通抵抗の実験に用いたパッケージは、図1に示した段差部付実装端子を有するパッケ
ージと、比較のために図3(a)〜(d)に示した一般的な実装端子を有するパッケージ
とを用いた。なお、実装端子とランド電極とを接合する半田の導通抵抗を測定するためで
あるので、パッケージ本体内部の電極パッド同士、例えば図1(a)の2個の電極パッド
15は短絡したパッケージを用いた。測定点は、ヒートサイクル前、500回、1000
回、1500回、2000回、2500回、3000回のヒートサイクル試験後の導通抵
抗を測定した。
When the package according to the present invention shown in FIG. 1 is mounted on a mounting board, that is, when the mounting terminal of the package is joined to the land electrode of the mounting board via solder, the conduction resistance between the land electrode and the mounting terminal is − Depending on the number of temperature cycles (heat cycles) from 40 ° C to + 125 ° C,
Experimented with how it changed. FIG. 5A shows a measurement pattern 40 on a substrate on which a package is mounted. 41a and 41b are land electrodes, 42a and 42b are wiring conductors, 43a and 4b.
3b is a terminal electrode for conducting resistance measurement. FIG. 5B is a plan view of the substrate 45 actually used for the conduction resistance measurement in which a plurality of measurement patterns 40 are arranged in a lattice pattern.
The package used in the conduction resistance experiment includes a package having a stepped mounting terminal shown in FIG. 1 and a package having a general mounting terminal shown in FIGS. 3A to 3D for comparison. Was used. Since it is for measuring the conduction resistance of the solder that joins the mounting terminal and the land electrode, the electrode pads inside the package body, for example, the two electrode pads 15 in FIG. It was. Measurement points are 500 times before heat cycle, 1000 times
, 1500 times, 2000 times, 2500 times, 3000 times, and the conduction resistance after 3000 heat cycle tests were measured.

図6は、各ヒートサイクル試験後の導通抵抗を示した折れ線グラフである。折れ線イ、
ロ、ハは、それぞれ図3(a)、図3(d)、図1(c)に示した実装端子を有するパッ
ケージの、ヒートサイクル回数と導通抵抗との関係を示す図である。
図6より本発明の段差部付実装端子を有するパッケージが、導通抵抗のヒートサイクル
試験でも良好な結果を示すことが判明した。
FIG. 6 is a line graph showing the conduction resistance after each heat cycle test. Line A
B and C are diagrams showing the relationship between the number of heat cycles and the conduction resistance of the package having the mounting terminals shown in FIGS. 3A, 3D, and 1C, respectively.
From FIG. 6, it was found that the package having the stepped mounting terminal according to the present invention shows a good result even in the heat cycle test of the conduction resistance.

図7は、第2実施例のパッケージ2の構成を示す底面図で、図1の実施例と異なる点は
段差部10d、11dの構成である。パッケージ2の実装端子10は、実装端子ベース1
0aと複数の円形の段差部10dとからなり、同様に実装端子11は、実装端子ベース1
1aと複数の円形の段差部11dとからなる。図7の実施例では段差部10d、11dが
共に5個ずつの場合で、パッケージ2の中心部寄りにそれぞれ2個の段差部10d、11
dを、パッケージ2の端部寄りにそれぞれ3個の段差部10d、11dを配置した例であ
る。このように段差部10d、11dを配置することにより、パッケージ2の中心から最
も離れた位置と、パッケージの中央部寄りを除く実装端子の周縁部の半田が厚くなり、パ
ッケージ2と回路基板との接続強度が高められると共に、パッケージ短手方向に比べて長
手方向に強く働く歪みを、各段差部10d、11dのエッジ部分で分散させることが可能
となり、半田の亀裂を防止することが可能となる。
FIG. 7 is a bottom view showing the configuration of the package 2 of the second embodiment. The difference from the embodiment of FIG. 1 is the configuration of the step portions 10d and 11d. Mounting terminal 10 of package 2 is mounting terminal base 1
0a and a plurality of circular stepped portions 10d. Similarly, the mounting terminal 11 is mounted on the mounting terminal base 1.
1a and a plurality of circular step portions 11d. In the embodiment shown in FIG. 7, there are five step portions 10d and 11d, and two step portions 10d and 11d are located closer to the center of the package 2, respectively.
d is an example in which three step portions 10d and 11d are arranged near the end of the package 2, respectively. By arranging the stepped portions 10d and 11d in this manner, the solder farthest from the center of the package 2 and the peripheral edge of the mounting terminal excluding the portion near the center of the package becomes thick, and the package 2 and the circuit board In addition to increasing the connection strength, it is possible to disperse the strain acting more strongly in the longitudinal direction than in the package short direction at the edge portions of the stepped portions 10d and 11d, thereby preventing cracks in the solder. .

図8は、第3の実施例のパッケージ3の構成を示す底面図で、図1に示すパッケージ1
と異なる点は、長辺方向の中央部で、短辺方向の端部寄りに2つのダミー電極12、13
とを設けたことである。ダミー電極12、13は、図8に示すように、それぞれダミー電
極ベース12a、13aと、矩形状の段差部12b、13bとにより構成される。段差部
12b、13bを付加したダミー電極12、13を設けることにより、パッケージ3と回
路基板の接続強度が高まると共に、環境温度が変化する際に生じる歪みを段差部12b、
13bの境界で分散させ、半田の亀裂を防止するパッケージが構成できる。
FIG. 8 is a bottom view showing the configuration of the package 3 of the third embodiment, and the package 1 shown in FIG.
Is different from the two dummy electrodes 12, 13 near the end in the short side direction at the center in the long side direction.
Is provided. As shown in FIG. 8, the dummy electrodes 12 and 13 include dummy electrode bases 12a and 13a and rectangular step portions 12b and 13b, respectively. By providing the dummy electrodes 12 and 13 to which the step portions 12b and 13b are added, the connection strength between the package 3 and the circuit board is increased, and distortion caused when the environmental temperature changes is reduced by the step portions 12b and 12b.
A package can be constructed that is dispersed at the boundary of 13b and prevents cracking of the solder.

図9は、第4実施例のパッケージ4の構成を示す底面図で、図7に示す第2実施例のパ
ッケージ2と異なる点は、長辺方向の中央部で、短辺方向の端部寄りに2つのダミー電極
16、17とを設けたことである。ダミー電極16、17は、図7に示すように、それぞ
れダミー電極ベース16a、17aと、円形状の段差部16b、17bとより構成される
。段差部16b、17bを付加したダミー電極16、17を設けることにより、パッケー
ジ4と回路基板の接続強度が高まると共に、環境温度が変化する際に生じる歪みを段差部
16b、17bのエッジ領域で分散させ、半田の亀裂を防止するパッケージが構成できる
FIG. 9 is a bottom view showing the configuration of the package 4 of the fourth embodiment, which is different from the package 2 of the second embodiment shown in FIG. 7 in the center portion in the long side direction and closer to the end portion in the short side direction. Two dummy electrodes 16 and 17 are provided. As shown in FIG. 7, the dummy electrodes 16 and 17 include dummy electrode bases 16a and 17a and circular step portions 16b and 17b, respectively. By providing the dummy electrodes 16 and 17 to which the step portions 16b and 17b are added, the connection strength between the package 4 and the circuit board is increased, and the distortion generated when the environmental temperature changes is distributed in the edge regions of the step portions 16b and 17b. Thus, a package for preventing cracking of the solder can be configured.

端子電極に凸部を有するパッケージが特許文献2に開示されているが、本発明に係るパ
ッケージの実装端子の構成は大きな歪みが加わる、パッケージの中心から遠い領域と、パ
ッケージの中央部寄りを除く実装端子の周縁部の領域の半田の厚さを厚くするような実装
端子の構造と、各段差部のエッジ領域に歪みを分散させる点が異なる。
図1に示した第1実施例では、パッケージ1の凹部に形成した電極パッド15上に音叉
型水晶振動素子を搭載した例を示したが、図7、8、9に示した第2〜4実施例のパッケ
ージ2、3、4の凹部に圧電振動素子を搭載し、表面実装型の圧電振動子を構成してもよ
い。
A package having a convex portion on the terminal electrode is disclosed in Patent Document 2, but the configuration of the mounting terminal of the package according to the present invention is greatly strained, excluding a region far from the center of the package and a portion near the center of the package. The difference is that the mounting terminal structure increases the thickness of the solder in the peripheral region of the mounting terminal and the strain is distributed to the edge region of each stepped portion.
In the first embodiment shown in FIG. 1, an example in which a tuning fork type crystal vibrating element is mounted on the electrode pad 15 formed in the concave portion of the package 1 is shown, but the second to fourth shown in FIGS. A piezoelectric vibration element may be mounted in the recesses of the packages 2, 3, and 4 of the embodiment to constitute a surface-mount type piezoelectric vibrator.

本発明に係る第1実施例のパッケージの構造を示す概略図で、(a)は断面図、(b)は底面図、(c)は底面図。BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic which shows the structure of the package of 1st Example based on this invention, (a) is sectional drawing, (b) is a bottom view, (c) is a bottom view. 回路基板のパッケージを実装した際の要部拡大側面図。The principal part enlarged side view at the time of mounting the package of a circuit board. (a)〜(d)はパッケージの底面図、(e)は実装端子の形状と相対半田歪みとの関係を示す図。(A)-(d) is a bottom view of a package, (e) is a figure which shows the relationship between the shape of a mounting terminal, and relative solder distortion. (a)は従来のパッケージの歪みの掛かる領域、(b)は本発明のパッケージの歪みの掛かる領域、を説明する断面。(A) is the cross section explaining the area | region where the distortion of the conventional package is applied, (b) is the area | region where the distortion of the package of this invention is applied. (a)は導通抵抗測定用パターンの平面図、(b)は基板上に配した測定用パターンの平面図。(A) is a top view of the pattern for conductive resistance measurement, (b) is a top view of the pattern for measurement distribute | arranged on the board | substrate. ヒートサイクル回数と導通抵抗との関係を示す図。The figure which shows the relationship between the heat cycle frequency and conduction resistance. 第2実施例のパッケージの底面図。The bottom view of the package of 2nd Example. 第3実施例のパッケージの底面図。The bottom view of the package of 3rd Example. 第4実施例のパッケージの底面図。The bottom view of the package of 4th Example. 従来のパッケージの、(a)は断面図、(b)は底面図。(A) is sectional drawing and (b) is a bottom view of the conventional package.

符号の説明Explanation of symbols

1、2、3、4…パッケージ、6…パッケージ本体、10、11…実装端子、10a、
11a…実装端子ベース、10b、10c、10d、11b、11c、11d、12b、
13b、16b、17b…段差部(バンプ)、12、13、16、17…ダミー電極、1
2a、13a、16a、17a…ダミー電極ベース、14…接続電極、15…電極パッド
、20…電子部品、25…回路基板、26…ランド電極、28…半田、30…蓋部材、C
’、C1、C2、C3、C4…キャスタレーション、A、B、C、D、E…歪みの大きな
領域、40…測定用パターン、41a、41b…ランド電極、42a、42b…配線導体
、43a、43b 測定用の端子電極、45…基板
1, 2, 3, 4 ... package, 6 ... package body, 10, 11 ... mounting terminal, 10a,
11a: Mounting terminal base, 10b, 10c, 10d, 11b, 11c, 11d, 12b,
13b, 16b, 17b ... stepped portion (bump), 12, 13, 16, 17 ... dummy electrode, 1
2a, 13a, 16a, 17a ... dummy electrode base, 14 ... connection electrode, 15 ... electrode pad, 20 ... electronic component, 25 ... circuit board, 26 ... land electrode, 28 ... solder, 30 ... lid member, C
', C1, C2, C3, C4 ... castellation, A, B, C, D, E ... large distortion region, 40 ... measurement pattern, 41a, 41b ... land electrode, 42a, 42b ... wiring conductor, 43a, 43b Terminal electrode for measurement, 45 ... Board

Claims (4)

電子部品が搭載されるパッケージ本体であって、
前記パッケージ本体の実装面には、前記実装面の中心点と前記パッケージ本体の外周縁との間に配置されている表面実装用の実装端子を備え、
前記実装端子には、前記外周縁側から前記中心点側に向かって第1のバンプ、第2のバンプが、この順番で配置されており、
前記第2のバンプが前記第1のバンプよりも平面視で面積が広いことを特徴とするパッケージ本体。
A package body on which electronic components are mounted,
The mounting surface of the package body includes a mounting terminal for surface mounting disposed between a center point of the mounting surface and an outer peripheral edge of the package body,
In the mounting terminal, a first bump and a second bump are arranged in this order from the outer peripheral edge side toward the center point side,
A package body, wherein the second bump has a larger area in plan view than the first bump.
前記第1のバンプと前記第2のバンプとの並んでいる方向と直交する方向を幅方向とし、前記第1のバンプの幅方向の大きさは前記第2のバンプの幅方向の大きさよりも小さいことを特徴とする請求項1に記載のパッケージ本体。   The direction perpendicular to the direction in which the first bump and the second bump are arranged is defined as the width direction, and the width direction of the first bump is larger than the width direction of the second bump. The package body according to claim 1, wherein the package body is small. 前記第1のバンプと前記第2のバンプとは、高さが異なっていることを特徴とする請求項1または2に記載のパッケージ本体。 Wherein the first bump and the second bump, the package body of claim 1 or 2, characterized in that different heights. 請求項1乃至の何れか一項に記載の前記パッケージ本体と、前記パッケージ本体上に搭載されている電子部品と、を備えることを特徴とする電子デバイス。 An electronic device comprising: the package body according to any one of claims 1 to 3 ; and an electronic component mounted on the package body.
JP2008252605A 2008-01-07 2008-09-30 Package body and electronic device Expired - Fee Related JP5277843B2 (en)

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