JP5269852B2 - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve high breakdown voltage by relaxing electric field concentration in a semiconductor device. <P>SOLUTION: A p-well 111 to be a channel region of a MOSFET is formed in one side of an n<SP>-</SP>layer 110, and an n<SP>+</SP>drain region 118 is formed in the other side. A plurality of second floating field plates FB are formed on an upper part of the n-layer 110 through a first insulation film LA and a second insulation film LB. A plurality of third floating field plates FC are formed thereon through a third insulation film LC. A drain electrode 119 connected on the n<SP>+</SP>drain region 118 has a first drain electrode DA extending on the first insulation film LA. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique for improving the withstand voltage (hereinafter referred to as “withstand voltage”) stability and increasing the withstand voltage in a high withstand voltage semiconductor device.

  For example, when driving two high-voltage side and low-voltage side power switching devices (MOSFET, IGBT, etc.) like a half-bridge type inverter, the high side (high potential island) that drives the high-voltage side power switching device is used. ) And a low-side drive circuit for driving the low-voltage side power switching device is used. Since the high-side circuit operates in a state of being floated with respect to the ground potential, a so-called level shift circuit for transmitting a driving signal to the high-side driving circuit is provided in such a power device driving device. Is provided. A general level shift circuit includes a high voltage switching element such as a MOSFET driven by a drive signal, and a level shift resistor connected in series thereto (see FIG. 2 described later). The voltage drop generated in the level shift resistor is transmitted to the drive circuit as a high-side drive signal. In order to prevent damage to the power device driving apparatus and generation of an erroneous signal in the level shift circuit, the high breakdown voltage switching element is required to have a stable high breakdown voltage.

  As a technique for improving the withstand voltage stability and increasing the withstand voltage of a high-breakdown-voltage switching element such as a diode, for example, a plurality of floating field plates (hereinafter simply referred to as “floating field” via an insulating film on a semiconductor substrate). A plate ")") to form a uniform electric field distribution on the substrate surface (for example, Patent Document 1), or to promote depletion in the substrate by using a RESURF structure (for example, Patent Document 2) as a semiconductor element structure. Techniques are known.

Japanese Patent Laid-Open No. 10-341018 U.S. Pat. No. 4,292,642

When a high voltage is applied to the high-voltage semiconductor device in the cutoff state (OFF state), the high-voltage semiconductor device holds the voltage. At this time, if a local electric field concentration (electric field peak) occurs in the semiconductor substrate on which the device is formed, the breakdown phenomenon of the p / n junction at that portion and the breakdown of the insulating film are likely to occur. It will cause deterioration of the pressure resistance. For example, in the case where the high breakdown voltage semiconductor device is an n-channel MOSFET having a RESURF structure, the vicinity of the drain-side n layer at the junction depth between the n ⁻ layer formed on the semiconductor substrate and the p ⁻ substrate therebelow, In addition, electric field peaks are likely to occur on the surface of the semiconductor substrate below the edge of the field plate (details will be described later).

  Further, when the high voltage semiconductor device is actually used, the upper surface thereof is covered with an overcoat insulating film or an epoxy resin for assembly. For example, when a high voltage is applied between the drain and source of the MOSFET in the cut-off state, and an electric field peak occurs at that time, the overcoat insulating film and the assembly epoxy resin are polarized by the influence. The charge generated by the polarization is held for a certain time after the application of the high voltage is finished. Next, when a high voltage is applied between the drain and the source, the spread of the depletion layer is locally suppressed (particularly near the surface of the silicon substrate) due to the influence of the electric charge. Where the depletion layer spread is suppressed, the electric field peak becomes higher. When the peak reaches the critical breakdown electric field on the silicon surface, the breakdown voltage is lowered, the breakdown voltage is changed, and in some cases, the semiconductor device is destroyed.

  The present invention has been made to solve the above-described problems, and aims to improve withstand voltage stability and increase withstand voltage by relaxing electric field concentration in a substrate on which a semiconductor device is formed. Objective.

A semiconductor device according to a first aspect of the present invention includes a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type formed so as to sandwich the first semiconductor region, and the first semiconductor. A first conductive type third semiconductor region having an impurity concentration higher than that of the region; an electrode formed on the third semiconductor region; a first insulating film formed on the first semiconductor region; A second insulating film formed on the insulating film; and a second insulating film formed on the second insulating film and arranged side by side in a first direction from the third semiconductor region to the second semiconductor region above the first semiconductor region. A plurality of second floating field plates provided; a third insulating film formed on the second floating field plate; and a third insulating film formed on the third insulating film. Arranged side by side in one direction A semiconductor device comprising a plurality of third floating field plates, wherein the electrode, the first electrode portion extending in the first direction on the first insulating film, and second extending over the second insulating film A second electrode portion and a third electrode portion extending on the third insulating film, and a length of a portion of the third electrode portion extending in the first direction above the first insulating film is the first electrode Longer than the length of the portion extending in the first direction on the first insulating film in the portion, and longer than the length of the portion extending in the first direction above the first insulating film in the second electrode portion. It's long .

  A semiconductor device according to a second aspect of the present invention includes a first conductive type first semiconductor region, a second conductive type second semiconductor region formed so as to sandwich the first semiconductor region, and the first semiconductor. A first conductive type third semiconductor region having an impurity concentration higher than that of the region; an electrode formed on the third semiconductor region; a first insulating film formed on the first semiconductor region; A second insulating film formed on the insulating film; and a second insulating film formed on the second insulating film and arranged side by side in a first direction from the third semiconductor region to the second semiconductor region above the first semiconductor region. A plurality of second floating field plates provided; a third insulating film formed on the second floating field plate; and a third insulating film formed on the third insulating film. Arranged side by side in one direction A semiconductor device comprising a plurality of third floating field plates, wherein the electrode has a first electrode portion extending on the first insulating film and a second electrode portion extending on the second insulating film; The length of the portion of the second electrode portion extending in the first direction above the first insulating film is longer than the length of the portion of the first electrode portion extending in the first direction on the first insulating film. Is also long.

  According to the present invention, the electric field concentration near the third semiconductor region on the upper surface of the first semiconductor region is reduced. The breakdown critical electric field point of the device is often in the vicinity of the third semiconductor region, and the concentration of the electric field in the vicinity of the device is mitigated. As a result, the device can stably maintain a high breakdown voltage.

It is a figure which shows a power device and a power device drive device. It is a circuit diagram of the principal part of the high voltage | pressure side drive part in a power device drive device. It is a schematic plan view which shows the layout of the high voltage | pressure side drive part in a power device drive device. It is a schematic sectional drawing of the principal part of the high voltage | pressure side drive part in a power device drive device. It is a schematic sectional drawing of the principal part of the high voltage | pressure side drive part in a power device drive device. 1 is a diagram illustrating a configuration of an HV-MOS according to a first embodiment. It is a figure which shows the electric field distribution between the drain-source in the interruption | blocking state of HV-MOS which concerns on Embodiment 1. FIG. It is a figure which shows the electric field distribution between the drain-sources in the interruption | blocking state of the conventional HV-MOS. FIG. 6 is a diagram for explaining an effect of the first embodiment. FIG. 3 is a diagram illustrating a potential distribution and a current distribution between a drain and a source in a cutoff state of the HV-MOS according to the first embodiment. It is a figure which shows the electric potential distribution and electric current distribution between the drain-source in the interruption | blocking state of the conventional HV-MOS. FIG. 6 is a diagram for explaining an effect of the first embodiment. It is a figure which shows the example which applied the invention which concerns on Embodiment 1 to the high voltage | pressure-resistant diode. FIG. 4 is a diagram illustrating a configuration of an HV-MOS according to a second embodiment. It is a figure which shows the electric field distribution between the drain-sources in the interruption | blocking state of HV-MOS which concerns on Embodiment 2. FIG. FIG. 10 is a diagram for explaining an effect of the second embodiment. FIG. 6 is a diagram illustrating a configuration of an HV-MOS according to a third embodiment. It is a figure which shows the electric field distribution between the drain-sources in the interruption | blocking state of HV-MOS which concerns on Embodiment 3. FIG. It is a figure which shows the electric potential distribution and electric current distribution between drain-source in the interruption | blocking state of HV-MOS which concerns on Embodiment 3. FIG. FIG. 6 is a diagram showing a configuration of an HV-MOS according to a fourth embodiment. It is a figure which shows the electric field distribution between the drain-sources in the interruption | blocking state of HV-MOS which concerns on Embodiment 4. FIG. It is a figure which shows the electric potential distribution and electric current distribution between drain-source in the interruption | blocking state of HV-MOS which concerns on Embodiment 4. FIG. FIG. 10 is a diagram showing a modification of the fourth embodiment. It is a figure which shows the electric field distribution between the drain-source in the interruption | blocking state of HV-MOS which is a modification of Embodiment 4. FIG. It is a figure which shows the electric potential distribution and electric current distribution between drain-source in the interruption | blocking state of HV-MOS which is a modification of Embodiment 4. FIG. FIG. 10 is a diagram showing a configuration of an HV-MOS according to a fifth embodiment. FIG. 10 is a diagram showing a configuration of an HV-MOS according to a sixth embodiment. It is a figure which shows the electric field distribution between the drain-sources in the interruption | blocking state of HV-MOS which concerns on Embodiment 6. FIG. FIG. 20 is a diagram showing a modification of the sixth embodiment. It is a figure which shows the electric field distribution between the drain-source in the interruption | blocking state of HV-MOS which is a modification of Embodiment 6. FIG. FIG. 10 is a diagram showing a configuration of an HV-MOS according to a seventh embodiment. It is a figure which shows the electric field distribution between the drain-sources in the interruption | blocking state of HV-MOS which concerns on Embodiment 7. FIG. FIG. 38 is a diagram showing a modification of the seventh embodiment. It is a figure which shows the electric field distribution between the drain-source in the interruption | blocking state of HV-MOS which is a modification of Embodiment 7. FIG. It is a figure which shows the example which applied the invention which concerns on Embodiment 7 to the high voltage | pressure-resistant diode. It is a figure which shows the electric field distribution between the drain-sources in the interruption | blocking state of the high voltage | pressure-resistant diode which concerns on Embodiment 7. FIG. It is a figure which shows the electric field distribution between the drain-source in the interruption | blocking state of the high voltage | pressure-resistant diode which concerns on Embodiment 7. FIG. FIG. 10 is a diagram showing a configuration of an HV-MOS according to an eighth embodiment. It is a figure which shows the electric field distribution between the drain-sources in the interruption | blocking state of HV-MOS which concerns on Embodiment 8. FIG. It is a figure for demonstrating the modification of embodiment of this invention. It is a figure for demonstrating the modification of embodiment of this invention.

<Embodiment 1>
FIG. 1 is a diagram for explaining an example of a semiconductor device to which the present invention is applicable, and is a diagram showing a general power device and a power device driving apparatus. N-channel IGBTs (Insulated Gate Bipolar Transistors) 51 and 52 which are power switching devices switch high voltage HV which is a main power source. A load is connected to the node N30, and free wheel diodes D1 and D2 are connected to the IGBTs 51 and 52, respectively, for protection from a back electromotive voltage caused by the load.

  The power device driving apparatus 100 that drives the IGBTs 51 and 52 operates according to a high-voltage side control input HIN that controls the high-voltage side IGBT 51 and a low-voltage side control input LIN that controls the low-voltage side IGBT 52. The power device driving apparatus 100 further includes a high voltage side driving unit 101 that drives the high voltage side IGBT 51, a low voltage side driving unit 102 that drives the low voltage side IGBT 52, and a control input processing unit 103.

  The control input processing unit 103 performs signal processing or the like for avoiding an unfavorable state in which, for example, the IGBTs 51 and 52 are simultaneously turned on and a through current flows through the IGBTs 51 and 52 and no current flows through the load. The high voltage side drive signal output HO of the high voltage side drive unit 101 is connected to the control terminal of the IGBT 51. The low-voltage side drive signal output LO of the low-voltage side drive unit 102 is connected to the control terminal of the IGBT 52.

  The low-voltage side fixed supply voltage VCC serving as the power source for the low-voltage side drive unit 102 is supplied from a low-voltage side fixed supply power source (not shown). The high-voltage side floating offset voltage VS becomes a reference potential of the high-voltage side drive unit 101. Further, the high-voltage side floating supply absolute voltage VB serving as a power source is supplied to the high-voltage side driving unit 101 by a high-voltage side floating power source (not shown). The common ground COM and the high-voltage side floating offset voltage VS are connected to the emitter terminals of the IGBTs 51 and 52, respectively.

  The power supply voltage supplied to the high-voltage side drive unit 101 and the low-voltage side drive unit 102 is between the high-voltage side floating supply absolute voltage VB and the high-voltage side floating offset voltage VS and between the common ground COM and the low-voltage side fixed supply voltage VCC. Are connected to capacitors C1 and C2 in order to follow the potential fluctuation accompanying the operation of the IGBTs 51 and 52.

  With the configuration as described above, a power device that performs switching of the main power supply HV of the IGBTs 51 and 52 based on the control inputs HIN and LIN is configured.

  Since the high-voltage side drive unit 101 operates in a state where it is floated with respect to the ground potential of the circuit, the high-voltage side drive unit 101 has a so-called level shift circuit for transmitting a drive signal to the high-voltage side circuit. FIG. 2 is a circuit diagram of the main part of the high voltage drive unit 101. In this figure, the same elements as those shown in FIG. The high voltage MOSFET (hereinafter “HV-MOS”) 11 is a high voltage switching element. The high voltage side drive signal output CMOS 12 includes a pMOS transistor and an nMOS transistor, and outputs a high voltage side drive signal. The level shift resistor 13 plays a role corresponding to a pull-up resistor for setting the gate potential of the high-voltage side drive signal output CMOS 12.

  The HV-MOS 11 switches according to the high voltage side control input HIN, and changes the gate potential of the high voltage side drive signal output CMOS 12. As a result, the high-voltage side drive signal output CMOS 12 switches the voltage between the high-voltage side floating supply absolute voltage VB and the high-voltage side floating offset voltage VS, and outputs a drive signal to the high-voltage side drive signal output HO to drive the IGBT 51. .

  FIG. 3 is a schematic plan view showing a layout provided on a high potential island in the power device driving apparatus 100. The high voltage side drive circuit composed of the high voltage side drive signal output CMOS 12 and the level shift resistor 13 is formed in a region called a high potential island. 2 is a schematic plan view showing a layout of a high voltage side drive unit 101. FIG. The aluminum wiring in the figure is in contact with the ground potential GND. FIG. 4 is a schematic cross-sectional view of the main part of the high voltage drive unit 101 shown in FIG. 2, and corresponds to the BB cross section of FIG. 4, elements similar to those shown in FIGS. 1 and 2 are denoted by the same reference numerals.

The bottom of the p ⁺ isolation 201 reaches the p ⁻ region 200 of the silicon substrate (p ⁻ substrate), and the potential of the p ⁺ isolation 201 and the p ⁻ region 200 is the lowest potential on the circuit (the ground potential GND or the common ground COM). Potential). In a region HV-MOS 11 is formed to reach the upper surface of the substrate, respectively, n as a first semiconductor region ^- impurity concentration than the layer 110 ^- the layer 110, p-well 111, n of the second semiconductor region An n region 117 and an n ⁺ drain region 118 are formed as high third semiconductor regions. p-well 111, n ^- the n inside the layer 110 ^- is formed in contact with the layer 110. N region 117 is formed at a position sandwiching n ⁻ layer 110 with respect to p well 111. That is, a p-well 111 is disposed on one side and an n region 117 is disposed on the other side so as to sandwich the n ⁻ layer 110.

An n ⁺ source region 112 and a p ⁺ region 113 are further formed inside the p well 111, and a source electrode 114 of the HV-MOS 11 is formed so as to be connected thereto. On the p well 111 between the n ⁺ source region 112 and the n ⁻ layer 110, a gate electrode 116 is formed via a gate insulating film 115. That is, the p well 111 functions as a channel region of the HV-MOS 11. The drain electrode 119 of the HV-MOS 11 is formed so as to be connected to the n ⁺ drain region 118.

A p ⁺ drain region 122, an n ⁺ region 127, and a p ⁺ source region 126 are formed in the n layer 121 where the pMOS transistor of the high voltage side drive signal output CMOS 12 is formed. p ⁺ drain electrode 123 on the drain region 122 is formed, on the p ⁺ source region 126 and n ⁺ region 127 is the source electrode 128 is formed, between the p ⁺ drain region 122 and the p ⁺ source region 126 A gate electrode 125 is formed on the n layer 121 with a gate insulating film 124 interposed therebetween. On the other hand, a p ⁺ region 132, an n ⁺ source region 133, and an n ⁺ drain region 137 are formed in the p well 131 in which the nMOS transistor of the high-voltage side drive signal output CMOS 12 is formed. The source electrode 134 is formed on the p ⁺ region 132 and n ⁺ source region 133 is formed, n ⁺ drain electrode 138 on the drain region 137 is formed between the n ⁺ source region 133 and n ⁺ drain region 137 A gate electrode 136 is formed on the p-well 131 via a gate insulating film 135.

  The drain electrode 119 of the HV-MOS 11 is connected to the pMOS transistor and nMOS transistor gate electrodes 125 and 136 of the high-voltage side drive signal output CMOS 12, and the pMOS transistor source electrode 128 and the high-voltage via the level shift resistor 13. Connect to side floating supply absolute voltage VB.

  FIG. 5 is another schematic cross-sectional view (different from FIG. 4) of the high-voltage side drive unit 101 in the power device drive apparatus 100, and corresponds to the AA or CC cross-section of FIG. In the figure, elements similar to those shown in FIG. A region 14 shown in FIG. 5 shows a high voltage diode (not shown in FIGS. 1 and 2) connected to the high voltage side drive unit 101.

The high breakdown voltage diode (hereinafter referred to as “HV-diode”) 14 has a structure similar to the HV-MOS 11 described above, and an n ⁻ layer 143 as a first semiconductor region, 2 includes a p ⁺ isolation 144 as a semiconductor region, an n layer 121 as a third semiconductor region having an impurity concentration higher than that of the n ⁻ layer 143, and an n ⁺ cathode region 141. The p ⁺ isolation 144 is in contact with one side of the n ⁻ layer 143, and the n layer 121 is in contact with the other side of the n ⁻ layer 143. That is, the p ⁺ isolation 144 and the n layer 121 are formed so as to sandwich the n ⁻ layer 143. Since the p ⁺ isolation 144 functions as the anode of the HV-diode 14, it will be referred to as “p ⁺ anode region 144” hereinafter. The cathode electrode 142 of the HV-diode 14 is formed so as to be connected to the n ⁺ cathode region 141, and the anode electrode 145 is formed to be connected to the p ⁺ anode region 144. The p ⁺ anode region 144 reaches the p ⁻ region 200. An anode electrode 145 is formed on the p ⁺ anode region 144, and the potential of the p ⁻ region 200 is the lowest potential (GND or COM potential) on the circuit. The HV-diode 14 holds a voltage between the high-voltage side floating supply absolute voltage VB and GND or COM.

  6 is a diagram showing a configuration of the HV-MOS according to the first embodiment, and is an enlarged view of the HV-MOS 11 in FIG. Elements similar to those shown in FIG. 4 are given the same reference numerals. However, in this figure, for the convenience of the following explanation, it is drawn with the left and right reversed from FIG.

A first insulating film LA is formed on the n ⁻ layer 110. A plurality of first floating field plates FA (FA1 to FA8) are formed on the upper surface of the first insulating film LA above the n ⁻ layer 110. Further, the second insulating film LB is formed on the first floating field plate FA. On the upper surface of the second insulating film LB, a plurality of second floating field plates FB (FB1 to FB8) are formed above the n ⁻ layer 110.

Here, in this specification, the direction from the third semiconductor region (here, the n region 117) to the second semiconductor region (here, the n ⁺ source region 112) is referred to as a “first direction”, and the first insulating film The thickness direction of LA and the second insulating film LB is referred to as a “second direction” (see the arrow in FIG. 6). The first floating field plates FA1 to FA8 are arranged side by side in the first direction, and the second floating field plates FB1 to FB8 are also arranged side by side in the first direction.

  Further, the drain electrode 119 has a portion DA extending on the first insulating film LA, and this portion functions as a normal (not floating state) field plate. Hereinafter, this part is referred to as “first drain electrode part DA”. On the other hand, the gate electrode 116 has a portion GA extending on the first insulating film LA and a portion GB extending on the second insulating film LB, and this portion also functions as a normal field plate. Hereinafter, both are referred to as “first gate electrode part GA” and “second gate electrode part GB”, respectively.

The first floating field plate FA and the second floating field plate FB promote the spread of the depletion layer in the n ⁻ layer 110 by the field plate effect. Each of the first floating field plate FA and the second floating field plate FB is capacitively coupled to each other via the second insulating film LB to form a plurality of capacitors (capacitors). Further, the second drain side field plate FB1 on the most drain side forms a capacitor with the first drain electrode part DA via the second insulating film LB, and the first insulating film LA8 on the most gate side includes the second insulating film LA8. A capacitor is formed between the second gate electrode portion GB and the insulating film LB. These many capacitors share and hold a high voltage applied between the drain electrode 119 and the source electrode 114 when the HV-MOS is cut off, whereby each of the first floating field plate FA and the second floating field plate. The potential of FB is determined. Thereby, it is suppressed that the expansion of the depletion layer is promoted too much by the field plate effect.

  For example, if it is assumed that the first floating field plate FA is a continuous one, the expansion of the depletion layer is promoted too much, the electric field concentration occurs on the silicon substrate surface near the drain, and the high breakdown voltage of the HV-MOS is increased. It becomes difficult. Therefore, in the present embodiment, a plurality of first floating field plates FA and second floating field plates FB are arranged side by side in the first direction, so that the depletion layer is prevented from spreading too much, and the HV-MOS has a high height. Aiming to withstand pressure.

Further, the HV-MOS in FIG. 6 is applied with a so-called RESURF structure to further increase the breakdown voltage. That is, a pn junction (hereinafter referred to as “first pn junction”) between the n ⁻ layer 110 and the p ⁻ region 200 (fourth semiconductor region) is connected to a pn junction (hereinafter referred to as “first pn junction”) between the n ⁻ layer 110 and the p well 111. By applying a reverse voltage lower than the breakdown voltage of the “second pn junction”), a depletion layer is formed in the n ⁻ layer 110 between the n region 117 and the p well 111 from the first pn junction to the upper surface of the substrate. N ⁻ layer 110 has a low impurity concentration and a small thickness.

  In the present embodiment, the thickness of the first insulating film LA is a, and the second direction between the first floating field plate FA and the second floating field plate FB (the thickness direction of the second insulating film LB) is set. When the distance is b, the first insulating film LA is thicker and the second insulating film LB is thinner than the conventional structure so that a> b.

7 shows a case where the gate electrode 116 and the source electrode 114 are short-circuited in the HV-MOS of FIG. 6 so that the HV-MOS is cut off and a high voltage is applied between the drain electrode 119 and the source electrode 114. It is a figure which shows the electric field distribution inside HV-MOS. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n region 117 and the p ⁻ region 200 is shown. In particular, the solid line indicates the electric field distribution on the silicon substrate surface and the electric field distribution of the first pn junction depth between the n ⁻ layer 110 and the p ⁻ region 200. On the other hand, FIG. 8 shows the same electric field distribution as in FIG. 7 in the conventional HV-MOS (a <b in FIG. 6 and the drain electrode 119 and the second floating field plate FB1 are connected). FIG.

  As can be seen from FIGS. 7 and 8, the portion with the highest electric field strength is a portion near the drain at the first pn junction depth. Accordingly, the breakdown critical electric field point, which is a part that determines the withstand voltage value of the HV-MOS, becomes that portion. On the other hand, on the surface of the silicon substrate, an electric field peak (electric field concentration) is observed below the tip of the first gate electrode portion GA and below the drain side edge or the source side edge of each of the first floating field plates FA1 to FA8. The

  As shown in FIG. 8, in the conventional structure HV-MOS, the electric field peak on the surface of the silicon substrate is relatively large, and the difference (margin) from the electric field strength at the breakdown critical electric field point is small. Therefore, due to the influence of the polarization of the overcoat insulating film and epoxy resin formed on the HV-MOS in actual use, the electric field peak on the surface of the silicon substrate easily exceeds the electric field strength at the breakdown critical electric field point, and the breakdown voltage is reduced. There is concern about the problem of instability.

  On the other hand, in the present embodiment shown in FIG. 7, it can be seen that the electric field peak on the surface of the silicon substrate is relatively small. That is, it can be seen that the electric field concentration is relaxed. Therefore, the margin for the electric field strength at the breakdown critical electric field point is increased, and the electric field peak on the silicon substrate surface is difficult to exceed the electric field strength at the breakdown critical electric field point. As a result, the HV-MOS can stably maintain a high breakdown voltage.

  FIG. 9 is a diagram showing the relationship between ab and the electric field peak value on the silicon substrate surface. It can be seen that the electric field peak value decreases as the value of a−b increases. That is, by increasing the thickness a, decreasing the distance b, and increasing the value of a−b, the margin for the electric field strength at the yield critical field point can be increased, and the above effect can be increased. .

  Further, FIG. 10 is a diagram showing a potential distribution and a current distribution in the HV-MOS when a high voltage is applied between the drain electrode 119 and the source electrode 114 in the cutoff state of the HV-MOS in FIG. The potential distribution is indicated by equipotential lines, and the shape corresponds to the shape of the depletion layer spreading from the source side to the drain side. On the other hand, FIG. 11 shows the same potential distribution and current distribution as in FIG. 10 in a conventional HV-MOS (that is, a <b in FIG. 6).

Reference numerals 0 to 6 in FIG. 10 and FIG. 11 indicate equipotential line intervals on the surface of the silicon substrate (interface between the n ⁻ layer 110 and the first insulating film LA). In the HV-MOS according to the present embodiment, since the thickness a of the first insulating film LA is large, distortion of the equipotential lines is relieved in the first insulating film LA as shown in FIG. Compared to the above, the sizes of the intervals 0 to 6 are uniform. This indicates that in the HV-MOS of this embodiment, the depletion layer spreads more uniformly in the vicinity of the silicon substrate surface than in the conventional structure. If the depletion layer spreads uniformly, electric field concentration is unlikely to occur. Therefore, in the HV-MOS of this embodiment, the magnitude of the electric field peak on the silicon substrate surface can be kept low. Thus, the effect described with reference to FIG. 7 can also be observed from the potential distribution of FIG.

  FIG. 12 shows the first floating field plate FA, the second floating field plate FB, the first drain electrode portion DA, the first gate electrode when a high voltage is applied between the source and drain of the HV-MOS in the cut-off state. 5 shows a drain-source distribution of a potential difference held by each capacitor formed between the portion GA and the second gate electrode portion GB. In FIG. 12, the solid line graph is a distribution graph in the HV-MOS of FIG. 6 according to the present embodiment, and the dotted line is a conventional HV-MOS (a <b in FIG. 2 is a graph of the distribution of the floating field plate FB1). In the HV-MOS having the conventional structure, a particularly high voltage tends to be held in the capacitors near the source side and the drain side, and there is a concern about the dielectric breakdown of the second insulating film LB at that portion. As shown in FIG. 12, the tendency is small in the HV-MOS of this embodiment, and the variation in potential difference held by each capacitor is small. That is, according to the present embodiment, there is also an effect that the dielectric breakdown of the second insulating film LB is less likely to occur, which can contribute to the high breakdown voltage of the HV-MOS.

In the HV-MOS of the present embodiment, the distance b in the thickness direction (second direction) between the first floating field plate FA and the second floating field plate FB is made smaller than in the conventional structure. The capacitance value of each capacitor increases. Therefore, since the capacitive coupling effect in each capacitor is increased, the polarization of the second insulating film LB is promoted. In the conventional structure, the depletion layer above the n ⁻ layer 110 tends to expand below the first floating field plates FA, but tends to hardly expand below the first floating field plates FA. However, in the present embodiment, the second insulating film LB is polarized due to the high capacitive coupling effect in each capacitor, and due to the influence, the depletion layer easily expands even below each first floating field plate FA. This also contributes to the high breakdown voltage of the HV-MOS.

As described above, the present invention can be applied to a semiconductor device having a RESURF structure. Thereby, it is possible to achieve a higher breakdown voltage than the conventional RESURF structure. It is also possible to apply to a so-called multi-RESURF structure (for example, US Pat. No. 4,422,089) in which the n ⁻ layer 110 has a multilayer structure with different impurity concentrations.

  In the above description, an example in which the present invention is applied to a MOSFET has been shown. However, the application of the present invention is not limited to this, and can be widely applied to, for example, a diode or an IGBT. FIG. 13 is a diagram showing an example in which the first embodiment is applied to a high voltage diode (HV-diode), and is an enlarged view of the HV-diode 14 in FIG. The same elements as those shown in FIGS. 5 and 6 are denoted by the same reference numerals, and detailed description thereof will be omitted here. Also in this figure, for the convenience of the following description, the drawing is drawn with the left and right reversed from FIG.

  The cathode electrode 142 has a portion CA extending on the first insulating film LA, and this portion functions as a normal field plate. Hereinafter, this part is referred to as “first cathode electrode part CA”. The anode electrode 145 has a portion AA extending on the first insulating film LA and a portion AB extending on the second insulating film LB, and these portions function as a normal field plate. Hereinafter, they are referred to as “first anode electrode portion AA” and “second anode electrode portion AB”, respectively.

As described above, in the HV-diode 14, the n ⁻ layer 143 functions as the first semiconductor region, the p ⁺ anode region 144 functions as the second semiconductor region, and the n layer 121 functions as the third semiconductor region. The “first direction” is a direction from the n layer 121 toward the p ⁺ anode region 144 (see the arrow in FIG. 13).

A so-called RESURF structure is also applied to the HV-diode 14. That is, the first pn junction between the n ⁻ layer 143 and the p ⁻ region 200 (fourth semiconductor region) has a reverse direction lower than the breakdown voltage of the second pn junction between the n ⁻ layer 143 and the p ⁺ anode region 144. As the voltage is applied, the n ⁻ layer 143 has an extent that the depletion layer extends from the first pn junction to the upper surface of the substrate in the n ⁻ layer 143 between the n layer 121 and the p ⁺ anode region 144. The impurity concentration is low and the thickness is thin.

  Also in the HV-diode of FIG. 13, when the thickness of the first insulating film LA is a and the distance in the second direction between the first floating field plate FA and the second floating field plate FB is b, a> The first insulating film LA is thicker and the second insulating film LB is thinner than the conventional structure so as to be b. Even in an HV-diode where a> b, the electric field peak on the surface of the silicon substrate is lowered, the electric field concentration is relaxed, and problems such as a decrease in breakdown voltage and instability of breakdown voltage characteristics can be suppressed. Can be obtained.

<Embodiment 2>
FIG. 14 is a diagram showing a configuration of the HV-MOS according to the second embodiment. The first embodiment is different from the HV-MOS shown in FIG. 6 in that the drain electrode 119 has a portion DB extending on the second insulating film LB. This part DB functions as a normal (not in a floating state) field plate, and is hereinafter referred to as “second drain electrode part DB”.

As shown in FIG. 14, the length of the portion of the second drain electrode portion DB extending in the first direction (the direction from the n region 117 to the n ⁺ source region 112) above the first insulating film LA is the first drain electrode portion DB. It is longer than the length of the portion extending in the first direction on the first insulating film LA in the electrode portion DA. That is, the second drain electrode portion DB covers the upper portion of the first drain electrode portion DA via the second insulating film LB. A portion of the second drain electrode portion DB overlaps a portion of the first floating field plate FA1 via the second insulating film LB. That is, as shown in FIG. 14, it can be said that the second drain electrode portion DB is obtained by connecting the second floating field plate FB1 to the drain electrode 119 of FIG.

15 shows a state in which the gate electrode 116 and the source electrode 114 are short-circuited in the HV-MOS of FIG. 14 to turn off the HV-MOS and a high voltage is applied between the drain electrode 119 and the source electrode 114. It is a figure which shows the electric field distribution inside HV-MOS. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n region 117 and the p ⁻ region 200 is shown. In particular, the solid line indicates the electric field distribution on the silicon substrate surface and the electric field distribution of the first pn junction depth between the n ⁻ layer 110 and the p ⁻ region 200.

  As can be seen by comparing FIG. 15 with FIG. 7 shown in the first embodiment, according to the present embodiment, the electric field below the edge portion of the first floating field plate FA1 on the most drain side on the silicon substrate surface. The peak is relaxed. Due to the influence, the electric field strength in the vicinity of the breakdown critical electric field point (the portion of the first pn junction depth of the n region 117 on the drain side) is lowered, so that the HV-MOS has a high breakdown voltage. That is, according to the present embodiment, a higher breakdown voltage than that of the first embodiment can be achieved.

  FIG. 16 shows the first floating field plate FA, the second floating field plate FB, the first drain electrode portion DA, the first gate electrode when a high voltage is applied between the source and drain of the HV-MOS in the cut-off state. 5 shows a drain-source distribution of a potential difference held by each capacitor formed between the portion GA and the second gate electrode portion GB. In FIG. 16, a solid line graph is a distribution graph in the HV-MOS of FIG. 14 according to the present embodiment, and a dotted line is a distribution graph in a conventional HV-MOS (in FIG. 14, a <b). is there. It can be seen that also in this embodiment, the variation in potential difference held by each capacitor is reduced as in the first embodiment. That is, also in the present embodiment, the dielectric breakdown of the second insulating film LB is unlikely to occur, which can contribute to the high breakdown voltage of the HV-MOS.

<Embodiment 3>
FIG. 17 is a diagram showing a configuration of the HV-MOS according to the third embodiment. In this figure, elements similar to those shown in FIGS. 6 and 14 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In the present embodiment, the width of each first floating field plate FA and the interval between the first floating field plates FA are made equal. That is, the width of each first floating field plate FA in the first direction (direction from the n region 117 toward the n ⁺ source region 112) is i, and the distance in the first direction between each first floating field plate is j. I = j. In the example of FIG. 17, the relationship between the thickness a (the thickness of the first insulating film LA) and the distance b (the distance in the second direction between the first floating field plate FA and the second floating field plate FB). Is the same as the conventional structure a <b. Points other than the above are the same as those in FIG. 14 described in the second embodiment.

18 shows a HV-MOS of FIG. 17 in which the gate electrode 116 and the source electrode 114 are short-circuited to turn off the HV-MOS, and a high voltage is applied between the drain electrode 119 and the source electrode 114. -It is a figure which shows the electric field distribution inside MOS. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n region 117 and the p ⁻ region 200 is shown. In particular, the solid line indicates the electric field distribution on the silicon substrate surface and the electric field distribution of the first pn junction depth between the n ⁻ layer 110 and the p ⁻ region 200. As can be seen from comparison with FIG. 8 showing the electric field distribution in the HV-MOS of the conventional structure, it can be seen that in FIG. 18 of the present embodiment, the electric field peak on the silicon substrate surface is lowered and the electric field concentration is relaxed. . Therefore, the margin for the electric field strength at the breakdown critical electric field point is increased, and the electric field peak on the silicon substrate surface is difficult to exceed the electric field strength at the breakdown critical electric field point. As a result, the HV-MOS can stably maintain a high breakdown voltage.

FIG. 19 is a diagram showing a potential distribution and a current distribution inside the HV-MOS when a high voltage is applied between the drain electrode 119 and the source electrode 114 in the HV-MOS cutoff state of FIG. Also in FIG. 19, the potential distribution is indicated by equipotential lines, and reference numerals 0 to 6 indicate the interval between the equipotential lines on the silicon substrate surface (interface between the n ⁻ layer 110 and the first insulating film LA). In the present embodiment, the widths of the individual first floating field plates FA are equal to the widths of the first floating field plates FA, so that the intervals 0 to 6 are evenly compared with the conventional FIG. It has become. That is, in the HV-MOS of the present embodiment, the depletion layer spreads more uniformly in the vicinity of the silicon substrate surface than in the conventional structure, and the magnitude of the electric field peak at that portion is kept low. Thus, the above effect can also be observed from the potential distribution of FIG.

  In FIG. 17, the relationship between the thickness a and the distance b is a <b, but a> b may be applied by applying the first embodiment. In that case, the effect described in the first embodiment can also be obtained, and a higher breakdown voltage can be achieved.

  Also in this embodiment, an example in which the present invention is applied to a MOSFET has been shown, but the application of the present invention is not limited thereto, and can be widely applied to, for example, a diode or an IGBT.

<Embodiment 4>
FIG. 20 is a diagram showing a configuration of the HV-MOS according to the fourth embodiment. In this figure, elements similar to those shown in FIGS. 6 and 14 are denoted by the same reference numerals, and detailed description thereof will be omitted.

In addition to the configuration of the HV-MOS of FIG. 6, the HV-MOS according to the present embodiment includes a third insulating film LC formed on the second floating field plate FB and a plurality of second films formed thereon. It has 3 floating field plates FC (FC1 to FC6). Third floating field plate FC is arranged above n ⁻ layer 110 in the first direction (the direction from n region 117 toward n ⁺ source region 112). The thickness of the first insulating film LA is a, and the second direction between the first floating field plate FA and the second floating field plate FB (the first insulating film LA, the second insulating film LB, the third insulating film). If the distance in the thickness direction of the film LC) is b and the distance in the second direction between the second floating field plate FB and the third floating field plate FC is c, then c <a and c <b. In addition, the distance c is made small (the third insulating film LC is made thin). In the example of FIG. 20, the relationship between the thickness a and the distance b is the same as a <b in the conventional structure.

  The drain electrode 119 has a portion DC extending on the third insulating film LC, and this portion functions as a normal (not in a floating state) field plate. Hereinafter, this part is referred to as “third drain electrode portion DC”. On the other hand, the source electrode 114 has a portion SC extending on the third insulating film LC, and this portion also functions as a normal field plate. Hereinafter, this portion is referred to as “source electrode portion SC”.

21 shows a HV-MOS in the case where a high voltage is applied between the drain electrode 119 and the source electrode 114 in the HV-MOS of FIG. 20 by short-circuiting the gate electrode 116 and the source electrode 114 to cut off the HV-MOS. It is a figure which shows the electric field distribution inside MOS. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n region 117 and the p ⁻ region 200 is shown. In particular, the solid line indicates the electric field distribution on the silicon substrate surface and the electric field distribution of the first pn junction depth between the n ⁻ layer 110 and the p ⁻ region 200. As can be seen from comparison with FIG. 8 showing the electric field distribution in the conventional structure HV-MOS, it can be seen in FIG. 21 that the electric field peak on the surface of the silicon substrate is lowered and the electric field concentration is relaxed. Therefore, the margin for the electric field strength at the breakdown critical electric field point is increased, and the electric field peak on the silicon substrate surface is difficult to exceed the electric field strength at the breakdown critical electric field point. As a result, the HV-MOS can stably maintain a high breakdown voltage.

FIG. 22 is a diagram showing a potential distribution and a current distribution when a high voltage is applied between the drain electrode 119 and the source electrode 114 in the HV-MOS cutoff state of FIG. Also in FIG. 22, the potential distribution is indicated by equipotential lines, and reference numerals 0 to 6 indicate the interval between the equipotential lines on the surface of the silicon substrate (interface between the n ⁻ layer 110 and the first insulating film LA). Yes. Compared to the conventional FIG. 11, the equipotential lines on the surface of the silicon substrate are shifted to the drain side, and it can be seen that the depletion layer easily spreads on the surface of the silicon substrate. This indicates that the electric field peak on the surface of the silicon substrate is lowered. Thus, the above effect can also be observed from the potential distribution of FIG.

  Further, in the HV-MOS of the present embodiment, since the distance c is reduced, the HV-MOS is formed by the second floating field plate FB, the third floating field plate FC, the third drain electrode portion DC, and the source electrode portion SC. The capacitance value of each capacitor increases. Accordingly, since the capacitive coupling effect in these capacitors is increased, the polarization of the third insulating film LC is promoted. Due to the influence, an effect that the depletion layer easily expands even between the first floating field plates FA in which the depletion layer is difficult to expand can be obtained, and this can contribute to the high breakdown voltage of the HV-MOS.

  In FIG. 20, the relationship between the thickness a and the distance b is a <b. However, a> b may be applied as shown in FIG. 23 by applying the first embodiment. In that case, the effect described in the first embodiment can also be obtained, and a higher breakdown voltage can be achieved.

FIG. 24 shows the HV− when the gate electrode 116 and the source electrode 114 are short-circuited in the HV-MOS of FIG. 23 to shut off the HV-MOS and a high voltage is applied between the drain electrode 119 and the source electrode 114. It is a figure which shows the electric field distribution inside MOS. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n region 117 and the p ⁻ region 200 is shown. In particular, the solid line indicates the electric field distribution on the silicon substrate surface and the electric field distribution of the first pn junction depth between the n ⁻ layer 110 and the p ⁻ region 200. Further, it can be seen that the electric field peak on the surface of the silicon substrate is lowered and the electric field concentration is relaxed.

  FIG. 25 is a diagram showing a potential distribution and a current distribution in the HV-MOS when a high voltage is applied between the drain electrode 119 and the source electrode 114 in the cutoff state of the HV-MOS in FIG. The potential distribution is indicated by equipotential lines, and reference numerals 0 to 6 indicate the intervals of the equipotential lines on the surface of the silicon substrate. In the HV-MOS of FIG. 23, since the thickness a of the first insulating film LA is large, distortion of equipotential lines is relieved in the first insulating film LA, so that the intervals 0 to 6 are more even than those in FIG. It has become. Therefore, it can be seen that the magnitude of the electric field peak on the surface of the silicon substrate can be kept low.

  As described above, by applying the first embodiment, it is possible to further increase the breakdown voltage. In the above description, an example in which the present invention is applied to a MOSFET has been shown. However, the application of the present invention is not limited to this, and can be widely applied to, for example, a diode or an IGBT.

<Embodiment 5>
FIG. 26 is a diagram showing a configuration of the HV-MOS according to the fifth embodiment. In this figure, elements similar to those shown in FIGS. 6 and 14 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the present embodiment, the first floating field plate FA and the second floating field plate FB are wider than the conventional structure. That is, in each first floating field plate FA, the width in the first direction of the portion that overlaps one second floating field plate FB via the second insulating film LB is defined as g, and between each second floating field plate FB. If the distance in the first direction is h, then g> h (see FIG. 26).

  In the example of FIG. 26, the relationship between the thickness a (the thickness of the first insulating film LA) and the distance b (the distance in the second direction between the first floating field plate FA and the second floating field plate FB). Is the same as the conventional structure a <b.

  Points other than the above are the same as those in FIG. 14 described in the second embodiment.

  According to this embodiment, since the width of the portion where the first floating field plate FA and the second floating field plate FB overlap is wide, each capacitor formed by the first floating field plate FA and the second floating field plate. The capacitance value becomes larger than that of the conventional structure. Therefore, since the capacitive coupling effect in each capacitor is increased, the polarization of the second insulating film LB is promoted. As a result, an effect that the depletion layer easily expands even between the first floating field plates FA can be obtained, which can contribute to a high breakdown voltage of the HV-MOS.

  In addition, since the capacitive coupling effect of each capacitor is increased, the variation in potential difference held by each capacitor is reduced between the source and the drain, and the second dielectric film LB is less likely to be broken down.

  Also in this embodiment, an example in which the present invention is applied to a MOSFET has been shown, but the application of the present invention is not limited thereto, and can be widely applied to, for example, a diode or an IGBT.

<Embodiment 6>
FIG. 27 is a diagram showing a configuration of the HV-MOS according to the sixth embodiment. In this figure, the same elements as those shown in FIG. 20 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The HV-MOS of FIG. 27 is obtained by eliminating the first floating field plate FA from the structure of FIG. When the thicknesses of the first insulating film LA and the second insulating film LB are a and b, respectively, and the distance in the second direction between the second floating field plate FB and the third floating field plate FC is c, a + b > C. That is, the second floating field plate FB and the third floating field plate FC of FIG. 27 function in the same manner as the first floating field plate FA and the second floating field plate FB of the first embodiment (FIG. 6), respectively. . Therefore, the HV-MOS can stably maintain a high breakdown voltage as in the first embodiment.

  In addition, the drain electrode 119 has a first drain electrode portion DA extending on the first insulating film LA. The first drain electrode portion DA extends in the first direction on the first insulating film LA so that a part thereof overlaps a part of the second floating field plate FB1 via the second insulating film LB. Further, the length of the portion of the third drain electrode portion DC that extends in the first direction above the first insulating film LA is the length of the portion of the first drain electrode portion DA that extends in the first direction on the first insulating film LA. It is longer than the length and longer than the length of the portion extending in the first direction above the first insulating film LA in the second drain electrode portion DB. That is, the third drain electrode portion DC covers the first drain electrode portion DA and the second drain electrode portion DB.

FIG. 28 shows the HV-MOS of FIG. 27 when the gate electrode 116 and the source electrode 114 are short-circuited to turn off the HV-MOS and a high voltage is applied between the drain electrode 119 and the source electrode 114. -It is a figure which shows the electric field distribution inside MOS. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n region 117 and the p ⁻ region 200 is shown. In particular, the solid line indicates the electric field distribution on the silicon substrate surface and the electric field distribution of the first pn junction depth between the n ⁻ layer 110 and the p ⁻ region 200. As in the first embodiment, it can be seen that the electric field peak on the surface of the silicon substrate is lowered and the electric field concentration is relaxed.

  Further, the electric field peak on the most drain side on the surface of the silicon substrate is below the drain side edge of the second floating field plate FB2, and no peak appears under the edge of the second floating field plate FB1. This is because the first drain electrode portion DA functioning as a normal field plate extends to a position overlapping with a part of the second floating field plate FB1. In addition, since the third drain electrode portion DC extends long above the first insulating film LA so as to cover the first drain electrode portion DA and the second drain electrode portion DB, the vicinity of the drain electrode on the silicon substrate surface The electric field concentration is further relaxed. Therefore, since the electric field strength in the vicinity of the breakdown critical electric field point (the portion of the first pn junction depth of the n region 117 on the drain side) decreases, the withstand voltage value of the HV-MOS increases. That is, according to the present embodiment, a higher breakdown voltage than that of the first embodiment can be achieved.

  FIG. 29 is a diagram illustrating a modification in which the second embodiment is applied to the present embodiment. That is, the difference from the structure of FIG. 27 is that the drain electrode 119 has a second drain electrode portion DB extending on the second insulating film LB. As shown in FIG. 29, the length of the portion extending in the first direction above the first insulating film LA in the second drain electrode portion DB is the same as the length in the first direction on the first insulating film LA in the first drain electrode portion DA. Longer than the length of the part extending to That is, the second drain electrode portion DB covers the upper portion of the first drain electrode portion DA via the second insulating film LB. As shown in FIG. 29, it can be said that the second drain electrode portion DB is obtained by connecting the drain electrode 119 and the second floating field plate FB1 of FIG.

  30 shows a case where the gate electrode 116 and the source electrode 114 are short-circuited in the HV-MOS of FIG. 29 so that the HV-MOS is cut off and a high voltage is applied between the drain electrode 119 and the source electrode 114. It is a figure which shows the electric field distribution inside HV-MOS. In FIG. 30, similarly to FIG. 28, the electric field peak on the most drain side on the surface of the silicon substrate is below the drain side edge of the second floating field plate FB2, and the peak appears below the edge of the second floating field plate FB1. Absent. Therefore, the electric field strength in the vicinity of the breakdown critical electric field point becomes low, and the withstand voltage value of the HV-MOS becomes high. That is, according to this modification, it is possible to further increase the breakdown voltage as compared with the second embodiment.

  Also in this embodiment, an example in which the present invention is applied to a MOSFET has been shown, but the application of the present invention is not limited thereto, and can be widely applied to, for example, a diode or an IGBT.

<Embodiment 7>
FIG. 31 is a diagram showing a configuration of the HV-MOS according to the seventh embodiment. In this figure, elements similar to those shown in FIGS. 6 and 14 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the HV-MOS according to the present embodiment, the drain electrode 119 has a first drain electrode portion DA extending on the first insulating film LA and a second drain electrode portion DB extending on the second insulating film LB. The first drain electrode portion DA and the second drain electrode portion DB are extended longer than the conventional structure. As shown in FIG. 31, when the length of the portion extending in the first direction on the first insulating film LA in the first drain electrode portion DA is d, the first insulating film LA in the second drain electrode portion DB. The length of the portion extending upward in the first direction is longer than the length d by the length e. At this time, the length d is made sufficiently large so that d> e. In the example of FIG. 31, the relationship between the thickness a of the first insulating film LA and the distance b in the second direction between the first floating field plate FA and the second floating field plate FB is the same as in the conventional structure. a <b. As shown in FIG. 31, the first drain electrode portion DA is obtained by connecting the drain electrode 119 of FIG. 6 to the first floating field plate FA1, and the second drain electrode portion DB is formed by connecting the drain electrode 119 of FIG. It can also be said that the drain electrode 119 is connected to the second floating field plates FB1, FB2.

FIG. 32 shows a HV-MOS in FIG. 31 when the gate electrode 116 and the source electrode 114 are short-circuited to turn off the HV-MOS and a high voltage is applied between the drain electrode 119 and the source electrode 114. -It is a figure which shows the electric field distribution inside MOS. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n region 117 and the p ⁻ region 200 is shown. In particular, the solid line indicates the electric field distribution on the silicon substrate surface and the electric field distribution of the first pn junction depth between the n ⁻ layer 110 and the p ⁻ region 200. The electric field peak on the most drain side on the surface of the silicon substrate is below the drain side edge of the first floating field plate FA2.

  For example, as can be seen from comparison with FIG. 7 and the like, according to the present embodiment, the electric field peak on the most drain side moves away from the breakdown critical electric field point (the portion of the first pn junction depth of the n region 117 on the drain side). It will be. Therefore, the electric field strength in the vicinity of the breakdown critical electric field point is reduced, and the withstand voltage value of the HV-MOS is increased.

In FIG. 31, the relationship between the thickness a and the distance b is a <b. However, a> b may be applied as shown in FIG. 33 by applying the first embodiment. FIG. 34 shows a state where the gate electrode 116 and the source electrode 114 are short-circuited in the HV-MOS of FIG. 33 so that the HV-MOS is cut off, and a high voltage is applied between the drain electrode 119 and the source electrode 114. It is a figure which shows the electric field distribution inside HV-MOS. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n region 117 and the p ⁻ region 200 is shown. In particular, the solid line indicates the electric field distribution on the silicon substrate surface and the electric field distribution of the first pn junction depth between the n ⁻ layer 110 and the p ⁻ region 200. Overall, it can be seen that the electric field peak on the silicon substrate surface is lower than that in FIG. 32 and the electric field concentration is relaxed. Therefore, if the first embodiment is applied, it is possible to further increase the breakdown voltage.

  The application of the present invention is not limited to MOSFETs, and can be widely applied to, for example, diodes and IGBTs. FIG. 35 is a diagram showing an example in which the present embodiment is applied to a high voltage diode (HV-diode), and is an enlarged view of the HV-diode 14 in FIG. The same elements as those shown in FIGS. 5 and 13 are denoted by the same reference numerals, and detailed description thereof will be omitted here. Also in this figure, for the convenience of the following description, the drawing is drawn with the left and right reversed from FIG. The HV-diode in FIG. 35 is different from the structure of a conventional HV-diode (a <b in FIG. 13 shown in Embodiment 1) in that the first cathode electrode portion CA and the second cathode electrode portion CB are As in the case of the first drain electrode portion DA and the second drain electrode portion DB of FIG.

FIG. 36 is a diagram showing an electric field distribution in the HV-diode when a reverse voltage is applied between the cathode electrode 142 and the anode electrode 145 in the HV-diode of FIG. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n layer 121 and the p ⁻ region 200 is shown. In particular, the solid line shows the electric field distribution on the surface of the silicon substrate and the electric field distribution of the first pn junction depth between the n ⁻ layer 143 and the p ⁻ region 200. Moreover, this figure has shown the electric field distribution in CC cross section (namely, corner part of a high potential island) of FIG. The electric field peak on the most cathode side on the surface of the silicon substrate is below the edge on the cathode side of the first floating field plate FA2, and is in the vicinity of the breakdown critical electric field point (the portion of the first pn junction depth of the n layer 121 on the cathode side). Electric field strength is reduced.

  On the other hand, FIG. 37 is a diagram showing an electric field distribution similar to that in FIG. 36 in a conventional HV-diode (a <b in FIG. 13 shown in the first embodiment). This figure also shows the electric field distribution in the CC cross section (corner portion of the high potential island) in FIG. The electric field peak on the most cathode side on the surface of the silicon substrate is under the edge on the drain side of the second floating field plate FB1, which was not shown in FIG.

  As can be seen by comparing FIG. 36 and FIG. 37, according to the present embodiment, the electric field peak on the most cathode side moves away from the critical critical electric field point. Therefore, the electric field strength in the vicinity of the breakdown critical electric field point is higher than that in the case of the HV-diode in FIG. Therefore, the HV-diode of FIG. 35 to which this embodiment is applied can obtain a higher withstand voltage.

  Generally, the electric field peak on the silicon substrate surface on the cathode side of the HV-diode (drain side in the case of HV-MOS) tends to increase due to the shape of the corner portion of the high potential island. For example, also in FIG. 37, it is observed that the electric field peak on the most cathode side on the surface of the silicon substrate is larger than the electric field peak on the most anode side. Therefore, conventionally, there has been a concern about a decrease in breakdown voltage due to an increase in the electric field strength in the vicinity of the breakdown critical electric field point in the HV-diode or HV-MOS formed in the corner portion. According to the present embodiment, the electric field strength in the vicinity of the breakdown critical electric field point of the HV-diode or HV-MOS can be kept low, so that the application to the HV-diode or HV-MOS at the corner is particularly effective. is there.

<Eighth embodiment>
In the eighth embodiment, an example in which the seventh embodiment is applied to the sixth embodiment will be described. FIG. 38 is a diagram showing a configuration of the HV-MOS according to the present embodiment. In this figure, elements similar to those shown in FIGS. 6 and 29 are denoted by the same reference numerals, and detailed description thereof will be omitted.

  In the HV-MOS according to the present embodiment, each of the first drain electrode portion DA, the second drain electrode portion DB, and the third drain electrode portion DC is extended longer than the structure of FIG. As shown in FIG. 38, if the length of the portion extending in the first direction on the first insulating film LA in the first drain electrode portion DA is d, the upper portion of the first drain electrode portion DB above the first insulating film LA is defined as d. The length of the portion extending in the first direction is longer than the length d by the length e. The length of the portion of the third drain electrode portion DC extending in the first direction above the first insulating film LA is longer than the length d + e by the length f. At this time, the length d is sufficiently large so that d> e and d> f.

  As shown in FIG. 38, the second drain electrode portion DB is obtained by connecting the drain electrode 119 of FIG. 29 to the second floating field plates FB1 and FB2, and the third drain electrode portion DC is It can also be said that the third floating field plate FC1 is connected to the drain electrode 119 of FIG.

FIG. 39 shows the HV-MOS when the gate electrode 116 and the source electrode 114 are short-circuited in the HV-MOS of FIG. 38 to turn off the HV-MOS and a high voltage is applied between the drain electrode 119 and the source electrode 114. It is a figure which shows the electric field distribution inside MOS. In the figure, the electric field distribution from the silicon substrate surface (Si surface) to the pn junction depth between the n region 117 and the p ⁻ region 200 is shown. In particular, the solid line indicates the electric field distribution on the silicon substrate surface and the electric field distribution of the first pn junction depth between the n ⁻ layer 110 and the p ⁻ region 200. The electric field peak on the most drain side on the surface of the silicon substrate is below the edge on the drain side of the second floating field plate FB3. As can be seen from comparison with FIG. 30, in this embodiment as well, the electric field peak on the most drain side is the breakdown critical electric field point (the portion of the first pn junction depth of the drain-side n region 117). It will be away from. Therefore, the electric field strength in the vicinity of the breakdown critical electric field point is reduced, and the withstand voltage value of the HV-MOS is increased.

  As described above, the electric field peak on the silicon substrate surface on the cathode side of the HV-diode (drain side in the case of HV-MOS) tends to increase at the corner portion of the high-potential island, and there is a concern that the withstand voltage may be lowered. It had been. According to the present embodiment, the electric field strength in the vicinity of the breakdown critical electric field point of the HV-diode or HV-MOS can be kept low, so that the application to the HV-diode at the corner portion of the high potential island is particularly effective. is there.

<Modification>
In each of the above embodiments, the present invention is applied to a horizontal device to which the RESURF structure is applied. However, the present invention can also be applied to a vertical device. Here, a modification in which the first embodiment is applied to a vertical device will be described.

  FIG. 40 is a top view of a vertical HV-MOS chip, and FIG. 41 is an enlarged cross-sectional view of the chip outer peripheral portion (edge termination portion) along the line DD. In FIG. 40 and FIG. 41, the same symbols are attached to the same elements. In both figures, elements having the same functions as those in FIG. 6 are denoted by the same reference numerals.

  As shown in FIG. 40, in the vertical HV-MOS, a source electrode 114 and a gate electrode 116 are disposed on the top surface of the chip, and a drain electrode (not shown) is disposed on the back surface side. A channel stopper layer 211 (see FIG. 41) is formed on the outer peripheral portion of the upper surface of the chip, and an electrode 212 (referred to as “channel stopper electrode”) is formed thereon.

In the vertical HV-MOS, unlike the vertical HV-MOS described in the first to eighth embodiments, the n ⁻ layer 210 as the first semiconductor region is formed on the n ⁺ substrate 220. That is, no p ⁻ region (fourth semiconductor region) is formed under the n ⁻ layer 210. The n ⁺ substrate 211 functions as the drain of the HV-MOS, and the drain electrode 221 is formed on the back side of the n ⁺ substrate 211. In the n ⁻ layer 210, a p well 111 as a second semiconductor region is formed, and a p ⁺ region 113 is formed therein. A gate electrode 116 is formed above the p well 111 via a first insulating film LA, and a source electrode 114 is formed above the p well 111 and the p ⁺ region 113. A channel stopper layer 211 as a third semiconductor region is formed on the chip outer periphery of the n ⁻ layer 210, and a channel stopper electrode 212 is formed thereon. The p well 111 and the channel stopper layer 211 are formed so as to sandwich the n ⁻ layer 210.

A plurality of first floating field plates FA are formed above the n ⁻ layer 210 between the wiring portion of the gate electrode 116 and the channel stopper electrode 212 via the first insulating film LA. Further, a second insulating film LB is formed on the first floating field plate FA, and a plurality of second floating field plates FB are formed on the second insulating film LB. As shown in FIG. 41, the first floating field plate FA and the second floating field plate FB are arranged in the first direction from the third semiconductor region (channel stopper layer 211) to the second semiconductor region (p well 111). (In FIG. 40, the first floating field plate FA and the second floating field plate FB are simplified).

  In the present modification, as in the first embodiment, the thickness of the first insulating film LA is a, and the second direction between the first floating field plate FA and the second floating field plate FB (the first insulating film LA). When the distance in the thickness direction of the second insulating film LB is b, the first insulating film LA is thicker and the second insulating film LB is thinner than the conventional structure so that a> b. .

Thus, by applying the first embodiment to the vertical HV-MOS, the electric field concentration at the interface between the first insulating film LA and the n ⁻ layer 210 when the HV-MOS is cut off is alleviated. Therefore, the HV-MOS can stably maintain a high breakdown voltage at the outer periphery of the chip, and can achieve a high breakdown voltage of the vertical HV-MOS.

  Although an example in which the present invention is applied to a vertical HV-MOS is shown here, the present invention can be applied to all vertical power devices such as IGBTs and diodes, and similar effects can be obtained. Moreover, in this modification, although only the case where Embodiment 1 was applied was shown, it cannot be overemphasized that other Embodiment may be applied.

110 n ⁻ layer, 111 p well, 112 n ⁺ source region, 113 p ⁺ region, 114 source electrode, 115 gate insulating film, 116 gate electrode, 117 n region, 118 n ⁺ drain region, 119 drain electrode, 121 n layer 141 n ⁺ cathode region, 142 cathode electrode, 143 n ⁻ layer, 144 p ⁺ anode region, 145 anode electrode, 200 p ⁻ region, 201 p ⁺ separation, 212 channel stopper electrode, 211 channel stopper layer, 210 n ⁻ layer LA first insulating film, LB second insulating film, LC third insulating film, FA first floating field plate, FB second floating field plate, FC third floating field plate, DA first drain electrode part, DB second Drain electrode part, DC third drain electrode part, CA first capacitor Over cathode electrode portion, CB second cathode electrode portion.

Claims (6)

A first semiconductor region of a first conductivity type;
A second conductivity type second semiconductor region formed so as to sandwich the first semiconductor region, and a first conductivity type third semiconductor region having an impurity concentration higher than that of the first semiconductor region;
An electrode formed on the third semiconductor region;
A first insulating film formed on the first semiconductor region;
A second insulating film formed on the first insulating film;
A plurality of second floating field plates formed on the second insulating film and arranged side by side in a first direction from the third semiconductor region to the second semiconductor region above the first semiconductor region;
A third insulating film formed on the second floating field plate;
A semiconductor device comprising a plurality of third floating field plates formed on the third insulating film and arranged in the first direction above the first semiconductor region;
The electrode includes a first electrode portion extending in the first direction on the first insulating film, a second electrode portion extending on the second insulating film, and a third electrode portion extending on the third insulating film. Have
The length of the portion extending in the first direction above the first insulating film in the third electrode portion is longer than the length of the portion extending in the first direction on the first insulating film in the first electrode portion. A semiconductor device , wherein the length of the second electrode portion is longer than a length of a portion extending in the first direction above the first insulating film in the second electrode portion . The semiconductor device according to claim 1,
The thickness of the first insulating film is a, the thickness of the second insulating film is b, and the distance between the second floating field plate and the third floating field plate in the second direction is the thickness direction. c
a + b> c
A semiconductor device. A first semiconductor region of a first conductivity type;
A second conductivity type second semiconductor region formed so as to sandwich the first semiconductor region, and a first conductivity type third semiconductor region having an impurity concentration higher than that of the first semiconductor region;
An electrode formed on the third semiconductor region;
A first insulating film formed on the first semiconductor region;
A second insulating film formed on the first insulating film;
A plurality of second floating field plates formed on the second insulating film and arranged side by side in a first direction from the third semiconductor region to the second semiconductor region above the first semiconductor region;
A third insulating film formed on the second floating field plate;
A semiconductor device comprising a plurality of third floating field plates formed on the third insulating film and arranged in the first direction above the first semiconductor region;
The electrode has a first electrode portion extending on the first insulating film and a second electrode portion extending on the second insulating film,
The length of the portion of the second electrode portion extending in the first direction above the first insulating film is longer than the length of the portion of the first electrode portion extending in the first direction on the first insulating film. Too long
A semiconductor device. The semiconductor device according to claim 3,
The electrode further includes a third electrode portion extending on the third insulating film,
The length of the portion of the third electrode portion extending in the first direction above the first insulating film is longer than the length of the portion of the second electrode portion extending in the first direction above the first insulating film. Is even longer
A semiconductor device. The semiconductor device according to claim 4,
The length of the portion extending in the first direction on the first insulating film in the first electrode portion is d,
The length of the portion extending in the first direction above the first insulating film in the second electrode portion is longer by the length e than the length d,
When the length of the portion extending in the first direction above the first insulating film in the third electrode portion is longer than the length d + e by the length f,
d> e and d> f.
A semiconductor device. A semiconductor device according to any one of claims 3 to 5,
The thickness of the first insulating film is a, the thickness of the second insulating film is b, and the distance between the second floating field plate and the third floating field plate in the second direction is the thickness direction. c
a + b> c
A semiconductor device.

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