JP5269294B2 - Electrostatic discharge protection element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrostatic discharge protection element which can be applied to a pad applied by supply voltage without generating the local teardown of the element. <P>SOLUTION: This element suppresses a generation of excessive current by a positive feedback of PNPN bonding and depletion controlling resistance. In a well of 1st conduction type, a 1st diffusion layer of the 1st conduction type is formed; and in a well of the 2nd conduction type, a 2nd diffusion layer of the 1st conduction type, a 3rd diffusion layer of the 2nd conduction type, and a 4th diffusion layer, are formed. The well of the 2nd conduction type includes a narrow width switching passage between the 3rd and 4th diffusion layers. <P>COPYRIGHT: (C)2006,JPO&amp;NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to an electrostatic discharge protection device for protecting an integrated circuit from electrical stress.

  Semiconductor integrated circuits are sensitive to high voltage and high current that are caused by instantaneous static discharge (ESD) and electrical over stress (EOS) generated by contact with the human body or abnormality of equipment. Affected by. Static electricity or an overload phenomenon causes a high voltage or high current to flow into an integrated circuit at a time, so that it induces breakdown of an insulating film formed in the integrated circuit, breakdown of a junction, and / or disconnection of a metal wiring, etc. The result is a permanent destruction of the integrated circuit.

  The electrostatic discharge protection element performs a function of discharging so that a high voltage or a high current that is instantaneously flown therein does not flow into the semiconductor integrated circuit. As a means for performing such an electrostatic discharge protection function, a silicon controlled rectifier (SCR) is known to be effective.

  FIG. 1 is a diagram illustrating an electrostatic discharge protection element using a general silicon controlled rectifier.

  Referring to FIG. 1, in the silicon controlled rectifier, a high concentration n-type first diffusion layer 2 and a p-type second diffusion layer 4 are formed in an n-well 10 formed on a semiconductor substrate, and the p-well 12 is also high. A concentration n-type third diffusion layer 6 and a p-type fourth diffusion layer 8 are formed. The first and second diffusion layers 2 and 4 are electrically connected to a first pad 13 to which a power supply voltage VDD is applied, and the third and fourth diffusion layers 6 and 8 are second to which a ground voltage is applied. It is electrically connected to the pad 14. The silicon controlled rectifier includes a PNP bipolar transistor Q1, an n-type third diffusion layer 6, and a p-well 12 having the p-type second diffusion layer 4, the n-well 10 and the p-well 12 as an emitter region, a base region and a collector region, respectively. And an NPN bipolar transistor Q2 having an n well 10 as an emitter region, a base region and a collector region, respectively. The p-well 12 functions as a collector region of the PNP bipolar transistor Q1 or a base region of the NPN bipolar transistor Q2. The path of the PNPN junction from the first pad 13 to the second pad 14 includes the second diffusion layer 4, the n well 10, the p well 12, and the third diffusion layer 6. The path of the PNPN junction constitutes a silicon controlled rectifier SCR. If a positive voltage is applied through the first pad 13 and the second pad 14 is grounded, the PN junction between the p-type second diffusion layer 4 and the n-well 10 and the p-well 12 and the n-type are used. The PN junction with the third diffusion layer 6 is forward biased, and the NP junction between the n well 10 and the p well 12 is reverse biased.

  If ESD current flows into the first pad 13 due to electrostatic discharge, the breakdown of the reverse biased NP junction turns on the PNP bipolar transistor Q1 and the NPN bipolar transistor Q2, and the reverse biased NP junction is forward biased. Discharge through the second pad 14 by positive feedback acting like a bonded junction. At this time, the voltage at which the reverse-biased NP junction composed of the n-well 10 and the p-well 12 breaks down becomes the trigger voltage of the silicon controlled rectifier. When the silicon controlled rectifier is triggered, the ESD current is instantaneously discharged by a strong snap back operation in which the voltage across the NP junction suddenly decreases.

  FIG. 2 is a graph showing current-voltage characteristics of a conventional electrostatic discharge protection element. In the graph, line A is the current-voltage curve of the silicon controlled rectifier, and line B is the current-voltage curve of the PN junction diode.

Referring to FIG. 2, in the case of the silicon controlled rectifier A, the externally applied voltage is mainly applied to the reverse biased NP junction, and the silicon controlled rectifier is very small as a high impedance state below the trigger voltage V _T. Current is shown (region (1)). If the voltage rises to the trigger voltage V _T of the silicon controlled rectifier due to ESD, the ESD current is discharged by a strong snapback operation ((2) region). If the voltage by means of a snap-back operation is them moved down to hold the voltage V _H, the silicon controlled rectifier can discharge a large amount of ESD current at a low impedance state. Such a low impedance state continues until the voltage drops below the hold voltage V _H or until the current decreases below the hold current I _H. Therefore, the silicon controlled rectifier is applied to a pad to which a voltage equal to or higher than the hold voltage V _H is applied when a continuous charge such as EOS is flown, or the current of the substrate or the wiring due to excessive current is applied. Can induce geothermal destruction.

In the case of the PN junction diode B, the PN junction reversely biased with the trigger voltage V _T is broken down and the current increases. However, unlike silicon controlled rectifiers, after the reverse-biased PN junction breaks down, it enters a positive impedance state and the current increases gradually with increasing voltage. Therefore, local thermal destruction due to excessive current can be prevented, but it is not effective for discharging a large amount of electric charge supplied instantaneously.

  An object of the present invention is to provide an electrostatic discharge protection element that does not cause local destruction of the element.

  Another object of the present invention is to provide an electrostatic discharge protection element that can be applied to a pad to which a power supply voltage is applied.

  In order to achieve the above object, the present invention provides an electrostatic discharge protection element in which the generation of excessive current is suppressed by positive feedback of a PNPN junction and a depletion control resistor. The element includes a first pad and a second pad, a first conductivity type well formed in a semiconductor substrate, and a second conductivity type well formed in contact with the first conductivity type well. A first conductive type first diffusion layer is formed in the first conductive type well and electrically connected to the first pad, and a first conductive type second diffusion layer is formed in the second conductive type well. And electrically connected to the second pad. A second conductivity type third diffusion layer and a fourth diffusion layer are formed in the second conductivity type well. The third diffusion layer is electrically connected to the first pad, and the fourth diffusion layer is electrically connected to the second pad. The second conductivity type well may include a narrow switching path between the third and fourth diffusion layers.

  More specifically, the switching path is fully depleted when a normal operating voltage is applied to the first pad and the second pad. When a positive voltage and a ground voltage are applied to the first pad and the second pad, respectively, the depletion region width formed at the junction between the first conductivity type well and the second conductivity type well is twice as large as the depletion region width. When the width of the switching path is small, the switching path can be completely depleted.

  The switching path may be located between the third diffusion layer and the fourth diffusion layer, and the second conductivity type well may include a plurality of switching paths. The first diffusion layer may be located between the third diffusion layer and the fourth diffusion layer.

  The second conductivity type well may be formed in the first conductivity type well or may be formed in contact with a sidewall of the first conductivity type well. For example, the second conductivity type well includes a first well formed in contact with a sidewall of the first conductivity type well and a second well formed in the first conductivity type well and connected to the first well. Can be included. In this case, the third and fourth diffusion layers may be formed in different second conductivity type wells.

  In the present invention, the switching path can provide a current path in a positive impedance state as a well depletion control resistor controlled by a depletion layer when charge flows by ESD or EOS.

  According to the present invention, when a normal operation voltage is applied by forming a switching path in the second conductivity type well constituting the electrostatic discharge protection element, the current path is interrupted, and a large amount of charge is generated by the high voltage or high current. When inflowing, a current path is formed. This not only repeats the snapback operation and the positive impedance state to discharge the instantaneous ESD, but also discharges the charge without generating excessive current even when an EOS pulse to which a large amount of charge is supplied is applied. can do.

  In addition, the silicon controlled rectifier is not suitable for application to the power supply voltage pad because it has a low hold voltage, but the electrostatic discharge protection element of the present invention is also applied to the pad to which the power supply voltage is applied. Can be protected.

  Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein, and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content will be thorough and complete, and will fully convey the spirit of the invention to those skilled in the art. In the figures, the thickness of layers and regions are exaggerated for clarity. When a layer is referred to as being “on” another layer or substrate, it can be formed directly on the other layer or substrate, or a third layer is interposed therebetween It is also possible. Also, when a component is referred to as adjacent to another component, it can be in direct contact with the other component, or is spaced apart by a third component therebetween. It can be. Parts denoted by the same reference numerals throughout the specification indicate the same components.

  FIG. 3 is a plan view showing the electrostatic discharge preventing element according to the first embodiment of the present invention.

  4A to 4C are cross-sectional views taken along lines I-I ', II-II ", and III-III' of FIG.

  Referring to FIGS. 3 and 4A to 4C, the device includes a first conductivity type well 50 formed on a substrate, and a second conductivity type well 52 formed by bonding to the first conductivity type well 50. Including. A first conductivity type first diffusion layer 54 is formed in the first conductivity type well 50, and a first conductivity type second diffusion layer 56 and a second conductivity type are formed in the second conductivity type well 52. A third diffusion layer 58 and a second conductivity type fourth diffusion layer 60 are formed. The first conductive type second diffusion layer 56 and the second conductive type fourth diffusion layer 60 may be formed adjacent to each other. In addition, the second diffusion layer 56 may be located between the first diffusion layer 54 and the fourth diffusion layer 60. The second conductivity type well 52 may include a switching path 52a having a narrow width W. The switching path 52 a may be located between the second diffusion layer 56 and the third diffusion layer 58. The first diffusion layer 54 may be formed in the first conductivity type well 50 adjacent to the switching path 52a. In the present invention, the second conductivity type well 52 may include a plurality of switching paths 52a. At this time, the first diffusion layer 54 may be located between the switching paths 52a. That is, the present invention may include a plurality of first diffusion layers 54 formed in the first conductivity type well 50 between the plurality of switching paths 52a.

  In this element, the second diffusion layer 56, the second conductivity type well 52, and the first conductivity type well 50 constitute an emitter region, a base region, and a collector region of an NPN bipolar transistor, respectively. The second conductivity type well 52 in which the layer 58 is formed, the first conductivity type well 50 and the second conductivity type well 52 in which the fourth diffusion layer 60 is formed are respectively an emitter region and a base of a PNP bipolar transistor. A region and a collector region are formed.

  The first diffusion layer 54 and the third diffusion layer 58 may be electrically connected to the first pad 64, and the second diffusion layer 56 and the fourth diffusion layer 60 may be electrically connected to the second pad 66. Can be linked to. A positive voltage such as a power supply voltage can be applied to the first pad 64, and a ground voltage can be applied to the second pad 66. When a positive voltage is applied to the first pad 64 and a ground voltage is applied to the second pad 66, the junction composed of the first conductivity type well 50 and the second conductivity type well 52 is reverse-biased. As a result, a depletion layer is formed. In the present invention, when a normal operating voltage is applied to the first pad 64 and the second pad 66, the switching path 52a is turned off and the current path from the first pad 64 to the second pad 66 is preferably cut off. . As a method for cutting off the current path, a method of completely depleting the switching path 52a can be applied. When a positive voltage and a ground voltage are connected to the first pad 64 and the second pad 66, if the width of the switching path 52a is smaller than twice the depletion region width, both junctions of the switching path 52a The switching path 52a can be completely depleted due to the extended depletion region. Accordingly, when a normal driving voltage is applied to the first pad 64 and the second pad 66, the current path from the first pad 64 to the second pad 66 is blocked by the fully depleted switching path 52a. be able to.

  5A to 5C and FIGS. 6A to 6C are diagrams for explaining the operation of the electrostatic discharge preventing device according to the first embodiment of the present invention.

  5A to 5C, when a positive voltage and a ground voltage, which are normal driving voltages, are applied to the first pad 64 and the second pad 66, the n-type well 50 and the p-type well 52 are used. The NP junction consisting of is reverse-biased, and the depletion layer 70 is expanded in the switching path 52a to form a fully depleted region connected to each other. In this state, the current path from the first pad 64 to the second pad 66 is interrupted.

  Referring to FIGS. 6A to 6C, if an abnormal high voltage or high current flows through the first pad 64, the reverse biased NP junction is broken down so that the PNP bipolar transistor Q3 and the NPN bipolar transistor Q4 The second conductive type well 52 on the first pad 64 side, the first conductive type well 50, the second conductive type well 52 on the second pad 66 side, and the second diffusion layer 56 are turned on. The electric charge is discharged through the PNPN junction path. At this time, the width of the depletion layer 70a of the NP junction composed of the n-type well 50 and the p-type well 52 is reduced by positive feedback. As a result, a current path from the first pad 64 to the second pad 66 is temporarily formed through the switching path 52a. Since the current path including the first pad 64, the third diffusion layer 58, the second conductivity type well 52, the second diffusion layer 56, and the second pad 66 has a resistance component, the current increases. As a result, the switching path 52 is completely depleted again while positive feedback is suppressed, and the PNP bipolar transistor Q3 and the NPN bipolar transistor Q4 are turned on to form a current path again.

  FIG. 7 is a graph showing characteristics of the electrostatic discharge preventing element according to the first embodiment of the present invention.

  In the graph, line A is the current-voltage curve of the silicon controlled rectifier, line B is the current-voltage curve of the reverse biased PN junction diode, and line C is the current-voltage of the electrostatic discharge protection element according to the present invention. It is a curve.

As shown in FIG. 7, when a typical silicon controlled rectifier reaches the trigger voltage V _T , the current suddenly increases due to latch-up after a strong snapback operation occurs. At this time, if the pad connected to the silicon controlled rectifier is a power supply voltage pad to which a voltage higher than the hold voltage V _H is applied, local thermal damage due to excessive current can be generated. A reverse-biased PN junction diode maintains a positive impedance state while the voltage continuously rises after the junction breakdown, and the current gradually increases. Therefore, local thermal damage due to excessive current occurs. However, it is not suitable for discharging a large amount of electric charge supplied instantaneously.

Compared to this, the electrostatic discharge protection device according to the present invention is temporarily snapback operation subsequent trigger voltage V _T occurs, decreasing the width of the depletion region by immediately positive feedback, role switching path 52 of the resistor And the voltage rises again. Subsequently, the electrostatic discharge protection element is triggered again and a snapback operation occurs. As can be seen from the current-voltage curve C, the electrostatic discharge protection device according to the present invention is not only effective in discharging an instantaneous ESD current by repeatedly performing a snapback operation and a voltage increase, but also a large amount of charge. Even if an EOS pulse supplied with the current is supplied, excessive current (current crowding) does not occur, and the current path is dispersed to prevent local thermal destruction.

  FIG. 8 is a plan view showing an electrostatic discharge preventing element according to a second embodiment of the present invention.

  9A to 9C are cross-sectional views taken along lines I-I ', II-II', and III-III 'of FIG.

  Referring to FIGS. 8 and 9A to 9C, the ESD protection device includes a second conductivity type well formed in the first conductivity type well and a first conductivity type well surrounding the second conductivity type well. It can have a conductive guard ring structure. The first conductivity type may be n-type, and the second conductivity type may be p-type.

  A second conductivity type well 112 is formed in the first conductivity type well 110 formed in the semiconductor substrate 100 and joined to the first conductivity type well 110. An isolation layer 105 is formed on the semiconductor substrate 100 to define a plurality of active regions. A conductive diffusion layer, which will be described later, is formed in the active region. A first conductivity type first diffusion layer 114 is formed in the first conductivity type well 110, and the first conductivity type second diffusion layer 116 and the second conductivity type are formed in the second conductivity type well 112. The third diffusion layer 118 and the second conductivity type fourth diffusion layer 120 are formed. The first conductive type second diffusion layer 116 and the second conductive type fourth diffusion layer 120 may be formed adjacent to each other. In addition, the second diffusion layer 116 may be positioned between the first diffusion layer 114 and the fourth diffusion layer 120. The second conductivity type well may include a switching path 112a having a narrow width. The switching path 112 a may be located between the second diffusion layer 116 and the third diffusion layer 118. The first diffusion layer 114 may be formed in the first conductivity type well 110 adjacent to the switching path 112a. Also in the present embodiment, the second conductivity type well may include a plurality of switching paths 112a. At this time, the first diffusion layer 114 may be located between the switching paths 112a. That is, the present invention may include a plurality of first diffusion layers 114 formed in the first conductivity type well 110 between the plurality of switching paths 112a.

  In this element, the second diffusion layer 116, the second conductivity type well 112, and the first conductivity type well 110 constitute an emitter region, a base region, and a collector region of an NPN bipolar transistor, respectively. The second conductivity type well 112 in which the third diffusion layer 118 of the type is formed, the first conductivity type well 110, and the second conductivity type well 112 in which the fourth diffusion type 120 of the second conductivity type is formed, respectively. An emitter region, a base region, and a collector region of the PNP bipolar transistor Q4 are formed.

  The first diffusion layer 114 and the third diffusion layer 118 may be electrically connected to the first pad 124, and the second diffusion layer 116 and the fourth diffusion layer 120 may be electrically connected to the second pad 126. Can be linked to. A positive voltage such as a power supply voltage can be applied to the first pad 124, and a ground voltage can be applied to the second pad 126. When a positive voltage is applied to the first pad 124 and a ground voltage is applied to the second pad 126, the junction composed of the first conductivity type well 110 and the second conductivity type well 112 is reverse biased. As a result, a depletion layer is formed. In the present invention, when a normal operating voltage is applied to the first pad 124 and the second pad 126, the switching path 112a is turned off, and the current path from the first pad 124 to the second pad 126 is preferably cut off. . As a method for interrupting the current path, a method for completely depleting the switching path 112a can be applied. When a positive voltage and a ground voltage are connected to the first pad 124 and the second pad 126, if the width of the switching path 112a is smaller than twice the width of the depletion region, it is expanded from both junctions of the switching path 112a. The switching path 112a can be completely depleted by the depleted region.

  A first conductivity type guard ring diffusion layer 122 may be further formed in an active region surrounding the periphery of the second conductivity type well 112. The guard ring diffusion layer 122 may be connected to the first pad 124 to apply a positive voltage.

  FIG. 10 is a plan view showing an electrostatic discharge preventing device according to a third embodiment of the present invention.

  11A and 11B are cross-sectional views taken along lines I-I 'and II-II' in FIG.

  Referring to FIGS. 10, 11A, and 11B, the electrostatic discharge protection device according to the present invention may be implemented with a triple well structure.

  A first conductivity type well 210 is formed in the semiconductor substrate 200, and a second conductivity type first well 211 is formed in contact with the side wall of the first conductivity type well 210. A second conductivity type second well 212 is formed in the first conductivity type well 210 and joined to the first conductivity type well 210. A device isolation layer 205 is formed on the semiconductor substrate 200 to define a plurality of active regions, and a conductive diffusion layer to be described later is formed in the active regions. A first conductivity type first diffusion layer 214 is formed in the first conductivity type well 210, and the first conductivity type second diffusion layer 216 and the second conductivity type are formed in the second conductivity type first well 211. The fourth diffusion layer 220 is formed, and the second conductivity type third diffusion layer 218 is formed in the second conductivity type second well 212. The first conductive type second diffusion layer 216 and the second conductive type fourth diffusion layer 220 may be formed adjacent to each other. In addition, the second diffusion layer 216 may be positioned between the first diffusion layer 214 and the fourth diffusion layer 220. The first conductivity type first well 211 and the second well 212 may include a switching path 212a having a narrow width. The switching path 212a may be a portion where the second conductivity type second well 212 is expanded, or may be a portion where the second conductivity type first well 212 is expanded. The switching path 212 a may be located between the second diffusion layer 216 and the third diffusion layer 218. The first diffusion layer 214 may be formed in the first conductivity type well 210 adjacent to the switching path 212a. The second conductivity type well may include a plurality of switching paths 212a, and the first diffusion layer 214 may be located between the switching paths 212a. That is, the present invention may include a number of first diffusion layers 214 formed in the first conductivity type well 210 between the number of switching paths 212a.

  In this element, the second diffusion layer 216, the second conductivity type well 212, and the first conductivity type well 210 constitute an emitter region, a base region, and a collector region of an NPN bipolar transistor, respectively. The second well 212 of the type, the well 210 of the first conductivity type, and the first well 212 of the second conductivity type constitute an emitter region, a base region, and a collector region of the PNP bipolar transistor, respectively.

  The first diffusion layer 214 and the third diffusion layer 218 may be electrically connected to the first pad 224, and the second diffusion layer 216 and the fourth diffusion layer 218 may be electrically connected to the second pad 226. Can be linked to. A positive voltage such as a power supply voltage can be applied to the first pad 224, and a ground voltage can be applied to the second pad 226. When a positive voltage is applied to the first pad 224 and a ground voltage is applied to the second pad 226, the junction composed of the first conductivity type well 210 and the second conductivity type wells 211 and 212 is reversed. Directionally biased to form a depletion layer. In the present invention, when a normal operating voltage is applied to the first pad 224 and the second pad 226, the switching path 212a is turned off, and the current path from the first pad 224 to the second pad 226 is preferably cut off. . As a method of interrupting the current path, a method of making the switching path 212a completely depleted can be applied. When a positive voltage and a ground voltage are connected to the first pad 224 and the second pad 226, if the width of the switching path 212a is smaller than twice the width of the depletion region, it is expanded from both junctions of the switching path 212a. The switching path 212a can be completely depleted by the depleted region.

  A first conductivity type guard ring diffusion layer 210 may be formed in an active region surrounding the second conductivity type second well 212 formed in the first conductivity type well 210. The guard ring diffusion layer 210 is electrically connected to the first pad 224.

It is a figure which shows the electrostatic discharge prevention element by a prior art. It is a graph which shows the characteristic of the electrostatic discharge prevention element by a prior art. It is a top view which shows the electrostatic discharge prevention element by 1st Embodiment of this invention. FIG. 4 is a cross-sectional view taken along the line I-I ′ of FIG. 3. FIG. 4 is a cross-sectional view taken along the line II-II ′ of FIG. 3. FIG. 4 is a cross-sectional view taken along line III-III ′ in FIG. 3. It is a figure for demonstrating operation | movement of the electrostatic discharge prevention element by 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the electrostatic discharge prevention element by 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the electrostatic discharge prevention element by 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the electrostatic discharge prevention element by 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the electrostatic discharge prevention element by 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the electrostatic discharge prevention element by 1st Embodiment of this invention. 3 is a graph illustrating characteristics of the electrostatic discharge preventing element according to the first embodiment of the present invention. It is a top view which shows the electrostatic discharge prevention element by 2nd Embodiment of this invention. It is sectional drawing cut | disconnected along I-I 'of FIG. It is sectional drawing cut | disconnected along II-II 'of FIG. It is sectional drawing cut | disconnected along III-III 'of FIG. It is a top view which shows the electrostatic discharge prevention element by 3rd Embodiment of this invention. It is sectional drawing cut | disconnected along I-I 'of FIG. It is sectional drawing cut | disconnected along II-II 'of FIG.

Explanation of symbols

50 First conductivity type well 52 Second conductivity type well 52a Switching path 54 First diffusion layer 56 Second diffusion layer 58 Third diffusion layer 60 Fourth diffusion layer 64 First pad 66 Second pad 70 Depletion layer

Claims (22)

A first well of a first conductivity type connected to the first pad;
A second well of the first conductivity type connected to the second pad;
A second diffusion layer of a second conductivity type in a second well connected to the second pad;
A second well of a second conductivity type connected to the first pad;
A PNPN junction path formed by the first well, the third well, the second well, and the second diffusion layer in this order;
A first conductive type switching path formed in the third well and connecting the first well and the second well;
The switching path is configured to be at least a depletion region when a normal operating voltage is applied to the first pad and the second pad, and the PNPN junction path is charged during at least part of the ESD generation. The depletion region width is narrowed by positive feedback to form a resistance path, and electrostatic current is discharged multiple times alternately through the PNPN junction path and the resistance path during ESD generation. An electrostatic discharge protection device, characterized by being configured to do so.   The electrostatic discharge protection element according to claim 1, wherein the first conductivity type is p-type, and the second conductivity type is n-type.   The electrostatic discharge protection device of claim 1, wherein the first pad is connected to a power supply voltage, and the second pad is connected to a ground voltage.   The electrostatic discharge protection device of claim 1, wherein the first well includes a third diffusion layer of a first conductivity type, and the third diffusion layer is connected to the first pad.   The electrostatic discharge protection device of claim 4, wherein the second well further includes a fourth diffusion layer of a first conductivity type, and the fourth diffusion layer is connected to the second pad.   The electrostatic discharge protection device of claim 5, wherein the third well includes a first diffusion layer of a second conductivity type, and the first diffusion layer is connected to the first pad.   The electrostatic discharge protection element according to claim 1, wherein both the first well and the second well are formed in the third well.   The electrostatic discharge protection device of claim 1, wherein the first well is formed in the third well, and the second well is formed in a substrate of a first conductivity type.   The electrostatic discharge protection device of claim 1, further comprising an isolation region for defining an active region including the switching path and a guard ring of a second conductivity type. In an electrostatic discharge circuit including an electrostatic discharge circuit element including a PNPN junction path and a resistance path and disposed between a first pad and a second pad,
The PNPN junction path is
A first well of a first conductivity type connected to the first pad;
A second well of a first conductivity type connected to the second pad;
A second diffusion layer of a second conductivity type in a second well connected to the second pad;
A second well of a second conductivity type connected to the first pad;
Are formed in the order of the first well, the third well, the second well, and the second diffusion layer,
The resistance path is formed in the third well, and is formed in a first conductivity type switching path connecting the first well and the second well,
The switching path is configured to be at least a depletion region when a normal operating voltage is applied to the first pad and the second pad, and the PNPN junction path is charged during at least part of the ESD generation. The depletion region is narrowed by positive feedback to form a resistance path, and the electrostatic discharge circuit element alternately passes through the PNPN junction path and the resistance path during ESD generation. An electrostatic discharge circuit configured to discharge an electrostatic current a plurality of times. Characterized in that the switching path is located between adjacent contact holes, the contact hole is a contact hole in the second conductive type first diffusion layer of the third in-well coupled to the first pad The electrostatic discharge circuit according to claim 10.   The electrostatic discharge circuit of claim 10, wherein the switching path has a width that allows a fully depleted region to be formed across the switching path.   The electrostatic discharge circuit of claim 10, wherein the PNPN junction path includes a silicon controlled rectifier.   14. The electrostatic discharge circuit of claim 13, wherein the silicon controlled rectifier includes a PNP bipolar transistor and an NPN bipolar transistor. Said PNP bipolar transistor and the NPN bipolar transistor is operating in a positive feedback condition, by triggering the silicon controlled rectifier, according to claim 14, characterized in that to form a low impedance discharge channel for discharging electrostatic current Electrostatic discharge circuit.   The electrostatic discharge circuit of claim 10, further comprising an isolation layer defining an active region including the switching path and a guard ring. A first well of a first conductivity type connected to the first pad;
A second well of the first conductivity type connected to the second pad;
A second diffusion layer of a second conductivity type in a second well connected to the second pad;
A second well of a second conductivity type connected to the first pad;
A PNPN junction path formed by the first well, the third well, the second well, and the second diffusion layer in this order;
An electrostatic discharge circuit element formed in the third well and including a resistance path formed in a first conductivity type switching path connecting the first well and the second well;
The switching path is configured to be at least a depletion region when a normal operating voltage is applied to the first pad and the second pad, and the PNPN junction path is charged during at least part of the ESD generation. The depletion region is narrowed by positive feedback to form a resistance path, and the electrostatic discharge circuit element is connected between the first pad and the second pad during ESD. An electrostatic current distribution method using electrostatic discharge, wherein electrostatic current is discharged alternately a plurality of times through the PNPN junction path and the resistance path. Discharging the electrostatic currents to each other
Inducing current flow through at least two bipolar transistors forming the PNPN junction path to form a positive feedback state to form a low impedance discharge channel for discharging electrostatic current. Item 18. The electrostatic current distribution method according to Item 17 . Discharging the electrostatic currents to each other
Due to the positive feedback state, the width of a depletion region near the NP junction including the third well, the first well, and the second well is reduced, and current flows through the resistance path formed in the switching path. The electrostatic current distribution method according to claim 18 , further comprising inducing. Discharging the electrostatic currents to each other
A full depletion region that blocks the flow of current through the resistance path formed in the switching path by suppressing positive feedback by current flowing through the resistance path, the third well, the first and the first and The electrostatic current distribution method according to claim 19 , further comprising: forming in the vicinity of an NP junction including the second well. Discharging the electrostatic currents to each other
21. The electrostatic current of claim 20 , comprising re-inducing current flow through at least two bipolar transistors forming the PNPN junction path in response to interruption of current through the resistance path. Distribution method. A first pad;
A second pad;
An electrostatic discharge circuit element connected between the first pad and the second pad;
The electrostatic discharge circuit element is
A first well of a first conductivity type connected to the first pad;
A second well of a first conductivity type connected to the second pad;
A second diffusion layer of a second conductivity type in a second well connected to the second pad;
A second well of a second conductivity type connected to the first pad;
A PNPN junction path formed by the first well, the third well, the second well, and the second diffusion layer in this order;
A resistance path formed in a switching path of a first conductivity type formed in the third well and connecting the first well and the second well;
The switching path is configured to be at least a depletion region when a normal operating voltage is applied to the first pad and the second pad, and the PNPN junction path is charged during at least part of the ESD generation. The depletion region is narrowed by positive feedback to form a resistance path, and a plurality of electrostatic discharge circuit elements are alternately provided through the PNPN junction path and the resistance path during ESD generation. An electrostatic discharge circuit comprising means for discharging a static electricity.

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