JP5268292B2 - Semiconductor memory device - Google Patents

Description

  The present invention relates to a read error prevention technique for a semiconductor memory device, particularly a mask ROM (Read Only Memory).

FIG. 2 is a configuration diagram of a conventional mask ROM described in Patent Document 1 below.
This mask ROM has a memory cell group consisting of 128 blocks of memory cell array 10 (however, only one block is shown in FIG. 2). Each memory cell array 10 has an array of two NAND-type cells each composed of eight memory cell transistors TR, and is connected to the bit lines BL1 to BL8 via the drain side selector transistor TRD. Are grounded via a selector transistor TRS on the source side.

The bit lines BL1 to BL8 are each connected to a common pre-bit line PBL via a column line transistor TRC as a column selection transistor . The prebit line PBL is connected to the precharge voltage VDD via the precharge transistor 22, and the precharge operation by the precharge transistor 22 is controlled by the two-input NAND gate 21 connected to the gate thereof. Yes.

  The mask ROM data read circuit 20 includes a NAND gate 21 and a precharge transistor 22, a clocked inverter 23 for inputting data read to the bit lines BL1 to BL8 and output to the prebit line PBL, The data latch circuit 24 latches the output of the clocked inverter 23, and the clocked buffer 25 outputs the output of the data latch 24 to the memory bus as read data DT.

  Note that the memory cell array 10, the selector transistors TRD and TRS, the bit line BL, the column line transistor TRC, and the data read circuit 20 indicated by the alternate long and short dash line in FIG. Is provided.

  Further, this mask ROM has a control circuit 30 for controlling the data reading unit circuit 20 and decoders 40 to 80 for selecting a memory cell transistor TR to be read.

The control circuit 30 includes the chip select signal CS Ru activate the mask ROM, the read control signal RD, the first and second clock signals PH1, PH2, the system clock signal TE, and on the basis of the precharge signal PC, The timing signal CSR for the clocked buffer 25, the activation signal ACT for the data latch 24, and the drive precharge signal PCE are generated. That is, the timing signal CSR is generated by the logical product of the chip selection signal CS, the read control signal RD, and the clock signal PH1, and the activation signal ACT is generated by the logical product of the clock signal PH2 and the system clock signal TE. Is output as a precharge signal PCE through a buffer.

The decoder 40 decodes the address signals AL1 and AL2 and outputs the internal address signals HA0 to HA3 for selecting the data read circuit 20 when the chip selection signal CS is given. The decoder 50 decodes the address signals AL3 to AL5 when the chip selection signal CS is supplied, and supplies the internal address signals AD0 to AD7 to the gates of the column line transistors TRC that select the bit lines BL1 to BL8. is there.

  When the chip selection signal CS is applied, the decoder 60 decodes the address signals AL10 to AL16, and a memory cell group consisting of 128 blocks (FIG. 2 shows only the first block of the memory cell group. Select signals LS0 to LS127 for selecting a block, and the selector transistor TRD on the drain side of the NAND cell in the corresponding block of the memory cell group is driven.

When the chip selection signal CS is applied, the decoder 70 decodes the address signals AL7 to AL9 , and selects the gates of the NAND type cells composed of the eight memory cell transistors TR through the corresponding word lines WL0 to WL7. Signals LAD0 to LAD7 are provided. Of the selection signals LAD0 to LAD7, only one designated by the address signals AL7 to AL9 has a level "L" corresponding to the ground potential GND, and all those not designated are levels "L" corresponding to the power supply potential VDD. H ”is set.

  That is, only the selected one of the internal address signals HA0 to HA3 output from the decoder 40, the internal address signals AD0 to AD7 output from the decoder 50, and the selection signals LS0 to LS127 output from the decoder 60 are “H”. ", And the non-selected signal is" L ", but the selection signals LAD0 to LAD7 output from the decoder 70 have opposite output levels.

  The decoder 80 decodes the address signal AL6 and generates the selection signals LL and LH when the chip selection signal CS is supplied and the precharge signal PC is not supplied. The selection signals LL and LH are signals for selecting one of the two NAND cells connected to the bit lines BL1 to BL8, and are the gates of the selector transistors TRS connected to the source side of the NAND cells. Is to be given to.

Next, the operation will be described.
In this NAND type mask ROM, data “0” is obtained by connecting the source and drain of the memory cell transistor (MOS transistor) TR constituting the memory cell by an aluminum wiring, and data is obtained by opening the source and drain. “1” is stored. The aluminum wiring between the source and the drain is usually performed at the manufacturing stage using the first layer aluminum wiring pattern.

  When reading data, the clock signals PH1 and PH2 are input, the chip selection signal CS is set to “H”, and the address signals AL1 to AL16 are input to the decoders 40 to 80. In each read cycle, first, after precharging the prebit line PBL to the precharge voltage VDD using the precharge signal PC, the precharge signal PC is stopped, and a read operation by the read control signal RD is performed.

Here, it is assumed that the bit line BL1 is selected by the internal address signal AD0, the block selection signal LS0 becomes “H”, and the first memory cell array 10 is selected. Further, it is assumed that the selection signal LAD0 is selected by the address signals AL7 to AL9, and the data of the memory cell transistor TR whose gate is connected to the row selection line (selected word line WL ) of the first row is read.

By the selection signals LL and LH, one selector transistor TRS of the two NAND cells connected to each bit line BL is turned on, and the source side of the NAND cell is grounded.

When the selection signal LAD0 is selected, the selection signal LAD0 becomes “L”, and the other selection signals LAD1 to LAD7 all become “H”. Therefore, all the memory cell transistors TR connected to the unselected word lines WL of the NAND cells are turned on regardless of the writing state.

At this time, if data “0” is written in the memory cell transistor TR connected to the selected word line WL (since the source and drain are connected by an aluminum wiring), the memory cell transistor TR is also on. . As a result, all the eight memory cell transistors TR connected in series to the bit line BL1 are turned on, the pre-bit line PBL is grounded via the bit line BL1, and its potential is lowered to the ground potential.

On the contrary, if data “1” is written in the memory cell transistor TR connected to the selected word line WL (because the source and drain are open), the memory cell transistor TR is turned off, The prebit line PBL is not grounded. Therefore, the potential of the prebit line PBL is held at the precharge voltage VDD.

The potential of the pre-bit line PBL is held in the data latch 24 via the clocked inverter 23 of the data read circuit 20, and is further output from the clocked buffer 25 as read data DT to the memory bus.

  Such a NAND-type mask ROM can be connected in series with a common source / drain diffusion layer of a plurality of adjacent memory cell transistors, so that it is highly integrated and widely used as a large-capacity ROM. .

JP 2001-266585 A

  However, the mask ROM has a problem that malfunction occurs under the following specific reading conditions.

  For example, when the memory cell transistors TR1, TR4, TR5 are sequentially read out of the memory cell transistors TR1, TR2, TR3, TR4, TR5, TR6,... Selected in common by the selection signal LAD0 in FIG. The data of the memory cell transistors TR1, TR4, TR5 are all “1”, and the data of at least one of the memory cell transistors TR2, TR6 is “0” (FIG. 2 shows the case where both are “0”). Suppose there is.

  When reading the data “1” of the memory cell transistor TR4, the data of the memory cell transistors TR2 and TR6 is “0”, so that it is not selected when the selection signal LH changes from “L” to “H”. At least one of the bit lines BL1 and BL3 (both in the example of FIG. 2) transitions to the ground potential GND. The bit line BL2 includes a parasitic capacitance C3 with respect to the ground potential GND in addition to the parasitic capacitances C1 and C2 between the adjacent bit lines BL1 and BL3. For this reason, the level of the precharge voltage VDD applied to the bit line BL2 is lowered by the parasitic capacitances C1 to C3, and the read level of the prebit line PBL is lowered. At this time, if the threshold of the clocked inverter 23 is high, the read data “1” is detected as “0” even if the input level is slightly reduced, and a read error occurs.

  In Patent Document 1, in order to prevent such a malfunction, a non-selected bit line is always fixed to “L”, and data “1” read to the pre-bit line is static except for the precharge period. A holding circuit for holding data “1” is provided.

  However, in Patent Document 1, a transistor for constantly fixing an unselected bit line to “L” and a control circuit therefor are required, and data “1” read to the pre-bit line is stored in the precharge period. Other than the above, a holding circuit for holding static data “1” is required, and the circuit scale increases.

  An object of the present invention is to provide a mask ROM capable of preventing malfunction without substantially increasing the circuit scale.

The semiconductor memory device of the present invention includes a plurality of memory cell transistors arranged at each intersection of a plurality of bit lines and a plurality of word lines arranged intersecting with the bit lines and selected by the bit lines and the word lines. A memory cell array, a plurality of column selection transistors for connecting one of the plurality of bit lines to a pre-bit line according to a first selection signal, and a delay precharge by delaying a predetermined time when a precharge signal is applied A timing circuit that outputs a signal and immediately stops the delayed precharge signal when the precharge signal stops, and inputs the delayed precharge signal to precharge the prebit line, and the precharge signal stops. Thereafter, a data read circuit for reading the stored contents of the selected memory cell transistor, Serial and certain time until the delay precharge signal from the precharge signal is given is output during the period from the pre-charge signal is stopped until the read of the storage contents by the data readout circuit is completed, And a decoding circuit having a plurality of selection transistors for discharging the plurality of bit lines in accordance with a second selection signal , wherein the plurality of selection transistors are connected to a source side of the memory cell array . .

  In the present invention, by providing the timing circuit, the address signal and its decode signal are switched earlier than the start of the precharge of the bit line, and the non-selected bit line is discharged. As a result, since the selected bit line is precharged after the charge of the parasitic capacitance of the unselected bit line is discharged, it is possible to prevent a read error due to the charge of the adjacent unselected bit line. effective.

  The above and other objects and novel features of the present invention will become more fully apparent when the following description of the preferred embodiment is read in conjunction with the accompanying drawings. However, the drawings are for explanation only, and do not limit the scope of the present invention.

  FIG. 1 is a block diagram of a mask ROM showing an embodiment of the present invention. Elements common to those in FIG. 2 are denoted by common reference numerals.

  This mask ROM has, for example, a memory cell group consisting of 128 blocks of the memory cell array 10 (however, only one block is shown in FIG. 1). In the memory cell array, memory cell transistors TR are arranged at intersections of a plurality of bit lines BL arranged in parallel and a plurality of word lines WL arranged in parallel to intersect with the bit lines BL.

The memory cell transistors TR are connected in series according to the corresponding bit line BL and are gate-controlled by the corresponding word line WL. Among these memory cell transistors TR, the first logic value ( For example, a memory cell transistor that stores “0”) is set to be always on regardless of whether or not the corresponding word line WL is selected, and stores a second logical value (for example, “1”). The memory cell transistor TR is set to be turned off only when selected by the corresponding word line WL.

  This memory cell array 10 has an array of NAND cells of two columns each consisting of eight memory cell transistors TR, and is connected to bit lines BL1 to BL8 via selector transistors TRD on the drain side thereof. Are connected to the ground potential GND via the selector transistor TRS on the source side. The bit lines BL1 to BL8 are each connected to a common prebit line PBL via a column line transistor TRC, and this prebit line PBL is connected to the data read circuit 20.

  The prebit line PBL is connected to the precharge voltage VDD via the precharge transistor 22 of the data read circuit 20, and the precharge operation by the precharge transistor 22 is based on the output of the 2-input NAND gate 21 connected to the gate. To be controlled.

  In addition to the NAND gate 21 and the precharge transistor 22, the data read circuit 20 includes a clocked inverter 23 that inputs the data read to the bit lines BL 1 to BL 8 and output to the pre-bit line PBL, and the clocked inverter 23 A data latch 24 that latches the output and a clocked buffer 25 that outputs the output of the data latch 24 as read data DT to the memory bus.

  Although only one set is shown in FIG. 1, the memory cell array 10, the selector transistors TRD and TRS, the bit line BL, the column line transistor TRC, and the data read circuit 20 shown in a one-dot chain line are actually The number of bits of the memory bus (for example, 8) is provided in parallel. The mask ROM further includes a control circuit 30A for controlling the data read circuit 20 and decoders 40 to 70, 80A for selecting the memory cell transistor TR to be read.

Control circuit 30A, the chip select signal CS Ru activate the mask ROM, the read control signal RD, the first and second clock signals PH1, PH2, the system clock signal TE, and on the basis of the precharge signal PC, The timing signal CSR for the clocked buffer 25, the activation signal ACT for the data latch 24, and the delay precharge signal PCD for driving are generated.

  That is, the timing signal CSR is generated by the AND gate 31 by ANDing the chip selection signal CS, the read control signal RD, and the clock signal PH1. The activation signal ACT is generated by ANDing the clock signal PH2 and the system clock signal TE by the AND gate 32. The delayed precharge signal PCD becomes “H” after a predetermined time delay when the precharge signal PC becomes “H”, and immediately becomes “L” when the precharge signal PC becomes “L”. Is a signal.

  The delayed precharge signal PCD includes a delay element 33 that delays the precharge signal PC for a predetermined time, a NAND gate 34 that performs a negative logical product of the output of the delay element 33 and the precharge signal PC, and an output of the NAND gate 34. Is generated by a timing circuit by an inverter 35 that inverts. The delay element 33 can be configured by, for example, an even number of inverters connected in cascade.

The decoder 40 decodes the address signals AL1 and AL2 and outputs the internal address signals HA0 to HA3 for selecting the data read circuit 20 when the chip selection signal CS is given. The decoder 50 decodes the address signals AL3 to AL5 when the chip selection signal CS is supplied, and supplies the internal address signals AD0 to AD7 to the gates of the column line transistors TRC that select the bit lines BL1 to BL8. is there.

  When the chip selection signal CS is applied, the decoder 60 decodes the address signals AL10 to AL16, and a memory cell group consisting of 128 blocks (FIG. 2 shows only the first block of the memory cell group. Select signals LS0 to LS127 for selecting a block, and the selector transistor TRD on the drain side of the NAND cell in the corresponding block of the memory cell group is driven.

When the chip selection signal CS is applied, the decoder 70 decodes the address signals AL7 to AL9 , and selects the gates of the NAND type cells composed of the eight memory cell transistors TR through the corresponding word lines WL0 to WL7. Signals LAD0 to LAD7 are provided. Note that only one of the selection signals LAD0 to LAD7 designated by the address signals AL7 to AL9 is set to “L”, and those not designated are set to “H”.

  That is, only the selected one of the internal address signals HA0 to HA3 output from the decoder 40, the internal address signals AD0 to AD7 output from the decoder 50, the selection signals LS0 to LS127 output from the decoder 60, etc. Although it becomes “H” and the unselected signal becomes “L”, the output levels of the selection signals LAD0 to LAD7 output from the decoder 70 are reversed.

The decoder 80A decodes the address signal AL6 and generates the selection signals LL and LH when the chip selection signal CS is supplied and the delayed precharge signal PCD is not supplied. The selection signals LL and LH are signals for selecting one of the two NAND cells connected to the bit lines BL1 to BL8, and are selectors as selection transistors connected to the source side of the NAND cells. The signal is supplied to the gate of the transistor TRS. The decoder 80A and the plurality of selector transistors TRS constitute a decoding circuit.

  The decoder 80A, for example, includes inverters 81 and 82 that invert the address signal AL6 and the delayed precharge signal PCD, respectively, and an AND gate 83 that outputs a logical product of the chip selection signal CS and the outputs of the inverters 81 and 82 as a selection signal LL. And an AND gate 84 that outputs the logical product of the chip selection signal CS, the address signal AL6, and the output of the inverter 82 as the selection signal LH.

  FIG. 3 is a signal waveform diagram showing the operation of FIG. The operation of FIG. 1 will be described below with reference to FIG.

  At time t1 in FIG. 3, an address ADR1 for reading out the memory cell transistor TR1 in FIG. 1 is given to the address signals AL1 to AL16, and an “H” signal is given to the clock signal PH1 and the precharge signal PC. . The chip selection signal CS is already “H”, and the read control signal RD is still “L”. As a result, the internal address signals HA0 and AD0 and the selection signal LS0 become “H”, and the selection signal LAD0 becomes “L”. The selection signals LAD1 to LAD7 are all “H”.

  At this time, since the delayed precharge signal PCD is still “L”, the decoder 80A decodes the address signal AL6 and outputs the “H” selection signal LL and the “L” selection signal LH. Thereby, each bit line BL1, BL2, BL3,... Is connected to the ground potential GND via the selector transistor TRS driven by the selection signal LL. On the other hand, the output of the NAND gate 21 of the data read circuit 20 is “H”, and the precharge transistor 22 is off. As a result, the discharge operation is started, the pre-bit line PBL is connected to the ground potential via the bit line BL connected to the ground potential GND, and its level PCB becomes “L”.

  When a predetermined time elapses after the precharge signal PC becomes “H” at time t2, the delayed precharge signal PCD becomes “H”. As a result, the selection signals LL and LH output from the decoder 80A are both “L”, and all the selector transistors TRS are turned off, and the discharge operation is completed. Further, the output of the NAND gate 21 of the data read circuit 20 becomes “L”, and the precharge transistor 22 is turned on. As a result, the precharge operation is started, the level PCB of the prebit line PBL rises to the precharge voltage VDD, and the level of the bit line BL1 selected by the internal address signal AD0 also rises to the precharge voltage VDD.

At time t3, the clock signals PH1 and PH2 become “L” and “H”, respectively.
At time t4, the clock signals PH1 and PH2 become “H” and “L”, respectively, and the precharge signal PC becomes “L”. As a result, the delayed precharge signal PCD also immediately becomes “L”, the precharge operation is terminated, and the selection signal LL becomes “H” again to start the read operation.

  If data “1” is written in the memory cell transistor TR1 to be read (because the source and drain are open), the memory cell transistor TR1 is off. Therefore, the bit line BL1 is not connected to the ground potential GND, and the pre-bit line PBL is not discharged. As a result, the level PCB of the pre-bit line PBL is held at the precharge voltage VDD. On the contrary, if data “0” is written in the memory cell transistor TR1 (because the source and drain are connected), the memory cell transistor TR1 is on. Therefore, the bit line BL1 is connected to the ground potential GND, and the pre-bit line PBL is discharged. As a result, the level PCB of the pre-bit line PBL is lowered to the ground potential GND.

At time t5, the clock signals PH1 and PH2 become “L” and “H”, respectively, and the read control signal RD and the system clock signal TE become “H”. As a result, the activation signal ACT becomes “H”, the level PCB of the pre-bit line PBL is input to the data latch 24 via the clocked inverter 23, and further output as data D0.

  At time t6, the clock signals PH1 and PH2 become “H” and “L”, respectively. Further, the address signals AL1 to AL16 are changed to, for example, the address ADR2 for reading the memory cell transistor TR4 in FIG. 1, and the signal “H” is given to the precharge signal PC. Note that the read control signal RD remains “H”.

  The activation signal ACT becomes “L” by the “L” clock signal PH 2, and the data D 0 of the memory cell transistor TR 1 read at the address ADR 1 in the previous period is held in the data latch 24. Then, the timing signal CSR becomes “H” by the read control signal RD of “H” and the clock signal PH1, and the data D0 held in the data latch 24 is output from the clocked buffer 25 to the memory bus as read data DT0. The On the other hand, according to the address ADR2, the internal address signals HA0 and AD1 and the selection signal LS0 are “H”, and the selection signal LAD0 is “L”.

  At this time, since the delayed precharge signal PCD is still “L”, the decoder 80A decodes the address signal AL6 and outputs the “L” selection signal LL and the “H” selection signal LH. Thereby, each bit line BL1, BL2, BL3,... Is connected to the ground potential GND via the selector transistor TRS driven by the selection signal LH. On the other hand, the output of the NAND gate 21 of the data read circuit 20 is “H”, and the precharge transistor 22 is off. As a result, the discharge operation is started, the pre-bit line PBL is connected to the ground potential via the bit line BL connected to the ground potential GND, and its level PCB becomes “L”.

  At time t7, after a predetermined time has elapsed since the precharge signal PC has become “H”, the delayed precharge signal PCD becomes “H” as in the case of time t2. As a result, the discharge operation ends, and the selection signals LL and LH output from the decoder 80A both become “L”. Further, the output of the NAND gate 21 of the data read circuit 20 becomes “L”, the precharge operation is started, the level PCB of the prebit line PBL rises to the precharge voltage VDD, and the bit selected by the internal address signal AD1. The level of the line BL2 also rises to the precharge voltage VDD.

  At time t8, the clock signals PH1 and PH2 become “L” and “H”, respectively. As a result, the timing signal CSR becomes “L”, and the output of the read data DT0 from the clocked buffer 25 to the memory bus is stopped.

  At time t9, the clock signals PH1 and PH2 become “H” and “L”, respectively, and the precharge signal PC becomes “L”. As a result, the delayed precharge signal PCD also immediately becomes “L”, the precharge operation ends, and the selection signal LH becomes “H” again to start the read operation.

  At time t10, the clock signals PH1 and PH2 become “L” and “H”, respectively, and the read control signal RD becomes “H”. As a result, the activation signal ACT becomes “H”, the level PCB of the pre-bit line PBL is input to the data latch 24 via the clocked inverter 23, and further output as data D0.

  At time t11, the clock signals PH1 and PH2 become “H” and “L”, respectively. Further, the address signals AL1 to AL16 are changed to addresses for reading the next memory cell transistor (for example, TR5), and a signal of “H” is given to the precharge signal PC.

As described above, in the mask ROM of this embodiment, when the precharge signal PC becomes “H”, the delay precharge signal PCD is set to “H” by delaying for a predetermined time. A timing circuit for immediately setting the delayed precharge signal PCD to “L” when it becomes “L” is provided so that the delay precharge signal PCD becomes “H” after the precharge signal PC becomes “H”. In the meantime, the bit line BL is connected to the ground potential GND for discharging. This discharge operation, since the charge of the parasitic capacitance of the bit line BL to the adjacent bit line BL and that of the read target is discharged, a simple circuit configuration, to prevent reading errors due to the charges in the parasitic capacitance There is an advantage that you can.

In addition, this invention is not limited to the said Example, A various deformation | transformation is possible. Examples of this modification include the following.
(A) Although the mask ROM of FIG. 1 has a 16-bit address space, the address size is not limited to this. Further, the address signal AL decoded by each of the decoders 40 to 80A is not limited to the illustrated one.
(B) Each memory cell transistor TR stores a logical value “0” by connecting the source and drain with an aluminum wiring. However, even if the gate voltage is 0V by implanting ions into the gate region. The threshold voltage may be changed so as to exhibit an on state.
(C) The control signals and circuit configurations exemplified in the control circuit 30A are examples, and other control signals and circuit configurations can be used.

It is a block diagram of the mask ROM which shows the Example of this invention. It is a block diagram of the conventional mask ROM. It is a signal waveform diagram which shows the operation | movement of FIG.

Explanation of symbols

10 memory cell array 20 data read circuit 30A control circuit 33 delay element 34 NAND gate 35 inverter 40, 50, 60, 70, 80A decoder BL bit line PBL pre-bit line TR memory cell transistor TRC column line transistor TRD, TRS selector transistor

Claims (3)

A memory cell array having a plurality of memory cell transistors arranged at each intersection of a plurality of bit lines and a plurality of word lines arranged crossing the bit lines, and selected by the bit lines and the word lines;
A plurality of column selection transistors for connecting one of the plurality of bit lines to a pre-bit line according to a first selection signal;
A timing circuit that outputs a delayed precharge signal with a predetermined time delay when a precharge signal is applied, and immediately stops the delayed precharge signal when the precharge signal is stopped;
A data read circuit for inputting the delayed precharge signal to precharge the prebit line and reading the storage contents of the selected memory cell transistor after the precharge signal is stopped;
A fixed time from when the precharge signal is applied to when the delayed precharge signal is output, and from when the precharge signal is stopped until the reading of the stored content by the data read circuit is completed . a decoding circuit having a plurality of selection transistors for discharging the plurality of bit lines according to a second selection signal,
Equipped with a,
The semiconductor memory device, wherein the plurality of selection transistors are connected to a source side of the memory cell array . The plurality of memory cell transistors are:
Said plurality of gated by the word line is connected in series according to the bit lines, when storing the first logic value is set to be always on regardless of whether the selection by the word line , when storing the second logic value is set to be turned off only when it is selected by the word line,
The selection transistor is:
2. The semiconductor memory device according to claim 1, wherein the discharging is performed by connecting the bit line to a ground potential in accordance with the second selection signal. Each bit line of said memory cell array is constituted by first and second bit lines which are provided adjacent respectively, the decoding circuit corresponding to the first and second bit lines of each bit line wherein a selection transistor, the second selection signal the first or second semiconductor memory according to claim 2, wherein the selected bit line, characterized by being configured to be connected to the ground potential according to apparatus.

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