JPS61151899A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent a malfunction produced in a data reading mode as well as a delay of the access time by using a means which discharges the electric charge stored to a selected bit line toward the earth when said bit line is not selected. CONSTITUTION:The transistors TR T12-Tn2 to which signals Y1'-Yn' of column selection signals Y1-Yn for selection of each bit line are supplied through the gates are connected between the bit lines B1-Bn and the earth side Vss. When data are read out of a cell C11, the electric charge stored to the line B1 is discharged to the Vss through the TR T12 to which the signal Y1' of a high level is supplied through the gate when the line B1 is not selected. It is avoided that the electric charge stored tot he bit line is discharged later through a cell TR connected to said bit line. This prevents a malfunction caused in a data reading mode or avoids a delay of the access time.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a bit line configuration in a semiconductor memory device such as an EFROM or a mask ROM.

[Conventional technology]

FIG. 3 shows the structure of a conventional example of an EFROM as this type of semiconductor memory device.

---------Tnl becomes conductive when the column selection signals Y+, Yz--Yn are input to its gates, respectively, and the corresponding bit lines B+, Bz-----B
Transistor connecting n to sense amplifier S, C+C
I! -...-G and n each have word lines w at their gates.
l is connected and its drain side is connected to the corresponding bit line B
A cell consisting of a cell transistor with a floating gate connected to l+B2...--Bn, C
n, , Cn, -=-Cnn are cell transistors with floating gates whose gates are connected to word lines Wn, and whose drains are further connected to corresponding bit lines B, , B, ------Bn. This is a cell composed of Note that the bit line selected by the column selection signal passes through the circuit in the sense amplifier S and is connected to the DC power supply V.
The charger knob is controlled to a predetermined potential by the current supplied from cc.

When reading data contents from each memory cell constituted by each of these cell transistors, a specific word line is selected by a selection signal from a row decoder (not shown), and a specific bit line is selected by the column selection signal. is selected, the data written in a specific selected cell connected to these selected word lines and bit lines, that is, a predetermined amount of electrons are accumulated in the floating gate of the cell transistor constituting the cell. Data is read out through the sense amplifier S depending on whether the current state is present or not.

In the memory cell array configured as described above, if the data of each cell C1l+Cat-------'Can is 0 (that is, electrons are accumulated in the floating gates of the cell transistors constituting each of these cells, Therefore, when reading data, the transistor is not energized), while each cell Cn, , Cn, .
---- It is assumed that the data of Cnn is 1 (that is, no electrons are accumulated in the floating gates of the transistors constituting each of these cells, and therefore the transistors are energized when reading data).

In such a state, when reading data from the memory cell array, the word line W1 is temporarily selected, and the column selection signals Y1, Y2-, -Y
By sequentially selecting the bit lines B, , B, .
If the data in each cell Cl1l c+z-----Ctn is O as described above, each cell transistor constituting each of these cells will not be energized. , As a result, the voltage of each bit line after the charge-up becomes, for example, 1V.In this way, each bit WA B + ,
Since each cell transistor is in a non-conductive state until the next word line is selected, the charges accumulated in B t . . . B n have no place to escape and are held as they are.

Assume that after such a state is formed, the cell Cnt is selected by selecting the word line Wn and the bit line B l . In this case, as mentioned above, cells Cn+, Cn
If the data of z-------Cnn is 1, each cell transistor forming the cell Cn++ Cnt-------Cnn is supplied with a high-level selection signal to the word line Wn. As a result, each bit line B1 . Bt・----
The charges accumulated in B n are each cell Cn, respectively.

It is emitted all at once through the cell transistors constituting Cnzt ---1.-Cnn.

On the other hand, the sources of the cell transistors constituting each of these cells are generally connected to the Vss side through a relatively long diffusion layer, and the discharged charge increases its resistance component (shown as parasitic resistance rn in FIG. 3). Due to the voltage drop caused by the current, the potential of the source part (in this case, the source part of the cell transistor constituting the cell Cn) temporarily increases, and therefore the selected cell Cnl
The amount of current that can flow through the cell transistors that make up the circuit temporarily decreases. Note that when the potential of the source part of the cell transistor increases in this way, the so-called bank bias effect (when the substrate potential becomes negative with respect to the potential of the source part of the cell transistor, the threshold voltage of the cell transistor increases) (This phenomenon refers to a phenomenon in which the current flows through the cell transistor.) The current flowing through the cell transistor further decreases.

In this way, when data is read from the cell Cn, since the data written in the cell CnI is 1, a predetermined current should be applied to the cell transistor constituting the cell Cn. Nevertheless, for the reasons mentioned above, each bit line B l+ B z.

-・-・-Until all the charges accumulated in Bn are released, the amount of current in the cell transistor will temporarily decrease, which may cause a temporary malfunction when reading data. There was a problem in that it caused a delay in access time.

[Problem that the invention seeks to solve]

The present invention has been made to solve the above problems,
Based on the idea of providing a means for discharging the charge accumulated in a selected bit line from the bit line to the ground side when the bit line is deselected, a cell to be selected subsequently is configured. This prevents the potential of the source portion of the cell transistor from rising temporarily, and eliminates malfunctions or delays in access time during data reading based on this.

Crj1! Means for Solving Point A] In order to solve the above problem, according to the present invention, the charges accumulated in the selected bit line are removed from the selected bit line when the bit line is deselected. A semiconductor memory device is provided that is provided with means for emitting radiation to the ground side.

In the first embodiment of the present invention, as the emitting means, a transistor whose gate receives an inverted signal of the column selection signal corresponding to the bit line is connected between the bit line and ground.

In another embodiment of the present invention, a depletion type transistor whose gate and source are connected is connected between each bit line and ground as the means for releasing the bit line.

[For production]

According to the above configuration, the charges accumulated in the selected focus line are discharged from the bit line to the ground side when the bit line is unselected. A transistor whose gate receives an inverted signal of the corresponding column selection signal is connected between the bit line and ground, or a depletion type transistor whose gate and source are connected is connected between each bit line and ground.) Therefore, the charge is prevented from being released through a predetermined cell transistor connected to the adjacent bit line, and therefore, even if there is a parasitic resistance in the source part of the cell transistor, the potential of the source part will not rise. This prevents malfunctions or access time delays when reading data from cell transistors constituting a given cell.

〔Example〕

FIG. 1 shows the configuration of a semiconductor memory device as an embodiment of the present invention, in which bit lines B I, B t -Bn are connected between each bit line B+, Bz/-Bn and a ground side 733.
Column selection signal Y In Y for selecting each
Each inverted signal Y ,, Y z − of z ・−・−Yn
−−−−−Transistors T + z, T zz, −−−−−− Yn is input to its gate, respectively.
Tn2 is connected. Note that the bit line selected by the column selection signal passes through a circuit within the sense amplifier S and is charged up to a predetermined potential by a current supplied from the DC power supply VCC.

Therefore, when data is read from a predetermined cell C0, the charges accumulated in the bit line B as described above will be transferred to the adjacent bit line B1 which is unselected (that is, if the column selection signal Y1 is not selected). When the selection signal becomes low level), a high-level inverted signal Y, which is the inversion of the selection signal, is released to the ground side (Vss side) through the transistor Tlz input to its gate (therefore, at this time, the focus line The potential of B temporarily drops to Ov). In this way, the charges accumulated in the bit line B are discharged to the ground side while the bit line B is not selected (that is, while another bit line is selected).

Further, FIG. 2 shows the configuration of a semiconductor memory device as another embodiment of the present invention, in which each pit t[B+.

A depletion type transistor TI3.Bz-----Bn and the ground side 733 are each connected between its gate and source (therefore, no specific signal is supplied to its gate). Tzz-----Tn
3 is connected. Note that the bit line selected by the column selection signal passes through a circuit within the sense amplifier S and is charged and amplified to a predetermined potential by a current supplied from the DC power supply Vcc.

Therefore, each bit line, for example, bit line B1, allows a small current to flow to the ground side (Vss side) through the depletion type transistor TI3 even while a cell connected to the bit line, for example, cell c11, is selected. Further, the charge accumulated in the bit line B at this time continues to flow to the ground side through the depletion type transistor TI3 even after the bit line B1 is deselected.

In this way, the charges accumulated in the bit line B are discharged to the ground side while the bit line B is not selected (that is, while another bit line is selected).

In the case of this embodiment, if data is read from cell C0 and the data is O, bit line B
There is no current flowing from + to the cell transistors that make up cell C11, but only from bit line B.

Only a minute current flows from the cell C11 to the ground through the depression type transistor TI3, and - if the cough data is 1, the bit line B has a minute current flowing through the cell transistor constituting the cell C11 and the minute current flowing to the ground through the depression type transistor TI3. Since the sum of the current and current flows, the data can be read accurately by determining these two energization states.

Note that if the above-mentioned depletion mode transistor is used, it is sufficient to simply connect its gate to the source, and no particular gate voltage is required. However, if a specific gate voltage is to be supplied, the depletion mode transistor can also be used as an enhancement mode transistor. The good news is obvious.

〔Effect of the invention〕

According to the present invention, even if there is a parasitic resistance in the source part of a cell transistor, the electric charge accumulated in the bit line does not flow through the parasitic resistance and the potential of the source part increases. Particularly, malfunctions or access time delays do not occur when reading data from cell transistors constituting certain cells.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a semiconductor memory device as one embodiment of the present invention; FIG. 2 is a circuit diagram showing the configuration of a semiconductor memory device as another embodiment of the present invention; FIG. 3 is a circuit diagram illustrating the configuration of a conventional semiconductor memory device. 2 (Explanation of symbols) C++, Crt, C1---'-Cn++
Cnz, Cnn...Cells constituting the memory cell array, TII, Tz+, Tnt...Transistors to which the column selection signal is input, Tlz, Tzt*Tnz...Inverted signal of the column selection signal Input transistors, 'r,, 'r,, Ta2...depression type transistor, r, -------r,...parasitic resistance, S...
sense amplifier.

Claims (1)

[Claims] 1. The device is characterized by being provided with means for discharging the charge accumulated in the selected bit line from the bit line to the ground side when the bit line is deselected. semiconductor storage device. 2. As the emitting means, a transistor whose gate receives an inverted signal of a column selection signal corresponding to the bit line is connected between the bit line and ground. Semiconductor storage device. 3. The semiconductor memory device according to claim 1, wherein a depletion type transistor whose gate and source are connected is connected between each bit line and ground as the emitting means.